STM32U535 Peripheral Coverage

ADC1

0x42028000: ADC1

16/165 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ADC_ISR																			LDORDY			AWD3	AWD2	AWD1	JEOS	JEOC	OVR	EOS	EOC	EOSMP	ADRDY
0x4	ADC_IER																						AWD3IE	AWD2IE	AWD1IE	JEOSIE	JEOCIE	OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	ADC_CR	ADCAL		DEEPPWD	ADVREGEN	CALINDEX										ADCALLIN											JADSTP	ADSTP	JADSTART	ADSTART	ADDIS	ADEN
0xc	ADC_CFGR1		AWD1CH					JAUTO	JAWD1EN	AWD1EN	AWD1SGL	JDISCEN	DISCNUM			DISCEN		AUTDLY	CONT	OVRMOD	EXTEN		EXTSEL						RES		DMNGT
0x10	ADC_CFGR2	LSHIFT				LFTRIG		OSR									SMPTRIG	SWTRIG	BULB			ROVSM	TROVS	OVSS							JOVSE	ROVSE
0x14	ADC_SMPR1			SMP9			SMP8			SMP7		SMP6			SMP5		SMP5	SMP4			SMP3			SMP2			SMP1			SMP0
0x18	ADC_SMPR2			SMP19			SMP18			SMP17		SMP16			SMP15		SMP15	SMP14			SMP13			SMP12			SMP11			SMP10
0x1c	ADC_PCSEL												PCSEL19	PCSEL18	PCSEL17	PCSEL16	PCSEL15	PCSEL14	PCSEL13	PCSEL12	PCSEL11	PCSEL10	PCSEL9	PCSEL8	PCSEL7	PCSEL6	PCSEL5	PCSEL4	PCSEL3	PCSEL2	PCSEL1	PCSEL0
0x30	ADC_SQR1				SQ4						SQ3					SQ2	SQ2					SQ1							L
0x34	ADC_SQR2				SQ9						SQ8					SQ7	SQ7					SQ6						SQ5
0x38	ADC_SQR3				SQ14						SQ13					SQ12	SQ12					SQ11						SQ10
0x3c	ADC_SQR4																					SQ16						SQ15
0x40	ADC_DR	RDATA															RDATA
0x4c	ADC_JSQR	JSQ4						JSQ3					JSQ2				JSQ2		JSQ1					JEXTEN		JEXTSEL					JL
0x60	ADC_OFR1	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x64	ADC_OFR2	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x68	ADC_OFR3	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x6c	ADC_OFR4	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x70	ADC_GCOMP	GCOMP																	GCOMPCOEFF
0x80	ADC_JDR1	JDATA															JDATA
0x84	ADC_JDR2	JDATA															JDATA
0x88	ADC_JDR3	JDATA															JDATA
0x8c	ADC_JDR4	JDATA															JDATA
0xa0	ADC_AWD2CR												AWD2CH				AWD2CH
0xa4	ADC_AWD3CR												AWD3CH				AWD3CH
0xa8	ADC_LTR1								LTR1								LTR1
0xac	ADC_HTR1	AWDFILT1							HTR1								HTR1
0xb0	ADC_LTR2								LTR2								LTR2
0xb4	ADC_HTR2								HTR2								HTR2
0xb8	ADC_LTR3								LTR3								LTR3
0xbc	ADC_HTR3								HTR3								HTR3
0xc0	ADC_DIFSEL												DIFSEL				DIFSEL
0xc4	ADC_CALFACT							CAPTURE_COEF	LATCH_COEF							VALIDITY	I_APB_DATA								I_APB_ADDR
0xc8	ADC_CALFACT2	CALFACT															CALFACT

Toggle registers

ADC_ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDY r			AWD3 rw	AWD2 rw	AWD1 rw	JEOS rw	JEOC rw	OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

LDORDY

Bit 12: LDORDY.

ADC_IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						AWD3IE rw	AWD2IE rw	AWD1IE rw	JEOSIE rw	JEOCIE rw	OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

ADC_CR

ADC control register

Offset: 0x8, size: 32, reset: 0x20000000, access: Unspecified

7/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL r		DEEPPWD rw	ADVREGEN rw	CALINDEX rw											ADCALLIN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										JADSTP r	ADSTP r	JADSTART r	ADSTART r	ADDIS r	ADEN r

Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADCALLIN

Bit 16: ADCALLIN.

CALINDEX

Bits 24-27: CALINDEX.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCAL

Bit 31: ADCAL.

ADC_CFGR1

ADC configuration register

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	AWD1CH rw					JAUTO rw	JAWD1EN rw	AWD1EN rw	AWD1SGL rw		JDISCEN rw	DISCNUM rw			DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	AUTDLY rw	CONT rw	OVRMOD rw	EXTEN rw		EXTSEL rw						RES rw		DMNGT rw

Toggle fields

DMNGT

Bits 0-1: DMNGT.

RES

Bits 2-3: RES.

EXTSEL

Bits 5-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWD1CH

Bits 26-30: AWD1CH.

ADC_CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LSHIFT rw				LFTRIG rw		OSR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPTRIG rw	SWTRIG rw	BULB rw			ROVSM rw	TROVS rw	OVSS rw							JOVSE rw	ROVSE rw

Toggle fields

ROVSE

Bit 0: ROVSE.

JOVSE

Bit 1: JOVSE.

OVSS

Bits 5-8: OVSS.

TROVS

Bit 9: TROVS.

ROVSM

Bit 10: ROVSM.

BULB

Bit 13: BULB.

SWTRIG

Bit 14: SWTRIG.

SMPTRIG

Bit 15: SMPTRIG.

OSR

Bits 16-25: OSR.

LFTRIG

Bit 27: LFTRIG.

LSHIFT

Bits 28-31: LSHIFT.

ADC_SMPR1

ADC sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP9 rw			SMP8 rw			SMP7 rw			SMP6 rw			SMP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5 rw	SMP4 rw			SMP3 rw			SMP2 rw			SMP1 rw			SMP0 rw

Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

ADC_SMPR2

ADC sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP19 rw			SMP18 rw			SMP17 rw			SMP16 rw			SMP15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15 rw	SMP14 rw			SMP13 rw			SMP12 rw			SMP11 rw			SMP10 rw

Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

SMP19

Bits 27-29: SMP19.

ADC_PCSEL

ADC channel preselection register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												PCSEL19 rw	PCSEL18 rw	PCSEL17 rw	PCSEL16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCSEL15 rw	PCSEL14 rw	PCSEL13 rw	PCSEL12 rw	PCSEL11 rw	PCSEL10 rw	PCSEL9 rw	PCSEL8 rw	PCSEL7 rw	PCSEL6 rw	PCSEL5 rw	PCSEL4 rw	PCSEL3 rw	PCSEL2 rw	PCSEL1 rw	PCSEL0 rw

Toggle fields

PCSEL0

Bit 0: PCSEL0.

PCSEL1

Bit 1: PCSEL1.

PCSEL2

Bit 2: PCSEL2.

PCSEL3

Bit 3: PCSEL3.

PCSEL4

Bit 4: PCSEL4.

PCSEL5

Bit 5: PCSEL5.

PCSEL6

Bit 6: PCSEL6.

PCSEL7

Bit 7: PCSEL7.

PCSEL8

Bit 8: PCSEL8.

PCSEL9

Bit 9: PCSEL9.

PCSEL10

Bit 10: PCSEL10.

PCSEL11

Bit 11: PCSEL11.

PCSEL12

Bit 12: PCSEL12.

PCSEL13

Bit 13: PCSEL13.

PCSEL14

Bit 14: PCSEL14.

PCSEL15

Bit 15: PCSEL15.

PCSEL16

Bit 16: PCSEL16.

PCSEL17

Bit 17: PCSEL17.

PCSEL18

Bit 18: PCSEL18.

PCSEL19

Bit 19: PCSEL19.

ADC_SQR1

ADC regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ4 rw						SQ3 rw						SQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ2 rw					SQ1 rw							L rw

Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

ADC_SQR2

ADC regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ9 rw						SQ8 rw						SQ7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ7 rw					SQ6 rw						SQ5 rw

Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

ADC_SQR3

ADC regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ14 rw						SQ13 rw						SQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ12 rw					SQ11 rw						SQ10 rw

Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

ADC_SQR4

ADC regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SQ16 rw						SQ15 rw

Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

ADC_DR

ADC regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA r

Toggle fields

RDATA

Bits 0-31: RDATA.

ADC_JSQR

ADC injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JSQ4 rw						JSQ3 rw						JSQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ2 rw		JSQ1 rw					JEXTEN rw		JEXTSEL rw					JL rw

Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-6: JEXTSEL.

JEXTEN

Bits 7-8: JEXTEN.

JSQ1

Bits 9-13: JSQ1.

JSQ2

Bits 15-19: JSQ2.

JSQ3

Bits 21-25: JSQ3.

JSQ4

Bits 27-31: JSQ4.

ADC_OFR1

ADC offset register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_OFR2

ADC offset register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_OFR3

ADC offset register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_OFR4

ADC offset register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_GCOMP

ADC gain compensation register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GCOMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		GCOMPCOEFF rw

Toggle fields

GCOMPCOEFF

Bits 0-13: GCOMPCOEFF.

GCOMP

Bit 31: GCOMP.

ADC_JDR1

ADC injected data register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_JDR2

ADC injected data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_JDR3

ADC injected data register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_JDR4

ADC injected data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AWD2CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH rw

Toggle fields

AWD2CH

Bits 0-19: AWD2CH.

ADC_AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AWD3CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH rw

Toggle fields

AWD3CH

Bits 0-19: AWD3CH.

ADC_LTR1

ADC watchdog threshold register 1

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							LTR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LTR1 rw

Toggle fields

LTR1

Bits 0-24: LTR1.

ADC_HTR1

ADC watchdog threshold register 1

Offset: 0xac, size: 32, reset: 0x01FFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AWDFILT1 rw							HTR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HTR1 rw

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CAPTURE_COEF rw	LATCH_COEF rw								VALIDITY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I_APB_DATA r								I_APB_ADDR r

Toggle fields

I_APB_ADDR

Bits 0-7: I_APB_ADDR.

I_APB_DATA

Bits 8-15: I_APB_DATA.

VALIDITY

Bit 16: VALIDITY.

LATCH_COEF

Bit 24: LATCH_COEF.

CAPTURE_COEF

Bit 25: CAPTURE_COEF.

ADC_CALFACT2

ADC calibration factor register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALFACT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALFACT rw

Toggle fields

CALFACT

Bits 0-31: CALFACT.

ADC12_Common

0x42028300: Analog-to-Digital Converter

25/32 fields covered.

Toggle register map

Offset	Name	31	28	25	24	23	22	21	20	19	18	17	16	15	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ADC12_CSR		LDORDY_SLV	AWD3_SLV	AWD2_SLV	AWD1_SLV	JEOS_SLV	JEOC_SLV	OVR_SLV	EOS_SLV	EOC_SLV	EOSMP_SLV	ADRDY_SLV		LDORDY_MST		AWD3_MST	AWD2_MST	AWD1_MST	JEOS_MST	JEOC_MST	OVR_MST	EOS_MST	EOC_MST	EOSMP_MST	ADRDY_MST
0x8	ADC12_CCR				VBATEN	VSENSESEL	VREFEN	PRESC						DAMDF		DELAY						DUAL
0xc	ADC12_CDR	RDATA_SLV												RDATA_MST
0x10	ADC12_CDR2	RDATA_ALT												RDATA_ALT

Toggle registers

ADC12_CSR

ADC common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			LDORDY_SLV r			AWD3_SLV r	AWD2_SLV r	AWD1_SLV r	JEOS_SLV r	JEOC_SLV r	OVR_SLV r	EOS_SLV r	EOC_SLV r	EOSMP_SLV r	ADRDY_SLV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDY_MST r			AWD3_MST r	AWD2_MST r	AWD1_MST r	JEOS_MST r	JEOC_MST r	OVR_MST r	EOS_MST r	EOC_MST r	EOSMP_MST r	ADRDY_MST r

Toggle fields

ADRDY_MST

Bit 0: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register..

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register..

EOC_MST

Bit 2: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register..

EOS_MST

Bit 3: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register..

OVR_MST

Bit 4: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register..

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register..

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register..

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register..

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register..

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register..

LDORDY_MST

Bit 12: ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register..

ADRDY_SLV

Bit 16: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register..

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register..

EOC_SLV

Bit 18: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register..

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register..

OVR_SLV

Bit 20: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register..

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register..

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register..

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register..

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register..

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register..

LDORDY_SLV

Bit 28: ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register..

ADC12_CCR

ADC_CCR system control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							VBATEN rw	VSENSESEL rw	VREFEN rw	PRESC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DAMDF rw				DELAY rw							DUAL rw

Toggle fields

DUAL

Bits 0-4: Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

DELAY

Bits 8-11: Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

DAMDF

Bits 14-15: Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register ADC12_CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

PRESC

Bits 18-21: ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VREFEN

Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VSENSESEL

Bit 23: Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VBATEN

Bit 24: VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

ADC12_CDR

ADC common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA_SLV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_MST r

Toggle fields

RDATA_MST

Bits 0-15: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF[1:0] = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]..

RDATA_SLV

Bits 16-31: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)).

ADC12_CDR2

ADC common regular data register for 32-bit dual mode

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA_ALT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_ALT r

Toggle fields

RDATA_ALT

Bits 0-31: Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)..

ADC4

0x46021000: ADC4

6/146 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ADC_ISR																				LDORDY	EOCAL		AWD3	AWD2	AWD1			OVR	EOS	EOC	EOSMP	ADRDY
0x4	ADC_IER																				LDORDYIE	EOCALIE		AWD3IE	AWD2IE	AWD1IE			OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	ADC_CR	ADCAL			ADVREGEN																								ADSTP		ADSTART	ADDIS	ADEN
0xc	ADC_CFGR1		AWD1CH							AWD1EN	AWD1SGL	CHSELRMOD					DISCEN		WAIT	CONT	OVRMOD	EXTEN			EXTSEL			ALIGN	SCANDIR	RES		DMACFG	DMAEN
0x10	ADC_CFGR2			LFTRIG																				TOVS	OVSS				OVSR				OVSE
0x14	ADC_SMPR	SMPSEL23	SMPSEL22	SMPSEL21	SMPSEL20	SMPSEL19	SMPSEL18	SMPSEL17	SMPSEL16	SMPSEL15	SMPSEL14	SMPSEL13	SMPSEL12	SMPSEL11	SMPSEL10	SMPSEL9	SMPSEL8	SMPSEL7	SMPSEL6	SMPSEL5	SMPSEL4	SMPSEL3	SMPSEL2	SMPSEL1	SMPSEL0		SMP2				SMP1
0x20	ADC_AWD1TR					HT1																LT1
0x24	ADC_AWD2TR					HT2																LT2
0x28	ADC_CHSELRMOD0									CHSEL								CHSEL
0x28	ADC_CHSELRMOD1	SQ8				SQ7				SQ6				SQ5				SQ4				SQ3				SQ2				SQ1
0x2c	ADC_AWD3TR					HT3																LT3
0x40	ADC_DR																	DATA
0x44	ADC_PWR																													VREFSECSMP	VREFPROT	DPD	AUTOFF
0xa0	ADC_AWD2CR									AWD2CH23	AWD2CH22	AWD2CH21	AWD2CH20	AWD2CH19	AWD2CH18	AWD2CH17	AWD2CH16	AWD2CH15	AWD2CH14	AWD2CH13	AWD2CH12	AWD2CH11	AWD2CH10	AWD2CH9	AWD2CH8	AWD2CH7	AWD2CH6	AWD2CH5	AWD2CH4	AWD2CH3	AWD2CH2	AWD2CH1	AWD2CH0
0xa4	ADC_AWD3CR									AWD3CH23	AWD3CH22	AWD3CH21	AWD3CH20	AWD3CH19	AWD3CH18	AWD3CH17	AWD3CH16	AWD3CH15	AWD3CH14	AWD3CH13	AWD3CH12	AWD3CH11	AWD3CH10	AWD3CH9	AWD3CH8	AWD3CH7	AWD3CH6	AWD3CH5	AWD3CH4	AWD3CH3	AWD3CH2	AWD3CH1	AWD3CH0
0xb4	ADC_CALFACT																										CALFACT
0xd0	ADC_OR																																CHN21SEL
0x308	ADC_CCR								VBATEN	TSEN	VREFEN	PRESC

Toggle registers

ADC_ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDY rw	EOCAL rw		AWD3 rw	AWD2 rw	AWD1 rw			OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

EOCAL

Bit 11: EOCAL.

LDORDY

Bit 12: LDORDY.

ADC_IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDYIE rw	EOCALIE rw		AWD3IE rw	AWD2IE rw	AWD1IE rw			OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

EOCALIE

Bit 11: EOCALIE.

LDORDYIE

Bit 12: LDORDYIE.

ADC_CR

ADC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL r			ADVREGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ADSTP r		ADSTART r	ADDIS r	ADEN r

Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

ADSTP

Bit 4: ADSTP.

ADVREGEN

Bit 28: ADVREGEN.

ADCAL

Bit 31: ADCAL.

ADC_CFGR1

ADC configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	AWD1CH rw							AWD1EN rw	AWD1SGL rw	CHSELRMOD rw					DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WAIT rw	CONT rw	OVRMOD rw	EXTEN rw			EXTSEL rw			ALIGN rw	SCANDIR rw	RES rw		DMACFG rw	DMAEN rw

Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 2-3: RES.

SCANDIR

Bit 4: SCANDIR.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-8: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

WAIT

Bit 14: WAIT.

DISCEN

Bit 16: DISCEN.

CHSELRMOD

Bit 21: CHSELRMOD.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

AWD1CH

Bits 26-30: AWD1CH.

ADC_CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		LFTRIG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TOVS rw	OVSS rw				OVSR rw				OVSE rw

Toggle fields

OVSE

Bit 0: OVSE.

OVSR

Bits 2-4: OVSR.

OVSS

Bits 5-8: OVSS.

TOVS

Bit 9: TOVS.

LFTRIG

Bit 29: LFTRIG.

ADC_SMPR

ADC sample time register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SMPSEL23 rw	SMPSEL22 rw	SMPSEL21 rw	SMPSEL20 rw	SMPSEL19 rw	SMPSEL18 rw	SMPSEL17 rw	SMPSEL16 rw	SMPSEL15 rw	SMPSEL14 rw	SMPSEL13 rw	SMPSEL12 rw	SMPSEL11 rw	SMPSEL10 rw	SMPSEL9 rw	SMPSEL8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPSEL7 rw	SMPSEL6 rw	SMPSEL5 rw	SMPSEL4 rw	SMPSEL3 rw	SMPSEL2 rw	SMPSEL1 rw	SMPSEL0 rw		SMP2 rw				SMP1 rw

Toggle fields

SMP1

Bits 0-2: SMP1.

SMP2

Bits 4-6: SMP2.

SMPSEL0

Bit 8: SMPSEL0.

SMPSEL1

Bit 9: SMPSEL1.

SMPSEL2

Bit 10: SMPSEL2.

SMPSEL3

Bit 11: SMPSEL3.

SMPSEL4

Bit 12: SMPSEL4.

SMPSEL5

Bit 13: SMPSEL5.

SMPSEL6

Bit 14: SMPSEL6.

SMPSEL7

Bit 15: SMPSEL7.

SMPSEL8

Bit 16: SMPSEL8.

SMPSEL9

Bit 17: SMPSEL9.

SMPSEL10

Bit 18: SMPSEL10.

SMPSEL11

Bit 19: SMPSEL11.

SMPSEL12

Bit 20: SMPSEL12.

SMPSEL13

Bit 21: SMPSEL13.

SMPSEL14

Bit 22: SMPSEL14.

SMPSEL15

Bit 23: SMPSEL15.

SMPSEL16

Bit 24: SMPSEL16.

SMPSEL17

Bit 25: SMPSEL17.

SMPSEL18

Bit 26: SMPSEL18.

SMPSEL19

Bit 27: SMPSEL19.

SMPSEL20

Bit 28: SMPSEL20.

SMPSEL21

Bit 29: SMPSEL21.

SMPSEL22

Bit 30: SMPSEL22.

SMPSEL23

Bit 31: SMPSEL23.

ADC_AWD1TR

ADC watchdog threshold register

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT1 rw

Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

ADC_AWD2TR

ADC watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT2 rw

Toggle fields

LT2

Bits 0-11: LT2.

HT2

Bits 16-27: HT2.

ADC_CHSELRMOD0

ADC channel selection register [alternate]

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CHSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CHSEL rw

Toggle fields

CHSEL

Bits 0-23: CHSEL.

ADC_CHSELRMOD1

ADC channel selection register [alternate]

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SQ8 rw				SQ7 rw				SQ6 rw				SQ5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4 rw				SQ3 rw				SQ2 rw				SQ1 rw

Toggle fields

SQ1

Bits 0-3: SQ1.

SQ2

Bits 4-7: SQ2.

SQ3

Bits 8-11: SQ3.

SQ4

Bits 12-15: SQ4.

SQ5

Bits 16-19: SQ5.

SQ6

Bits 20-23: SQ6.

SQ7

Bits 24-27: SQ7.

SQ8

Bits 28-31: SQ8.

ADC_AWD3TR

ADC watchdog threshold register

Offset: 0x2c, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT3 rw

Toggle fields

LT3

Bits 0-11: LT3.

HT3

Bits 16-27: HT3.

ADC_DR

ADC data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA r

Toggle fields

DATA

Bits 0-15: DATA.

ADC_PWR

ADC data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VREFSECSMP rw	VREFPROT rw	DPD rw	AUTOFF rw

Toggle fields

AUTOFF

Bit 0: AUTOFF.

DPD

Bit 1: DPD.

VREFPROT

Bit 2: VREFPROT.

VREFSECSMP

Bit 3: VREFSECSMP.

ADC_AWD2CR

ADC Analog Watchdog 2 Configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								AWD2CH23 rw	AWD2CH22 rw	AWD2CH21 rw	AWD2CH20 rw	AWD2CH19 rw	AWD2CH18 rw	AWD2CH17 rw	AWD2CH16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH15 rw	AWD2CH14 rw	AWD2CH13 rw	AWD2CH12 rw	AWD2CH11 rw	AWD2CH10 rw	AWD2CH9 rw	AWD2CH8 rw	AWD2CH7 rw	AWD2CH6 rw	AWD2CH5 rw	AWD2CH4 rw	AWD2CH3 rw	AWD2CH2 rw	AWD2CH1 rw	AWD2CH0 rw

Toggle fields

AWD2CH0

Bit 0: AWD2CH0.

AWD2CH1

Bit 1: AWD2CH1.

AWD2CH2

Bit 2: AWD2CH2.

AWD2CH3

Bit 3: AWD2CH3.

AWD2CH4

Bit 4: AWD2CH4.

AWD2CH5

Bit 5: AWD2CH5.

AWD2CH6

Bit 6: AWD2CH6.

AWD2CH7

Bit 7: AWD2CH7.

AWD2CH8

Bit 8: AWD2CH8.

AWD2CH9

Bit 9: AWD2CH9.

AWD2CH10

Bit 10: AWD2CH10.

AWD2CH11

Bit 11: AWD2CH11.

AWD2CH12

Bit 12: AWD2CH12.

AWD2CH13

Bit 13: AWD2CH13.

AWD2CH14

Bit 14: AWD2CH14.

AWD2CH15

Bit 15: AWD2CH15.

AWD2CH16

Bit 16: AWD2CH16.

AWD2CH17

Bit 17: AWD2CH17.

AWD2CH18

Bit 18: AWD2CH18.

AWD2CH19

Bit 19: AWD2CH19.

AWD2CH20

Bit 20: AWD2CH20.

AWD2CH21

Bit 21: AWD2CH21.

AWD2CH22

Bit 22: AWD2CH22.

AWD2CH23

Bit 23: AWD2CH23.

ADC_AWD3CR

ADC Analog Watchdog 3 Configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								AWD3CH23 rw	AWD3CH22 rw	AWD3CH21 rw	AWD3CH20 rw	AWD3CH19 rw	AWD3CH18 rw	AWD3CH17 rw	AWD3CH16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH15 rw	AWD3CH14 rw	AWD3CH13 rw	AWD3CH12 rw	AWD3CH11 rw	AWD3CH10 rw	AWD3CH9 rw	AWD3CH8 rw	AWD3CH7 rw	AWD3CH6 rw	AWD3CH5 rw	AWD3CH4 rw	AWD3CH3 rw	AWD3CH2 rw	AWD3CH1 rw	AWD3CH0 rw

Toggle fields

AWD3CH0

Bit 0: AWD3CH0.

AWD3CH1

Bit 1: AWD3CH1.

AWD3CH2

Bit 2: AWD3CH2.

AWD3CH3

Bit 3: AWD3CH3.

AWD3CH4

Bit 4: AWD3CH4.

AWD3CH5

Bit 5: AWD3CH5.

AWD3CH6

Bit 6: AWD3CH6.

AWD3CH7

Bit 7: AWD3CH7.

AWD3CH8

Bit 8: AWD3CH8.

AWD3CH9

Bit 9: AWD3CH9.

AWD3CH10

Bit 10: AWD3CH10.

AWD3CH11

Bit 11: AWD3CH11.

AWD3CH12

Bit 12: AWD3CH12.

AWD3CH13

Bit 13: AWD3CH13.

AWD3CH14

Bit 14: AWD3CH14.

AWD3CH15

Bit 15: AWD3CH15.

AWD3CH16

Bit 16: AWD3CH16.

AWD3CH17

Bit 17: AWD3CH17.

AWD3CH18

Bit 18: AWD3CH18.

AWD3CH19

Bit 19: AWD3CH19.

AWD3CH20

Bit 20: AWD3CH20.

AWD3CH21

Bit 21: AWD3CH21.

AWD3CH22

Bit 22: AWD3CH22.

AWD3CH23

Bit 23: AWD3CH23.

ADC_CALFACT

ADC Calibration factor

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CALFACT rw

Toggle fields

CALFACT

Bits 0-6: CALFACT.

ADC_OR

ADC option register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CHN21SEL rw

Toggle fields

CHN21SEL

Bit 0: CHN21SEL.

ADC_CCR

ADC common configuration register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							VBATEN rw	TSEN rw	VREFEN rw	PRESC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRESC

Bits 18-21: PRESC.

VREFEN

Bit 22: VREFEN.

TSEN

Bit 23: TSEN.

VBATEN

Bit 24: VBATEN.

ADF1

0x46024000: ADF1

7/68 fields covered.

Toggle register map

Offset	Name	31	30	28	27	25	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ADF_GCR																							TRGO
0x4	ADF_CKGCR	CKGACTIVE	PROCDIV				CCKDIV		TRGSRC							TRGSENS		CCK1DIR	CCK0DIR	CKGMOD		CCK1EN	CCK0EN	CKGDEN
0x80	ADF_SITF0CR	SITFACTIVE										STH							SITFMOD			SCKSRC		SITFEN
0x84	ADF_BSMX0CR	BSMXACTIVE																		BSSEL
0x88	ADF_DFLT0CR	DFLTACTIVE	DFLTRUN		NBDIS				TRGSRC									ACQMOD				FTH	DMAEN	DFLTEN
0x8c	ADF_DFLT0CICR					SCALE		MCICD	MCICD									CICMOD					DATSRC
0x90	ADF_DFLT0RSFR														HPFC		HPFBYP			RSFLTD				RSFLTBYP
0xa4	ADF_DLY0CR	SKPBF																SKPDLY
0xac	ADF_DFLT0IER										SDLVLIE	SDDETIE	RFOVRIE	CKABIE	SATIE								DOVRIE	FTHIE
0xb0	ADF_DFLT0ISR										SDLVLF	SDDETF	RFOVRF	CKABF	SATF						RXNEF		DOVRF	FTHF
0xb8	ADF_SADCR	SADACTIVE									SADMOD			FRSIZE			HYSTEN		SADST		DETCFG	DATCAP		SADEN
0xbc	ADF_SADCFGR			ANMIN						HGOVR				LFRNB				ANSLP			SNTHR
0xc0	ADF_SADSDLVR									SDLVL
0xc4	ADF_SADANLVR									ANLVL
0xf0	ADF_DFLT0DR	DR							DR

Toggle registers

ADF_GCR

ADF Global Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TRGO rw

Toggle fields

TRGO

Bit 0: Trigger output control Set by software and reset by.

ADF_CKGCR

ADF clock generator control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKGACTIVE rw	PROCDIV rw											CCKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		CCK1DIR rw	CCK0DIR rw	CKGMOD rw		CCK1EN rw	CCK0EN rw	CKGDEN rw

Toggle fields

CKGDEN

Bit 0: CKGEN dividers enable.

CCK0EN

Bit 1: ADF_CCK0 clock enable.

CCK1EN

Bit 2: ADF_CCK1 clock enable.

CKGMOD

Bit 4: Clock generator mode.

CCK0DIR

Bit 5: ADF_CCK0 direction.

CCK1DIR

Bit 6: ADF_CCK1 direction.

TRGSENS

Bit 8: CKGEN trigger sensitivity selection.

TRGSRC

Bits 12-15: Digital filter trigger signal selection.

CCKDIV

Bits 16-19: Divider to control the ADF_CCK clock.

PROCDIV

Bits 24-30: Divider to control the serial interface clock.

CKGACTIVE

Bit 31: Clock generator active flag.

ADF_SITF0CR

ADF serial interface control register 0

Offset: 0x80, size: 32, reset: 0x00001F00, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: SITFEN.

SCKSRC

Bits 1-2: SCKSRC.

SITFMOD

Bits 4-5: SITFMOD.

STH

Bits 8-12: STH.

SITFACTIVE

Bit 31: SITFACTIVE.

ADF_BSMX0CR

ADF bitstream matrix control register 0

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream selection.

BSMXACTIVE

Bit 31: BSMX active flag.

ADF_DFLT0CR

ADF digital filter control register 0

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE rw	DFLTRUN rw			NBDIS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw									ACQMOD rw				FTH rw	DMAEN rw	DFLTEN rw

Toggle fields

DFLTEN

Bit 0: DFLT0 enable.

DMAEN

Bit 1: DMA requests enable.

FTH

Bit 2: RXFIFO threshold selection.

ACQMOD

Bits 4-6: DFLT0 trigger mode.

TRGSRC

Bits 12-15: DFLT0 trigger signal selection.

NBDIS

Bits 20-27: Number of samples to be discarded.

DFLTRUN

Bit 30: DFLT0 run status flag.

DFLTACTIVE

Bit 31: DFLT0 active flag.

ADF_DFLT0CICR

ADF digital filer configuration register 0

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter.

CICMOD

Bits 4-6: Select the CIC order.

MCICD

Bits 8-16: CIC decimation ratio selection.

SCALE

Bits 20-25: Scaling factor selection.

ADF_DFLT0RSFR

ADF reshape filter configuration register 0

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass.

RSFLTD

Bit 4: Reshaper filter decimation ratio.

HPFBYP

Bit 7: High-pass filter bypass.

HPFC

Bits 8-9: High-pass filter cut-off frequency.

ADF_DLY0CR

ADF delay control register 0

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream.

SKPBF

Bit 31: Skip busy flag.

ADF_DFLT0IER

ADF DFLT0 interrupt enable register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SDLVLIE rw	SDDETIE rw	RFOVRIE rw	CKABIE rw	SATIE rw								DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable.

DOVRIE

Bit 1: Data overflow interrupt enable.

SATIE

Bit 9: Saturation detection interrupt enable.

CKABIE

Bit 10: Clock absence detection interrupt enable.

RFOVRIE

Bit 11: Reshape filter overrun interrupt enable.

SDDETIE

Bit 12: Sound activity detection interrupt enable.

SDLVLIE

Bit 13: SAD sound-level value ready enable.

ADF_DFLT0ISR

ADF DFLT0 interrupt status register 0

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SDLVLF rw	SDDETF rw	RFOVRF rw	CKABF rw	SATF rw						RXNEF r		DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag.

DOVRF

Bit 1: Data overflow flag.

RXNEF

Bit 3: RXFIFO not empty flag.

SATF

Bit 9: Saturation detection flag.

CKABF

Bit 10: Clock absence detection flag.

RFOVRF

Bit 11: Reshape filter overrun detection flag.

SDDETF

Bit 12: Sound activity detection flag.

SDLVLF

Bit 13: Sound level value ready flag.

ADF_SADCR

ADF SAD control register

Offset: 0xb8, size: 32, reset: 0x00000000, access: Unspecified

2/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SADACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SADMOD rw			FRSIZE rw			HYSTEN rw		SADST r		DETCFG rw	DATCAP rw		SADEN rw

Toggle fields

SADEN

Bit 0: Sound activity detector enable.

DATCAP

Bits 1-2: Data capture mode.

DETCFG

Bit 3: Sound trigger event configuration.

SADST

Bits 4-5: SAD state.

HYSTEN

Bit 7: Hysteresis enable.

FRSIZE

Bits 8-10: Frame size.

SADMOD

Bits 12-13: SAD working mode.

SADACTIVE

Bit 31: SAD Active flag.

ADF_SADCFGR

ADF SAD configuration register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ANMIN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	HGOVR rw				LFRNB rw				ANSLP rw			SNTHR rw

Toggle fields

SNTHR

Bits 0-3: SNTHR.

ANSLP

Bits 4-6: ANSLP.

LFRNB

Bits 8-10: LFRNB.

HGOVR

Bits 12-14: Hangover time window.

ANMIN

Bits 16-28: ANMIN.

ADF_SADSDLVR

ADF SAD sound level register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SDLVL r

Toggle fields

SDLVL

Bits 0-14: SDLVL.

ADF_SADANLVR

ADF SAD ambient noise level register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	ANLVL r

Toggle fields

ANLVL

Bits 0-14: ANLVL.

ADF_DFLT0DR

ADF digital filter data register 0

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: DR.

COMP

0x46005400: Comparator

2/22 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	COMP1_CSR	COMP1_LOCK	COMP1_VALUE						COMP1_BLANKSEL					COMP1_PWRMODE		COMP1_HYST		COMP1_POLARITY	COMP1_WINOUT			COMP1_WINMODE		COMP1_INPSEL		COMP1_INMSEL							COMP1_EN
0x4	COMP2_CSR	COM2_LOCK	COM2_VALUE						COM2_BLANKSEL					COM2_PWRMODE		COM2_HYST		COM2_POLARITY	COM2_WINOUT			COM2_WINMODE		COM2_INPSEL		COM2_INMSEL							COM2_EN

Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP1_LOCK rw	COMP1_VALUE r						COMP1_BLANKSEL rw					COMP1_PWRMODE rw		COMP1_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP1_POLARITY rw	COMP1_WINOUT rw			COMP1_WINMODE rw		COMP1_INPSEL rw		COMP1_INMSEL rw							COMP1_EN rw

Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_INMSEL

Bits 4-7: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bits 8-9: Comparator1 input plus selection bit.

COMP1_WINMODE

Bit 11: COMP1_WINMODE.

COMP1_WINOUT

Bit 14: COMP1_WINOUT.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_PWRMODE

Bits 18-19: COMP1_PWRMODE.

COMP1_BLANKSEL

Bits 20-24: COMP1_BLANKSEL.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COM2_LOCK rw	COM2_VALUE r						COM2_BLANKSEL rw					COM2_PWRMODE rw		COM2_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COM2_POLARITY rw	COM2_WINOUT rw			COM2_WINMODE rw		COM2_INPSEL rw		COM2_INMSEL rw							COM2_EN rw

Toggle fields

COM2_EN

Bit 0: Comparator 2 enable bit.

COM2_INMSEL

Bits 4-7: Comparator 2 Input Minus connection configuration bit.

COM2_INPSEL

Bits 8-9: Comparator 2 input plus selection bit.

COM2_WINMODE

Bit 11: COM2_WINMODE.

COM2_WINOUT

Bit 14: COM2_WINOUT.

COM2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COM2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COM2_PWRMODE

Bits 18-19: COM2_PWRMODE.

COM2_BLANKSEL

Bits 20-24: COM2_BLANKSEL.

COM2_VALUE

Bit 30: Comparator 2 output status bit.

COM2_LOCK

Bit 31: COMP2_CSR register lock bit.

CORDIC

0x40021000: CORDIC Co-processor

2/13 fields covered.

Toggle register map

Offset	Name	31	22	21	20	19	18	17	16	15	10	7	3
0x0	CSR	RRDY	ARGSIZE	RESSIZE	NARGS	NRES	DMAWEN	DMAREN	IEN		SCALE	PRECISION	FUNC
0x4	WDATA	ARG								ARG
0x8	RDATA	RES								RES

Toggle registers

CSR

CORDIC Control Status register

Offset: 0x0, size: 32, reset: 0x00000050, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RRDY r									ARGSIZE rw	RESSIZE rw	NARGS rw	NRES rw	DMAWEN rw	DMAREN rw	IEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SCALE rw			PRECISION rw				FUNC rw

Toggle fields

FUNC

Bits 0-3: Function.

PRECISION

Bits 4-7: Precision required (number of iterations).

SCALE

Bits 8-10: Scaling factor.

IEN

Bit 16: Enable interrupt.

DMAREN

Bit 17: Enable DMA read channel.

DMAWEN

Bit 18: Enable DMA write channel.

NRES

Bit 19: Number of results in the CORDIC_RDATA register.

NARGS

Bit 20: Number of arguments expected by the CORDIC_WDATA register.

RESSIZE

Bit 21: Width of output data.

ARGSIZE

Bit 22: Width of input data.

RRDY

Bit 31: Result ready flag.

WDATA

FMAC Write Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARG w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARG w

Toggle fields

ARG

Bits 0-31: Function input arguments.

RDATA

FMAC Read Data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES r

Toggle fields

RES

Bits 0-31: Function result.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	CRC_INIT	CRC_INIT
0x14	POL	POL	POL

Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle fields

IDR

Bits 0-31: General-purpose 8-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT rw

Toggle fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle fields

POL

Bits 0-31: Programmable polynomial.

CRS

0x40006000: Clock recovery system

9/26 fields covered.

Toggle register map

Offset	Name	31	29	26	23	15	14	10	9	8	7	6	5	3	2	1	0
0x0	CR						TRIM				SWSYNC	AUTOTRIMEN	CEN	ESYNCIE	ERRIE	SYNCWARNIE	SYNCOKIE
0x4	CFGR	SYNCPOL	SYNCSRC	SYNCDIV	FELIM	RELOAD
0x8	ISR	FECAP				FEDIR		TRIMOVF	SYNCMISS	SYNCERR				ESYNCF	ERRF	SYNCWARNF	SYNCOKF
0xc	ICR													ESYNCC	ERRC	SYNCWARNC	SYNCOKC

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00004000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TRIM rw							SWSYNC rw	AUTOTRIMEN rw	CEN rw		ESYNCIE rw	ERRIE rw	SYNCWARNIE rw	SYNCOKIE rw

Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-14: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SYNCPOL rw		SYNCSRC rw			SYNCDIV rw			FELIM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FECAP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FEDIR r					TRIMOVF r	SYNCMISS r	SYNCERR r					ESYNCF r	ERRF r	SYNCWARNF r	SYNCOKF r

Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ESYNCC rw	ERRC rw	SYNCWARNC rw	SYNCOKC rw

Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DAC1

0x46021800: Digital-to-analog converter

12/66 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	25	24	23	22	21	20	18	17	16	15	14	13	12	11	9	8	7	5	4	2	1	0
0x0	DAC_CR		CEN2	DMAUDRIE2	DMAEN2	MAMP2			WAVE2		TSEL2			TEN2	EN2		CEN1	DMAUDRIE1	DMAEN1	MAMP1			WAVE1	TSEL1			TEN1	EN1
0x4	DAC_SWTRGR																										SWTRIG2	SWTRIG1
0x8	DAC_DHR12R1					DACC1DHRB														DACC1DHR
0xc	DAC_DHR12L1	DACC1DHRB														DACC1DHR
0x10	DAC_DHR8R1															DACC1DHRB							DACC1DHR
0x14	DAC_DHR12R2					DACC2DHRB														DACC2DHR
0x18	DAC_DHR12L2	DACC2DHRB														DACC2DHR
0x1c	DAC_DHR8R2															DACC2DHRB							DACC2DHR
0x20	DAC_DHR12RD					DACC2DHR														DACC1DHR
0x24	DAC_DHR12LD	DACC2DHR														DACC1DHR
0x28	DAC_DHR8RD															DACC2DHR							DACC1DHR
0x2c	DAC_DOR1					DACC1DORB														DACC1DOR
0x30	DAC_DOR2					DACC2DORB														DACC2DOR
0x34	DAC_SR	BWST2	CAL_FLAG2	DMAUDR2	DORSTAT2	DAC2RDY										BWST1	CAL_FLAG1	DMAUDR1	DORSTAT1	DAC1RDY
0x38	DAC_CCR											OTRIM2													OTRIM1
0x3c	DAC_MCR						SINFORMAT2	DMADOUBLE2					MODE2			HFSEL					SINFORMAT1	DMADOUBLE1				MODE1
0x40	DAC_SHSR1																				TSAMPLE1
0x44	DAC_SHSR2																				TSAMPLE2
0x48	DAC_SHHR						THOLD2														THOLD1
0x4c	DAC_SHRR								TREFRESH2														TREFRESH1
0x54	DAC_AUTOCR									AUTOMODE

Toggle registers

DAC_CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CEN2 rw	DMAUDRIE2 rw	DMAEN2 rw	MAMP2 rw				WAVE2 rw		TSEL2 rw				TEN2 rw	EN2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CEN1 rw	DMAUDRIE1 rw	DMAEN1 rw	MAMP1 rw				WAVE1 rw		TSEL1 rw				TEN1 rw	EN1 rw

Toggle fields

EN1

Bit 0: DAC channel1 enable.

TEN1

Bit 1: DAC channel1 trigger enable.

TSEL1

Bits 2-5: DAC channel1 trigger selection.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

CEN1

Bit 14: DAC channel1 calibration enable.

EN2

Bit 16: DAC channel2 enable.

TEN2

Bit 17: DAC channel2 trigger enable.

TSEL2

Bits 18-21: DAC channel2 trigger selection.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

DMAEN2

Bit 28: DAC channel2 DMA enable.

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

CEN2

Bit 30: DAC channel2 calibration enable.

DAC_SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SWTRIG2 w	SWTRIG1 w

Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

SWTRIG2

Bit 1: DAC channel2 software trigger.

DAC_DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC1DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC1DHRB

Bits 16-27: DAC channel1 12-bit right-aligned data B.

DAC_DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC1DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC1DHRB

Bits 20-31: DAC channel1 12-bit left-aligned data B.

DAC_DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHRB rw								DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC1DHRB

Bits 8-15: DAC channel1 8-bit right-aligned Sdata.

DAC_DHR12R2

DAC channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DHR rw

Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

DACC2DHRB

Bits 16-27: DAC channel2 12-bit right-aligned data.

DAC_DHR12L2

DAC channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC2DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw

Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

DACC2DHRB

Bits 20-31: DAC channel2 12-bit left-aligned data B.

DAC_DHR8R2

DAC channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHRB rw								DACC2DHR rw

Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

DACC2DHRB

Bits 8-15: DAC channel2 8-bit right-aligned data.

DAC_DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

DAC_DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

DAC_DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw								DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

DAC_DOR1

DAC channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC1DORB r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DOR r

Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DACC1DORB

Bits 16-27: DAC channel1 data output.

DAC_DOR2

DAC channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DORB r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DOR r

Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

DACC2DORB

Bits 16-27: DAC channel2 data output.

DAC_SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

8/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BWST2 r	CAL_FLAG2 r	DMAUDR2 rw	DORSTAT2 r	DAC2RDY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BWST1 r	CAL_FLAG1 r	DMAUDR1 rw	DORSTAT1 r	DAC1RDY r

Toggle fields

DAC1RDY

Bit 11: DAC channel1 ready status bit.

DORSTAT1

Bit 12: DAC channel1 output register status bit.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag.

DAC2RDY

Bit 27: DAC channel 2 ready status bit.

DORSTAT2

Bit 28: DAC channel 2 output register status bit.

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag.

DAC_CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											OTRIM2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											OTRIM1 rw

Toggle fields

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

DAC_MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SINFORMAT2 rw	DMADOUBLE2 rw						MODE2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HFSEL rw						SINFORMAT1 rw	DMADOUBLE1 rw						MODE1 rw

Toggle fields

MODE1

Bits 0-2: DAC Channel 1 mode.

DMADOUBLE1

Bit 8: DAC Channel1 DMA double data mode.

SINFORMAT1

Bit 9: Enable signed format for DAC channel1.

HFSEL

Bits 14-15: High frequency interface mode selection.

MODE2

Bits 16-18: DAC Channel 2 mode.

DMADOUBLE2

Bit 24: DAC Channel2 DMA double data mode.

SINFORMAT2

Bit 25: Enable signed format for DAC channel2.

DAC_SHSR1

DAC Sample and Hold sample time register 1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TSAMPLE1 rw

Toggle fields

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode).

DAC_SHSR2

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TSAMPLE2 rw

Toggle fields

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time (only valid in sample and hold mode).

DAC_SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						THOLD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						THOLD1 rw

Toggle fields

THOLD1

Bits 0-9: DAC Channel 1 hold Time (only valid in sample and hold mode).

THOLD2

Bits 16-25: DAC Channel 2 hold time (only valid in sample and hold mode).

DAC_SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TREFRESH2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TREFRESH1 rw

Toggle fields

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time (only valid in sample and hold mode).

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time (only valid in sample and hold mode).

DAC_AUTOCR

Autonomous mode control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									AUTOMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

AUTOMODE

Bit 22: DAC Autonomous mode.

DBGMCU

0xe0044000: MCU debug component

21/68 fields covered.

Toggle register map

Offset	Name	31	30	22	21	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IDCODE	REV_ID												DEV_ID
0x4	CR																	TRACE_MODE		TRACE_EN	TRACE_IOEN		DBG_STANDBY	DBG_STOP
0x8	APB1LFZR			DBG_I2C2_STOP	DBG_I2C1_STOP								DBG_IWDG_STOP	DBG_WWDG_STOP						DBG_TIM7_STOP	DBG_TIM6_STOP	DBG_TIM5_STOP	DBG_TIM4_STOP	DBG_TIM3_STOP	DBG_TIM2_STOP
0xc	APB1HFZR																			DBG_LPTIM2_STOP				DBG_I2C4_STOP
0x10	APB2FZR						DBG_TIM17_STOP	DBG_TIM16_STOP	DBG_TIM15_STOP			DBG_TIM8_STOP		DBG_TIM1_STOP
0x14	APB3FZR		DBG_RTC_STOP			DBG_LPTIM4_STOP	DBG_LPTIM3_STOP	DBG_LPTIM1_STOP							DBG_I2C3_STOP
0x20	AHB1FZR									DBG_GPDMA15_STOP	DBG_GPDMA14_STOP	DBG_GPDMA13_STOP	DBG_GPDMA12_STOP	DBG_GPDMA11_STOP	DBG_GPDMA10_STOP	DBG_GPDMA9_STOP	DBG_GPDMA8_STOP	DBG_GPDMA7_STOP	DBG_GPDMA6_STOP	DBG_GPDMA5_STOP	DBG_GPDMA4_STOP	DBG_GPDMA3_STOP	DBG_GPDMA2_STOP	DBG_GPDMA1_STOP	DBG_GPDMA0_STOP
0x28	AHB3FZR																					DBG_LPDMA3_STOP	DBG_LPDMA2_STOP	DBG_LPDMA1_STOP	DBG_LPDMA0_STOP
0xfc	SR									AP_LOCKED								AP_PRESENT
0x100	DBGMCU_DBG_AUTH_HOST	AUTH_KEY								AUTH_KEY
0x104	DBG_AUTH_DEVICE									AUTH_ID
0xfd0	PIDR4																	KCOUNT_4				JEP106CON
0xfe0	PIDR0																	PARTNUM
0xfe4	PIDR1																	JEP106ID				PARTNUM
0xfe8	PIDR2																	REVISION				JEDEC	JEP106ID
0xfec	PIDR3																	REVAND				CMOD
0xff0	CIDR0																	PREAMBLE
0xff4	CIDR1																	CLASS				PREAMBLE
0xff8	CIDR2																	PREAMBLE
0xffc	CIDR3																	PREAMBLE

Toggle registers

IDCODE

DBGMCU_IDCODE

Offset: 0x0, size: 32, reset: 0x10016455, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DEV_ID r

Toggle fields

DEV_ID

Bits 0-11: Device dentification.

REV_ID

Bits 16-31: Revision.

CR

Debug MCU configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TRACE_MODE rw		TRACE_EN rw	TRACE_IOEN rw		DBG_STANDBY rw	DBG_STOP rw

Toggle fields

DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby mode.

TRACE_IOEN

Bit 4: Trace pin assignment control.

TRACE_EN

Bit 5: trace port and clock enable.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1LFZR

Debug MCU APB1L peripheral freeze register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									DBG_I2C2_STOP rw	DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw	DBG_WWDG_STOP rw						DBG_TIM7_STOP rw	DBG_TIM6_STOP rw	DBG_TIM5_STOP rw	DBG_TIM4_STOP rw	DBG_TIM3_STOP rw	DBG_TIM2_STOP rw

Toggle fields

DBG_TIM2_STOP

Bit 0: TIM2 stop in debug.

DBG_TIM3_STOP

Bit 1: TIM3 stop in debug.

DBG_TIM4_STOP

Bit 2: TIM4 stop in debug.

DBG_TIM5_STOP

Bit 3: TIM5 stop in debug.

DBG_TIM6_STOP

Bit 4: TIM6 stop in debug.

DBG_TIM7_STOP

Bit 5: TIM7 stop in debug.

DBG_WWDG_STOP

Bit 11: Window watchdog counter stop in debug.

DBG_IWDG_STOP

Bit 12: Independent watchdog counter stop in debug.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout stop in debug.

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout stop in debug.

APB1HFZR

Debug MCU APB1H peripheral freeze register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DBG_LPTIM2_STOP rw				DBG_I2C4_STOP rw

Toggle fields

DBG_I2C4_STOP

Bit 1: I2C4 stop in debug.

DBG_LPTIM2_STOP

Bit 5: LPTIM2 stop in debug.

APB2FZR

Debug MCU APB2 peripheral freeze register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw	DBG_TIM15_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		DBG_TIM8_STOP rw		DBG_TIM1_STOP rw

Toggle fields

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM8_STOP

Bit 13: TIM8 stop in debug.

DBG_TIM15_STOP

Bit 16: TIM15 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

APB3FZR

Debug MCU APB3 peripheral freeze register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DBG_RTC_STOP rw											DBG_LPTIM4_STOP rw	DBG_LPTIM3_STOP rw	DBG_LPTIM1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DBG_I2C3_STOP rw

Toggle fields

DBG_I2C3_STOP

Bit 10: I2C3 stop in debug.

DBG_LPTIM1_STOP

Bit 17: LPTIM1 stop in debug.

DBG_LPTIM3_STOP

Bit 18: LPTIM3 stop in debug.

DBG_LPTIM4_STOP

Bit 19: LPTIM4 stop in debug.

DBG_RTC_STOP

Bit 30: RTC stop in debug.

AHB1FZR

Debug MCU AHB1 peripheral freeze register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBG_GPDMA15_STOP rw	DBG_GPDMA14_STOP rw	DBG_GPDMA13_STOP rw	DBG_GPDMA12_STOP rw	DBG_GPDMA11_STOP rw	DBG_GPDMA10_STOP rw	DBG_GPDMA9_STOP rw	DBG_GPDMA8_STOP rw	DBG_GPDMA7_STOP rw	DBG_GPDMA6_STOP rw	DBG_GPDMA5_STOP rw	DBG_GPDMA4_STOP rw	DBG_GPDMA3_STOP rw	DBG_GPDMA2_STOP rw	DBG_GPDMA1_STOP rw	DBG_GPDMA0_STOP rw

Toggle fields

DBG_GPDMA0_STOP

Bit 0: GPDMA channel 0 stop in debug.

DBG_GPDMA1_STOP

Bit 1: GPDMA channel 1 stop in debug.

DBG_GPDMA2_STOP

Bit 2: GPDMA channel 2 stop in debug.

DBG_GPDMA3_STOP

Bit 3: GPDMA channel 3 stop in debug.

DBG_GPDMA4_STOP

Bit 4: GPDMA channel 4 stop in debug.

DBG_GPDMA5_STOP

Bit 5: GPDMA channel 5 stop in debug.

DBG_GPDMA6_STOP

Bit 6: GPDMA channel 6 stop in debug.

DBG_GPDMA7_STOP

Bit 7: GPDMA channel 7 stop in debug.

DBG_GPDMA8_STOP

Bit 8: GPDMA channel 8 stop in debug.

DBG_GPDMA9_STOP

Bit 9: GPDMA channel 9 stop in debug.

DBG_GPDMA10_STOP

Bit 10: GPDMA channel 10 stop in debug.

DBG_GPDMA11_STOP

Bit 11: GPDMA channel 11 stop in debug.

DBG_GPDMA12_STOP

Bit 12: GPDMA channel 12 stop in debug.

DBG_GPDMA13_STOP

Bit 13: GPDMA channel 13 stop in debug.

DBG_GPDMA14_STOP

Bit 14: GPDMA channel 14 stop in debug.

DBG_GPDMA15_STOP

Bit 15: GPDMA channel 15 stop in debug.

AHB3FZR

Debug MCU AHB3 peripheral freeze register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												DBG_LPDMA3_STOP rw	DBG_LPDMA2_STOP rw	DBG_LPDMA1_STOP rw	DBG_LPDMA0_STOP rw

Toggle fields

DBG_LPDMA0_STOP

Bit 0: LPDMA channel 0 stop in debug.

DBG_LPDMA1_STOP

Bit 1: LPDMA channel 1 stop in debug.

DBG_LPDMA2_STOP

Bit 2: LPDMA channel 2 stop in debug.

DBG_LPDMA3_STOP

Bit 3: LPDMA channel 3 stop in debug.

SR

DBGMCU status register

Offset: 0xfc, size: 32, reset: 0x00000001, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AP_LOCKED r								AP_PRESENT r

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KCOUNT_4 r				JEP106CON r

Toggle fields

JEP106CON

Bits 0-3: JEP106 continuation code.

KCOUNT_4

Bits 4-7: register file size.

PIDR0

Debug MCU CoreSight peripheral identity register 0

Offset: 0xfe0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PARTNUM r

Toggle fields

PARTNUM

Bits 0-7: part number bits [7:0].

PIDR1

Debug MCU CoreSight peripheral identity register 1

Offset: 0xfe4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								JEP106ID r				PARTNUM r

Toggle fields

PARTNUM

Bits 0-3: part number bits [11:8].

JEP106ID

Bits 4-7: JEP106 identity code bits [3:0].

PIDR2

Debug MCU CoreSight peripheral identity register 2

Offset: 0xfe8, size: 32, reset: 0x0000000A, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REVISION r				JEDEC r	JEP106ID r

Toggle fields

JEP106ID

Bits 0-2: JEP106 identity code bits [6:4].

JEDEC

Bit 3: JEDEC assigned value.

REVISION

Bits 4-7: component revision number.

PIDR3

Debug MCU CoreSight peripheral identity register 3

Offset: 0xfec, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REVAND r				CMOD r

Toggle fields

CMOD

Bits 0-3: customer modified.

REVAND

Bits 4-7: metal fix version.

CIDR0

Debug MCU CoreSight component identity register 0

Offset: 0xff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PREAMBLE r

Toggle fields

PREAMBLE

Bits 0-7: component identification bits [7:0].

CIDR1

Debug MCU CoreSight component identity register 1

Offset: 0xff4, size: 32, reset: 0x000000F0, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CLASS r				PREAMBLE r

Toggle register map

Offset	Name	31	23	22	21	20	19	18	17	16	15	11	10	4	3	2	1	0
0x0	DCACHE_CR	HBURST	WMISSMRST	WHITMRST	WMISSMEN	WHITMEN	RMISSMRST	RHITMRST	RMISSMEN	RHITMEN		STARTCMD	CACHECMD				CACHEINV	EN
0x4	DCACHE_SR													CMDENDF	BUSYCMDF	ERRF	BSYENDF	BUSYF
0x8	DCACHE_IER													CMDENDIE		ERRIE	BSYENDIE
0xc	DCACHE_FCR													CCMDENDF		CERRF	CBSYENDF
0x10	DCACHE_RHMONR	RHITMON									RHITMON
0x14	DCACHE_RMMONR										MRISSMON
0x20	DCACHE_WHMONR	WHITMON									WHITMON
0x24	DCACHE_WMMONR										WMISSMON
0x28	DCACHE_CMDRSADDRR	CMDSTARTADDR									CMDSTARTADDR
0x2c	DCACHE_CMDREADDRR	CMDENDADDR									CMDENDADDR

Toggle registers

DCACHE_CR

DCACHE control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw								WMISSMRST rw	WHITMRST rw	WMISSMEN rw	WHITMEN rw	RMISSMRST rw	RHITMRST rw	RMISSMEN rw	RHITMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				STARTCMD w	CACHECMD rw									CACHEINV w	EN rw

Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

CACHECMD

Bits 8-10: CACHECMD.

STARTCMD

Bit 11: STARTCMD.

RHITMEN

Bit 16: RHITMEN.

RMISSMEN

Bit 17: RMISSMEN.

RHITMRST

Bit 18: RHITMRST.

RMISSMRST

Bit 19: RMISSMRST.

WHITMEN

Bit 20: WHITMEN.

WMISSMEN

Bit 21: WMISSMEN.

WHITMRST

Bit 22: WHITMRST.

WMISSMRST

Bit 23: WMISSMRST.

HBURST

Bit 31: HBURST.

DCACHE_SR

DCACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMDENDF r	BUSYCMDF r	ERRF r	BSYENDF r	BUSYF r

Toggle fields

BUSYF

Bit 0: BUSYF.

BSYENDF

Bit 1: BSYENDF.

ERRF

Bit 2: ERRF.

BUSYCMDF

Bit 3: BUSYCMDF.

CMDENDF

Bit 4: CMDENDF.

DCACHE_IER

DCACHE interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMDENDIE rw		ERRIE rw	BSYENDIE rw

Toggle fields

BSYENDIE

Bit 1: BSYENDIE.

ERRIE

Bit 2: ERRIE.

CMDENDIE

Bit 4: CMDENDIE.

DCACHE_FCR

DCACHE flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CCMDENDF w		CERRF w	CBSYENDF w

Toggle fields

CBSYENDF

Bit 1: CBSYENDF.

CERRF

Bit 2: CERRF.

CCMDENDF

Bit 4: CCMDENDF.

DCACHE_RHMONR

DCACHE read-hit monitor register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RHITMON r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RHITMON r

Toggle fields

RHITMON

Bits 0-31: RHITMON.

DCACHE_RMMONR

DCACHE read-miss monitor register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRISSMON r

Toggle fields

MRISSMON

Bits 0-15: RMISSMON.

DCACHE_WHMONR

write-hit monitor register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WHITMON r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WHITMON r

Toggle fields

WHITMON

Bits 0-31: WHITMON.

DCACHE_WMMONR

write-miss monitor register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WMISSMON r

Toggle fields

WMISSMON

Bits 0-15: WMISSMON.

DCACHE_CMDRSADDRR

command range start address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDSTARTADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDSTARTADDR rw

Toggle fields

CMDSTARTADDR

Bits 4-31: CMDSTARTADDR.

DCACHE_CMDREADDRR

command range start address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDENDADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDENDADDR rw

Toggle fields

CMDENDADDR

Bits 4-31: CMDENDADDR.

DCB

0xe000ee08: Debug Control Block

0/1 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DSCSR																CDS

Toggle registers

DSCSR

Debug Security Control and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															CDS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

CDS

Bit 16: Current domain Secure.

DCMI

0x4202c000: Digital camera interface

17/54 fields covered.

Toggle register map

Offset	Name	31	29	28	23	20	19	18	17	15	14	13	11	9	7	6	5	4	3	2	1	0
0x0	CR					OELS	LSM	OEBS	BSM		ENABLE		EDM	FCRC	VSPOL	HSPOL	PCKPOL	ESS	JPEG	CROP	CM	CAPTURE
0x4	SR																			FNE	VSYNC	HSYNC
0x8	RIS																	LINE_RIS	VSYNC_RIS	ERR_RIS	OVR_RIS	FRAME_RIS
0xc	IER																	LINE_IE	VSYNC_IE	ERR_IE	OVR_IE	FRAME_IE
0x10	MIS																	LINE_MIS	VSYNC_MIS	ERR_MIS	OVR_MIS	FRAME_MIS
0x14	ICR																	LINE_ISC	VSYNC_ISC	ERR_ISC	OVR_ISC	FRAME_ISC
0x18	ESCR	FEC			LEC					LSC					FSC
0x1c	ESUR	FEU			LEU					LSU					FSU
0x20	CWSTRT			VST								HOFFCNT
0x24	CWSIZE		VLINE									CAPCNT
0x28	DR	BYTE3			BYTE2					BYTE1					BYTE0

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											OELS rw	LSM rw	OEBS rw	BSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	ENABLE rw			EDM rw		FCRC rw		VSPOL rw	HSPOL rw	PCKPOL rw	ESS rw	JPEG rw	CROP rw	CM rw	CAPTURE rw

Toggle fields

CAPTURE

Bit 0: Capture enable.

CM

Bit 1: Capture mode.

CROP

Bit 2: Crop feature.

JPEG

Bit 3: JPEG format.

ESS

Bit 4: Embedded synchronization select.

PCKPOL

Bit 5: Pixel clock polarity.

HSPOL

Bit 6: Horizontal synchronization polarity.

VSPOL

Bit 7: Vertical synchronization polarity.

FCRC

Bits 8-9: Frame capture rate control.

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: DCMI enable.

BSM

Bits 16-17: Byte Select mode.

OEBS

Bit 18: Odd/Even Byte Select (Byte Select Start).

LSM

Bit 19: Line Select mode.

OELS

Bit 20: Odd/Even Line Select (Line Select Start).

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FNE r	VSYNC r	HSYNC r

Toggle fields

HSYNC

Bit 0: Horizontal synchronization.

VSYNC

Bit 1: Vertical synchronization.

FNE

Bit 2: FIFO not empty.

RIS

raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_RIS r	VSYNC_RIS r	ERR_RIS r	OVR_RIS r	FRAME_RIS r

Toggle fields

FRAME_RIS

Bit 0: Capture complete raw interrupt status.

OVR_RIS

Bit 1: Overrun raw interrupt status.

ERR_RIS

Bit 2: Synchronization error raw interrupt status.

VSYNC_RIS

Bit 3: DCMI_VSYNC raw interrupt status.

LINE_RIS

Bit 4: Line raw interrupt status.

IER

interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_IE rw	VSYNC_IE rw	ERR_IE rw	OVR_IE rw	FRAME_IE rw

Toggle fields

FRAME_IE

Bit 0: Capture complete interrupt enable.

OVR_IE

Bit 1: Overrun interrupt enable.

ERR_IE

Bit 2: Synchronization error interrupt enable.

VSYNC_IE

Bit 3: DCMI_VSYNC interrupt enable.

LINE_IE

Bit 4: Line interrupt enable.

MIS

masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_MIS r	VSYNC_MIS r	ERR_MIS r	OVR_MIS r	FRAME_MIS r

Toggle fields

FRAME_MIS

Bit 0: Capture complete masked interrupt status.

OVR_MIS

Bit 1: Overrun masked interrupt status.

ERR_MIS

Bit 2: Synchronization error masked interrupt status.

VSYNC_MIS

Bit 3: VSYNC masked interrupt status.

LINE_MIS

Bit 4: Line masked interrupt status.

ICR

interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_ISC w	VSYNC_ISC w	ERR_ISC w	OVR_ISC w	FRAME_ISC w

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			VST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		HOFFCNT rw

Toggle fields

HOFFCNT

Bits 0-13: Horizontal offset count.

VST

Bits 16-28: Vertical start line count.

CWSIZE

crop window size

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		VLINE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CAPCNT rw

Toggle fields

CAPCNT

Bits 0-13: Capture count.

VLINE

Bits 16-29: Vertical line count.

DR

data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BYTE3 r								BYTE2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BYTE1 r								BYTE0 r

Toggle fields

BYTE0

Bits 0-7: Data byte 0.

BYTE1

Bits 8-15: Data byte 1.

BYTE2

Bits 16-23: Data byte 2.

BYTE3

Bits 24-31: Data byte 3.

DLYBOS

0x420cf000: The delay block (DLYB) is used to generate an output clock that is dephased from the input clock

2/6 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DLYB_CR																															SEN	DEN
0x4	DLYB_CFGR	LNGF				LNG													UNIT											SEL

Toggle registers

DLYB_CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SEN rw	DEN rw

Toggle fields

DEN

Bit 0: Operational amplifier Enable.

SEN

Bit 1: OPALPM.

DLYB_CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LNGF r				LNG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	UNIT rw											SEL rw

Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

DLYBSD

0x420c8400: The delay block (DLYB) is used to generate an output clock that is dephased from the input clock

2/6 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DLYB_CR																															SEN	DEN
0x4	DLYB_CFGR	LNGF				LNG													UNIT											SEL

Toggle registers

DLYB_CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SEN rw	DEN rw

Toggle fields

DEN

Bit 0: Operational amplifier Enable.

SEN

Bit 1: OPALPM.

DLYB_CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LNGF r				LNG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	UNIT rw											SEL rw

Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

EXTI

0x46022000: External interrupt/event controller

0/251 fields covered.

Toggle register map

Offset	Name	31	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	EXTI_RTSR1		RT25	RT24	RT23	RT22	RT21	RT20	RT19	RT18	RT17	RT16	RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
0x4	EXTI_FTSR1		FT25	FT24	FT23	FT22	FT21	FT20	FT19	FT18	FT17	FT16	FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
0x8	EXTI_SWIER1		SWI25	SWI24	SWI23	SWI22	SWI21	SWI20	SWI19	SWI18	SWI17	SWI16	SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
0xc	EXTI_RPR1		RPIF25	RPIF24	RPIF23	RPIF22	RPIF21	RPIF20	RPIF19	RPIF18	RPIF17	RPIF16	RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
0x10	EXTI_FPR1		FPIF25	FPIF24	FPIF23	FPIF22	FPIF21	FPIF20	FPIF19	FPIF18	FPIF17	FPIF16	FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
0x14	EXTI_SECCFGR1		SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x18	EXTI_PRIVCFGR1		PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x60	EXTI_EXTICR1	EXTI3			EXTI2								EXTI1								EXTI0
0x64	EXTI_EXTICR2	EXTI7			EXTI6								EXTI5								EXTI4
0x68	EXTI_EXTICR3	EXTI11			EXTI10								EXTI9								EXTI8
0x6c	EXTI_EXTICR4	EXTI15			EXTI14								EXTI13								EXTI12
0x70	EXTI_LOCKR																											LOCK
0x80	EXTI_IMR1		IM25	IM24	IM23	IM22	IM21	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x84	EXTI_EMR1		EM25	EM24	EM23	EM22	EM21	EM20	EM19	EM18	EM17	EM16	EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0

Toggle registers

EXTI_RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RT25 rw	RT24 rw	RT23 rw	RT22 rw	RT21 rw	RT20 rw	RT19 rw	RT18 rw	RT17 rw	RT16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15 rw	RT14 rw	RT13 rw	RT12 rw	RT11 rw	RT10 rw	RT9 rw	RT8 rw	RT7 rw	RT6 rw	RT5 rw	RT4 rw	RT3 rw	RT2 rw	RT1 rw	RT0 rw

Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT1

Bit 1: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT2

Bit 2: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT3

Bit 3: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT4

Bit 4: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT5

Bit 5: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT6

Bit 6: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT7

Bit 7: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT8

Bit 8: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT9

Bit 9: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT10

Bit 10: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT11

Bit 11: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT12

Bit 12: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT13

Bit 13: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT14

Bit 14: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT15

Bit 15: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT16

Bit 16: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT17

Bit 17: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT18

Bit 18: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT19

Bit 19: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT20

Bit 20: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT21

Bit 21: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT22

Bit 22: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT23

Bit 23: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT24

Bit 24: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT25

Bit 25: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FT25 rw	FT24 rw	FT23 rw	FT22 rw	FT21 rw	FT20 rw	FT19 rw	FT18 rw	FT17 rw	FT16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15 rw	FT14 rw	FT13 rw	FT12 rw	FT11 rw	FT10 rw	FT9 rw	FT8 rw	FT7 rw	FT6 rw	FT5 rw	FT4 rw	FT3 rw	FT2 rw	FT1 rw	FT0 rw

Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT1

Bit 1: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT2

Bit 2: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT3

Bit 3: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT4

Bit 4: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT5

Bit 5: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT6

Bit 6: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT7

Bit 7: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT8

Bit 8: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT9

Bit 9: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT10

Bit 10: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT11

Bit 11: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT12

Bit 12: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT13

Bit 13: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT14

Bit 14: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT15

Bit 15: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT16

Bit 16: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT17

Bit 17: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT18

Bit 18: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT19

Bit 19: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT20

Bit 20: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT21

Bit 21: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT22

Bit 22: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT23

Bit 23: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT24

Bit 24: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT25

Bit 25: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SWI25 rw	SWI24 rw	SWI23 rw	SWI22 rw	SWI21 rw	SWI20 rw	SWI19 rw	SWI18 rw	SWI17 rw	SWI16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15 rw	SWI14 rw	SWI13 rw	SWI12 rw	SWI11 rw	SWI10 rw	SWI9 rw	SWI8 rw	SWI7 rw	SWI6 rw	SWI5 rw	SWI4 rw	SWI3 rw	SWI2 rw	SWI1 rw	SWI0 rw

Toggle fields

SWI0

Bit 0: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI1

Bit 1: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI2

Bit 2: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI3

Bit 3: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI4

Bit 4: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI5

Bit 5: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI6

Bit 6: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI7

Bit 7: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI8

Bit 8: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI9

Bit 9: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI10

Bit 10: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI11

Bit 11: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI12

Bit 12: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI13

Bit 13: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI14

Bit 14: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI15

Bit 15: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI16

Bit 16: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI17

Bit 17: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI18

Bit 18: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI19

Bit 19: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI20

Bit 20: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI21

Bit 21: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI22

Bit 22: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI23

Bit 23: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI24

Bit 24: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI25

Bit 25: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_RPR1

EXTI rising edge pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RPIF25 rw	RPIF24 rw	RPIF23 rw	RPIF22 rw	RPIF21 rw	RPIF20 rw	RPIF19 rw	RPIF18 rw	RPIF17 rw	RPIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15 rw	RPIF14 rw	RPIF13 rw	RPIF12 rw	RPIF11 rw	RPIF10 rw	RPIF9 rw	RPIF8 rw	RPIF7 rw	RPIF6 rw	RPIF5 rw	RPIF4 rw	RPIF3 rw	RPIF2 rw	RPIF1 rw	RPIF0 rw

Toggle fields

RPIF0

Bit 0: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF1

Bit 1: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF2

Bit 2: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF3

Bit 3: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF4

Bit 4: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF5

Bit 5: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF6

Bit 6: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF7

Bit 7: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF8

Bit 8: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF9

Bit 9: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF10

Bit 10: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF11

Bit 11: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF12

Bit 12: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF13

Bit 13: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF14

Bit 14: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF15

Bit 15: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF16

Bit 16: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF17

Bit 17: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF18

Bit 18: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF19

Bit 19: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF20

Bit 20: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF21

Bit 21: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF22

Bit 22: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF23

Bit 23: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF24

Bit 24: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF25

Bit 25: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

EXTI_FPR1

EXTI falling edge pending register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FPIF25 rw	FPIF24 rw	FPIF23 rw	FPIF22 rw	FPIF21 rw	FPIF20 rw	FPIF19 rw	FPIF18 rw	FPIF17 rw	FPIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15 rw	FPIF14 rw	FPIF13 rw	FPIF12 rw	FPIF11 rw	FPIF10 rw	FPIF9 rw	FPIF8 rw	FPIF7 rw	FPIF6 rw	FPIF5 rw	FPIF4 rw	FPIF3 rw	FPIF2 rw	FPIF1 rw	FPIF0 rw

Toggle fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF1

Bit 1: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF2

Bit 2: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF3

Bit 3: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF4

Bit 4: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF5

Bit 5: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF6

Bit 6: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF7

Bit 7: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF8

Bit 8: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF9

Bit 9: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF10

Bit 10: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF11

Bit 11: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF12

Bit 12: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF13

Bit 13: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF14

Bit 14: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF15

Bit 15: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF16

Bit 16: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF17

Bit 17: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF18

Bit 18: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF19

Bit 19: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF20

Bit 20: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF21

Bit 21: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF22

Bit 22: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF23

Bit 23: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF24

Bit 24: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF25

Bit 25: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_SECCFGR1

EXTI security configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC1

Bit 1: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC2

Bit 2: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC3

Bit 3: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC4

Bit 4: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC5

Bit 5: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC6

Bit 6: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC7

Bit 7: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC8

Bit 8: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC9

Bit 9: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC10

Bit 10: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC11

Bit 11: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC12

Bit 12: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC13

Bit 13: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC14

Bit 14: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC15

Bit 15: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC16

Bit 16: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC17

Bit 17: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC18

Bit 18: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC19

Bit 19: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC20

Bit 20: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC21

Bit 21: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC22

Bit 22: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC23

Bit 23: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC24

Bit 24: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC25

Bit 25: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_PRIVCFGR1

EXTI privilege configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV1

Bit 1: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV2

Bit 2: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV3

Bit 3: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV4

Bit 4: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV5

Bit 5: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV6

Bit 6: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV7

Bit 7: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV8

Bit 8: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV9

Bit 9: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV10

Bit 10: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV11

Bit 11: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV12

Bit 12: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV13

Bit 13: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV14

Bit 14: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV15

Bit 15: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV16

Bit 16: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV17

Bit 17: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV18

Bit 18: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV19

Bit 19: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV20

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LOCK rw

Toggle fields

LOCK

Bit 0: Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset..

EXTI_IMR1

EXTI CPU wake-up with interrupt mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						IM25 rw	IM24 rw	IM23 rw	IM22 rw	IM21 rw	IM20 rw	IM19 rw	IM18 rw	IM17 rw	IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle fields

IM0

Bit 0: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM1

Bit 1: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM2

Bit 2: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM3

Bit 3: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM4

Bit 4: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM5

Bit 5: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM6

Bit 6: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM7

Bit 7: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM8

Bit 8: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM9

Bit 9: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM10

Bit 10: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM11

Bit 11: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM12

Bit 12: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM13

Bit 13: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM14

Bit 14: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM15

Bit 15: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM16

Bit 16: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM17

Bit 17: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM18

Bit 18: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM19

Bit 19: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM20

Bit 20: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM21

Bit 21: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM22

Bit 22: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM23

Bit 23: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM24

Bit 24: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM25

Bit 25: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_EMR1

EXTI CPU wake-up with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						EM25 rw	EM24 rw	EM23 rw	EM22 rw	EM21 rw	EM20 rw	EM19 rw	EM18 rw	EM17 rw	EM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM15 rw	EM14 rw	EM13 rw	EM12 rw	EM11 rw	EM10 rw	EM9 rw	EM8 rw	EM7 rw	EM6 rw	EM5 rw	EM4 rw	EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle fields

EM0

Bit 0: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM1

Bit 1: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM2

Bit 2: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM3

Bit 3: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM4

Bit 4: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM5

Bit 5: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM6

Bit 6: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM7

Bit 7: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM8

Bit 8: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM9

Bit 9: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM10

Bit 10: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM11

Bit 11: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM12

Bit 12: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM13

Bit 13: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM14

Bit 14: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM15

Bit 15: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM16

Bit 16: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM17

Bit 17: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM18

Bit 18: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM19

Bit 19: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM20

Bit 20: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM21

Bit 21: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM22

Bit 22: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM23

Bit 23: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM24

Bit 24: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM25

Bit 25: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FDCAN1

0x4000a400: FDCAN1_RAM

43/160 fields covered.

Toggle register map

Offset	Name	31	28	27	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	FDCAN_CREL	REL		STEP			SUBSTEP				YEAR				MON								DAY
0x4	FDCAN_ENDN	ETV													ETV
0xc	FDCAN_DBTP						TDC			DBRP								DTSEG1					DTSEG2				DSJW
0x10	FDCAN_TEST																						RX	TX		LBCK
0x14	FDCAN_RWD														WDV								WDC
0x18	FDCAN_CCCR														NISO	TXP	EFBI	PXHD			BRSE	FDOE	TEST	DAR	MON	CSR	CSA	ASM	CCE	INIT
0x1c	FDCAN_NBTP	NSJW				NBRP									NTSEG1									NTSEG2
0x20	FDCAN_TSCC										TCP																		TSS
0x24	FDCAN_TSCV														TSC
0x28	FDCAN_TOCC	TOP																										TOS		ETOC
0x2c	FDCAN_TOCV														TOC
0x40	FDCAN_ECR						CEL								RP	REC							TEC
0x44	FDCAN_PSR							TDCV								PXE	REDL	RBRS	RESI	DLEC			BO	EW	EP	ACT		LEC
0x48	FDCAN_TDCR															TDCO								TDCF
0x50	FDCAN_IR						ARA	PED	PEA	WDI	BO	EW	EP	ELO	TOO	MRAF	TSW	TEFL	TEFF	TEFN	TFE	TCF	TC	HPM	RF1L	RF1F	RF1N	RF0L	RF0F	RF0N
0x54	FDCAN_IE						ARAE	PEDE	PEAE	WDIE	BOE	EWE	EPE	ELOE	TOOE	MRAFE	TSWE	TEFLE	TEFFE	TEFNE	TEFE	TCFE	TCE	HPME	RF1LE	RF1FE	RF1NE	RF0LE	RF0FE	RF0NE
0x58	FDCAN_ILS																							PERR	BERR	MISC	TFERR	SMSG	RxFIFO1	RxFIFO0
0x5c	FDCAN_ILE																												EINT1	EINT0
0x80	FDCAN_RXGFC			LSE						LSS											F0OM	F1OM			ANFS		ANFE		RRFS	RRFE
0x84	FDCAN_XIDAM		EIDM												EIDM
0x88	FDCAN_HPMS														FLST			FIDX					MSI					BIDX
0x90	FDCAN_RXF0S				RF0L	F0F							F0PI								F0GI						F0FL
0x94	FDCAN_RXF0A																											F0AI
0x98	FDCAN_RXF1S				RF1L	F1F							F1PI								F1GI						F1FL
0x9c	FDCAN_RXF1A																											F1AI
0xc0	FDCAN_TXBC					TFQM
0xc4	FDCAN_TXFQS								TFQF				TFQPI								TFGI							TFFL
0xc8	FDCAN_TXBRP																											TRP
0xcc	FDCAN_TXBAR																											AR
0xd0	FDCAN_TXBCR																											CR
0xd4	FDCAN_TXBTO																											TO
0xd8	FDCAN_TXBCF																											CF
0xdc	FDCAN_TXBTIE																											TIE
0xe0	FDCAN_TXBCIE																											CFIE
0xe4	FDCAN_TXEFS				TEFL	EFF							EFPI								EFGI							EFFL
0xe8	FDCAN_TXEFA																												EFAI
0x100	FDCAN_CKDIV																										PDIV

Toggle registers

FDCAN_CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REL r				STEP r				SUBSTEP r				YEAR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MON r								DAY r

Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

FDCAN_ENDN

FDCAN endian register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETV r

Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TDC rw			DBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DTSEG1 rw					DTSEG2 rw				DSJW rw

Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

FDCAN_TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RX r	TX rw		LBCK rw

Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

FDCAN_RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDV r								WDC rw

Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

FDCAN_CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NISO rw	TXP rw	EFBI rw	PXHD rw			BRSE rw	FDOE rw	TEST rw	DAR rw	MON rw	CSR rw	CSA rw	ASM rw	CCE rw	INIT rw

Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BRSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSJW rw							NBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NTSEG1 rw									NTSEG2 rw

Toggle fields

NTSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: Nominal (Re)Synchronization Jump Width.

FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TCP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TSS rw

Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

FDCAN_TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSC rw

Toggle fields

TSC

Bits 0-15: Timestamp Counter.

FDCAN_TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TOS rw		ETOC rw

Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

FDCAN_TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOC rw

Toggle fields

FDCAN_ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RP r	REC r							TEC r

Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

FDCAN_PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TDCV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PXE rw	REDL rw	RBRS rw	RESI rw	DLEC rw			BO r	EW r	EP r	ACT r		LEC rw

Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDCO rw								TDCF rw

Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

FDCAN_IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARA rw	PED rw	PEA rw	WDI rw	BO rw	EW rw	EP rw	ELO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOO rw	MRAF rw	TSW rw	TEFL rw	TEFF rw	TEFN rw	TFE rw	TCF rw	TC rw	HPM rw	RF1L rw	RF1F rw	RF1N rw	RF0L rw	RF0F rw	RF0N rw

Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

FDCAN_IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARAE rw	PEDE rw	PEAE rw	WDIE rw	BOE rw	EWE rw	EPE rw	ELOE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOOE rw	MRAFE rw	TSWE rw	TEFLE rw	TEFFE rw	TEFNE rw	TEFE rw	TCFE rw	TCE rw	HPME rw	RF1LE rw	RF1FE rw	RF1NE rw	RF0LE rw	RF0FE rw	RF0NE rw

Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

TSWE

Bit 13: TSWE.

MRAFE

Bit 14: Message RAM Access Failure Enable.

TOOE

Bit 15: Timeout Occurred Enable.

ELOE

Bit 16: Error Logging Overflow Enable.

EPE

Bit 17: Error Passive Enable.

EWE

Bit 18: Warning Status Enable.

BOE

Bit 19: Bus_Off Status Enable.

WDIE

Bit 20: Watchdog Interrupt Enable.

PEAE

Bit 21: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 22: Protocol Error in Data Phase Enable.

ARAE

Bit 23: Access to Reserved Address Enable.

FDCAN_ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PERR rw	BERR rw	MISC rw	TFERR rw	SMSG rw	RxFIFO1 rw	RxFIFO0 rw

Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

FDCAN_ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EINT1 rw	EINT0 rw

Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

FDCAN_RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				LSE rw							LSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0OM rw	F1OM rw			ANFS rw		ANFE rw		RRFS rw	RRFE rw

Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

FDCAN_XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			EIDM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIDM rw

Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

FDCAN_HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLST r			FIDX r					MSI r					BIDX r

Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF0L r	F0F r							F0PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0GI r						F0FL r

Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F0AI rw

Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF1L r	F1F r							F1PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F1GI r						F1FL r

Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F1AI rw

Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

FDCAN_TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TFQM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TFQF r				TFQPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TFGI r							TFFL r

Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TRP r

Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													AR rw

Toggle fields

AR

Bits 0-2: Add Request.

FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CR rw

Toggle fields

CR

Bits 0-2: Cancellation Request.

FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TO r

Toggle fields

TO

Bits 0-2: Transmission Occurred..

FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CF r

Toggle fields

CF

Bits 0-2: Cancellation Finished.

FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TIE rw

Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CFIE rw

Toggle fields

CFIE

Bits 0-2: Cancellation Finished Interrupt Enable.

FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TEFL r	EFF r							EFPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EFGI r							EFFL r

Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EFAI rw

Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

FDCAN_CKDIV

FDCAN CFG clock divider register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PDIV rw

Toggle fields

PDIV

Bits 0-3: PDIV.

FDCAN1_RAM

0x4000ac00: FDCAN1_RAM

43/160 fields covered.

Toggle register map

Offset	Name	31	28	27	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	FDCAN_CREL	REL		STEP			SUBSTEP				YEAR				MON								DAY
0x4	FDCAN_ENDN	ETV													ETV
0xc	FDCAN_DBTP						TDC			DBRP								DTSEG1					DTSEG2				DSJW
0x10	FDCAN_TEST																						RX	TX		LBCK
0x14	FDCAN_RWD														WDV								WDC
0x18	FDCAN_CCCR														NISO	TXP	EFBI	PXHD			BRSE	FDOE	TEST	DAR	MON	CSR	CSA	ASM	CCE	INIT
0x1c	FDCAN_NBTP	NSJW				NBRP									NTSEG1									NTSEG2
0x20	FDCAN_TSCC										TCP																		TSS
0x24	FDCAN_TSCV														TSC
0x28	FDCAN_TOCC	TOP																										TOS		ETOC
0x2c	FDCAN_TOCV														TOC
0x40	FDCAN_ECR						CEL								RP	REC							TEC
0x44	FDCAN_PSR							TDCV								PXE	REDL	RBRS	RESI	DLEC			BO	EW	EP	ACT		LEC
0x48	FDCAN_TDCR															TDCO								TDCF
0x50	FDCAN_IR						ARA	PED	PEA	WDI	BO	EW	EP	ELO	TOO	MRAF	TSW	TEFL	TEFF	TEFN	TFE	TCF	TC	HPM	RF1L	RF1F	RF1N	RF0L	RF0F	RF0N
0x54	FDCAN_IE						ARAE	PEDE	PEAE	WDIE	BOE	EWE	EPE	ELOE	TOOE	MRAFE	TSWE	TEFLE	TEFFE	TEFNE	TEFE	TCFE	TCE	HPME	RF1LE	RF1FE	RF1NE	RF0LE	RF0FE	RF0NE
0x58	FDCAN_ILS																							PERR	BERR	MISC	TFERR	SMSG	RxFIFO1	RxFIFO0
0x5c	FDCAN_ILE																												EINT1	EINT0
0x80	FDCAN_RXGFC			LSE						LSS											F0OM	F1OM			ANFS		ANFE		RRFS	RRFE
0x84	FDCAN_XIDAM		EIDM												EIDM
0x88	FDCAN_HPMS														FLST			FIDX					MSI					BIDX
0x90	FDCAN_RXF0S				RF0L	F0F							F0PI								F0GI						F0FL
0x94	FDCAN_RXF0A																											F0AI
0x98	FDCAN_RXF1S				RF1L	F1F							F1PI								F1GI						F1FL
0x9c	FDCAN_RXF1A																											F1AI
0xc0	FDCAN_TXBC					TFQM
0xc4	FDCAN_TXFQS								TFQF				TFQPI								TFGI							TFFL
0xc8	FDCAN_TXBRP																											TRP
0xcc	FDCAN_TXBAR																											AR
0xd0	FDCAN_TXBCR																											CR
0xd4	FDCAN_TXBTO																											TO
0xd8	FDCAN_TXBCF																											CF
0xdc	FDCAN_TXBTIE																											TIE
0xe0	FDCAN_TXBCIE																											CFIE
0xe4	FDCAN_TXEFS				TEFL	EFF							EFPI								EFGI							EFFL
0xe8	FDCAN_TXEFA																												EFAI
0x100	FDCAN_CKDIV																										PDIV

Toggle registers

FDCAN_CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REL r				STEP r				SUBSTEP r				YEAR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MON r								DAY r

Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

FDCAN_ENDN

FDCAN endian register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETV r

Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TDC rw			DBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DTSEG1 rw					DTSEG2 rw				DSJW rw

Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

FDCAN_TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RX r	TX rw		LBCK rw

Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

FDCAN_RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDV r								WDC rw

Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

FDCAN_CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NISO rw	TXP rw	EFBI rw	PXHD rw			BRSE rw	FDOE rw	TEST rw	DAR rw	MON rw	CSR rw	CSA rw	ASM rw	CCE rw	INIT rw

Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BRSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSJW rw							NBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NTSEG1 rw									NTSEG2 rw

Toggle fields

NTSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: Nominal (Re)Synchronization Jump Width.

FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TCP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TSS rw

Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

FDCAN_TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSC rw

Toggle fields

TSC

Bits 0-15: Timestamp Counter.

FDCAN_TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TOS rw		ETOC rw

Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

FDCAN_TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOC rw

Toggle fields

FDCAN_ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RP r	REC r							TEC r

Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

FDCAN_PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TDCV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PXE rw	REDL rw	RBRS rw	RESI rw	DLEC rw			BO r	EW r	EP r	ACT r		LEC rw

Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDCO rw								TDCF rw

Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

FDCAN_IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARA rw	PED rw	PEA rw	WDI rw	BO rw	EW rw	EP rw	ELO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOO rw	MRAF rw	TSW rw	TEFL rw	TEFF rw	TEFN rw	TFE rw	TCF rw	TC rw	HPM rw	RF1L rw	RF1F rw	RF1N rw	RF0L rw	RF0F rw	RF0N rw

Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

FDCAN_IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARAE rw	PEDE rw	PEAE rw	WDIE rw	BOE rw	EWE rw	EPE rw	ELOE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOOE rw	MRAFE rw	TSWE rw	TEFLE rw	TEFFE rw	TEFNE rw	TEFE rw	TCFE rw	TCE rw	HPME rw	RF1LE rw	RF1FE rw	RF1NE rw	RF0LE rw	RF0FE rw	RF0NE rw

Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

TSWE

Bit 13: TSWE.

MRAFE

Bit 14: Message RAM Access Failure Enable.

TOOE

Bit 15: Timeout Occurred Enable.

ELOE

Bit 16: Error Logging Overflow Enable.

EPE

Bit 17: Error Passive Enable.

EWE

Bit 18: Warning Status Enable.

BOE

Bit 19: Bus_Off Status Enable.

WDIE

Bit 20: Watchdog Interrupt Enable.

PEAE

Bit 21: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 22: Protocol Error in Data Phase Enable.

ARAE

Bit 23: Access to Reserved Address Enable.

FDCAN_ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PERR rw	BERR rw	MISC rw	TFERR rw	SMSG rw	RxFIFO1 rw	RxFIFO0 rw

Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

FDCAN_ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EINT1 rw	EINT0 rw

Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

FDCAN_RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				LSE rw							LSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0OM rw	F1OM rw			ANFS rw		ANFE rw		RRFS rw	RRFE rw

Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

FDCAN_XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			EIDM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIDM rw

Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

FDCAN_HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLST r			FIDX r					MSI r					BIDX r

Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF0L r	F0F r							F0PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0GI r						F0FL r

Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F0AI rw

Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF1L r	F1F r							F1PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F1GI r						F1FL r

Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F1AI rw

Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

FDCAN_TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TFQM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TFQF r				TFQPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TFGI r							TFFL r

Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TRP r

Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													AR rw

Toggle fields

AR

Bits 0-2: Add Request.

FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CR rw

Toggle fields

CR

Bits 0-2: Cancellation Request.

FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TO r

Toggle fields

TO

Bits 0-2: Transmission Occurred..

FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CF r

Toggle fields

CF

Bits 0-2: Cancellation Finished.

FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TIE rw

Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CFIE rw

Toggle fields

CFIE

Bits 0-2: Cancellation Finished Interrupt Enable.

FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TEFL r	EFF r							EFPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EFGI r							EFFL r

Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EFAI rw

Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

FDCAN_CKDIV

FDCAN CFG clock divider register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PDIV rw

Toggle fields

PDIV

Bits 0-3: PDIV.

FLASH

0x40022000: Flash

15/1153 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	FLASH_ACR																		SLEEP_PD	PDREQ2	PDREQ1	LPM			PRFTEN					LATENCY
0x8	FLASH_NSKEYR	NSKEY																NSKEY
0xc	FLASH_SECKEYR	SECKEY																SECKEY
0x10	FLASH_OPTKEYR	OPTKEY																OPTKEY
0x18	FLASH_PDKEY1R	PDKEY1																PDKEY1
0x1c	FLASH_PDKEY2R	PDKEY2																PDKEY2
0x20	FLASH_NSSR											PD2	PD1	OEM2LOCK	OEM1LOCK	WDW	BSY			OPTWERR						PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x24	FLASH_SECSR															WDW	BSY		RDERR							PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x28	FLASH_NSCR	LOCK	OPTLOCK			OBL_LAUNCH		ERRIE	EOPIE							OPTSTRT	STRT	MER2	BWR			BKER	PNB								MER1	PER	PG
0x2c	FLASH_SECCR	LOCK		INV			RDERRIE	ERRIE	EOPIE								STRT	MER2	BWR			BKER	PNB								MER1	PER	PG
0x30	FLASH_ECCR	ECCD	ECCC						ECCIE		SYSF_ECC	BK_ECC	ADDR_ECC					ADDR_ECC
0x34	FLASH_OPSR	CODE_OP									SYSF_OP	BK_OP	ADDR_OP					ADDR_OP
0x40	FLASH_OPTR	TZEN	IO_VDDIO2_HSLV	IO_VDD_HSLV	PA15_PUPEN	nBOOT0	nSWBOOT0	SRAM2_RST	SRAM2_ECC		BKPRAM_ECC	DUALBANK	SWAP_BANK	WWDG_SW	IWDG_STDBY	IWDG_STOP	IWDG_SW	SRAM1345_RST	nRST_SHDW	nRST_STDBY	nRST_STOP		BOR_LEV			RDP
0x44	FLASH_NSBOOTADD0R	NSBOOTADD0																NSBOOTADD0
0x48	FLASH_NSBOOTADD1R	NSBOOTADD1																NSBOOTADD1
0x4c	FLASH_SECBOOTADD0R	SECBOOTADD0																SECBOOTADD0															BOOT_LOCK
0x50	FLASH_SECWM1R1									SECWM1_PEND																SECWM1_PSTRT
0x54	FLASH_SECWM1R2	HDP1EN								HDP1_PEND								PCROP1EN								PCROP1_PSTRT
0x58	FLASH_WRP1AR	UNLOCK								WRP1A_PEND																WRP1A_PSTRT
0x5c	FLASH_WRP1BR	UNLOCK								WRP1B_PEND																WRP1B_PSTRT
0x60	FLASH_SECWM2R1									SECWM2_PEND																SECWM2_PSTRT
0x64	FLASH_SECWM2R2	HDP2EN								HDP2_PEND								PCROP2EN								PCROP2_PSTRT
0x68	FLASH_WRP2AR	UNLOCK								WRP2A_PEND																WRP2A_PSTRT
0x6c	FLASH_WRP2BR	UNLOCK								WRP2B_PEND																WRP2B_PSTRT
0x70	FLASH_OEM1KEYR1	OEM1KEY																OEM1KEY
0x74	FLASH_OEM1KEYR2	OEM1KEY																OEM1KEY
0x78	FLASH_OEM2KEYR1	OEM2KEY																OEM2KEY
0x7c	FLASH_OEM2KEYR2	OEM2KEY																OEM2KEY
0x80	FLASH_SEC1BBR1	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x84	FLASH_SEC1BBR2	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x88	FLASH_SEC1BBR3	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x8c	FLASH_SEC1BBR4	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x90	FLASH_SEC1BBR5	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x94	FLASH_SEC1BBR6	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x98	FLASH_SEC1BBR7	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x9c	FLASH_SEC1BBR8	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0xa0	FLASH_SEC2BBR1	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xa4	FLASH_SEC2BBR2	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xa8	FLASH_SEC2BBR3	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xac	FLASH_SEC2BBR4	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xb0	FLASH_SEC2BBR5	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xb4	FLASH_SEC2BBR6	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xb8	FLASH_SEC2BBR7	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xbc	FLASH_SEC2BBR8	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xc0	FLASH_SECHDPCR																															HDP2_ACCDIS	HDP1_ACCDIS
0xc4	FLASH_PRIVCFGR																															NSPRIV	SPRIV
0xd0	FLASH_PRIV1BBR1	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xd4	FLASH_PRIV1BBR2	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xd8	FLASH_PRIV1BBR3	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xdc	FLASH_PRIV1BBR4	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xe0	FLASH_PRIV1BBR5	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xe4	FLASH_PRIV1BBR6	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xe8	FLASH_PRIV1BBR7	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xec	FLASH_PRIV1BBR8	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xf0	FLASH_PRIV2BBR1	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0xf4	FLASH_PRIV2BBR2	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0xf8	FLASH_PRIV2BBR3	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0xfc	FLASH_PRIV2BBR4	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x100	FLASH_PRIV2BBR5	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x104	FLASH_PRIV2BBR6	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x108	FLASH_PRIV2BBR7	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x10c	FLASH_PRIV2BBR8	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0

Toggle registers

FLASH_ACR

FLASH access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SLEEP_PD rw	PDREQ2 rw	PDREQ1 rw	LPM rw			PRFTEN rw					LATENCY rw

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LATENCY

Bits 0-3: Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. ....

PRFTEN

Bit 8: Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory..

LPM

Bit 11: Low-power read mode This bit puts the Flash memory in low-power read mode..

PDREQ1

6/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										PD2 r	PD1 r	OEM2LOCK r	OEM1LOCK r	WDW r	BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OPTWERR rw						PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

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EOP

Bit 0: Non-secure end of operation This bit is set by hardware when one or more Flash memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_NSCR). This bit is cleared by writing 1..

OPERR

Bit 1: Non-secure operation error This bit is set by hardware when a Flash memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1..

PROGERR

Bit 3: Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1..

WRPERR

Bit 4: Non-secure write protection error This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. Refer to for full conditions of error flag setting..

PGAERR

Bit 5: Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1..

SIZERR

Bit 6: Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1..

PGSERR

Bit 7: Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting..

OPTWERR

Bit 13: Option write error This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. Refer to for full conditions of error flag setting..

BSY

Bit 16: Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs..

WDW

Bit 17: Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory..

OEM1LOCK

Bit 18: OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active..

OEM2LOCK

Bit 19: OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active..

PD1

Bit 20: Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken..

PD2

Bit 21: Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken..

FLASH_SECSR

FLASH secure status register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														WDW r	BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	RDERR rw							PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle fields

EOP

Bit 0: Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1..

OPERR

Bit 1: Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1..

PROGERR

Bit 3: Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1..

WRPERR

Bit 4: Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. Refer to for full conditions of error flag setting..

PGAERR

Bit 5: Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1..

SIZERR

Bit 6: Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1..

PGSERR

Bit 7: Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting..

RDERR

Bit 14: Secure readout protection error This bit is set by hardware when a read access is performed to a secure PCROP area and when a cacheable fetch access is performed to a secure PCROP area. An interrupt is generated if RDERRIE is set in FLASH_SECCR register. This bit is cleared by writing 1..

BSY

Bit 16: Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs..

WDW

Bit 17: Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory..

FLASH_NSCR

FLASH non-secure control register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	OPTLOCK rw			OBL_LAUNCH rw		ERRIE rw	EOPIE rw							OPTSTRT rw	STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MER2 rw	BWR rw			BKER rw	PNB rw								MER1 rw	PER rw	PG rw

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PG

Bit 0: Non-secure programming.

PER

Bit 1: Non-secure page erase.

MER1

Bit 2: Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set..

PNB

Bits 3-10: Non-secure page number selection These bits select the page to erase. ... ....

BKER

Bit 11: Non-secure bank selection for page erase.

BWR

Bit 14: Non-secure burst write programming mode When set, this bit selects the burst write programming mode..

MER2

Bit 15: Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set..

STRT

Bit 16: Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR..

OPTSTRT

Bit 17: Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR..

EOPIE

Bit 24: Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1..

ERRIE

Bit 25: Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1..

OBL_LAUNCH

Bit 27: Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set..

OPTLOCK

Bit 30: Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset..

LOCK

Bit 31: Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset..

FLASH_SECCR

FLASH secure control register

Offset: 0x2c, size: 32, reset: 0x80000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw		INV rw			RDERRIE rw	ERRIE rw	EOPIE rw								STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MER2 rw	BWR rw			BKER rw	PNB rw								MER1 rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Secure programming.

PER

Bit 1: Secure page erase.

MER1

Bit 2: Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set..

PNB

Bits 3-10: Secure page number selection These bits select the page to erase. ... ....

BKER

Bit 11: Secure bank selection for page erase.

BWR

Bit 14: Secure burst write programming mode When set, this bit selects the burst write programming mode..

MER2

Bit 15: Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set..

STRT

Bit 16: Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR..

EOPIE

Bit 24: Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1..

ERRIE

Bit 25: Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_SECSR is set to 1..

RDERRIE

Bit 26: Secure PCROP read error interrupt enable This bit enables the interrupt generation when the RDERR bit in the FLASH_SECSR is set to 1..

INV

Bit 29: Flash memory security state invert This bit inverts the Flash memory security state..

LOCK

Bit 31: Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset..

FLASH_ECCR

FLASH ECC register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

3/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECCD rw	ECCC rw						ECCIE rw		SYSF_ECC r	BK_ECC r	ADDR_ECC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_ECC r

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ADDR_ECC

Bits 0-20: ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given by bank from address 0x0 0000 to 0x1F FFF0..

BK_ECC

Bit 21: ECC fail bank This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection..

SYSF_ECC

Bit 22: System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory..

ECCIE

Bit 24: ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set..

ECCC

Bit 30: ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1..

ECCD

Bit 31: ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1..

FLASH_OPSR

FLASH operation status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CODE_OP r									SYSF_OP r	BK_OP r	ADDR_OP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_OP r

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ADDR_OP

Bits 0-20: Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0x1F FFF0..

BK_OP

Bit 21: Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred.

SYSF_OP

Bit 22: Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory..

CODE_OP

Bits 29-31: Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset:.

FLASH_OPTR

FLASH option register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TZEN rw	IO_VDDIO2_HSLV rw	IO_VDD_HSLV rw	PA15_PUPEN rw	nBOOT0 rw	nSWBOOT0 rw	SRAM2_RST rw	SRAM2_ECC rw		BKPRAM_ECC rw	DUALBANK rw	SWAP_BANK rw	WWDG_SW rw	IWDG_STDBY rw	IWDG_STOP rw	IWDG_SW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRAM1345_RST rw	nRST_SHDW rw	nRST_STDBY rw	nRST_STOP rw		BOR_LEV rw			RDP rw

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RDP

Bits 0-7: Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details..

BOR_LEV

Bits 8-10: BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset..

nRST_STOP

Bit 12: Reset generation in Stop mode.

nRST_STDBY

Bit 13: Reset generation in Standby mode.

nRST_SHDW

Bit 14: Reset generation in Shutdown mode.

SRAM1345_RST

Bit 15: SRAM1, SRAM4 and SRAM5 erase upon system reset.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

SWAP_BANK

Bit 20: Swap banks.

DUALBANK

Bit 21: Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices.

BKPRAM_ECC

Bit 22: Backup RAM ECC detection and correction enable.

SRAM2_ECC

Bit 24: SRAM2 ECC detection and correction enable.

SRAM2_RST

Bit 25: SRAM2 erase when system reset.

nSWBOOT0

Bit 26: Software BOOT0.

nBOOT0

Bit 27: nBOOT0 option bit.

PA15_PUPEN

Bit 28: PA15 pull-up enable.

IO_VDD_HSLV

Bit 29: High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V.

IO_VDDIO2_HSLV

Bit 30: High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V..

TZEN

Bit 31: Global TrustZone security enable.

FLASH_NSBOOTADD0R

FLASH non-secure boot address 0 register

Offset: 0x44, size: 32, reset: 0x0000000F, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSBOOTADD0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NSBOOTADD0 rw

Toggle fields

NSBOOTADD0

Bits 7-31: Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000).

FLASH_NSBOOTADD1R

FLASH non-secure boot address 1 register

Offset: 0x48, size: 32, reset: 0x0000000F, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSBOOTADD1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NSBOOTADD1 rw

Toggle fields

NSBOOTADD1

Bits 7-31: Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000).

FLASH_SECBOOTADD0R

FLASH secure boot address 0 register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SECBOOTADD0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SECBOOTADD0 rw															BOOT_LOCK rw

Toggle fields

BOOT_LOCK

Bit 0: Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0..

SECBOOTADD0

Bits 7-31: Secure boot base address 0 The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000).

FLASH_SECWM1R1

FLASH secure watermark1 register 1

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SECWM1_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SECWM1_PSTRT rw

Toggle fields

SECWM1_PSTRT

Bits 0-7: Start page of first secure area This field contains the first page of the secure area in bank 1..

SECWM1_PEND

Bits 16-23: End page of first secure area This field contains the last page of the secure area in bank 1..

FLASH_SECWM1R2

FLASH secure watermark1 register 2

Offset: 0x54, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HDP1EN rw								HDP1_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCROP1EN rw								PCROP1_PSTRT rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SECWM2_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SECWM2_PSTRT rw

Toggle fields

SECWM2_PSTRT

Bits 0-7: Start page of second secure area This field contains the first page of the secure area in bank 2..

SECWM2_PEND

Bits 16-23: End page of second secure area This field contains the last page of the secure area in bank 2..

FLASH_SECWM2R2

FLASH secure watermark2 register 2

Offset: 0x64, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HDP2EN rw								HDP2_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCROP2EN rw								PCROP2_PSTRT rw

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

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SEC1BB5

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SEC1BB6

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SEC1BB7

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SEC1BB8

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SEC1BB9

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SEC1BB10

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SEC1BB11

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SEC1BB12

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SEC1BB13

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SEC1BB14

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SEC1BB15

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SEC1BB16

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SEC1BB17

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SEC1BB18

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SEC1BB19

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR2

FLASH secure block based bank 1 register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

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SEC1BB4

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SEC1BB5

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SEC1BB6

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SEC1BB7

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SEC1BB8

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SEC1BB9

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SEC1BB10

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SEC1BB11

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SEC1BB12

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SEC1BB13

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SEC1BB14

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SEC1BB15

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SEC1BB16

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SEC1BB17

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SEC1BB18

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SEC1BB19

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR3

FLASH secure block based bank 1 register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

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SEC1BB5

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SEC1BB6

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SEC1BB7

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SEC1BB8

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SEC1BB9

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SEC1BB10

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SEC1BB11

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SEC1BB12

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SEC1BB13

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SEC1BB14

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SEC1BB15

Bit 15: .

SEC1BB16

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SEC1BB17

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SEC1BB18

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SEC1BB19

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR4

FLASH secure block based bank 1 register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

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SEC1BB6

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SEC1BB7

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SEC1BB8

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SEC1BB9

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SEC1BB10

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SEC1BB11

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SEC1BB12

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SEC1BB13

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SEC1BB14

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SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

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SEC1BB18

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SEC1BB19

Bit 19: .

SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR5

FLASH secure block based bank 1 register 5

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

Bit 9: .

SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

Bit 13: .

SEC1BB14

Bit 14: .

SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

Bit 17: .

SEC1BB18

Bit 18: .

SEC1BB19

Bit 19: .

SEC1BB20

Bit 20: .

SEC1BB21

Bit 21: .

SEC1BB22

Bit 22: .

SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR6

FLASH secure block based bank 1 register 6

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

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SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

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SEC1BB14

Bit 14: .

SEC1BB15

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SEC1BB16

Bit 16: .

SEC1BB17

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SEC1BB18

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SEC1BB19

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

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SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR7

FLASH secure block based bank 1 register 7

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

Bit 9: .

SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

Bit 13: .

SEC1BB14

Bit 14: .

SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

Bit 17: .

SEC1BB18

Bit 18: .

SEC1BB19

Bit 19: .

SEC1BB20

Bit 20: .

SEC1BB21

Bit 21: .

SEC1BB22

Bit 22: .

SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR8

FLASH secure block based bank 1 register 8

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

Bit 9: .

SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

Bit 13: .

SEC1BB14

Bit 14: .

SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

Bit 17: .

SEC1BB18

Bit 18: .

SEC1BB19

Bit 19: .

SEC1BB20

Bit 20: .

SEC1BB21

Bit 21: .

SEC1BB22

Bit 22: .

SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC2BBR1

FLASH secure block based bank 2 register 1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR2

FLASH secure block based bank 2 register 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR3

FLASH secure block based bank 2 register 3

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR4

FLASH secure block based bank 2 register 4

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR5

FLASH secure block based bank 2 register 5

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR6

FLASH secure block based bank 2 register 6

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR7

FLASH secure block based bank 2 register 7

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR8

FLASH secure block based bank 2 register 8

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SECHDPCR

FLASH secure HDP control register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														HDP2_ACCDIS rw	HDP1_ACCDIS rw

Toggle fields

HDP1_ACCDIS

Bit 0: HDP1 area access disable When set, this bit is only cleared by a system reset..

HDP2_ACCDIS

Bit 1: HDP2 area access disable When set, this bit is only cleared by a system reset..

FLASH_PRIVCFGR

FLASH privilege configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														NSPRIV rw	SPRIV rw

Toggle fields

SPRIV

Bit 0: Privileged protection for secure registers.

NSPRIV

Bit 1: Privileged protection for non-secure registers.

FLASH_PRIV1BBR1

FLASH privilege block based bank 1 register 1

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR2

FLASH privilege block based bank 1 register 2

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR3

FLASH privilege block based bank 1 register 3

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR4

FLASH privilege block based bank 1 register 4

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR5

FLASH privilege block based bank 1 register 5

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR6

FLASH privilege block based bank 1 register 6

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR7

FLASH privilege block based bank 1 register 7

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR8

FLASH privilege block based bank 1 register 8

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV2BBR1

FLASH privilege block based bank 2 register 1

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR2

FLASH privilege block based bank 2 register 2

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR3

FLASH privilege block based bank 2 register 3

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR4

FLASH privilege block based bank 2 register 4

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR5

FLASH privilege block based bank 2 register 5

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR6

FLASH privilege block based bank 2 register 6

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR7

FLASH privilege block based bank 2 register 7

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR8

FLASH privilege block based bank 2 register 8

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FMAC

0x40021400: Filter Math Accelerator

6/29 fields covered.

Toggle register map

Offset	Name	31	30	25	23	16	15	10	9	8	7	4	3	2	1	0
0x0	X1BUFCFG			FULL_WM			X1_BUF_SIZE				X1_BASE
0x4	X2BUFCFG						X2_BUF_SIZE				X2_BASE
0x8	YBUFCFG			EMPTY_WM			Y_BUF_SIZE				Y_BASE
0xc	PARAM	START	FUNC		R		Q				P
0x10	CR					RESET	CLIPEN		DMAWEN	DMAREN		SATIEN	UNFLIEN	OVFLIEN	WIEN	RIEN
0x14	SR							SAT	UNFL	OVFL					X1FULL	YEMPTY
0x18	WDATA						WDATA
0x1c	RDATA						RDATA

Toggle registers

X1BUFCFG

FMAC X1 Buffer Configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FULL_WM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
X1_BUF_SIZE rw								X1_BASE rw

Toggle fields

X1_BASE

Bits 0-7: Base address of X1 buffer.

X1_BUF_SIZE

Bits 8-15: Allocated size of X1 buffer in 16-bit words.

FULL_WM

Bits 24-25: Watermark for buffer full flag.

X2BUFCFG

FMAC X2 Buffer Configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
X2_BUF_SIZE rw								X2_BASE rw

Toggle fields

X2_BASE

Bits 0-7: Base address of X2 buffer.

X2_BUF_SIZE

Bits 8-15: Size of X2 buffer in 16-bit words.

YBUFCFG

FMAC Y Buffer Configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						EMPTY_WM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Y_BUF_SIZE rw								Y_BASE rw

Toggle fields

Y_BASE

Bits 0-7: Base address of Y buffer.

Y_BUF_SIZE

Bits 8-15: Size of Y buffer in 16-bit words.

EMPTY_WM

Bits 24-25: Watermark for buffer empty flag.

PARAM

FMAC Parameter register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
START rw	FUNC rw							R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Q rw								P rw

Toggle fields

P

Bits 0-7: Input parameter P.

Q

Bits 8-15: Input parameter Q.

R

Bits 16-23: Input parameter R.

FUNC

Bits 24-30: Function.

START

Bit 31: Enable execution.

CR

FMAC Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RESET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLIPEN rw						DMAWEN rw	DMAREN rw				SATIEN rw	UNFLIEN rw	OVFLIEN rw	WIEN rw	RIEN rw

Toggle fields

RIEN

Bit 0: Enable read interrupt.

WIEN

Bit 1: Enable write interrupt.

OVFLIEN

Bit 2: Enable overflow error interrupts.

UNFLIEN

Bit 3: Enable underflow error interrupts.

SATIEN

Bit 4: Enable saturation error interrupts.

DMAREN

Bit 8: Enable DMA read channel requests.

DMAWEN

Bit 9: Enable DMA write channel requests.

CLIPEN

Bit 15: Enable clipping.

RESET

Bit 16: Reset FMAC unit.

SR

FMAC Status register

Offset: 0x14, size: 32, reset: 0x00000001, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SAT r	UNFL r	OVFL r							X1FULL r	YEMPTY r

Toggle fields

YEMPTY

Bit 0: Y buffer empty flag.

X1FULL

Bit 1: X1 buffer full flag.

OVFL

Bit 8: Overflow error flag.

UNFL

Bit 9: Underflow error flag.

SAT

Bit 10: Saturation error flag.

WDATA

FMAC Write Data register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDATA w

Toggle fields

WDATA

Bits 0-15: Write data.

RDATA

FMAC Read Data register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA r

Toggle fields

RDATA

Bits 0-15: Read data.

GPDMA1

0x40020000: GPDMA1

160/900 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	21	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPDMA_SECCFGR													SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x4	GPDMA_PRIVCFGR													PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0xc	MISR													MIS15	MIS14	MIS13	MIS12	MIS11	MIS10	MIS9	MIS8	MIS7	MIS6	MIS5	MIS4	MIS3	MIS2	MIS1	MIS0
0x10	SMISR													MIS15	MIS14	MIS13	MIS12	MIS11	MIS10	MIS9	MIS8	MIS7	MIS6	MIS5	MIS4	MIS3	MIS2	MIS1	MIS0
0x50	GPDMA_C0LBAR	LBA
0x5c	GPDMA_C0FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x60	GPDMA_C0SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x64	GPDMA_C0CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x90	GPDMA_C0TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x94	GPDMA_C0TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x98	GPDMA_C0BR1													BNDT
0x9c	GPDMA_C0SAR	SA												SA
0xa0	GPDMA_C0DAR	DA												DA
0xcc	GPDMA_C0LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0xd0	GPDMA_C1LBAR	LBA
0xdc	GPDMA_C1FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0xe0	GPDMA_C1SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0xe4	GPDMA_C1CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x110	GPDMA_C1TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x114	GPDMA_C1TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x118	GPDMA_C1BR1													BNDT
0x11c	GPDMA_C1SAR	SA												SA
0x120	GPDMA_C1DAR	DA												DA
0x14c	GPDMA_C1LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x150	GPDMA_C2LBAR	LBA
0x15c	GPDMA_C2FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x160	GPDMA_C2SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x164	GPDMA_C2CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x190	GPDMA_C2TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x194	GPDMA_C2TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x198	GPDMA_C2BR1													BNDT
0x19c	GPDMA_C2SAR	SA												SA
0x1a0	GPDMA_C2DAR	DA												DA
0x1cc	GPDMA_C2LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x1d0	GPDMA_C3LBAR	LBA
0x1dc	GPDMA_C3FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x1e0	GPDMA_C3SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x1e4	GPDMA_C3CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x210	GPDMA_C3TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x214	GPDMA_C3TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x218	GPDMA_C3BR1													BNDT
0x21c	GPDMA_C3SAR	SA												SA
0x220	GPDMA_C3DAR	DA												DA
0x24c	GPDMA_C3LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x250	GPDMA_C4LBAR	LBA
0x25c	GPDMA_C4FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x260	GPDMA_C4SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x264	GPDMA_C4CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x294	GPDMA_C4TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x298	GPDMA_C4BR1													BNDT
0x29c	GPDMA_C4SAR	SA												SA
0x2a0	GPDMA_C4DAR	DA												DA
0x2cc	GPDMA_C4LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x2d0	GPDMA_C5LBAR	LBA
0x2dc	GPDMA_C5FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x2e0	GPDMA_C5SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x2e4	GPDMA_C5CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x314	GPDMA_C5TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x318	GPDMA_C5BR1													BNDT
0x31c	GPDMA_C5SAR	SA												SA
0x320	GPDMA_C5DAR	DA												DA
0x34c	GPDMA_C5LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x350	GPDMA_C6LBAR	LBA
0x35c	GPDMA_C6FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x360	GPDMA_C6SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x364	GPDMA_C6CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x394	GPDMA_C6TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x398	GPDMA_C6BR1													BNDT
0x39c	GPDMA_C6SAR	SA												SA
0x3a0	GPDMA_C6DAR	DA												DA
0x3cc	GPDMA_C6LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x3d0	GPDMA_C7LBAR	LBA
0x3dc	GPDMA_C7FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x3e0	GPDMA_C7SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x3e4	GPDMA_C7CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x414	GPDMA_C7TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x418	GPDMA_C7BR1													BNDT
0x41c	GPDMA_C7SAR	SA												SA
0x420	GPDMA_C7DAR	DA												DA
0x44c	GPDMA_C7LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x450	GPDMA_C8LBAR	LBA
0x45c	GPDMA_C8FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x460	GPDMA_C8SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x464	GPDMA_C8CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x494	GPDMA_C8TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x498	GPDMA_C8BR1													BNDT
0x49c	GPDMA_C8SAR	SA												SA
0x4a0	GPDMA_C8DAR	DA												DA
0x4cc	GPDMA_C8LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x4d0	GPDMA_C9LBAR	LBA
0x4dc	GPDMA_C9FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x4e0	GPDMA_C9SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x4e4	GPDMA_C9CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x514	GPDMA_C9TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x518	GPDMA_C9BR1													BNDT
0x51c	GPDMA_C9SAR	SA												SA
0x520	GPDMA_C9DAR	DA												DA
0x54c	GPDMA_C9LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x550	GPDMA_C10LBAR	LBA
0x55c	GPDMA_C10FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x560	GPDMA_C10SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x564	GPDMA_C10CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x594	GPDMA_C10TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x598	GPDMA_C10BR1													BNDT
0x59c	GPDMA_C10SAR	SA												SA
0x5a0	GPDMA_C10DAR	DA												DA
0x5cc	GPDMA_C10LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x5d0	GPDMA_C11LBAR	LBA
0x5dc	GPDMA_C11FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x5e0	GPDMA_C11SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x5e4	GPDMA_C11CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x614	GPDMA_C11TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x618	GPDMA_C11BR1													BNDT
0x61c	GPDMA_C11SAR	SA												SA
0x620	GPDMA_C11DAR	DA												DA
0x64c	GPDMA_C11LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x650	GPDMA_C12LBAR	LBA
0x65c	GPDMA_C12FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x660	GPDMA_C12SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x664	GPDMA_C12CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x694	GPDMA_C12TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x698	GPDMA_C12BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x69c	GPDMA_C12SAR	SA												SA
0x6a0	GPDMA_C12DAR	DA												DA
0x6a4	GPDMA_C12TR3				DAO												SAO
0x6a8	GPDMA_C12BR2	BRDAO												BRSAO
0x6cc	GPDMA_C12LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA
0x6d0	GPDMA_C13LBAR	LBA
0x6dc	GPDMA_C13FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x6e0	GPDMA_C13SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x6e4	GPDMA_C13CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x714	GPDMA_C13TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x718	GPDMA_C13BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x71c	GPDMA_C13SAR	SA												SA
0x720	GPDMA_C13DAR	DA												DA
0x724	GPDMA_C13TR3				DAO												SAO
0x728	GPDMA_C13BR2	BRDAO												BRSAO
0x74c	GPDMA_C13LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA
0x750	GPDMA_C14LBAR	LBA
0x75c	GPDMA_C14FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x760	GPDMA_C14SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x764	GPDMA_C14CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x794	GPDMA_C14TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x798	GPDMA_C14BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x79c	GPDMA_C14SAR	SA												SA
0x7a0	GPDMA_C14DAR	DA												DA
0x7a4	GPDMA_C14TR3				DAO												SAO
0x7a8	GPDMA_C14BR2	BRDAO												BRSAO
0x7cc	GPDMA_C14LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA
0x7d0	GPDMA_C15LBAR	LBA
0x7dc	GPDMA_C15FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x7e0	GPDMA_C15SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x7e4	GPDMA_C15CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x814	GPDMA_C15TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x818	GPDMA_C15BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x81c	GPDMA_C15SAR	SA												SA
0x820	GPDMA_C15DAR	DA												DA
0x824	GPDMA_C15TR3				DAO												SAO
0x828	GPDMA_C15BR2	BRDAO												BRSAO
0x84c	GPDMA_C15LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA

Toggle registers

GPDMA_SECCFGR

GPDMA secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

GPDMA_PRIVCFGR

GPDMA privileged configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

MISR

non-secure masked interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MIS15 r	MIS14 r	MIS13 r	MIS12 r	MIS11 r	MIS10 r	MIS9 r	MIS8 r	MIS7 r	MIS6 r	MIS5 r	MIS4 r	MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

MIS4

Bit 4: MIS4.

MIS5

Bit 5: MIS5.

MIS6

Bit 6: MIS6.

MIS7

Bit 7: MIS7.

MIS8

Bit 8: MIS8.

MIS9

Bit 9: MIS9.

MIS10

Bit 10: MIS10.

MIS11

Bit 11: MIS11.

MIS12

Bit 12: MIS12.

MIS13

Bit 13: MIS13.

MIS14

Bit 14: MIS14.

MIS15

Bit 15: MIS15.

SMISR

secure masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MIS15 r	MIS14 r	MIS13 r	MIS12 r	MIS11 r	MIS10 r	MIS9 r	MIS8 r	MIS7 r	MIS6 r	MIS5 r	MIS4 r	MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

MIS4

Bit 4: MIS4.

MIS5

Bit 5: MIS5.

MIS6

Bit 6: MIS6.

MIS7

Bit 7: MIS7.

MIS8

Bit 8: MIS8.

MIS9

Bit 9: MIS9.

MIS10

Bit 10: MIS10.

MIS11

Bit 11: MIS11.

MIS12

Bit 12: MIS12.

MIS13

Bit 13: MIS13.

MIS14

Bit 14: MIS14.

MIS15

Bit 15: MIS15.

GPDMA_C0LBAR

channel x linked-list base address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C0FCR

GPDMA channel x flag clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C0SR

channel x status register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C0CR

channel x control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C0TR1

GPDMA channel x transfer register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C0TR2

GPDMA channel x transfer register 2

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C0BR1

GPDMA channel x block register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

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BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C0SAR

GPDMA channel x source address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

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SA

Bits 0-31: source address.

GPDMA_C0DAR

GPDMA channel x destination address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

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DA

Bits 0-31: destination address.

GPDMA_C0LLR

GPDMA channel x linked-list address register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

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LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C1LBAR

channel x linked-list base address register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C1FCR

GPDMA channel x flag clear register

Offset: 0xdc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C1SR

channel x status register

Offset: 0xe0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

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IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C1CR

channel x control register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C1TR1

GPDMA channel x transfer register 1

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C1TR2

GPDMA channel x transfer register 2

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: TRIGM mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C1BR1

GPDMA channel x block register 1

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C1SAR

GPDMA channel x source address register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C1DAR

GPDMA channel x destination address register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C1LLR

GPDMA channel x linked-list address register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C2LBAR

channel x linked-list base address register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C2FCR

GPDMA channel x flag clear register

Offset: 0x15c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C2SR

channel x status register

Offset: 0x160, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C2CR

channel x control register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C2TR1

GPDMA channel x transfer register 1

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C2TR2

GPDMA channel x transfer register 2

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C2BR1

GPDMA channel x block register 1

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C2SAR

GPDMA channel x source address register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C2DAR

GPDMA channel x destination address register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C2LLR

GPDMA channel x linked-list address register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C3LBAR

channel x linked-list base address register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C3FCR

GPDMA channel x flag clear register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C3SR

channel x status register

Offset: 0x1e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C3CR

channel x control register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel. i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C3TR1

GPDMA channel x transfer register 1

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C3TR2

GPDMA channel x transfer register 2

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C3BR1

GPDMA channel x block register 1

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C3SAR

GPDMA channel x source address register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C3DAR

GPDMA channel x destination address register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C3LLR

GPDMA channel x linked-list address register

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C4LBAR

channel x linked-list base address register

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C4FCR

GPDMA channel x flag clear register

Offset: 0x25c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C4SR

channel x status register

Offset: 0x260, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C4CR

channel x control register

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C4TR2

GPDMA channel x transfer register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode.

GPDMA_C4BR1

GPDMA channel x block register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C4SAR

GPDMA channel x source address register

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C4DAR

GPDMA channel x destination address register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C4LLR

GPDMA channel x linked-list address register

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C5LBAR

channel x linked-list base address register

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C5FCR

GPDMA channel x flag clear register

Offset: 0x2dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C5SR

channel x status register

Offset: 0x2e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C5CR

channel x control register

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C5TR2

GPDMA channel x transfer register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C5BR1

GPDMA channel x block register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C5SAR

GPDMA channel x source address register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C5DAR

GPDMA channel x destination address register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C5LLR

GPDMA channel x linked-list address register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C6LBAR

channel x linked-list base address register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C6FCR

GPDMA channel x flag clear register

Offset: 0x35c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C6SR

channel x status register

Offset: 0x360, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C6CR

channel x control register

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C6TR2

GPDMA channel x transfer register 2

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C6BR1

GPDMA channel x block register 1

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C6SAR

GPDMA channel x source address register

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C6DAR

GPDMA channel x destination address register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C6LLR

GPDMA channel x linked-list address register

Offset: 0x3cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C7LBAR

channel x linked-list base address register

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C7FCR

GPDMA channel x flag clear register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C7SR

channel x status register

Offset: 0x3e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C7CR

channel x control register

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C7TR2

GPDMA channel x transfer register 2

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C7BR1

GPDMA channel x block register 1

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C7SAR

GPDMA channel x source address register

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C7DAR

GPDMA channel x destination address register

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C7LLR

GPDMA channel x linked-list address register

Offset: 0x44c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C8LBAR

channel x linked-list base address register

Offset: 0x450, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C8FCR

GPDMA channel x flag clear register

Offset: 0x45c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C8SR

channel x status register

Offset: 0x460, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C8CR

channel x control register

Offset: 0x464, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C8TR2

GPDMA channel x transfer register 2

Offset: 0x494, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C8BR1

GPDMA channel x block register 1

Offset: 0x498, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C8SAR

GPDMA channel x source address register

Offset: 0x49c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C8DAR

GPDMA channel x destination address register

Offset: 0x4a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C8LLR

GPDMA channel x linked-list address register

Offset: 0x4cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C9LBAR

channel x linked-list base address register

Offset: 0x4d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C9FCR

GPDMA channel x flag clear register

Offset: 0x4dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C9SR

channel x status register

Offset: 0x4e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C9CR

channel x control register

Offset: 0x4e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C9TR2

GPDMA channel x transfer register 2

Offset: 0x514, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C9BR1

GPDMA channel x block register 1

Offset: 0x518, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C9SAR

GPDMA channel x source address register

Offset: 0x51c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C9DAR

GPDMA channel x destination address register

Offset: 0x520, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C9LLR

GPDMA channel x linked-list address register

Offset: 0x54c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C10LBAR

channel x linked-list base address register

Offset: 0x550, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C10FCR

GPDMA channel x flag clear register

Offset: 0x55c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C10SR

channel x status register

Offset: 0x560, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C10CR

channel x control register

Offset: 0x564, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C10TR2

GPDMA channel x transfer register 2

Offset: 0x594, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C10BR1

GPDMA channel x block register 1

Offset: 0x598, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C10SAR

GPDMA channel x source address register

Offset: 0x59c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C10DAR

GPDMA channel x destination address register

Offset: 0x5a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C10LLR

GPDMA channel x linked-list address register

Offset: 0x5cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C11LBAR

channel x linked-list base address register

Offset: 0x5d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C11FCR

GPDMA channel x flag clear register

Offset: 0x5dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C11SR

channel x status register

Offset: 0x5e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C11CR

channel x control register

Offset: 0x5e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C11TR2

GPDMA channel x transfer register 2

Offset: 0x614, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C11BR1

GPDMA channel x block register 1

Offset: 0x618, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C11SAR

GPDMA channel x source address register

Offset: 0x61c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C11DAR

GPDMA channel x destination address register

Offset: 0x620, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C11LLR

GPDMA channel x linked-list address register

Offset: 0x64c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C12LBAR

channel x linked-list base address register

Offset: 0x650, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C12FCR

GPDMA channel x flag clear register

Offset: 0x65c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C12SR

channel x status register

Offset: 0x660, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C12CR

channel x control register

Offset: 0x664, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C12TR2

GPDMA channel x transfer register 2

Offset: 0x694, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C12BR1

GPDMA channel x block register 1

Offset: 0x698, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C12SAR

GPDMA channel x source address register

Offset: 0x69c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C12DAR

GPDMA channel x destination address register

Offset: 0x6a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C12TR3

GPDMA channel x transfer register 3

Offset: 0x6a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C12BR2

GPDMA channel x block register 2

Offset: 0x6a8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C12LLR

GPDMA channel x linked-list address register

Offset: 0x6cc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C13LBAR

channel x linked-list base address register

Offset: 0x6d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C13FCR

GPDMA channel x flag clear register

Offset: 0x6dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C13SR

channel x status register

Offset: 0x6e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C13CR

channel x control register

Offset: 0x6e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C13TR2

GPDMA channel x transfer register 2

Offset: 0x714, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C13BR1

GPDMA channel x block register 1

Offset: 0x718, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C13SAR

GPDMA channel x source address register

Offset: 0x71c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C13DAR

GPDMA channel x destination address register

Offset: 0x720, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C13TR3

GPDMA channel x transfer register 3

Offset: 0x724, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C13BR2

GPDMA channel x block register 2

Offset: 0x728, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C13LLR

GPDMA channel x linked-list address register

Offset: 0x74c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C14LBAR

channel x linked-list base address register

Offset: 0x750, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C14FCR

GPDMA channel x flag clear register

Offset: 0x75c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C14SR

channel x status register

Offset: 0x760, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C14CR

channel x control register

Offset: 0x764, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C14TR2

GPDMA channel x transfer register 2

Offset: 0x794, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C14BR1

GPDMA channel x block register 1

Offset: 0x798, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C14SAR

GPDMA channel x source address register

Offset: 0x79c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C14DAR

GPDMA channel x destination address register

Offset: 0x7a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C14TR3

GPDMA channel x transfer register 3

Offset: 0x7a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C14BR2

GPDMA channel x block register 2

Offset: 0x7a8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C14LLR

GPDMA channel x linked-list address register

Offset: 0x7cc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C15LBAR

channel x linked-list base address register

Offset: 0x7d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C15FCR

GPDMA channel x flag clear register

Offset: 0x7dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C15SR

channel x status register

Offset: 0x7e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C15CR

channel x control register

Offset: 0x7e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C15TR2

GPDMA channel x transfer register 2

Offset: 0x814, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C15BR1

GPDMA channel x block register 1

Offset: 0x818, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C15SAR

GPDMA channel x source address register

Offset: 0x81c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C15DAR

GPDMA channel x destination address register

Offset: 0x820, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C15TR3

GPDMA channel x transfer register 3

Offset: 0x824, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C15BR2

GPDMA channel x block register 2

Offset: 0x828, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C15LLR

GPDMA channel x linked-list address register

Offset: 0x84c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPIOA

0x42020000: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GPIOB

0x42020400: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GPIOC

0x42020800: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GPIOD

0x42020c00: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GPIOE

0x42021000: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GPIOG

0x42021800: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GPIOH

0x42021c00: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

GTZC1_MPCBB1

0x40032c00: GTZC1_MPCBB1

0/3383 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MPCBB1_CR	SRWILADIS	INVSECSTATE																														GLOCK
0x10	MPCBB1_CFGLOCK1	SPLCK31	SPLCK30	SPLCK29	SPLCK28	SPLCK27	SPLCK26	SPLCK25	SPLCK24	SPLCK23	SPLCK22	SPLCK21	SPLCK20	SPLCK19	SPLCK18	SPLCK17	SPLCK16	SPLCK15	SPLCK14	SPLCK13	SPLCK12	SPLCK11	SPLCK10	SPLCK9	SPLCK8	SPLCK7	SPLCK6	SPLCK5	SPLCK4	SPLCK3	SPLCK2	SPLCK1	SPLCK0
0x14	MPCBB1_CFGLOCK2													SPLCK51	SPLCK50	SPLCK49	SPLCK48	SPLCK47	SPLCK46	SPLCK45	SPLCK44	SPLCK43	SPLCK42	SPLCK41	SPLCK40	SPLCK39	SPLCK38	SPLCK37	SPLCK36	SPLCK35	SPLCK34	SPLCK33	SPLCK32
0x100	MPCBB1_SECCFGR0	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x104	MPCBB1_SECCFGR1	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x108	MPCBB1_SECCFGR2	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x10c	MPCBB1_SECCFGR3	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x110	MPCBB1_SECCFGR4	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x114	MPCBB1_SECCFGR5	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x118	MPCBB1_SECCFGR6	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x11c	MPCBB1_SECCFGR7	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x120	MPCBB1_SECCFGR8	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x124	MPCBB1_SECCFGR9	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x128	MPCBB1_SECCFGR10	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x12c	MPCBB1_SECCFGR11	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x130	MPCBB1_SECCFGR12	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x134	MPCBB1_SECCFGR13	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x138	MPCBB1_SECCFGR14	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x13c	MPCBB1_SECCFGR15	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x140	MPCBB1_SECCFGR16	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x144	MPCBB1_SECCFGR17	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x148	MPCBB1_SECCFGR18	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x14c	MPCBB1_SECCFGR19	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x150	MPCBB1_SECCFGR20	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x154	MPCBB1_SECCFGR21	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x158	MPCBB1_SECCFGR22	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x15c	MPCBB1_SECCFGR23	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x160	MPCBB1_SECCFGR24	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x164	MPCBB1_SECCFGR25	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x168	MPCBB1_SECCFGR26	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x16c	MPCBB1_SECCFGR27	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x170	MPCBB1_SECCFGR28	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x174	MPCBB1_SECCFGR29	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x178	MPCBB1_SECCFGR30	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x17c	MPCBB1_SECCFGR31	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x180	MPCBB1_SECCFGR32	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x184	MPCBB1_SECCFGR33	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x188	MPCBB1_SECCFGR34	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x18c	MPCBB1_SECCFGR35	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x190	MPCBB1_SECCFGR36	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x194	MPCBB1_SECCFGR37	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x198	MPCBB1_SECCFGR38	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x19c	MPCBB1_SECCFGR39	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a0	MPCBB1_SECCFGR40	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a4	MPCBB1_SECCFGR41	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a8	MPCBB1_SECCFGR42	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1ac	MPCBB1_SECCFGR43	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b0	MPCBB1_SECCFGR44	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b4	MPCBB1_SECCFGR45	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b8	MPCBB1_SECCFGR46	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1bc	MPCBB1_SECCFGR47	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c0	MPCBB1_SECCFGR48	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c4	MPCBB1_SECCFGR49	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c8	MPCBB1_SECCFGR50	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1cc	MPCBB1_SECCFGR51	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x200	MPCBB1_PRIVCFGR0	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x204	MPCBB1_PRIVCFGR1	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x208	MPCBB1_PRIVCFGR2	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x20c	MPCBB1_PRIVCFGR3	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x210	MPCBB1_PRIVCFGR4	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x214	MPCBB1_PRIVCFGR5	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x218	MPCBB1_PRIVCFGR6	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x21c	MPCBB1_PRIVCFGR7	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x220	MPCBB1_PRIVCFGR8	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x224	MPCBB1_PRIVCFGR9	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x228	MPCBB1_PRIVCFGR10	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x22c	MPCBB1_PRIVCFGR11	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x230	MPCBB1_PRIVCFGR12	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x234	MPCBB1_PRIVCFGR13	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x238	MPCBB1_PRIVCFGR14	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x23c	MPCBB1_PRIVCFGR15	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x240	MPCBB1_PRIVCFGR16	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x244	MPCBB1_PRIVCFGR17	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x248	MPCBB1_PRIVCFGR18	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x24c	MPCBB1_PRIVCFGR19	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x250	MPCBB1_PRIVCFGR20	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x254	MPCBB1_PRIVCFGR21	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x258	MPCBB1_PRIVCFGR22	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x25c	MPCBB1_PRIVCFGR23	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x260	MPCBB1_PRIVCFGR24	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x264	MPCBB1_PRIVCFGR25	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x268	MPCBB1_PRIVCFGR26	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x26c	MPCBB1_PRIVCFGR27	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x270	MPCBB1_PRIVCFGR28	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x274	MPCBB1_PRIVCFGR29	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x278	MPCBB1_PRIVCFGR30	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x27c	MPCBB1_PRIVCFGR31	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x280	MPCBB1_PRIVCFGR32	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x284	MPCBB1_PRIVCFGR33	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x288	MPCBB1_PRIVCFGR34	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x28c	MPCBB1_PRIVCFGR35	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x290	MPCBB1_PRIVCFGR36	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x294	MPCBB1_PRIVCFGR37	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x298	MPCBB1_PRIVCFGR38	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x29c	MPCBB1_PRIVCFGR39	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a0	MPCBB1_PRIVCFGR40	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a4	MPCBB1_PRIVCFGR41	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a8	MPCBB1_PRIVCFGR42	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2ac	MPCBB1_PRIVCFGR43	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b0	MPCBB1_PRIVCFGR44	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b4	MPCBB1_PRIVCFGR45	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b8	MPCBB1_PRIVCFGR46	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2bc	MPCBB1_PRIVCFGR47	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c0	MPCBB1_PRIVCFGR48	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c4	MPCBB1_PRIVCFGR49	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c8	MPCBB1_PRIVCFGR50	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2cc	MPCBB1_PRIVCFGR51	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0

Toggle registers

MPCBB1_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRWILADIS rw	INVSECSTATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															GLOCK rw

Toggle fields

GLOCK

Bit 0: lock the control register of the MPCBB until next reset.

INVSECSTATE

Bit 30: SRAMx clocks security state.

SRWILADIS

Bit 31: secure read/write illegal access disable.

MPCBB1_CFGLOCK1

GTZC1 SRAMz MPCBB configuration lock register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SPLCK31 rw	SPLCK30 rw	SPLCK29 rw	SPLCK28 rw	SPLCK27 rw	SPLCK26 rw	SPLCK25 rw	SPLCK24 rw	SPLCK23 rw	SPLCK22 rw	SPLCK21 rw	SPLCK20 rw	SPLCK19 rw	SPLCK18 rw	SPLCK17 rw	SPLCK16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK15 rw	SPLCK14 rw	SPLCK13 rw	SPLCK12 rw	SPLCK11 rw	SPLCK10 rw	SPLCK9 rw	SPLCK8 rw	SPLCK7 rw	SPLCK6 rw	SPLCK5 rw	SPLCK4 rw	SPLCK3 rw	SPLCK2 rw	SPLCK1 rw	SPLCK0 rw

Toggle fields

SPLCK0

Bit 0: SPLCK0.

SPLCK1

Bit 1: SPLCK1.

SPLCK2

Bit 2: SPLCK2.

SPLCK3

Bit 3: SPLCK3.

SPLCK4

Bit 4: SPLCK4.

SPLCK5

Bit 5: SPLCK5.

SPLCK6

Bit 6: SPLCK6.

SPLCK7

Bit 7: SPLCK7.

SPLCK8

Bit 8: SPLCK8.

SPLCK9

Bit 9: SPLCK9.

SPLCK10

Bit 10: SPLCK10.

SPLCK11

Bit 11: SPLCK11.

SPLCK12

Bit 12: SPLCK12.

SPLCK13

Bit 13: SPLCK13.

SPLCK14

Bit 14: SPLCK14.

SPLCK15

Bit 15: SPLCK15.

SPLCK16

Bit 16: SPLCK16.

SPLCK17

Bit 17: SPLCK17.

SPLCK18

Bit 18: SPLCK18.

SPLCK19

Bit 19: SPLCK19.

SPLCK20

Bit 20: SPLCK20.

SPLCK21

Bit 21: SPLCK21.

SPLCK22

Bit 22: SPLCK22.

SPLCK23

Bit 23: SPLCK23.

SPLCK24

Bit 24: SPLCK24.

SPLCK25

Bit 25: SPLCK25.

SPLCK26

Bit 26: SPLCK26.

SPLCK27

Bit 27: SPLCK27.

SPLCK28

Bit 28: SPLCK28.

SPLCK29

Bit 29: SPLCK29.

SPLCK30

Bit 30: SPLCK30.

SPLCK31

Bit 31: SPLCK31.

MPCBB1_CFGLOCK2

GTZC1 SRAMz MPCBB configuration lock register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												SPLCK51 rw	SPLCK50 rw	SPLCK49 rw	SPLCK48 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK47 rw	SPLCK46 rw	SPLCK45 rw	SPLCK44 rw	SPLCK43 rw	SPLCK42 rw	SPLCK41 rw	SPLCK40 rw	SPLCK39 rw	SPLCK38 rw	SPLCK37 rw	SPLCK36 rw	SPLCK35 rw	SPLCK34 rw	SPLCK33 rw	SPLCK32 rw

Toggle fields

SPLCK32

Bit 0: SPLCK32.

SPLCK33

Bit 1: SPLCK33.

SPLCK34

Bit 2: SPLCK34.

SPLCK35

Bit 3: SPLCK35.

SPLCK36

Bit 4: SPLCK36.

SPLCK37

Bit 5: SPLCK37.

SPLCK38

Bit 6: SPLCK38.

SPLCK39

Bit 7: SPLCK39.

SPLCK40

Bit 8: SPLCK40.

SPLCK41

Bit 9: SPLCK41.

SPLCK42

Bit 10: SPLCK42.

SPLCK43

Bit 11: SPLCK43.

SPLCK44

Bit 12: SPLCK44.

SPLCK45

Bit 13: SPLCK45.

SPLCK46

Bit 14: SPLCK46.

SPLCK47

Bit 15: SPLCK47.

SPLCK48

Bit 16: SPLCK48.

SPLCK49

Bit 17: SPLCK49.

SPLCK50

Bit 18: SPLCK50.

SPLCK51

Bit 19: SPLCK51.

MPCBB1_SECCFGR0

MPCBBx security configuration for super-block x register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR1

MPCBBx security configuration for super-block x register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR2

MPCBBx security configuration for super-block x register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR3

MPCBBx security configuration for super-block x register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR4

MPCBBx security configuration for super-block x register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR5

MPCBBx security configuration for super-block x register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR6

MPCBBx security configuration for super-block x register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR7

MPCBBx security configuration for super-block x register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR8

MPCBBx security configuration for super-block x register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR9

MPCBBx security configuration for super-block x register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR10

MPCBBx security configuration for super-block x register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR11

MPCBBx security configuration for super-block x register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR12

MPCBBx security configuration for super-block x register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR13

MPCBBx security configuration for super-block x register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR14

MPCBBx security configuration for super-block x register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR15

MPCBBx security configuration for super-block x register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR16

MPCBBx security configuration for super-block x register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR17

MPCBBx security configuration for super-block x register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR18

MPCBBx security configuration for super-block x register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR19

MPCBBx security configuration for super-block x register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR20

MPCBBx security configuration for super-block x register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR21

MPCBBx security configuration for super-block x register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR22

MPCBBx security configuration for super-block x register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR23

MPCBBx security configuration for super-block x register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR24

MPCBBx security configuration for super-block x register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR25

MPCBBx security configuration for super-block x register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR26

MPCBBx security configuration for super-block x register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR27

MPCBBx security configuration for super-block x register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR28

MPCBBx security configuration for super-block x register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR29

MPCBBx security configuration for super-block x register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR30

MPCBBx security configuration for super-block x register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR31

MPCBBx security configuration for super-block x register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR32

MPCBBx security configuration for super-block x register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR33

MPCBBx security configuration for super-block x register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR34

MPCBBx security configuration for super-block x register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR35

MPCBBx security configuration for super-block x register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR36

MPCBBx security configuration for super-block x register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR37

MPCBBx security configuration for super-block x register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR38

MPCBBx security configuration for super-block x register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR39

MPCBBx security configuration for super-block x register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR40

MPCBBx security configuration for super-block x register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR41

MPCBBx security configuration for super-block x register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR42

MPCBBx security configuration for super-block x register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR43

MPCBBx security configuration for super-block x register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR44

MPCBBx security configuration for super-block x register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR45

MPCBBx security configuration for super-block x register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR46

MPCBBx security configuration for super-block x register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR47

MPCBBx security configuration for super-block x register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR48

MPCBBx security configuration for super-block x register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR49

MPCBBx security configuration for super-block x register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR50

MPCBBx security configuration for super-block x register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR51

MPCBBx security configuration for super-block x register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_PRIVCFGR0

MPCBB privileged configuration for super-block x register

Offset: 0x200, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR1

MPCBB privileged configuration for super-block x register

Offset: 0x204, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR2

MPCBB privileged configuration for super-block x register

Offset: 0x208, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR3

MPCBB privileged configuration for super-block x register

Offset: 0x20c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR4

MPCBB privileged configuration for super-block x register

Offset: 0x210, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR5

MPCBB privileged configuration for super-block x register

Offset: 0x214, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR6

MPCBB privileged configuration for super-block x register

Offset: 0x218, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR7

MPCBB privileged configuration for super-block x register

Offset: 0x21c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR8

MPCBB privileged configuration for super-block x register

Offset: 0x220, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR9

MPCBB privileged configuration for super-block x register

Offset: 0x224, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR10

MPCBB privileged configuration for super-block x register

Offset: 0x228, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR11

MPCBB privileged configuration for super-block x register

Offset: 0x22c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR12

MPCBB privileged configuration for super-block x register

Offset: 0x230, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR13

MPCBB privileged configuration for super-block x register

Offset: 0x234, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR14

MPCBB privileged configuration for super-block x register

Offset: 0x238, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR15

MPCBB privileged configuration for super-block x register

Offset: 0x23c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR16

MPCBB privileged configuration for super-block x register

Offset: 0x240, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR17

MPCBB privileged configuration for super-block x register

Offset: 0x244, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR18

MPCBB privileged configuration for super-block x register

Offset: 0x248, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR19

MPCBB privileged configuration for super-block x register

Offset: 0x24c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR20

MPCBB privileged configuration for super-block x register

Offset: 0x250, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR21

MPCBB privileged configuration for super-block x register

Offset: 0x254, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR22

MPCBB privileged configuration for super-block x register

Offset: 0x258, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR23

MPCBB privileged configuration for super-block x register

Offset: 0x25c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR24

MPCBB privileged configuration for super-block x register

Offset: 0x260, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR25

MPCBB privileged configuration for super-block x register

Offset: 0x264, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR26

MPCBB privileged configuration for super-block x register

Offset: 0x268, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR27

MPCBB privileged configuration for super-block x register

Offset: 0x26c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR28

MPCBB privileged configuration for super-block x register

Offset: 0x270, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR29

MPCBB privileged configuration for super-block x register

Offset: 0x274, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR30

MPCBB privileged configuration for super-block x register

Offset: 0x278, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR31

MPCBB privileged configuration for super-block x register

Offset: 0x27c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR32

MPCBB privileged configuration for super-block x register

Offset: 0x280, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR33

MPCBB privileged configuration for super-block x register

Offset: 0x284, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR34

MPCBB privileged configuration for super-block x register

Offset: 0x288, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR35

MPCBB privileged configuration for super-block x register

Offset: 0x28c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR36

MPCBB privileged configuration for super-block x register

Offset: 0x290, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR37

MPCBB privileged configuration for super-block x register

Offset: 0x294, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR38

MPCBB privileged configuration for super-block x register

Offset: 0x298, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR39

MPCBB privileged configuration for super-block x register

Offset: 0x29c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR40

MPCBB privileged configuration for super-block x register

Offset: 0x2a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR41

MPCBB privileged configuration for super-block x register

Offset: 0x2a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR42

MPCBB privileged configuration for super-block x register

Offset: 0x2a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR43

MPCBB privileged configuration for super-block x register

Offset: 0x2ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR44

MPCBB privileged configuration for super-block x register

Offset: 0x2b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR45

MPCBB privileged configuration for super-block x register

Offset: 0x2b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR46

MPCBB privileged configuration for super-block x register

Offset: 0x2b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR47

MPCBB privileged configuration for super-block x register

Offset: 0x2bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR48

MPCBB privileged configuration for super-block x register

Offset: 0x2c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR49

MPCBB privileged configuration for super-block x register

Offset: 0x2c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR50

MPCBB privileged configuration for super-block x register

Offset: 0x2c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR51

MPCBB privileged configuration for super-block x register

Offset: 0x2cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

GTZC1_MPCBB2

0x40033000: GTZC1_MPCBB2

0/3383 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MPCBB2_CR	SRWILADIS	INVSECSTATE																														GLOCK
0x10	MPCBB2_CFGLOCK1	SPLCK31	SPLCK30	SPLCK29	SPLCK28	SPLCK27	SPLCK26	SPLCK25	SPLCK24	SPLCK23	SPLCK22	SPLCK21	SPLCK20	SPLCK19	SPLCK18	SPLCK17	SPLCK16	SPLCK15	SPLCK14	SPLCK13	SPLCK12	SPLCK11	SPLCK10	SPLCK9	SPLCK8	SPLCK7	SPLCK6	SPLCK5	SPLCK4	SPLCK3	SPLCK2	SPLCK1	SPLCK0
0x14	MPCBB2_CFGLOCK2													SPLCK51	SPLCK50	SPLCK49	SPLCK48	SPLCK47	SPLCK46	SPLCK45	SPLCK44	SPLCK43	SPLCK42	SPLCK41	SPLCK40	SPLCK39	SPLCK38	SPLCK37	SPLCK36	SPLCK35	SPLCK34	SPLCK33	SPLCK32
0x100	MPCBB2_SECCFGR0	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x104	MPCBB2_SECCFGR1	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x108	MPCBB2_SECCFGR2	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x10c	MPCBB2_SECCFGR3	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x110	MPCBB2_SECCFGR4	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x114	MPCBB2_SECCFGR5	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x118	MPCBB2_SECCFGR6	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x11c	MPCBB2_SECCFGR7	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x120	MPCBB2_SECCFGR8	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x124	MPCBB2_SECCFGR9	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x128	MPCBB2_SECCFGR10	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x12c	MPCBB2_SECCFGR11	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x130	MPCBB2_SECCFGR12	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x134	MPCBB2_SECCFGR13	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x138	MPCBB2_SECCFGR14	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x13c	MPCBB2_SECCFGR15	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x140	MPCBB2_SECCFGR16	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x144	MPCBB2_SECCFGR17	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x148	MPCBB2_SECCFGR18	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x14c	MPCBB2_SECCFGR19	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x150	MPCBB2_SECCFGR20	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x154	MPCBB2_SECCFGR21	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x158	MPCBB2_SECCFGR22	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x15c	MPCBB2_SECCFGR23	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x160	MPCBB2_SECCFGR24	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x164	MPCBB2_SECCFGR25	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x168	MPCBB2_SECCFGR26	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x16c	MPCBB2_SECCFGR27	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x170	MPCBB2_SECCFGR28	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x174	MPCBB2_SECCFGR29	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x178	MPCBB2_SECCFGR30	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x17c	MPCBB2_SECCFGR31	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x180	MPCBB2_SECCFGR32	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x184	MPCBB2_SECCFGR33	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x188	MPCBB2_SECCFGR34	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x18c	MPCBB2_SECCFGR35	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x190	MPCBB2_SECCFGR36	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x194	MPCBB2_SECCFGR37	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x198	MPCBB2_SECCFGR38	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x19c	MPCBB2_SECCFGR39	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a0	MPCBB2_SECCFGR40	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a4	MPCBB2_SECCFGR41	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a8	MPCBB2_SECCFGR42	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1ac	MPCBB2_SECCFGR43	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b0	MPCBB2_SECCFGR44	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b4	MPCBB2_SECCFGR45	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b8	MPCBB2_SECCFGR46	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1bc	MPCBB2_SECCFGR47	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c0	MPCBB2_SECCFGR48	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c4	MPCBB2_SECCFGR49	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c8	MPCBB2_SECCFGR50	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1cc	MPCBB2_SECCFGR51	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x200	MPCBB2_PRIVCFGR0	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x204	MPCBB2_PRIVCFGR1	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x208	MPCBB2_PRIVCFGR2	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x20c	MPCBB2_PRIVCFGR3	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x210	MPCBB2_PRIVCFGR4	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x214	MPCBB2_PRIVCFGR5	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x218	MPCBB2_PRIVCFGR6	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x21c	MPCBB2_PRIVCFGR7	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x220	MPCBB2_PRIVCFGR8	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x224	MPCBB2_PRIVCFGR9	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x228	MPCBB2_PRIVCFGR10	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x22c	MPCBB2_PRIVCFGR11	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x230	MPCBB2_PRIVCFGR12	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x234	MPCBB2_PRIVCFGR13	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x238	MPCBB2_PRIVCFGR14	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x23c	MPCBB2_PRIVCFGR15	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x240	MPCBB2_PRIVCFGR16	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x244	MPCBB2_PRIVCFGR17	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x248	MPCBB2_PRIVCFGR18	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x24c	MPCBB2_PRIVCFGR19	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x250	MPCBB2_PRIVCFGR20	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x254	MPCBB2_PRIVCFGR21	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x258	MPCBB2_PRIVCFGR22	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x25c	MPCBB2_PRIVCFGR23	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x260	MPCBB2_PRIVCFGR24	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x264	MPCBB2_PRIVCFGR25	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x268	MPCBB2_PRIVCFGR26	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x26c	MPCBB2_PRIVCFGR27	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x270	MPCBB2_PRIVCFGR28	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x274	MPCBB2_PRIVCFGR29	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x278	MPCBB2_PRIVCFGR30	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x27c	MPCBB2_PRIVCFGR31	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x280	MPCBB2_PRIVCFGR32	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x284	MPCBB2_PRIVCFGR33	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x288	MPCBB2_PRIVCFGR34	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x28c	MPCBB2_PRIVCFGR35	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x290	MPCBB2_PRIVCFGR36	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x294	MPCBB2_PRIVCFGR37	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x298	MPCBB2_PRIVCFGR38	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x29c	MPCBB2_PRIVCFGR39	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a0	MPCBB2_PRIVCFGR40	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a4	MPCBB2_PRIVCFGR41	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a8	MPCBB2_PRIVCFGR42	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2ac	MPCBB2_PRIVCFGR43	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b0	MPCBB2_PRIVCFGR44	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b4	MPCBB2_PRIVCFGR45	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b8	MPCBB2_PRIVCFGR46	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2bc	MPCBB2_PRIVCFGR47	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c0	MPCBB2_PRIVCFGR48	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c4	MPCBB2_PRIVCFGR49	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c8	MPCBB2_PRIVCFGR50	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2cc	MPCBB2_PRIVCFGR51	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0

Toggle registers

MPCBB2_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRWILADIS rw	INVSECSTATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															GLOCK rw

Toggle fields

GLOCK

Bit 0: lock the control register of the MPCBB until next reset.

INVSECSTATE

Bit 30: SRAMx clocks security state.

SRWILADIS

Bit 31: secure read/write illegal access disable.

MPCBB2_CFGLOCK1

GTZC1 SRAMz MPCBB configuration lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SPLCK31 rw	SPLCK30 rw	SPLCK29 rw	SPLCK28 rw	SPLCK27 rw	SPLCK26 rw	SPLCK25 rw	SPLCK24 rw	SPLCK23 rw	SPLCK22 rw	SPLCK21 rw	SPLCK20 rw	SPLCK19 rw	SPLCK18 rw	SPLCK17 rw	SPLCK16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK15 rw	SPLCK14 rw	SPLCK13 rw	SPLCK12 rw	SPLCK11 rw	SPLCK10 rw	SPLCK9 rw	SPLCK8 rw	SPLCK7 rw	SPLCK6 rw	SPLCK5 rw	SPLCK4 rw	SPLCK3 rw	SPLCK2 rw	SPLCK1 rw	SPLCK0 rw

Toggle fields

SPLCK0

Bit 0: SPLCK0.

SPLCK1

Bit 1: SPLCK1.

SPLCK2

Bit 2: SPLCK2.

SPLCK3

Bit 3: SPLCK3.

SPLCK4

Bit 4: SPLCK4.

SPLCK5

Bit 5: SPLCK5.

SPLCK6

Bit 6: SPLCK6.

SPLCK7

Bit 7: SPLCK7.

SPLCK8

Bit 8: SPLCK8.

SPLCK9

Bit 9: SPLCK9.

SPLCK10

Bit 10: SPLCK10.

SPLCK11

Bit 11: SPLCK11.

SPLCK12

Bit 12: SPLCK12.

SPLCK13

Bit 13: SPLCK13.

SPLCK14

Bit 14: SPLCK14.

SPLCK15

Bit 15: SPLCK15.

SPLCK16

Bit 16: SPLCK16.

SPLCK17

Bit 17: SPLCK17.

SPLCK18

Bit 18: SPLCK18.

SPLCK19

Bit 19: SPLCK19.

SPLCK20

Bit 20: SPLCK20.

SPLCK21

Bit 21: SPLCK21.

SPLCK22

Bit 22: SPLCK22.

SPLCK23

Bit 23: SPLCK23.

SPLCK24

Bit 24: SPLCK24.

SPLCK25

Bit 25: SPLCK25.

SPLCK26

Bit 26: SPLCK26.

SPLCK27

Bit 27: SPLCK27.

SPLCK28

Bit 28: SPLCK28.

SPLCK29

Bit 29: SPLCK29.

SPLCK30

Bit 30: SPLCK30.

SPLCK31

Bit 31: SPLCK31.

MPCBB2_CFGLOCK2

GTZC1 SRAMz MPCBB configuration lock register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												SPLCK51 rw	SPLCK50 rw	SPLCK49 rw	SPLCK48 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK47 rw	SPLCK46 rw	SPLCK45 rw	SPLCK44 rw	SPLCK43 rw	SPLCK42 rw	SPLCK41 rw	SPLCK40 rw	SPLCK39 rw	SPLCK38 rw	SPLCK37 rw	SPLCK36 rw	SPLCK35 rw	SPLCK34 rw	SPLCK33 rw	SPLCK32 rw

Toggle fields

SPLCK32

Bit 0: SPLCK32.

SPLCK33

Bit 1: SPLCK33.

SPLCK34

Bit 2: SPLCK34.

SPLCK35

Bit 3: SPLCK35.

SPLCK36

Bit 4: SPLCK36.

SPLCK37

Bit 5: SPLCK37.

SPLCK38

Bit 6: SPLCK38.

SPLCK39

Bit 7: SPLCK39.

SPLCK40

Bit 8: SPLCK40.

SPLCK41

Bit 9: SPLCK41.

SPLCK42

Bit 10: SPLCK42.

SPLCK43

Bit 11: SPLCK43.

SPLCK44

Bit 12: SPLCK44.

SPLCK45

Bit 13: SPLCK45.

SPLCK46

Bit 14: SPLCK46.

SPLCK47

Bit 15: SPLCK47.

SPLCK48

Bit 16: SPLCK48.

SPLCK49

Bit 17: SPLCK49.

SPLCK50

Bit 18: SPLCK50.

SPLCK51

Bit 19: SPLCK51.

MPCBB2_SECCFGR0

MPCBBx security configuration for super-block x register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR1

MPCBBx security configuration for super-block x register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR2

MPCBBx security configuration for super-block x register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR3

MPCBBx security configuration for super-block x register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR4

MPCBBx security configuration for super-block x register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR5

MPCBBx security configuration for super-block x register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR6

MPCBBx security configuration for super-block x register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR7

MPCBBx security configuration for super-block x register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR8

MPCBBx security configuration for super-block x register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR9

MPCBBx security configuration for super-block x register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR10

MPCBBx security configuration for super-block x register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR11

MPCBBx security configuration for super-block x register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR12

MPCBBx security configuration for super-block x register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR13

MPCBBx security configuration for super-block x register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR14

MPCBBx security configuration for super-block x register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR15

MPCBBx security configuration for super-block x register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR16

MPCBBx security configuration for super-block x register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR17

MPCBBx security configuration for super-block x register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR18

MPCBBx security configuration for super-block x register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR19

MPCBBx security configuration for super-block x register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR20

MPCBBx security configuration for super-block x register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR21

MPCBBx security configuration for super-block x register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR22

MPCBBx security configuration for super-block x register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR23

MPCBBx security configuration for super-block x register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR24

MPCBBx security configuration for super-block x register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR25

MPCBBx security configuration for super-block x register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR26

MPCBBx security configuration for super-block x register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR27

MPCBBx security configuration for super-block x register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR28

MPCBBx security configuration for super-block x register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR29

MPCBBx security configuration for super-block x register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR30

MPCBBx security configuration for super-block x register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR31

MPCBBx security configuration for super-block x register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR32

MPCBBx security configuration for super-block x register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR33

MPCBBx security configuration for super-block x register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR34

MPCBBx security configuration for super-block x register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR35

MPCBBx security configuration for super-block x register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR36

MPCBBx security configuration for super-block x register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR37

MPCBBx security configuration for super-block x register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR38

MPCBBx security configuration for super-block x register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR39

MPCBBx security configuration for super-block x register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR40

MPCBBx security configuration for super-block x register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR41

MPCBBx security configuration for super-block x register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR42

MPCBBx security configuration for super-block x register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR43

MPCBBx security configuration for super-block x register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR44

MPCBBx security configuration for super-block x register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR45

MPCBBx security configuration for super-block x register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR46

MPCBBx security configuration for super-block x register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR47

MPCBBx security configuration for super-block x register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR48

MPCBBx security configuration for super-block x register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR49

MPCBBx security configuration for super-block x register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR50

MPCBBx security configuration for super-block x register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR51

MPCBBx security configuration for super-block x register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_PRIVCFGR0

MPCBB privileged configuration for super-block x register

Offset: 0x200, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR1

MPCBB privileged configuration for super-block x register

Offset: 0x204, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR2

MPCBB privileged configuration for super-block x register

Offset: 0x208, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR3

MPCBB privileged configuration for super-block x register

Offset: 0x20c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR4

MPCBB privileged configuration for super-block x register

Offset: 0x210, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR5

MPCBB privileged configuration for super-block x register

Offset: 0x214, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR6

MPCBB privileged configuration for super-block x register

Offset: 0x218, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR7

MPCBB privileged configuration for super-block x register

Offset: 0x21c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR8

MPCBB privileged configuration for super-block x register

Offset: 0x220, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR9

MPCBB privileged configuration for super-block x register

Offset: 0x224, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR10

MPCBB privileged configuration for super-block x register

Offset: 0x228, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR11

MPCBB privileged configuration for super-block x register

Offset: 0x22c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR12

MPCBB privileged configuration for super-block x register

Offset: 0x230, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR13

MPCBB privileged configuration for super-block x register

Offset: 0x234, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR14

MPCBB privileged configuration for super-block x register

Offset: 0x238, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR15

MPCBB privileged configuration for super-block x register

Offset: 0x23c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR16

MPCBB privileged configuration for super-block x register

Offset: 0x240, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR17

MPCBB privileged configuration for super-block x register

Offset: 0x244, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR18

MPCBB privileged configuration for super-block x register

Offset: 0x248, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR19

MPCBB privileged configuration for super-block x register

Offset: 0x24c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR20

MPCBB privileged configuration for super-block x register

Offset: 0x250, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR21

MPCBB privileged configuration for super-block x register

Offset: 0x254, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR22

MPCBB privileged configuration for super-block x register

Offset: 0x258, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR23

MPCBB privileged configuration for super-block x register

Offset: 0x25c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR24

MPCBB privileged configuration for super-block x register

Offset: 0x260, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR25

MPCBB privileged configuration for super-block x register

Offset: 0x264, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR26

MPCBB privileged configuration for super-block x register

Offset: 0x268, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR27

MPCBB privileged configuration for super-block x register

Offset: 0x26c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR28

MPCBB privileged configuration for super-block x register

Offset: 0x270, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR29

MPCBB privileged configuration for super-block x register

Offset: 0x274, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR30

MPCBB privileged configuration for super-block x register

Offset: 0x278, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR31

MPCBB privileged configuration for super-block x register

Offset: 0x27c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR32

MPCBB privileged configuration for super-block x register

Offset: 0x280, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR33

MPCBB privileged configuration for super-block x register

Offset: 0x284, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR34

MPCBB privileged configuration for super-block x register

Offset: 0x288, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR35

MPCBB privileged configuration for super-block x register

Offset: 0x28c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR36

MPCBB privileged configuration for super-block x register

Offset: 0x290, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR37

MPCBB privileged configuration for super-block x register

Offset: 0x294, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR38

MPCBB privileged configuration for super-block x register

Offset: 0x298, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR39

MPCBB privileged configuration for super-block x register

Offset: 0x29c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR40

MPCBB privileged configuration for super-block x register

Offset: 0x2a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR41

MPCBB privileged configuration for super-block x register

Offset: 0x2a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR42

MPCBB privileged configuration for super-block x register

Offset: 0x2a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR43

MPCBB privileged configuration for super-block x register

Offset: 0x2ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR44

MPCBB privileged configuration for super-block x register

Offset: 0x2b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR45

MPCBB privileged configuration for super-block x register

Offset: 0x2b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR46

MPCBB privileged configuration for super-block x register

Offset: 0x2b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR47

MPCBB privileged configuration for super-block x register

Offset: 0x2bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR48

MPCBB privileged configuration for super-block x register

Offset: 0x2c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR49

MPCBB privileged configuration for super-block x register

Offset: 0x2c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR50

MPCBB privileged configuration for super-block x register

Offset: 0x2c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR51

MPCBB privileged configuration for super-block x register

Offset: 0x2cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

GTZC1_TZIC

0x40032800: GTZC1_TZIC

55/164 fields covered.

Toggle register map

Offset	Name	30	27	26	25	24	23	22	20	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IER1									FDCAN1IE	LPTIM2IE	I2C4IE	CRSIE	I2C2IE	I2C1IE	UART5IE	USART4IE	USART3IE		SPI2IE	IWDGIE	WWDGIE	TIM7IE	TIM6IE	TIM5IE	TIM4IE	TIM3IE	TIM2IE
0x4	IER2																				SAI1IE	TIM17IE	TIM16IE	TIM15IE	USART1IE	TIM8IE	SPI1IE	TIM1IE
0x8	IER3			HSPI1_REGIE			GPU2DIE	RAMCFGIE	OCTOSPI1_REGIE		SDMMC1IE				RNGIE	HASHIE			DCMIIE	ADC1I2E	DCACHE1_REGIE	ICACHE_REGIE		TSCIE	CRCIE	FMACIE	CORDICIE	MDF1IE
0xc	IER4	SRAM5IE	MPCBB2_REGIE	SRAM2IE	MPCBB1_REGIE	SRAM1IE			HSPI1_MEMIE	BKPSRAMIE		OCTOSPI1_MEMIE	TZIC1IE	TZSC1IE												FLASHIE	FLASH_REGIE	GPDMA1IE
0x10	SR1									FDCAN1F	LPTIM2F	I2C4F	CRSF	I2C2F	I2C1F	UART5F	UART4F	USART3F		SPI2F	IWDGF	WWDGF	TIM7F	TIM6F	TIM5F	TIM4F	TIM3F	TIM2F
0x14	SR2																				SAI1F	TIM17F	TIM16F	TIM15F	USART1F	TIM8F	SPI1F	TIM1F
0x18	SR3			HSPI1_REGF			GPU2DF	RAMCFGF	OCTOSPI1_REGF		SDMMC1F				RNGF	HASHF			DCMIF	ADC12F	DCACHE1_REGF	ICACHE_REGF		TSCF	CRCF	FMACF	CORDICF	MDF1F
0x1c	SR4	SRAM5F	MPCBB2_REGF	SRAM2F	MPCBB1_REGF	SRAM1F			HSPI1_MEMF	BKPSRAMF		OCTOSPI1_MEMF	TZIC1F	TZSC1F												FLASHF	FLASH_REGF	GPDMA1F
0x20	FCR1									CFDCAN1F	CLPTIM2F	CI2C4F	CCRSF	CI2C2F	CI2C1F	CUART5F	CUART4F	CUSART3F		CSPI2F	CIWDGF	CWWDGF	CTIM7F	CTIM6F	CTIM5F	CTIM4F	CTIM3F	CTIM2F
0x24	FCR2																				CSAI1F	CTIM17F	CTIM16F	CTIM15F	CUSART1F	CTIM8F	CSPI1F	CTIM1F
0x28	FCR3						CGPU2DF	CRAMCFGF	COCTOSPI1_REGF		CSDMMC1F				CRNGF	CHASHF			CDCMIF	CADC12F	CDCACHE1_REGF	CICACHE_REGF		CTSCF	CCRCF	CFMACF	CCORDICF	CMDF1F
0x2c	FCR4	CSRAM5F	CMPCBB2_REGF	CSRAM2F	CMPCBB1_REGF	CSRAM1F			CHSPI1_MEMF	CBKPSRAMF		COCTOSPI1_MEMF	CTZIC1F	CTZSC1F												CFLASHF	CFLASH_REGF	CGPDMA1F

Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1IE rw	LPTIM2IE rw	I2C4IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSIE rw	I2C2IE rw	I2C1IE rw	UART5IE rw	USART4IE rw	USART3IE rw		SPI2IE rw	IWDGIE rw	WWDGIE rw	TIM7IE rw	TIM6IE rw	TIM5IE rw	TIM4IE rw	TIM3IE rw	TIM2IE rw

Toggle fields

TIM2IE

Bit 0: TIM2IE.

TIM3IE

Bit 1: TIM3IE.

TIM4IE

Bit 2: TIM4IE.

TIM5IE

Bit 3: TIM5IE.

TIM6IE

Bit 4: TIM6IE.

TIM7IE

Bit 5: TIM7IE.

WWDGIE

Bit 6: WWDGIE.

IWDGIE

Bit 7: IWDGIE.

SPI2IE

Bit 8: SPI2IE.

USART3IE

Bit 10: illegal access interrupt enable for USART3.

USART4IE

Bit 11: illegal access interrupt enable for UART4.

UART5IE

Bit 12: illegal access interrupt enable for UART5.

I2C1IE

Bit 13: illegal access interrupt enable for I2C1.

I2C2IE

Bit 14: illegal access interrupt enable for I2C2.

CRSIE

Bit 15: illegal access interrupt enable for CRS.

I2C4IE

Bit 16: illegal access interrupt enable for I2C4.

LPTIM2IE

Bit 17: illegal access interrupt enable for LPTIM2.

FDCAN1IE

Bit 18: illegal access interrupt enable for FDCAN1.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1IE rw	TIM17IE rw	TIM16IE rw	TIM15IE rw	USART1IE rw	TIM8IE rw	SPI1IE rw	TIM1IE rw

Toggle fields

TIM1IE

Bit 0: illegal access interrupt enable for TIM1.

SPI1IE

Bit 1: illegal access interrupt enable for SPI1.

TIM8IE

Bit 2: illegal access interrupt enable for TIM8.

USART1IE

Bit 3: illegal access interrupt enable for USART1.

TIM15IE

Bit 4: illegal access interrupt enable for TIM5.

TIM16IE

Bit 5: illegal access interrupt enable for TIM6.

TIM17IE

Bit 6: illegal access interrupt enable for TIM7.

SAI1IE

Bit 7: illegal access interrupt enable for SAI1.

IER3

TZIC interrupt enable register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGIE rw			GPU2DIE rw	RAMCFGIE rw		OCTOSPI1_REGIE rw			SDMMC1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGIE rw	HASHIE rw			DCMIIE rw	ADC1I2E rw	DCACHE1_REGIE rw	ICACHE_REGIE rw		TSCIE rw	CRCIE rw	FMACIE rw	CORDICIE rw	MDF1IE rw

Toggle fields

MDF1IE

Bit 0: illegal access interrupt enable for MDF1.

CORDICIE

Bit 1: illegal access interrupt enable for CORDIC.

FMACIE

Bit 2: illegal access interrupt enable for FMAC.

CRCIE

Bit 3: illegal access interrupt enable for CRC.

TSCIE

Bit 4: illegal access interrupt enable for TSC.

ICACHE_REGIE

Bit 6: illegal access interrupt enable for ICACHE registers.

DCACHE1_REGIE

Bit 7: illegal access interrupt enable for DCACHE registers.

ADC1I2E

Bit 8: illegal access interrupt enable for ADC1 or ADC2.

DCMIIE

Bit 9: illegal access interrupt enable for DCMI.

HASHIE

Bit 12: illegal access interrupt enable for HASH.

RNGIE

Bit 13: illegal access interrupt enable for RNG.

SDMMC1IE

Bit 17: illegal access interrupt enable.

OCTOSPI1_REGIE

Bit 20: illegal access interrupt enable for OCTOSPI1 registers.

RAMCFGIE

Bit 22: illegal access interrupt enable for RAMCFG.

GPU2DIE

Bit 23: GPU2DIE.

HSPI1_REGIE

Bit 26: HSPI1_REGIE.

IER4

TZIC interrupt enable register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SRAM5IE rw			MPCBB2_REGIE rw	SRAM2IE rw	MPCBB1_REGIE rw	SRAM1IE rw				HSPI1_MEMIE rw		BKPSRAMIE rw		OCTOSPI1_MEMIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC1IE rw	TZSC1IE rw												FLASHIE rw	FLASH_REGIE rw	GPDMA1IE rw

Toggle fields

GPDMA1IE

Bit 0: illegal access interrupt enable for GPDMA1.

FLASH_REGIE

Bit 1: illegal access interrupt enable for FLASH registers.

FLASHIE

Bit 2: illegal access interrupt enable for FLASH memory.

TZSC1IE

Bit 14: illegal access interrupt enable for GTZC1 TZSC registers.

TZIC1IE

Bit 15: illegal access interrupt enable for GTZC1 TZIC registers.

OCTOSPI1_MEMIE

Bit 16: illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank.

BKPSRAMIE

Bit 18: illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank.

HSPI1_MEMIE

Bit 20: illegal access interrupt enable for HSPI1 memory bank.

SRAM1IE

Bit 24: illegal access interrupt enable for SRAM1.

MPCBB1_REGIE

Bit 25: illegal access interrupt enable for MPCBB1 registers.

SRAM2IE

Bit 26: illegal access interrupt enable for SRAM2.

MPCBB2_REGIE

Bit 27: illegal access interrupt enable for MPCBB2 registers.

SRAM5IE

Bit 30: illegal access interrupt enable for SRAM5.

SR1

TZIC status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1F r	LPTIM2F r	I2C4F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSF r	I2C2F r	I2C1F r	UART5F r	UART4F r	USART3F r		SPI2F r	IWDGF r	WWDGF r	TIM7F r	TIM6F r	TIM5F r	TIM4F r	TIM3F r	TIM2F r

Toggle fields

TIM2F

Bit 0: illegal access flag for TIM2.

TIM3F

Bit 1: illegal access flag for TIM3.

TIM4F

Bit 2: illegal access flag for TIM4.

TIM5F

Bit 3: illegal access flag for TIM5.

TIM6F

Bit 4: illegal access flag for TIM6.

TIM7F

Bit 5: illegal access flag for TIM7.

WWDGF

Bit 6: illegal access flag for WWDG.

IWDGF

Bit 7: illegal access flag for IWDG.

SPI2F

Bit 8: illegal access flag for SPI2.

USART3F

Bit 10: illegal access flag for USART3.

UART4F

Bit 11: illegal access flag for UART4.

UART5F

Bit 12: illegal access flag for UART5.

I2C1F

Bit 13: illegal access flag for I2C1.

I2C2F

Bit 14: illegal access flag for I2C2.

CRSF

Bit 15: illegal access flag for CRS.

I2C4F

Bit 16: illegal access flag for I2C4.

LPTIM2F

Bit 17: illegal access flag for LPTIM2.

FDCAN1F

Bit 18: illegal access flag for FDCAN1.

SR2

TZIC status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1F r	TIM17F r	TIM16F r	TIM15F r	USART1F r	TIM8F r	SPI1F r	TIM1F r

Toggle fields

TIM1F

Bit 0: illegal access flag for TIM1.

SPI1F

Bit 1: illegal access flag for SPI1.

TIM8F

Bit 2: illegal access flag for TIM8.

USART1F

Bit 3: illegal access flag for USART1.

TIM15F

Bit 4: illegal access flag for TIM5.

TIM16F

Bit 5: illegal access flag for TIM6.

TIM17F

Bit 6: illegal access flag for TIM7.

SAI1F

Bit 7: illegal access flag for SAI1.

SR3

TZIC status register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGF r			GPU2DF r	RAMCFGF r		OCTOSPI1_REGF r			SDMMC1F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGF r	HASHF r			DCMIF r	ADC12F r	DCACHE1_REGF r	ICACHE_REGF r		TSCF r	CRCF r	FMACF r	CORDICF r	MDF1F r

Toggle fields

MDF1F

Bit 0: illegal access flag for MDF1.

CORDICF

Bit 1: illegal access flag for CORDIC.

FMACF

Bit 2: illegal access flag for FMAC.

CRCF

Bit 3: illegal access flag for CRC.

TSCF

Bit 4: illegal access flag for TSC.

ICACHE_REGF

Bit 6: illegal access flag for ICACHE registers.

DCACHE1_REGF

Bit 7: illegal access flag for DCACHE registers.

ADC12F

Bit 8: illegal access flag for ADC1 and ADC2.

DCMIF

Bit 9: illegal access flag for DCMI.

HASHF

Bit 12: illegal access flag for HASH.

RNGF

Bit 13: illegal access flag for RNG.

SDMMC1F

Bit 17: illegal access flag.

OCTOSPI1_REGF

Bit 20: illegal access flag for OCTOSPI1 registers.

RAMCFGF

Bit 22: illegal access flag for RAMCFG.

GPU2DF

Bit 23: illegal access flag for GPU2D.

HSPI1_REGF

Bit 26: illegal access flag for HSPI1 registers.

SR4

TZIC status register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SRAM5F r			MPCBB2_REGF r	SRAM2F r	MPCBB1_REGF r	SRAM1F r				HSPI1_MEMF r		BKPSRAMF r		OCTOSPI1_MEMF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC1F r	TZSC1F r												FLASHF r	FLASH_REGF r	GPDMA1F r

Toggle fields

GPDMA1F

Bit 0: illegal access flag for GPDMA1.

FLASH_REGF

Bit 1: illegal access flag for FLASH registers.

FLASHF

Bit 2: illegal access flag for FLASH memory.

TZSC1F

Bit 14: illegal access flag for GTZC1 TZSC registers.

TZIC1F

Bit 15: illegal access flag for GTZC1 TZIC registers.

OCTOSPI1_MEMF

Bit 16: illegal access flag for MPCWM1 (OCTOSPI1) memory bank.

BKPSRAMF

Bit 18: illegal access flag for MPCWM3 (BKPSRAM) memory bank.

HSPI1_MEMF

Bit 20: illegal access flag for HSPI1 memory bank.

SRAM1F

Bit 24: illegal access flag for SRAM1.

MPCBB1_REGF

Bit 25: illegal access flag for MPCBB1 registers.

SRAM2F

Bit 26: illegal access flag for SRAM2.

MPCBB2_REGF

Bit 27: illegal access flag for MPCBB2 registers.

SRAM5F

Bit 30: illegal access flag for SRAM5.

FCR1

TZIC flag clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													CFDCAN1F w	CLPTIM2F w	CI2C4F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCRSF w	CI2C2F w	CI2C1F w	CUART5F w	CUART4F w	CUSART3F w		CSPI2F w	CIWDGF w	CWWDGF w	CTIM7F w	CTIM6F w	CTIM5F w	CTIM4F w	CTIM3F w	CTIM2F w

Toggle fields

CTIM2F

Bit 0: clear the illegal access flag for TIM2.

CTIM3F

Bit 1: clear the illegal access flag for TIM3.

CTIM4F

Bit 2: clear the illegal access flag for TIM4.

CTIM5F

Bit 3: clear the illegal access flag for TIM5.

CTIM6F

Bit 4: clear the illegal access flag for TIM6.

CTIM7F

Bit 5: clear the illegal access flag for TIM7.

CWWDGF

Bit 6: clear the illegal access flag for WWDG.

CIWDGF

Bit 7: clear the illegal access flag for IWDG.

CSPI2F

Bit 8: clear the illegal access flag for SPI2.

CUSART3F

Bit 10: clear the illegal access flag for USART3.

CUART4F

Bit 11: clear the illegal access flag for UART4.

CUART5F

Bit 12: clear the illegal access flag for UART5.

CI2C1F

Bit 13: clear the illegal access flag for I2C1.

CI2C2F

Bit 14: clear the illegal access flag for I2C2.

CCRSF

Bit 15: clear the illegal access flag for CRS.

CI2C4F

Bit 16: clear the illegal access flag for I2C4.

CLPTIM2F

Bit 17: clear the illegal access flag for LPTIM2.

CFDCAN1F

Bit 18: clear the illegal access flag for FDCAN1.

FCR2

TZIC flag clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CSAI1F w	CTIM17F w	CTIM16F w	CTIM15F w	CUSART1F w	CTIM8F w	CSPI1F w	CTIM1F w

Toggle fields

CTIM1F

Bit 0: clear the illegal access flag for TIM1.

CSPI1F

Bit 1: clear the illegal access flag for SPI1.

CTIM8F

Bit 2: clear the illegal access flag for TIM8.

CUSART1F

Bit 3: clear the illegal access flag for USART1.

CTIM15F

Bit 4: clear the illegal access flag for TIM5.

CTIM16F

Bit 5: clear the illegal access flag for TIM6.

CTIM17F

Bit 6: clear the illegal access flag for TIM7.

CSAI1F

Bit 7: clear the illegal access flag for SAI1.

FCR3

TZIC flag clear register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CGPU2DF w	CRAMCFGF w		COCTOSPI1_REGF w			CSDMMC1F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CRNGF w	CHASHF w			CDCMIF w	CADC12F w	CDCACHE1_REGF w	CICACHE_REGF w		CTSCF w	CCRCF w	CFMACF w	CCORDICF w	CMDF1F w

Toggle fields

CMDF1F

Bit 0: clear the illegal access flag for MDF1.

CCORDICF

Bit 1: clear the illegal access flag for CORDIC.

CFMACF

Bit 2: clear the illegal access flag for FMAC.

CCRCF

Bit 3: clear the illegal access flag for CRC.

CTSCF

Bit 4: clear the illegal access flag for TSC.

CICACHE_REGF

Bit 6: clear the illegal access flag for ICACHE registers.

CDCACHE1_REGF

Bit 7: clear the illegal access flag for DCACHE1 registers.

CADC12F

Bit 8: clear the illegal access flag for ADC1 and ADC2.

CDCMIF

Bit 9: clear the illegal access flag for DCMI.

CHASHF

Bit 12: clear the illegal access flag for HASH.

CRNGF

Bit 13: clear the illegal access flag for RNG.

CSDMMC1F

Bit 17: clear the illegal access flag.

COCTOSPI1_REGF

Bit 20: clear the illegal access flag for OCTOSPI1 registers.

CRAMCFGF

Bit 22: clear the illegal access flag for RAMCFG.

CGPU2DF

Bit 23: clear the illegal access flag for GPU2D.

FCR4

TZIC flag clear register 4

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CSRAM5F w			CMPCBB2_REGF w	CSRAM2F w	CMPCBB1_REGF w	CSRAM1F w				CHSPI1_MEMF w		CBKPSRAMF w		COCTOSPI1_MEMF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTZIC1F w	CTZSC1F w												CFLASHF w	CFLASH_REGF w	CGPDMA1F w

Toggle fields

CGPDMA1F

Bit 0: clear the illegal access flag for GPDMA1.

CFLASH_REGF

Bit 1: clear the illegal access flag for FLASH registers.

CFLASHF

Bit 2: clear the illegal access flag for FLASH memory.

CTZSC1F

Bit 14: clear the illegal access flag for GTZC1 TZSC registers.

CTZIC1F

Bit 15: clear the illegal access flag for GTZC1 TZIC registers.

COCTOSPI1_MEMF

Bit 16: clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank.

CBKPSRAMF

Bit 18: clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank.

CHSPI1_MEMF

Bit 20: clear the illegal access flag for HSPI1 memory bank.

CSRAM1F

Bit 24: clear the illegal access flag for SRAM1.

CMPCBB1_REGF

Bit 25: clear the illegal access flag for MPCBB1 registers.

CSRAM2F

Bit 26: clear the illegal access flag for SRAM2.

CMPCBB2_REGF

Bit 27: clear the illegal access flag for MPCBB2 registers.

CSRAM5F

Bit 30: clear the illegal access flag for SRAM5.

GTZC1_TZSC

0x40032400: GTZC1_TZSC

0/145 fields covered.

Toggle register map

Offset	Name	27	26	23	22	20	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TZSC_CR																								LCK
0x10	TZSC_SECCFGR1						FDCAN1SEC	LPTIM2SEC	I2C4SEC	CRSSEC	I2C2SEC	I2C1SEC	UART5SEC	UART4SEC	USART3SEC		SPI2SEC	IWDGSEC	WWDGSEC	TIM7SEC	TIM6SEC	TIM5SEC	TIM4SEC	TIM3SEC	TIM2SEC
0x14	TZSC_SECCFGR2																	SAI1SEC	TIM17SEC	TIM16SEC	TIM15SEC	USART1SEC	TIM8SEC	SPI1SEC	TIM1SEC
0x18	TZSC_SECCFGR3		HSPI1_REGSEC	GPU2DSEC	RAMCFGSEC	OCTOSPI1_REGSEC		SDMMC1SEC				RNGSEC	HASHSEC			DCMISEC	ADC1SEC	DCACHE1_REGSEC	ICACHE_REGSEC		TSCSEC	CRCSEC	FMACSEC	CORDICSEC	MDF1SEC
0x20	TZSC_PRIVCFGR1						FDCAN1PRIV	LPTIM2PRIV	I2C4PRIV	CRSPRIV	I2C2PRIV	I2C1PRIV	UART5PRIV	UART4PRIV	USART3PRIV		SPI2PRIV	IWDGPRIV	WWDGPRIV	TIM7PRIV	TIM6PRIV	TIM5PRIV	TIM4PRIV	TIM3PRIV	TIM2PRIV
0x24	TZSC_PRIVCFGR2																	SAI1PRIV	TIM17PRIV	TIM16PRIV	TIM15PRIV	USART1PRIV	TIM8PRIV	SPI1PRIV	TIM1PRIV
0x28	TZSC_PRIVCFGR3		HSPI1_REGPRIV	GPU2DPRIV	RAMCFGPRIV	OCTOSPI1_REGPRIV		SDMMC1PRIV				RNGPRIV	HASHPRIV			DCMIPRIV	ADC1PRIV	DCACHE1_REGPRIV	ICACHE_REGPRIV		TSCPRIV	CRCPRIV	FMACPRIV	CORDICPRIV	MDF1PRIV
0x40	TZSC_MPCWM1ACFGR															PRIV	SEC							SRLOCK	SREN
0x44	TZSC_MPCWM1AR	SUBA_LENGTH													SUBA_START
0x48	TZSC_MPCWM1BCFGR															PRIV	SEC							SRLOCK	SREN
0x4c	TZSC_MPCWM1BR	SUBB_LENGTH													SUBB_START
0x50	TZSC_MPCWM2ACFGR															PRIV	SEC							SRLOCK	SREN
0x54	TZSC_MPCWM2AR	SUBA_LENGTH													SUBA_START
0x58	TZSC_MPCWM2BCFGR															PRIV	SEC							SRLOCK	SREN
0x5c	TZSC_MPCWM2BR	SUBB_LENGTH													SUBB_START
0x60	TZSC_MPCWM3ACFGR															PRIV	SEC							SRLOCK	SREN
0x64	TZSC_MPCWM3AR	SUBA_LENGTH													SUBA_START
0x70	TZSC_MPCWM4ACFGR															PRIV	SEC							SRLOCK	SREN
0x74	TZSC_MPCWM4AR	SUBA_LENGTH													SUBA_START
0x80	TZSC_MPCWM5ACFGR															PRIV	SEC							SRLOCK	SREN
0x84	TZSC_MPCWM5AR	SUBA_LENGTH													SUBA_START
0x88	TZSC_MPCWM5BCFGR															PRIV	SEC							SRLOCK	SREN
0x8c	TZSC_MPCWM5BR	SUBB_LENGTH													SUBB_START
0x90	TZSC_MPCWM6ACFGR															PRIV	SEC							SRLOCK	SREN
0x94	TZSC_MPCWM6AR	SUBA_LENGTH													SUBA_START
0x98	TZSC_MPCWM6BCFGR															PRIV	SEC							SRLOCK	SREN
0x9c	TZSC_MPCWM6BR	SUBB_LENGTH													SUBB_START

Toggle registers

TZSC_CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LCK rw

Toggle fields

LCK

Bit 0: lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset.

TZSC_SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1SEC rw	LPTIM2SEC rw	I2C4SEC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSSEC rw	I2C2SEC rw	I2C1SEC rw	UART5SEC rw	UART4SEC rw	USART3SEC rw		SPI2SEC rw	IWDGSEC rw	WWDGSEC rw	TIM7SEC rw	TIM6SEC rw	TIM5SEC rw	TIM4SEC rw	TIM3SEC rw	TIM2SEC rw

Toggle fields

TIM2SEC

Bit 0: secure access mode for TIM2.

TIM3SEC

Bit 1: secure access mode for TIM3.

TIM4SEC

Bit 2: secure access mode for TIM4.

TIM5SEC

Bit 3: secure access mode for TIM5.

TIM6SEC

Bit 4: secure access mode for TIM6.

TIM7SEC

Bit 5: secure access mode for TIM7.

WWDGSEC

Bit 6: secure access mode for WWDG.

IWDGSEC

Bit 7: secure access mode for IWDG.

SPI2SEC

Bit 8: secure access mode for SPI2.

USART3SEC

Bit 10: secure access mode for USART3.

UART4SEC

Bit 11: secure access mode for UART4.

UART5SEC

Bit 12: secure access mode for UART5.

I2C1SEC

Bit 13: secure access mode for I2C1.

I2C2SEC

Bit 14: secure access mode for I2C2.

CRSSEC

Bit 15: secure access mode for CRS.

I2C4SEC

Bit 16: secure access mode for I2C4.

LPTIM2SEC

Bit 17: secure access mode for LPTIM2.

FDCAN1SEC

Bit 18: secure access mode for FDCAN1.

TZSC_SECCFGR2

TZSC secure configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1SEC rw	TIM17SEC rw	TIM16SEC rw	TIM15SEC rw	USART1SEC rw	TIM8SEC rw	SPI1SEC rw	TIM1SEC rw

Toggle fields

TIM1SEC

Bit 0: secure access mode for TIM1.

SPI1SEC

Bit 1: secure access mode for SPI1.

TIM8SEC

Bit 2: secure access mode for TIM8.

USART1SEC

Bit 3: secure access mode for USART1.

TIM15SEC

Bit 4: secure access mode for TIM5.

TIM16SEC

Bit 5: secure access mode for TIM6.

TIM17SEC

Bit 6: secure access mode for TIM7.

SAI1SEC

Bit 7: secure access mode for SAI1.

TZSC_SECCFGR3

TZSC secure configuration register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGSEC rw			GPU2DSEC rw	RAMCFGSEC rw		OCTOSPI1_REGSEC rw			SDMMC1SEC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGSEC rw	HASHSEC rw			DCMISEC rw	ADC1SEC rw	DCACHE1_REGSEC rw	ICACHE_REGSEC rw		TSCSEC rw	CRCSEC rw	FMACSEC rw	CORDICSEC rw	MDF1SEC rw

Toggle fields

MDF1SEC

Bit 0: secure access mode for MDF1.

CORDICSEC

Bit 1: secure access mode for CORDIC.

FMACSEC

Bit 2: secure access mode for FMAC.

CRCSEC

Bit 3: secure access mode for CRC.

TSCSEC

Bit 4: secure access mode for TSC.

ICACHE_REGSEC

Bit 6: secure access mode for ICACHE registers.

DCACHE1_REGSEC

Bit 7: secure access mode for DCACHE1 registers.

ADC1SEC

Bit 8: secure access mode for ADC1.

DCMISEC

Bit 9: secure access mode for DCMI.

HASHSEC

Bit 12: secure access mode for HASH.

RNGSEC

Bit 13: secure access mode for RNG.

SDMMC1SEC

Bit 17: secure access mode.

OCTOSPI1_REGSEC

Bit 20: secure access mode for OCTOSPI1 registers.

RAMCFGSEC

Bit 22: secure access mode for RAMCFG.

GPU2DSEC

Bit 23: GPU2DSEC.

HSPI1_REGSEC

Bit 26: HSPI1_REGSEC.

TZSC_PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1PRIV rw	LPTIM2PRIV rw	I2C4PRIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSPRIV rw	I2C2PRIV rw	I2C1PRIV rw	UART5PRIV rw	UART4PRIV rw	USART3PRIV rw		SPI2PRIV rw	IWDGPRIV rw	WWDGPRIV rw	TIM7PRIV rw	TIM6PRIV rw	TIM5PRIV rw	TIM4PRIV rw	TIM3PRIV rw	TIM2PRIV rw

Toggle fields

TIM2PRIV

Bit 0: privileged access mode for TIM2.

TIM3PRIV

Bit 1: privileged access mode for TIM3.

TIM4PRIV

Bit 2: privileged access mode for TIM4.

TIM5PRIV

Bit 3: privileged access mode for TIM5.

TIM6PRIV

Bit 4: privileged access mode for TIM6.

TIM7PRIV

Bit 5: privileged access mode for TIM7.

WWDGPRIV

Bit 6: privileged access mode for WWDG.

IWDGPRIV

Bit 7: privileged access mode for IWDG.

SPI2PRIV

Bit 8: privileged access mode for SPI2.

USART3PRIV

Bit 10: privileged access mode for USART3.

UART4PRIV

Bit 11: privileged access mode for UART4.

UART5PRIV

Bit 12: privileged access mode for UART5.

I2C1PRIV

Bit 13: privileged access mode for I2C1.

I2C2PRIV

Bit 14: privileged access mode for I2C2.

CRSPRIV

Bit 15: privileged access mode for CRS.

I2C4PRIV

Bit 16: privileged access mode for I2C4.

LPTIM2PRIV

Bit 17: privileged access mode for LPTIM2.

FDCAN1PRIV

Bit 18: privileged access mode for FDCAN1.

TZSC_PRIVCFGR2

TZSC privilege configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1PRIV rw	TIM17PRIV rw	TIM16PRIV rw	TIM15PRIV rw	USART1PRIV rw	TIM8PRIV rw	SPI1PRIV rw	TIM1PRIV rw

Toggle fields

TIM1PRIV

Bit 0: privileged access mode for TIM1.

SPI1PRIV

Bit 1: privileged access mode for SPI1PRIV.

TIM8PRIV

Bit 2: privileged access mode for TIM8.

USART1PRIV

Bit 3: privileged access mode for USART1.

TIM15PRIV

Bit 4: privileged access mode for TIM15.

TIM16PRIV

Bit 5: privileged access mode for TIM16.

TIM17PRIV

Bit 6: privileged access mode for TIM17.

SAI1PRIV

Bit 7: privileged access mode for SAI1.

TZSC_PRIVCFGR3

TZSC privilege configuration register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGPRIV rw			GPU2DPRIV rw	RAMCFGPRIV rw		OCTOSPI1_REGPRIV rw			SDMMC1PRIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGPRIV rw	HASHPRIV rw			DCMIPRIV rw	ADC1PRIV rw	DCACHE1_REGPRIV rw	ICACHE_REGPRIV rw		TSCPRIV rw	CRCPRIV rw	FMACPRIV rw	CORDICPRIV rw	MDF1PRIV rw

Toggle fields

MDF1PRIV

Bit 0: privileged access mode for MDF1.

CORDICPRIV

Bit 1: privileged access mode for CORDIC.

FMACPRIV

Bit 2: privileged access mode for FMAC.

CRCPRIV

Bit 3: privileged access mode for CRC.

TSCPRIV

Bit 4: privileged access mode for TSC.

ICACHE_REGPRIV

Bit 6: privileged access mode for ICACHE registers.

DCACHE1_REGPRIV

Bit 7: privileged access mode for DCACHE1 registers.

ADC1PRIV

Bit 8: privileged access mode for ADC1.

DCMIPRIV

Bit 9: privileged access mode for DCMI.

HASHPRIV

Bit 12: privileged access mode for HASH.

RNGPRIV

Bit 13: privileged access mode for RNG.

SDMMC1PRIV

Bit 17: privileged access mode.

OCTOSPI1_REGPRIV

Bit 20: privileged access mode for OCTOSPI1.

RAMCFGPRIV

Bit 22: privileged access mode for RAMCFG.

GPU2DPRIV

Bit 23: GPU2DPRIV.

HSPI1_REGPRIV

Bit 26: HSPI1_REGPRIV.

TZSC_MPCWM1ACFGR

TZSC memory 1 sub-region A watermark configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM1AR

TZSC memory 1 sub-region A watermark register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM1BCFGR

TZSC memory 1 sub-region B watermark configuration register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM1BR

TZSC memory 1 sub-region B watermark register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM2ACFGR

TZSC memory 2 sub-region A watermark configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM2AR

TZSC memory 2 sub-region A watermark register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM2BCFGR

TZSC memory 2 sub-region B watermark configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM2BR

TZSC memory 2 sub-region B watermark register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM3ACFGR

TZSC memory 3 sub-region A watermark configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM3AR

TZSC memory 3 sub-region A watermark register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM4ACFGR

TZSC memory 4 sub-region A watermark configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM4AR

TZSC memory 4 sub-region A watermark register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM5ACFGR

TZSC memory 5 sub-region A watermark configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM5AR

TZSC memory 5 sub-region A watermark register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM5BCFGR

TZSC memory 5 sub-region B watermark configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM5BR

TZSC memory 5 sub-region B watermark register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM6ACFGR

TZSC memory 6 sub-region B watermark configuration register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM6AR

TZSC memory 6 sub-region B watermark register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM6BCFGR

TZSC memory 6 sub-region B watermark configuration register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM6BR

TZSC memory 6 sub-region B watermark register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

GTZC2_MPCBB4

0x46023800: GTZC2_MPCBB4

0/68 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MPCBB4_CR	SRWILADIS	INVSECSTATE																														GLOCK
0x10	MPCBB4_CFGLOCK																																SPLCK0
0x100	MPCBB4_SECCFGR0	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x200	MPCBB4_PRIVCFGR0	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0

Toggle registers

MPCBB4_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRWILADIS rw	INVSECSTATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															GLOCK rw

Toggle fields

GLOCK

Bit 0: lock the control register of the MPCBB until next reset.

INVSECSTATE

Bit 30: SRAMx clocks security state.

SRWILADIS

Bit 31: secure read/write illegal access disable.

MPCBB4_CFGLOCK

GTZC2 SRAM4 MPCBB configuration lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															SPLCK0 rw

Toggle fields

SPLCK0

Bit 0: Security/privilege configuration lock for super-block 0.

MPCBB4_SECCFGR0

MPCBB security configuration for super-block 0 register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB4_PRIVCFGR0

MPCBB privileged configuration for super-block 0 register

Offset: 0x200, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

GTZC2_TZIC

0x46023400: GTZC2_TZIC

22/67 fields covered.

Toggle register map

Offset	Name	25	24	15	14	12	11	9	8	7	6	5	4	3	2	1	0
0x0	IER1					ADF1IE	DAC1IE	VREFBUFIE		COMPIE	OPAMPIE	LPTIM4IE	LPTIM3IE	LPTIM1IE	I2C3IE	LPUART1IE	SPI3IE
0x4	IER2	MPCBB4_REGIE	SRAM4IE	TZIC2IE	TZSC2IE						EXTIIE	LPDMA1IE	RCCIE	PWRIE	TAMPIE	RTCIE	SYSCFGIE
0x10	SR1					ADF1F	DAC1F	VREFBUFF		COMPF	OPAMPF	LPTIM4F	LPTIM3F	LPTIM1F	I2C3F	LPUART1F	SPI3F
0x14	SR2	MPCBB4_REGF	SRAM4F	TZIC2F	TZSC2F						EXTIF	LPDMA1F	RCCF	PWRF	TAMPF	RTCF	SYSCFGF
0x20	FCR1					CADF1F	CDAC1F	CVREFBUFF	CADC2F	CCOMPF	COPAMPF	CLPTIM4F	CLPTIM3F	CLPTIM1F	CI2C3F	CLPUART1F	CSPI3F
0x24	FCR2	CMPCBB4_REGF	CSRAM4F	CTZIC2F	CTZSC2F						CEXTIF	CLPDMA1F	CRCCF	CPWRF	CTAMPF	CRTCF	CSYSCFGF

Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1IE rw	DAC1IE rw		VREFBUFIE rw		COMPIE rw	OPAMPIE rw	LPTIM4IE rw	LPTIM3IE rw	LPTIM1IE rw	I2C3IE rw	LPUART1IE rw	SPI3IE rw

Toggle fields

SPI3IE

Bit 0: illegal access interrupt enable for SPI3.

LPUART1IE

Bit 1: illegal access interrupt enable for LPUART1.

I2C3IE

Bit 2: illegal access interrupt enable for I2C3.

LPTIM1IE

Bit 3: illegal access interrupt enable for LPTIM1.

LPTIM3IE

Bit 4: illegal access interrupt enable for LPTIM3.

LPTIM4IE

Bit 5: illegal access interrupt enable for LPTIM4.

OPAMPIE

Bit 6: illegal access interrupt enable for OPAMP.

COMPIE

Bit 7: illegal access interrupt enable for COMP.

VREFBUFIE

Bit 9: illegal access interrupt enable for VREFBUF.

DAC1IE

Bit 11: illegal access interrupt enable for DAC1.

ADF1IE

Bit 12: illegal access interrupt enable for ADF1.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MPCBB4_REGIE rw	SRAM4IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC2IE rw	TZSC2IE rw								EXTIIE rw	LPDMA1IE rw	RCCIE rw	PWRIE rw	TAMPIE rw	RTCIE rw	SYSCFGIE rw

Toggle fields

SYSCFGIE

Bit 0: illegal access interrupt enable for SYSCFG.

RTCIE

Bit 1: illegal access interrupt enable for RTC.

TAMPIE

Bit 2: illegal access interrupt enable for TAMP.

PWRIE

Bit 3: illegal access interrupt enable for PWR.

RCCIE

Bit 4: illegal access interrupt enable for RCC.

LPDMA1IE

Bit 5: illegal access interrupt enable for LPDMA.

EXTIIE

Bit 6: illegal access interrupt enable for EXTI.

TZSC2IE

Bit 14: illegal access interrupt enable for GTZC2 TZSC registers.

TZIC2IE

Bit 15: illegal access interrupt enable for GTZC2 TZIC registers.

SRAM4IE

Bit 24: illegal access interrupt enable for SRAM4.

MPCBB4_REGIE

Bit 25: illegal access interrupt enable for MPCBB4 registers.

SR1

TZIC status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1F r	DAC1F r		VREFBUFF r		COMPF r	OPAMPF r	LPTIM4F r	LPTIM3F r	LPTIM1F r	I2C3F r	LPUART1F r	SPI3F r

Toggle fields

SPI3F

Bit 0: illegal access flag for SPI3.

LPUART1F

Bit 1: illegal access flag for LPUART1.

I2C3F

Bit 2: illegal access flag for I2C3.

LPTIM1F

Bit 3: illegal access flag for LPTIM1.

LPTIM3F

Bit 4: illegal access flag for LPTIM3.

LPTIM4F

Bit 5: illegal access flag for LPTIM4.

OPAMPF

Bit 6: illegal access flag for OPAMP.

COMPF

Bit 7: illegal access flag for COMP.

VREFBUFF

Bit 9: illegal access flag for VREFBUF.

DAC1F

Bit 11: illegal access flag for DAC1.

ADF1F

Bit 12: illegal access flag for ADF1.

SR2

TZIC status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MPCBB4_REGF r	SRAM4F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC2F r	TZSC2F r								EXTIF r	LPDMA1F r	RCCF r	PWRF r	TAMPF r	RTCF r	SYSCFGF r

Toggle fields

SYSCFGF

Bit 0: illegal access flag for SYSCFG.

RTCF

Bit 1: illegal access flag for RTC.

TAMPF

Bit 2: illegal access flag for TAMP.

PWRF

Bit 3: illegal access flag for PWRUSART1F.

RCCF

Bit 4: illegal access flag for RCC.

LPDMA1F

Bit 5: illegal access flag for LPDMA.

EXTIF

Bit 6: illegal access flag for EXTI.

TZSC2F

Bit 14: illegal access flag for GTZC2 TZSC registers.

TZIC2F

Bit 15: illegal access flag for GTZC2 TZIC registers.

SRAM4F

Bit 24: illegal access flag for SRAM4.

MPCBB4_REGF

Bit 25: illegal access flag for MPCBB4 registers.

FCR1

TZIC flag clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CADF1F w	CDAC1F w		CVREFBUFF w	CADC2F w	CCOMPF w	COPAMPF w	CLPTIM4F w	CLPTIM3F w	CLPTIM1F w	CI2C3F w	CLPUART1F w	CSPI3F w

Toggle fields

CSPI3F

Bit 0: clear the illegal access flag for SPI3.

CLPUART1F

Bit 1: clear the illegal access flag for LPUART1.

CI2C3F

Bit 2: clear the illegal access flag for I2C3.

CLPTIM1F

Bit 3: clear the illegal access flag for LPTIM1.

CLPTIM3F

Bit 4: clear the illegal access flag for LPTIM3.

CLPTIM4F

Bit 5: clear the illegal access flag for LPTIM4.

COPAMPF

Bit 6: clear the illegal access flag for OPAMP.

CCOMPF

Bit 7: clear the illegal access flag for COMP.

CADC2F

Bit 8: clear the illegal access flag for ADC2.

CVREFBUFF

Bit 9: clear the illegal access flag for VREFBUF.

CDAC1F

Bit 11: clear the illegal access flag for DAC1.

CADF1F

Bit 12: clear the illegal access flag for ADF1.

FCR2

TZIC flag clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CMPCBB4_REGF w	CSRAM4F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTZIC2F w	CTZSC2F w								CEXTIF w	CLPDMA1F w	CRCCF w	CPWRF w	CTAMPF w	CRTCF w	CSYSCFGF w

Toggle fields

CSYSCFGF

Bit 0: clear the illegal access flag for SYSCFG.

CRTCF

Bit 1: clear the illegal access flag for RTC.

CTAMPF

Bit 2: clear the illegal access flag for TAMP.

CPWRF

Bit 3: clear the illegal access flag for PWR.

CRCCF

Bit 4: clear the illegal access flag for RCC.

CLPDMA1F

Bit 5: clear the illegal access flag for LPDMA.

CEXTIF

Bit 6: clear the illegal access flag for EXTI.

CTZSC2F

Bit 14: clear the illegal access flag for GTZC2 TZSC registers.

CTZIC2F

Bit 15: clear the illegal access flag for GTZC2 TZIC registers.

CSRAM4F

Bit 24: clear the illegal access flag for SRAM4.

CMPCBB4_REGF

Bit 25: clear the illegal access flag for MPCBB4 registers.

GTZC2_TZSC

0x46023000: GTZC2_TZSC

0/23 fields covered.

Toggle register map

Offset	Name	12	11	9	7	6	5	4	3	2	1	0
0x0	TZSC_CR											LCK
0x10	TZSC_SECCFGR1	ADF1SEC	DAC1SEC	VREFBUFSEC	COMPSEC	OPAMPSEC	LPTIM4SEC	LPTIM3SEC	LPTIM1SEC	I2C3SEC	LPUART1SEC	SPI3SEC
0x20	TZSC_PRIVCFGR1	ADF1PRIV	DAC1PRIV	VREFBUFPRIV	COMPPRIV	OPAMPPRIV	LPTIM4PRIV	LPTIM3PRIV	LPTIM1PRIV	I2C3PRIV	LPUART1PRIV	SPI3PRIV

Toggle registers

TZSC_CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LCK rw

Toggle fields

LCK

Bit 0: lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset.

TZSC_SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1SEC rw	DAC1SEC rw		VREFBUFSEC rw		COMPSEC rw	OPAMPSEC rw	LPTIM4SEC rw	LPTIM3SEC rw	LPTIM1SEC rw	I2C3SEC rw	LPUART1SEC rw	SPI3SEC rw

Toggle fields

SPI3SEC

Bit 0: secure access mode for SPI3.

LPUART1SEC

Bit 1: secure access mode for LPUART1.

I2C3SEC

Bit 2: secure access mode for I2C3.

LPTIM1SEC

Bit 3: secure access mode for LPTIM1.

LPTIM3SEC

Bit 4: secure access mode for LPTIM3.

LPTIM4SEC

Bit 5: secure access mode for LPTIM4.

OPAMPSEC

Bit 6: secure access mode for OPAMP.

COMPSEC

Bit 7: secure access mode for COMP.

VREFBUFSEC

Bit 9: secure access mode for VREFBUF.

DAC1SEC

Bit 11: secure access mode for DAC1.

ADF1SEC

Bit 12: secure access mode for ADF1.

TZSC_PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1PRIV rw	DAC1PRIV rw		VREFBUFPRIV rw		COMPPRIV rw	OPAMPPRIV rw	LPTIM4PRIV rw	LPTIM3PRIV rw	LPTIM1PRIV rw	I2C3PRIV rw	LPUART1PRIV rw	SPI3PRIV rw

Toggle fields

SPI3PRIV

Bit 0: privileged access mode for SPI3.

LPUART1PRIV

Bit 1: privileged access mode for LPUART1.

I2C3PRIV

Bit 2: privileged access mode for I2C3.

LPTIM1PRIV

Bit 3: privileged access mode for LPTIM1.

LPTIM3PRIV

Bit 4: privileged access mode for LPTIM3.

LPTIM4PRIV

Bit 5: privileged access mode for LPTIM4.

OPAMPPRIV

Bit 6: privileged access mode for OPAMP.

COMPPRIV

Bit 7: privileged access mode for COMP.

VREFBUFPRIV

Bit 9: privileged access mode for VREFBUF.

DAC1PRIV

Bit 11: privileged access mode for DAC1.

ADF1PRIV

Bit 12: privileged access mode for ADF1.

HASH

0x420c0400: Hash processor

20/88 fields covered.

Toggle register map

Offset	Name	31	20	18	16	15	13	12	11	8	6	5	4	3	2	1	0
0x0	CR			ALGO	LKEY		MDMAT	DINNE	NBW		MODE	DATATYPE		DMAE	INIT
0x4	DIN	DATAIN				DATAIN
0x8	STR									DCAL			NBLW
0xc	HRA0	H0				H0
0x10	HRA1	H1				H1
0x14	HRA2	H2				H2
0x18	HRA3	H3				H3
0x1c	HRA4	H4				H4
0x20	IMR															DCIE	DINIE
0x24	SR		NBWE			DINNE	NBWP							BUSY	DMAS	DCIS	DINIS
0xf8	CSR0	CS0				CS0
0xfc	CSR1	CS1				CS1
0x100	CSR2	CS2				CS2
0x104	CSR3	CS3				CS3
0x108	CSR4	CS4				CS4
0x10c	CSR5	CS5				CS5
0x110	CSR6	CS6				CS6
0x114	CSR7	CS7				CS7
0x118	CSR8	CS8				CS8
0x11c	CSR9	CS9				CS9
0x120	CSR10	CS10				CS10
0x124	CSR11	CS11				CS11
0x128	CSR12	CS12				CS12
0x12c	CSR13	CS13				CS13
0x130	CSR14	CS14				CS14
0x134	CSR15	CS15				CS15
0x138	CSR16	CS16				CS16
0x13c	CSR17	CS17				CS17
0x140	CSR18	CS18				CS18
0x144	CSR19	CS19				CS19
0x148	CSR20	CS20				CS20
0x14c	CSR21	CS21				CS21
0x150	CSR22	CS22				CS22
0x154	CSR23	CS23				CS23
0x158	CSR24	CS24				CS24
0x15c	CSR25	CS25				CS25
0x160	CSR26	CS26				CS26
0x164	CSR27	CS27				CS27
0x168	CSR28	CS28				CS28
0x16c	CSR29	CS29				CS29
0x170	CSR30	CS30				CS30
0x174	CSR31	CS31				CS31
0x178	CSR32	CS32				CS32
0x17c	CSR33	CS33				CS33
0x180	CSR34	CS34				CS34
0x184	CSR35	CS35				CS35
0x188	CSR36	CS36				CS36
0x18c	CSR37	CS37				CS37
0x190	CSR38	CS38				CS38
0x194	CSR39	CS39				CS39
0x198	CSR40	CS40				CS40
0x19c	CSR41	CS41				CS41
0x1a0	CSR42	CS42				CS42
0x1a4	CSR43	CS43				CS43
0x1a8	CSR44	CS44				CS44
0x1ac	CSR45	CS45				CS45
0x1b0	CSR46	CS46				CS46
0x1b4	CSR47	CS47				CS47
0x1b8	CSR48	CS48				CS48
0x1bc	CSR49	CS49				CS49
0x1c0	CSR50	CS50				CS50
0x1c4	CSR51	CS51				CS51
0x1c8	CSR52	CS52				CS52
0x1cc	CSR53	CS53				CS53
0x310	HR0	H0				H0
0x314	HR1	H1				H1
0x318	HR2	H2				H2
0x31c	HR3	H3				H3
0x320	HR4	H4				H4
0x324	HR5	H5				H5
0x328	HR6	H6				H6
0x32c	HR7	H7				H7

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													ALGO rw		LKEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MDMAT rw	DINNE r	NBW r					MODE rw	DATATYPE rw		DMAE rw	INIT w

Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO

Bits 17-18: Algorithm selection.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATAIN w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAIN w

Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DCAL w				NBLW rw

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DCIE rw	DINIE rw

Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											NBWE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DINNE r		NBWP r										BUSY r	DMAS r	DCIS rw	DINIS rw

Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

NBWP

Bits 9-13: Number of words already pushed.

DINNE

Bit 15: DIN not empty.

NBWE

Bits 16-20: Number of words expected.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS0 rw

Toggle fields

CS0

Bits 0-31: CS0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS1 rw

Toggle fields

CS1

Bits 0-31: CS1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS2 rw

Toggle fields

CS2

Bits 0-31: CS2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS3 rw

Toggle fields

CS3

Bits 0-31: CS3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS4 rw

Toggle fields

CS4

Bits 0-31: CS4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS5 rw

Toggle fields

CS5

Bits 0-31: CS5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS6 rw

Toggle fields

CS6

Bits 0-31: CS6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS7 rw

Toggle fields

CS7

Bits 0-31: CS7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS8 rw

Toggle fields

CS8

Bits 0-31: CS8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS9 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS9 rw

Toggle fields

CS9

Bits 0-31: CS9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS10 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS10 rw

Toggle fields

CS10

Bits 0-31: CS10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS11 rw

Toggle fields

CS11

Bits 0-31: CS11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS12 rw

Toggle fields

CS12

Bits 0-31: CS12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS13 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS13 rw

Toggle fields

CS13

Bits 0-31: CS13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS14 rw

Toggle fields

CS14

Bits 0-31: CS14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS15 rw

Toggle fields

CS15

Bits 0-31: CS15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS16 rw

Toggle fields

CS16

Bits 0-31: CS16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS17 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS17 rw

Toggle fields

CS17

Bits 0-31: CS17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS18 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS18 rw

Toggle fields

CS18

Bits 0-31: CS18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS19 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS19 rw

Toggle fields

CS19

Bits 0-31: CS19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS20 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS20 rw

Toggle fields

CS20

Bits 0-31: CS20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS21 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS21 rw

Toggle fields

CS21

Bits 0-31: CS21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS22 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS22 rw

Toggle fields

CS22

Bits 0-31: CS22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS23 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS23 rw

Toggle fields

CS23

Bits 0-31: CS23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS24 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS24 rw

Toggle fields

CS24

Bits 0-31: CS24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS25 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS25 rw

Toggle fields

CS25

Bits 0-31: CS25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS26 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS26 rw

Toggle fields

CS26

Bits 0-31: CS26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS27 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS27 rw

Toggle fields

CS27

Bits 0-31: CS27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS28 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS28 rw

Toggle fields

CS28

Bits 0-31: CS28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS29 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS29 rw

Toggle fields

CS29

Bits 0-31: CS29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS30 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS30 rw

Toggle fields

CS30

Bits 0-31: CS30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS31 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS31 rw

Toggle fields

CS31

Bits 0-31: CS31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS32 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS32 rw

Toggle fields

CS32

Bits 0-31: CS32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS33 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS33 rw

Toggle fields

CS33

Bits 0-31: CS33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS34 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS34 rw

Toggle fields

CS34

Bits 0-31: CS34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS35 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS35 rw

Toggle fields

CS35

Bits 0-31: CS35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS36 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS36 rw

Toggle fields

CS36

Bits 0-31: CS36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS37 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS37 rw

Toggle fields

CS37

Bits 0-31: CS37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS38 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS38 rw

Toggle fields

CS38

Bits 0-31: CS38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS39 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS39 rw

Toggle fields

CS39

Bits 0-31: CS39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS40 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS40 rw

Toggle fields

CS40

Bits 0-31: CS40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS41 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS41 rw

Toggle fields

CS41

Bits 0-31: CS41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS42 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS42 rw

Toggle fields

CS42

Bits 0-31: CS42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS43 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS43 rw

Toggle fields

CS43

Bits 0-31: CS43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS44 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS44 rw

Toggle fields

CS44

Bits 0-31: CS44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS45 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS45 rw

Toggle fields

CS45

Bits 0-31: CS45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS46 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS46 rw

Toggle fields

CS46

Bits 0-31: CS46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS47 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS47 rw

Toggle fields

CS47

Bits 0-31: CS47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS48 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS48 rw

Toggle fields

CS48

Bits 0-31: CS48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS49 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS49 rw

Toggle fields

CS49

Bits 0-31: CS49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS50 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS50 rw

Toggle fields

CS50

Bits 0-31: CS50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS51 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS51 rw

Toggle fields

CS51

Bits 0-31: CS51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS52 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS52 rw

Toggle fields

CS52

Bits 0-31: CS52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS53 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS53 rw

Toggle fields

CS53

Bits 0-31: CS53.

HR0

digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H0 r

Toggle fields

H0

Bits 0-31: H0.

HR1

digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H1 r

Toggle fields

H1

Bits 0-31: H1.

HR2

digest register 4

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H2 r

Toggle fields

H2

Bits 0-31: H2.

HR3

digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H3 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H3 r

Toggle fields

H3

Bits 0-31: H3.

HR4

digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H4 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H4 r

Toggle fields

H4

Bits 0-31: H4.

HR5

supplementary digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H5 r

Toggle fields

H5

Bits 0-31: H5.

HR6

supplementary digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H6 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H6 r

Toggle fields

H6

Bits 0-31: H6.

HR7

supplementary digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H7 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H7 r

Toggle fields

H7

Bits 0-31: H7.

I2C1

0x40005400: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

I2C2

0x40005800: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

I2C3

0x46002800: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

I2C4

0x40008400: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

ICache

0x40030400: ICache

5/40 fields covered.

Toggle register map

Offset	Name	31	28	26	19	18	17	16	15	11	7	2	1	0
0x0	ICACHE_CR				MISSMRST	HITMRST	MISSMEN	HITMEN				WAYSEL	CACHEINV	EN
0x4	ICACHE_SR											ERRF	BSYENDF	BUSYF
0x8	ICACHE_IER											ERRIE	BSYENDIE
0xc	ICACHE_FCR											CERRF	CBSYENDF
0x10	ICACHE_HMONR	HITMON							HITMON
0x14	ICACHE_MMONR								MISSMON
0x20	ICACHE_CRR0	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR
0x24	ICACHE_CRR1	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR
0x28	ICACHE_CRR2	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR
0x2c	ICACHE_CRR3	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR

Toggle registers

ICACHE_CR

ICACHE control register

Offset: 0x0, size: 32, reset: 0x00000004, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												MISSMRST rw	HITMRST rw	MISSMEN rw	HITMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WAYSEL rw	CACHEINV w	EN rw

Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

WAYSEL

Bit 2: WAYSEL.

HITMEN

Bit 16: HITMEN.

MISSMEN

Bit 17: MISSMEN.

HITMRST

Bit 18: HITMRST.

MISSMRST

Bit 19: MISSMRST.

ICACHE_SR

ICACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													ERRF r	BSYENDF r	BUSYF r

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

ICACHE_CRR1

ICACHE region configuration register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

ICACHE_CRR2

ICACHE region configuration register

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

ICACHE_CRR3

ICACHE region configuration register

Offset: 0x2c, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

IWDG

0x40003000: Independent watchdog

5/12 fields covered.

Toggle register map

Offset	Name	15	14	11	3	2	1	0
0x0	KR	KEY
0x4	PR				PR
0x8	RLR			RL
0xc	SR		EWIF		EWU	WVU	RVU	PVU
0x10	WINR			WIN
0x14	EWCR	EWIE	EWIC	EWIT

Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PR rw

Toggle fields

PR

Bits 0-3: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EWIF r											EWU r	WVU r	RVU r	PVU r

Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

EWU

Bit 3: Watchdog interrupt comparator value update.

EWIF

Bit 14: Watchdog Early interrupt flag.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

EWCR

IWDG early wakeup interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EWIE rw	EWIC rw			EWIT rw

Toggle fields

EWIT

Bits 0-11: Watchdog counter window value.

EWIC

Bit 14: Watchdog early interrupt acknowledge.

EWIE

Bit 15: Watchdog early interrupt enable.

LPDMA1

0x46025000: LPDMA1

36/212 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	25	23	20	19	17	16	15	13	12	11	10	9	8	4	3	2	1	0
0x0	LPDMA_SECCFGR																				SEC3	SEC2	SEC1	SEC0
0x4	LPDMA_PRIVCFGR																				PRIV3	PRIV2	PRIV1	PRIV0
0xc	MISR																				MIS3	MIS2	MIS1	MIS0
0x10	SMISR																				MIS3	MIS2	MIS1	MIS0
0x50	LPDMA_C0LBAR	LBA
0x5c	LPDMA_C0FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x60	LPDMA_C0SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0x64	LPDMA_C0CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x90	LPDMA_C0TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x94	LPDMA_C0TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x98	LPDMA_C0BR1												BNDT
0x9c	LPDMA_C0SAR	SA											SA
0xa0	LPDMA_C0DAR	DA											DA
0xcc	LPDMA_C0LLR	UT1	UT2	UB1	USA	UDA						ULL	LA
0xd0	LPDMA_C1LBAR	LBA
0xdc	LPDMA_C1FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0xe0	LPDMA_C1SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0xe4	LPDMA_C1CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x110	LPDMA_C1TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x114	LPDMA_C1TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x118	LPDMA_C1BR1												BNDT
0x11c	LPDMA_C1SAR	SA											SA
0x120	LPDMA_C1DAR	DA											DA
0x14c	LPDMA_C1LLR	UT1	UT2	UB1	USA	UDA						ULL	LA
0x150	LPDMA_C2LBAR	LBA
0x15c	LPDMA_C2FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x160	LPDMA_C2SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0x164	LPDMA_C2CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x190	LPDMA_C2TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x194	LPDMA_C2TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x198	LPDMA_C2BR1												BNDT
0x19c	LPDMA_C2SAR	SA											SA
0x1a0	LPDMA_C2DAR	DA											DA
0x1cc	LPDMA_C2LLR	UT1	UT2	UB1	USA	UDA						ULL	LA
0x1d0	LPDMA_C3LBAR	LBA
0x1dc	LPDMA_C3FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x1e0	LPDMA_C3SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0x1e4	LPDMA_C3CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x210	LPDMA_C3TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x214	LPDMA_C3TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x218	LPDMA_C3BR1												BNDT
0x21c	LPDMA_C3SAR	SA											SA
0x220	LPDMA_C3DAR	DA											DA
0x24c	LPDMA_C3LLR	UT1	UT2	UB1	USA	UDA						ULL	LA

Toggle registers

LPDMA_SECCFGR

LPDMA secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

LPDMA_PRIVCFGR

LPDMA privileged configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

MISR

LPDMA non-secure masked interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

SMISR

LPDMA secure masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

LPDMA_C0LBAR

channel x linked-list base address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C0FCR

LPDMA channel x flag clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C0SR

channel x status register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C0CR

channel x control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C0TR1

LPDMA channel x transfer register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C0TR2

LPDMA channel x transfer register 2

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if LPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C0BR1

LPDMA channel x block register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

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BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C0SAR

LPDMA channel x source address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C0DAR

LPDMA channel x destination address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C0LLR

LPDMA channel x linked-list address register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPDMA_C1LBAR

channel x linked-list base address register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C1FCR

LPDMA channel x flag clear register

Offset: 0xdc, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C1SR

channel x status register

Offset: 0xe0, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C1CR

channel x control register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C1TR1

LPDMA channel x transfer register 1

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C1TR2

LPDMA channel x transfer register 2

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C1BR1

LPDMA channel x block register 1

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C1SAR

LPDMA channel x source address register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C1DAR

LPDMA channel x destination address register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C1LLR

LPDMA channel x linked-list address register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPDMA_C2LBAR

channel x linked-list base address register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C2FCR

LPDMA channel x flag clear register

Offset: 0x15c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C2SR

channel x status register

Offset: 0x160, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C2CR

channel x control register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C2TR1

LPDMA channel x transfer register 1

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C2TR2

LPDMA channel x transfer register 2

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C2BR1

LPDMA channel x block register 1

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C2SAR

LPDMA channel x source address register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C2DAR

LPDMA channel x destination address register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C2LLR

LPDMA channel x linked-list address register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPDMA_C3LBAR

channel x linked-list base address register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C3FCR

LPDMA channel x flag clear register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C3SR

channel x status register

Offset: 0x1e0, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C3CR

channel x control register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C3TR1

LPDMA channel x transfer register 1

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C3TR2

LPDMA channel x transfer register 2

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C3BR1

LPDMA channel x block register 1

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C3SAR

LPDMA channel x source address register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C3DAR

LPDMA channel x destination address register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C3LLR

LPDMA channel x linked-list address register

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPGPIO1

0x46020000: LPGPIO1

16/96 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	LPGPIO_MODER																	MODE15	MODE14	MODE13	MODE12	MODE11	MODE10	MODE9	MODE8	MODE7	MODE6	MODE5	MODE4	MODE3	MODE2	MODE1	MODE0
0x10	LPGPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	LPGPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	LPGPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x28	LPGPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

LPGPIO_MODER

LPGPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE15 rw	MODE14 rw	MODE13 rw	MODE12 rw	MODE11 rw	MODE10 rw	MODE9 rw	MODE8 rw	MODE7 rw	MODE6 rw	MODE5 rw	MODE4 rw	MODE3 rw	MODE2 rw	MODE1 rw	MODE0 rw

Toggle fields

MODE0

Bit 0: MODE0.

MODE1

Bit 1: MODE1.

MODE2

Bit 2: MODE2.

MODE3

Bit 3: MODE3.

MODE4

Bit 4: MODE4.

MODE5

Bit 5: MODE5.

MODE6

Bit 6: MODE6.

MODE7

Bit 7: MODE7.

MODE8

Bit 8: MODE8.

MODE9

Bit 9: MODE9.

MODE10

Bit 10: MODE10.

MODE11

Bit 11: MODE11.

MODE12

Bit 12: MODE12.

MODE13

Bit 13: MODE13.

MODE14

Bit 14: MODE14.

MODE15

Bit 15: MODE15.

LPGPIO_IDR

LPGPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: ID0.

ID1

Bit 1: ID1.

ID2

Bit 2: ID2.

ID3

Bit 3: ID3.

ID4

Bit 4: ID4.

ID5

Bit 5: ID5.

ID6

Bit 6: ID6.

ID7

Bit 7: ID7.

ID8

Bit 8: ID8.

ID9

Bit 9: ID9.

ID10

Bit 10: ID10.

ID11

Bit 11: ID11.

ID12

Bit 12: ID12.

ID13

Bit 13: ID13.

ID14

Bit 14: ID14.

ID15

Bit 15: ID15.

LPGPIO_ODR

LPGPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: OD0.

OD1

Bit 1: OD1.

OD2

Bit 2: OD2.

OD3

Bit 3: OD3.

OD4

Bit 4: OD4.

OD5

Bit 5: OD5.

OD6

Bit 6: OD6.

OD7

Bit 7: OD7.

OD8

Bit 8: OD8.

OD9

Bit 9: OD9.

OD10

Bit 10: OD10.

OD11

Bit 11: OD11.

OD12

Bit 12: OD12.

OD13

Bit 13: OD13.

OD14

Bit 14: OD14.

OD15

Bit 15: OD15.

LPGPIO_BSRR

LPGPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LPGPIO_BRR

LPGPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

LPTIM1

0x46004400: Low power timer

25/110 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR_input			DIEROK										CC2OF	CC1OF		CC2IF	REPOK	UE	DOWN	UP	ARROK		EXTTRIG	ARRM	CC1IF
0x0	ISR_output			DIEROK					CMP2OK								CC2IF	REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR_input			DIEROKCF										CC2OCF	CC1OCF		CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF		EXTTRIGCF	ARRMCF	CC1IF
0x4	ICR_output			DIEROKCF					CMP2OKCF								CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER_input		CC2DE									CC1DE		CC2OIE	CC1OIE		CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE		EXTTRIGIE	ARRMIE	CC1IF
0x8	DIER_output				UEDE				CMP2OKIE								CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL			PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																					RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL										IN2SEL				IN1SEL
0x28	RCR																		REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F			IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR_input

Interrupt and Status Register (intput mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OF r	CC1OF r			CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r		EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Capture 2 interrupt flag.

CC1OF

Bit 12: Capture 1 over-capture flag.

CC2OF

Bit 13: Capture 2 over-capture flag.

DIEROK

Bit 24: Interrupt enable register update OK.

ISR_output

Interrupt and Status Register (output mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r					CMP2OK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Compare 2 interrupt flag.

CMP2OK

Bit 19: Compare register 2 update OK.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR_input

Interrupt Clear Register (intput mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OCF w	CC1OCF w			CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w		EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CC1OCF

Bit 12: Capture/compare 1 over-capture clear flag.

CC2OCF

Bit 13: Capture/compare 2 over-capture clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

ICR_output

Interrupt Clear Register (output mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w					CMP2OKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CMP2OKCF

Bit 19: Compare register 2 update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER_input

LPTIM interrupt Enable Register (intput mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CC2DE rw									CC1DE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OIE rw	CC1OIE rw			CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw		EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CC1OIE

Bit 12: Capture/compare 1 over-capture interrupt enable.

CC2OIE

Bit 13: Capture/compare 2 over-capture interrupt enable.

CC1DE

Bit 16: Capture/compare 1 DMA request enable.

CC2DE

Bit 25: Capture/compare 2 DMA request enable.

DIER_output

LPTIM interrupt Enable Register (output mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UEDE rw				CMP2OKIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CMP2OKIE

Bit 19: Compare register 2 update OK interrupt enable.

UEDE

Bit 23: Update event DMA request enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

LPTIM2

0x40009400: Low power timer

25/110 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR_input			DIEROK										CC2OF	CC1OF		CC2IF	REPOK	UE	DOWN	UP	ARROK		EXTTRIG	ARRM	CC1IF
0x0	ISR_output			DIEROK					CMP2OK								CC2IF	REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR_input			DIEROKCF										CC2OCF	CC1OCF		CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF		EXTTRIGCF	ARRMCF	CC1IF
0x4	ICR_output			DIEROKCF					CMP2OKCF								CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER_input		CC2DE									CC1DE		CC2OIE	CC1OIE		CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE		EXTTRIGIE	ARRMIE	CC1IF
0x8	DIER_output				UEDE				CMP2OKIE								CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL			PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																					RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL										IN2SEL				IN1SEL
0x28	RCR																		REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F			IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR_input

Interrupt and Status Register (intput mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OF r	CC1OF r			CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r		EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Capture 2 interrupt flag.

CC1OF

Bit 12: Capture 1 over-capture flag.

CC2OF

Bit 13: Capture 2 over-capture flag.

DIEROK

Bit 24: Interrupt enable register update OK.

ISR_output

Interrupt and Status Register (output mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r					CMP2OK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Compare 2 interrupt flag.

CMP2OK

Bit 19: Compare register 2 update OK.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR_input

Interrupt Clear Register (intput mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OCF w	CC1OCF w			CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w		EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CC1OCF

Bit 12: Capture/compare 1 over-capture clear flag.

CC2OCF

Bit 13: Capture/compare 2 over-capture clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

ICR_output

Interrupt Clear Register (output mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w					CMP2OKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CMP2OKCF

Bit 19: Compare register 2 update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER_input

LPTIM interrupt Enable Register (intput mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CC2DE rw									CC1DE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OIE rw	CC1OIE rw			CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw		EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CC1OIE

Bit 12: Capture/compare 1 over-capture interrupt enable.

CC2OIE

Bit 13: Capture/compare 2 over-capture interrupt enable.

CC1DE

Bit 16: Capture/compare 1 DMA request enable.

CC2DE

Bit 25: Capture/compare 2 DMA request enable.

DIER_output

LPTIM interrupt Enable Register (output mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UEDE rw				CMP2OKIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CMP2OKIE

Bit 19: Compare register 2 update OK interrupt enable.

UEDE

Bit 23: Update event DMA request enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

LPTIM3

0x46004800: Low power timer

25/110 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR_input			DIEROK										CC2OF	CC1OF		CC2IF	REPOK	UE	DOWN	UP	ARROK		EXTTRIG	ARRM	CC1IF
0x0	ISR_output			DIEROK					CMP2OK								CC2IF	REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR_input			DIEROKCF										CC2OCF	CC1OCF		CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF		EXTTRIGCF	ARRMCF	CC1IF
0x4	ICR_output			DIEROKCF					CMP2OKCF								CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER_input		CC2DE									CC1DE		CC2OIE	CC1OIE		CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE		EXTTRIGIE	ARRMIE	CC1IF
0x8	DIER_output				UEDE				CMP2OKIE								CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL			PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																					RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL										IN2SEL				IN1SEL
0x28	RCR																		REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F			IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR_input

Interrupt and Status Register (intput mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OF r	CC1OF r			CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r		EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Capture 2 interrupt flag.

CC1OF

Bit 12: Capture 1 over-capture flag.

CC2OF

Bit 13: Capture 2 over-capture flag.

DIEROK

Bit 24: Interrupt enable register update OK.

ISR_output

Interrupt and Status Register (output mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r					CMP2OK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Compare 2 interrupt flag.

CMP2OK

Bit 19: Compare register 2 update OK.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR_input

Interrupt Clear Register (intput mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OCF w	CC1OCF w			CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w		EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CC1OCF

Bit 12: Capture/compare 1 over-capture clear flag.

CC2OCF

Bit 13: Capture/compare 2 over-capture clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

ICR_output

Interrupt Clear Register (output mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w					CMP2OKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CMP2OKCF

Bit 19: Compare register 2 update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER_input

LPTIM interrupt Enable Register (intput mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CC2DE rw									CC1DE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OIE rw	CC1OIE rw			CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw		EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CC1OIE

Bit 12: Capture/compare 1 over-capture interrupt enable.

CC2OIE

Bit 13: Capture/compare 2 over-capture interrupt enable.

CC1DE

Bit 16: Capture/compare 1 DMA request enable.

CC2DE

Bit 25: Capture/compare 2 DMA request enable.

DIER_output

LPTIM interrupt Enable Register (output mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UEDE rw				CMP2OKIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CMP2OKIE

Bit 19: Compare register 2 update OK interrupt enable.

UEDE

Bit 23: Update event DMA request enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

LPTIM4

0x46004c00: Low power timer

11/66 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR			DIEROK													REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR			DIEROKCF													REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER																REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL		PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																				RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL									IN2SEL				IN1SEL
0x28	RCR																	REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F		IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER

LPTIM interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

LPUART1

0x46002400: Universal synchronous asynchronous receiver transmitter

37/120 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1			DEAT					DEDT						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1			DEAT					DEDT						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD												MSBFIRST	DATAINV	TXINV	RXINV	SWAP		STOP									ADDM7
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG				TXFTIE								DEP	DEM	DDRE	OVRDIS		CTSIE	CTSE	RTSE	DMAT	DMAR			HDSEL			EIE
0xc	BRR													BRR				BRR
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ
0x1c	ISR_disabled										REACK	TEACK		RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT		RXFF	TXFF	REACK	TEACK		RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF								CTSCF			TCCF		IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR										TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFNEIE.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFNEIE.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw												MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw		STOP rw									ADDM7 rw

Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

STOP

Bits 12-13: STOP bits.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ADD

Bits 24-31: Address of the LPUART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw				TXFTIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw		CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw			HDSEL rw			EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

TXFTIE

Bit 23: TXFTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BRR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-19: BRR.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w

Toggle fields

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: TXFRQ.

ISR_disabled

Interrupt and status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXE r	TC r	RXNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ISR_enabled

Interrupt and status register

Offset: 0x1c, size: 32, reset: 0x008000C0, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r		RXFF r	TXFF r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFF

Bit 23: TXFF.

RXFF

Bit 24: RXFF.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTSCF w			TCCF w		IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TCCF

Bit 6: Transmission complete clear flag.

CTSCF

Bit 9: CTS clear flag.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Autonomous mode control register

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIGPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

MDF1

0x40025000: Multi-function digital filter

90/415 fields covered.

Toggle register map

Offset	Name	31	30	27	25	21	19	16	15	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GCR															ILVNB							TRGO
0x4	CKGCR	CKGACTIVE	PROCDIV				CCKDIV		TRGSRC						TRGSENS		CCK1DIR	CCK0DIR	CKGMOD		CCK1EN	CCK0EN	CKGDEN
0x80	MDF_SITF0CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x84	MDF_BSMX0CR	BSMXACTIVE																	BSSEL
0x88	MDF_DFLT0CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x8c	MDF_DFLT0CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x90	MDF_DFLT0RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x94	MDF_DFLT0INTR												INTVAL									INTDIV
0x98	MDF_OLD0CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x9c	MDF_OLD0THLR				OLDTHL				OLDTHL
0xa0	MDF_OLD0THHR				OLDTHH				OLDTHH
0xa4	MDF_DLY0CR	SKPBF															SKPDLY
0xa8	MDF_SCD0CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0xac	MDF_DFLT0IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0xb0	MDF_DFLT0ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0xb4	MDF_OEC0CR				OFFSET				OFFSET
0xec	MDF_SNPS0DR	SDR							EXTSDR						MCICDC
0xf0	MDF_DFLT0DR	DR							DR
0x100	MDF_SITF1CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x104	MDF_BSMX1CR	BSMXACTIVE																	BSSEL
0x108	MDF_DFLT1CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x10c	MDF_DFLT1CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x110	MDF_DFLT1RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x114	MDF_DFLT1INTR												INTVAL									INTDIV
0x118	MDF_OLD1CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x11c	MDF_OLD1THLR				OLDTHL				OLDTHL
0x120	MDF_OLD1THHR				OLDTHH				OLDTHH
0x124	MDF_DLY1CR	SKPBF															SKPDLY
0x128	MDF_SCD1CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x12c	MDF_DFLT1IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x130	MDF_DFLT1ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x134	MDF_OEC1CR				OFFSET				OFFSET
0x16c	MDF_SNPS1DR	SDR							EXTSDR						MCICDC
0x170	MDF_DFLT1DR	DR							DR
0x180	MDF_SITF2CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x184	MDF_BSMX2CR	BSMXACTIVE																	BSSEL
0x188	MDF_DFLT2CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x18c	MDF_DFLT2CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x190	MDF_DFLT2RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x194	MDF_DFLT2INTR												INTVAL									INTDIV
0x198	MDF_OLD2CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x19c	MDF_OLD2THLR				OLDTHL				OLDTHL
0x1a0	MDF_OLD2THHR				OLDTHH				OLDTHH
0x1a4	MDF_DLY2CR	SKPBF															SKPDLY
0x1a8	MDF_SCD2CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x1ac	MDF_DFLT2IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x1b0	MDF_DFLT2ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x1b4	MDF_OEC2CR				OFFSET				OFFSET
0x1ec	MDF_SNPS2DR	SDR							EXTSDR						MCICDC
0x1f0	MDF_DFLT2DR	DR							DR
0x200	MDF_SITF3CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x204	MDF_BSMX3CR	BSMXACTIVE																	BSSEL
0x208	MDF_DFLT3CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x20c	MDF_DFLT3CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x210	MDF_DFLT3RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x214	MDF_DFLT3INTR												INTVAL									INTDIV
0x218	MDF_OLD3CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x21c	MDF_OLD3THLR				OLDTHL				OLDTHL
0x220	MDF_OLD3THHR				OLDTHH				OLDTHH
0x224	MDF_DLY3CR	SKPBF															SKPDLY
0x228	MDF_SCD3CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x22c	MDF_DFLT3IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x230	MDF_DFLT3ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x234	MDF_OEC3CR				OFFSET				OFFSET
0x26c	MDF_SNPS3DR	SDR							EXTSDR						MCICDC
0x270	MDF_DFLT3DR	DR							DR
0x280	MDF_SITF4CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x284	MDF_BSMX4CR	BSMXACTIVE																	BSSEL
0x288	MDF_DFLT4CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x28c	MDF_DFLT4CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x290	MDF_DFLT4RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x294	MDF_DFLT4INTR												INTVAL									INTDIV
0x298	MDF_OLD4CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x29c	MDF_OLD4THLR				OLDTHL				OLDTHL
0x2a0	MDF_OLD4THHR				OLDTHH				OLDTHH
0x2a4	MDF_DLY4CR	SKPBF															SKPDLY
0x2a8	MDF_SCD4CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x2ac	MDF_DFLT4IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x2b0	MDF_DFLT4ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x2b4	MDF_OEC4CR				OFFSET				OFFSET
0x2ec	MDF_SNPS4DR	SDR							EXTSDR						MCICDC
0x2f0	MDF_DFLT4DR	DR							DR
0x300	MDF_SITF5CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x304	MDF_BSMX5CR	BSMXACTIVE																	BSSEL
0x308	MDF_DFLT5CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x30c	MDF_DFLT5CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x310	MDF_DFLT5RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x314	MDF_DFLT5INTR												INTVAL									INTDIV
0x318	MDF_OLD5CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x31c	MDF_OLD5THLR				OLDTHL				OLDTHL
0x320	MDF_OLD5THHR				OLDTHH				OLDTHH
0x324	MDF_DLY5CR	SKPBF															SKPDLY
0x328	MDF_SCD5CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x32c	MDF_DFLT5IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x330	MDF_DFLT5ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x334	MDF_OEC5CR				OFFSET				OFFSET
0x36c	MDF_SNPS5DR	SDR							EXTSDR						MCICDC
0x370	MDF_DFLT5DR	DR							DR

Toggle registers

GCR

MDF global control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ILVNB rw							TRGO rw

Toggle fields

TRGO

Bit 0: TRGO.

ILVNB

Bits 4-7: ILVNB.

CKGCR

MDF clock generator control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKGACTIVE rw	PROCDIV rw											CCKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		CCK1DIR rw	CCK0DIR rw	CKGMOD rw		CCK1EN rw	CCK0EN rw	CKGDEN rw

Toggle fields

CKGDEN

Bit 0: CKGDEN.

CCK0EN

Bit 1: CCK0EN.

CCK1EN

Bit 2: CCK1EN.

CKGMOD

Bit 4: CKGMOD.

CCK0DIR

Bit 5: CCK0DIR.

CCK1DIR

Bit 6: CCK1DIR.

TRGSENS

Bit 8: TRGSENS.

TRGSRC

Bits 12-15: TRGSRC.

CCKDIV

Bits 16-19: CCKDIV.

PROCDIV

Bits 24-30: PROCDIV.

CKGACTIVE

Bit 31: CKGACTIVE.

MDF_SITF0CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x80, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX0CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT0CR

This register is used to control the digital filter x.

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT0CICR

This register is used to control the main CIC filter.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT0RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT0INTR

This register is used to the integrator (INT) settings.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD0CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD0THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD0THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY0CR

This register is used for the adjustment stream delays.

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD0CR

This register is used for the adjustment stream delays.

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT0IER

This register is used for allowing or not the events to generate an interrupt.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT0ISR

MDF DFLT0 interrupt status register 0

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: FTHF.

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on , writing 0 has no effect. - 1: Reading 1 means that a new data is available on , writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was higher than OLDTHL when the last OLD event occurred. - 1: The signal was lower than OLDTHL when the last OLD event occurred..

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH when the last OLD event occurred. - 1: The signal was higher than OLDTHH when the last OLD event occurred..

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC0CR

This register contains the offset compensation value.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS0DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0xec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT0DR

This register is used to read the data processed by each digital filter.

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF1CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x100, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag.

MDF_BSMX1CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT1CR

This register is used to control the digital filter x.

Offset: 0x108, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT1CICR

This register is used to control the main CIC filter.

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT1RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT1INTR

This register is used to the integrator (INT) settings.

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD1CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x118, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD1THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD1THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY1CR

This register is used for the adjustment stream delays.

Offset: 0x124, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD1CR

This register is used for the adjustment stream delays.

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT1IER

MDF DFLTx interrupt enable register x

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT1ISR

This register contains the status flags for each digital filter path.

Offset: 0x130, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC1CR

This register contains the offset compensation value.

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS1DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT1DR

This register is used to read the data processed by each digital filter.

Offset: 0x170, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF2CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x180, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag.

MDF_BSMX2CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x184, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT2CR

This register is used to control the digital filter 2.

Offset: 0x188, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT2CICR

This register is used to control the main CIC filter.

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT2RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT2INTR

This register is used to the integrator (INT) settings.

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD2CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x198, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD2THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD2THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY2CR

This register is used for the adjustment stream delays.

Offset: 0x1a4, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD2CR

This register is used for the adjustment stream delays.

Offset: 0x1a8, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT2IER

MDF DFLTx interrupt enable register x

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT2ISR

This register contains the status flags for each digital filter path.

Offset: 0x1b0, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC2CR

This register contains the offset compensation value.

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS2DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT2DR

This register is used to read the data processed by each digital filter.

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF3CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x200, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX3CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x204, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to a in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT3CR

This register is used to control the digital filter 3.

Offset: 0x208, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT3CICR

This register is used to control the main CIC filter.

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT3RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT3INTR

This register is used to the integrator (INT) settings.

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD3CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x218, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD3THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD3THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY3CR

This register is used for the adjustment stream delays.

Offset: 0x224, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD3CR

This register is used for the adjustment stream delays.

Offset: 0x228, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT3IER

MDF DFLTx interrupt enable register x

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT3ISR

This register contains the status flags for each digital filter path.

Offset: 0x230, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC3CR

This register contains the offset compensation value.

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS3DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT3DR

This register is used to read the data processed by each digital filter.

Offset: 0x270, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF4CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x280, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX4CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x284, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT4CR

This register is used to control the digital filter 4.

Offset: 0x288, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT4CICR

This register is used to control the main CIC filter.

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT4RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT4INTR

This register is used to the integrator (INT) settings.

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD4CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x298, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD4THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD4THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY4CR

This register is used for the adjustment stream delays.

Offset: 0x2a4, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD4CR

This register is used for the adjustment stream delays.

Offset: 0x2a8, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT4IER

MDF DFLTx interrupt enable register x

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT4ISR

This register contains the status flags for each digital filter path.

Offset: 0x2b0, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC4CR

This register contains the offset compensation value.

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS4DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT4DR

This register is used to read the data processed by each digital filter.

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF5CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x300, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX5CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x304, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT5CR

This register is used to control the digital filter x.

Offset: 0x308, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT5CICR

This register is used to control the main CIC filter.

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT5RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT5INTR

This register is used to the integrator (INT) settings.

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD5CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x318, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD5THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD5THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY5CR

This register is used for the adjustment stream delays.

Offset: 0x324, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD5CR

This register is used for the adjustment stream delays.

Offset: 0x328, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT5IER

MDF DFLTx interrupt enable register x

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT5ISR

This register contains the status flags for each digital filter path.

Offset: 0x330, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC5CR

This register contains the offset compensation value.

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS5DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x36c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT5DR

This register is used to read the data processed by each digital filter.

Offset: 0x370, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

OCTOSPI1

0x420d1400: OctoSPI

7/95 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	23	22	21	20	19	18	17	16	15	13	12	11	10	7	6	5	4	3	2	1	0
0x0	CR			FMODE				PMM	APMS		TOIE	SMIE	FTIE	TCIE	TEIE			FTHRES			FSEL	DQM			TCEN	DMAEN	ABORT	EN
0x8	DCR1						MTYP				DEVSIZE						CSHT								DLYBYP		FRCK	CKMODE
0xc	DCR2												WRAPSIZE								PRESCALER
0x10	DCR3										CSBOUND										MAXTRAN
0x14	DCR4	REFRESH														REFRESH
0x20	SR																FLEVEL						BUSY	TOF	SMF	FTF	TCF	TEF
0x24	FCR																							CTOF	CSMF		CTCF	CTEF
0x40	DLR	DL														DL
0x48	AR	ADDRESS														ADDRESS
0x50	DR	DATA														DATA
0x80	PSMKR	MASK														MASK
0x88	PSMAR	MATCH														MATCH
0x90	PIR															INTERVAL
0x100	CCR	SIOO		DQSE		DDTR	DMODE			ABSIZE		ABDTR	ABMODE						ADDTR	ADMODE			ISIZE		IDTR	IMODE
0x108	TCR		SSHIFT		DHQC																			DCYC
0x110	IR	INSTRUCTION														INSTRUCTION
0x120	ABR	ALTERNATE														ALTERNATE
0x130	LPTR															TIMEOUT
0x140	WPCCR			DQSE		DDTR	DMODE			ABSIZE		ABDTR	ABMODE						ADDTR	ADMODE			ISIZE		IDTR	IMODE
0x148	WPTCR		SSHIFT		DHQC																			DCYC
0x150	WPIR	INSTRUCTION														INSTRUCTION
0x160	WPABR	ALTERNATE														ALTERNATE
0x180	WCCR			DQSE		DDTR	DMODE			ABSIZE		ABDTR	ABMODE						ADDTR	ADMODE			ISIZE		IDTR	IMODE
0x188	WTCR																							DCYC
0x190	WIR	INSTRUCTION														INSTRUCTION
0x1a0	WABR	ALTERNATE														ALTERNATE
0x200	HLCR							TRWR								TACC											WZL	LM

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FMODE rw						PMM rw	APMS rw		TOIE rw	SMIE rw	FTIE rw	TCIE rw	TEIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTHRES rw					FSEL rw	DQM rw			TCEN rw	DMAEN rw	ABORT rw	EN rw

Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					MTYP rw						DEVSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CSHT rw										DLYBYP rw		FRCK rw	CKMODE rw

Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

DLYBYP

Bit 3: Delay block bypass.

CSHT

Bits 8-13: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-26: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WRAPSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PRESCALER rw

Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											CSBOUND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAXTRAN rw

Toggle fields

MAXTRAN

Bits 0-7: Maximum transfer.

CSBOUND

Bits 16-20: CS boundary.

DCR4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REFRESH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REFRESH rw

Toggle fields

REFRESH

Bits 0-31: Refresh rate.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		FLEVEL r								BUSY r	TOF r	SMF r	FTF r	TCF r	TEF r

Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: status match flag.

TOF

Bit 4: timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CTOF w	CSMF w		CTCF w	CTEF w

Toggle fields

CTEF

Bit 0: Clear Transfer error flag.

CTCF

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SIOO rw		DQSE rw		DDTR rw	DMODE rw					ABSIZE rw		ABDTR rw	ABMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ADDTR rw	ADMODE rw					ISIZE rw		IDTR rw	IMODE rw

Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SSHIFT rw		DHQC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DCYC rw

Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INSTRUCTION rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUT rw

Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WPCCR

wrap communication configuration register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		DQSE rw		DDTR rw	DMODE rw					ABSIZE rw		ABDTR rw	ABMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ADDTR rw	ADMODE rw					ISIZE rw		IDTR rw	IMODE rw

Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPTCR

wrap timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SSHIFT rw		DHQC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DCYC rw

Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPIR

wrap instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INSTRUCTION rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPABR

wrap alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WCCR

write communication configuration register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		DQSE rw		DDTR rw	DMODE rw					ABSIZE rw		ABDTR rw	ABMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ADDTR rw	ADMODE rw					ISIZE rw		IDTR rw	IMODE rw

Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WTCR

write timing configuration register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DCYC rw

Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

WIR

write instruction register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INSTRUCTION rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: ALTERNATE.

HLCR

HyperBus latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TRWR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TACC rw														WZL rw	LM rw

Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

OPAMP

0x46005000: Operational amplifiers

2/31 fields covered.

Toggle register map

Offset	Name	31	30	15	14	13	12	10	9	5	4	3	1	0
0x0	OPAMP1_CSR	OPA_RANGE	OPAHSM	CALOUT	USERTRIM	CALSEL	CALON	VP_SEL	VM_SEL	PGA_GAIN		OPAMODE	OPALPM	OPAEN
0x4	OPAMP1_OTR						TRIMOFFSETP				TRIMOFFSETN
0x8	OPAMP1_LPOTR						TRIMLPOFFSETP				TRIMLPOFFSETN
0x10	OPAMP2_CRS		OPAHSM	CALOUT	USERTRIM	CALSEL	CALON	VP_SEL	VM_SEL	PGA_GAIN		OPAMODE	OPALPM	OPAEN
0x14	OPAMP2_OTR						TRIMOFFSETP				TRIMOFFSETN
0x18	OPAMP2_LPOTR						TRIMLPOFFSETP				TRIMLPOFFSETN

Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPA_RANGE rw	OPAHSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALOUT r	USERTRIM rw	CALSEL rw	CALON rw		VP_SEL rw	VM_SEL rw				PGA_GAIN rw		OPAMODE rw		OPALPM rw	OPAEN rw

Toggle fields

OPAEN

Bit 0: OPAMP enable.

OPALPM

Bit 1: OPAMP low-power mode The OPAMP must be disabled to change this configuration..

OPAMODE

Bits 2-3: OPAMP PGA mode 00 and 01: internal PGA disabled.

PGA_GAIN

Bits 4-5: OPAMP programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 1x: inverting input not externally connected.

VP_SEL

Bit 10: Non-inverted input selection.

CALON

Bit 12: Calibration mode enable.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-power modes..

CALOUT

Bit 15: OPAMP calibration output During the calibration mode, the offset is trimmed when this signal toggles..

OPAHSM

Bit 30: OPAMP high-speed mode This bit is effective for both normal and low-power modes..

OPA_RANGE

Bit 31: OPAMP range setting This bit must be set before enabling the OPAMP and this bit affects all OPAMP instances..

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMOFFSETP rw								TRIMOFFSETN rw

Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-power mode

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMLPOFFSETP rw								TRIMLPOFFSETN rw

Toggle fields

TRIMLPOFFSETN

Bits 0-4: Low-power mode trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Low-power mode trim for PMOS differential pairs.

OPAMP2_CRS

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	OPAHSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALOUT r	USERTRIM rw	CALSEL rw	CALON rw		VP_SEL rw	VM_SEL rw				PGA_GAIN rw		OPAMODE rw		OPALPM rw	OPAEN rw

Toggle fields

OPAEN

Bit 0: OPAMP enable.

OPALPM

Bit 1: OPAMP low-power mode The OPAMP must be disabled to change this configuration..

OPAMODE

Bits 2-3: OPAMP PGA mode 00 and 01: internal PGA disabled.

PGA_GAIN

Bits 4-5: OPAMP programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. in PGA mode for filtering) 1x: inverting input not externally connected.

VP_SEL

Bit 10: Non inverted input selection.

CALON

Bit 12: Calibration mode enable.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-power modes..

CALOUT

Bit 15: OPAMP calibration output During calibration mode, the offset is trimmed when this signal toggles..

OPAHSM

Bit 30: OPAMP high-speed mode This bit is effective for both normal and high-speed modes..

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMOFFSETP rw								TRIMOFFSETN rw

Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMLPOFFSETP rw								TRIMLPOFFSETN rw

Toggle fields

TRIMLPOFFSETN

Bits 0-4: Low-power mode trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Low-power mode trim for PMOS differential pairs.

PSSI

0x4202c400: PSSI

4/18 fields covered.

Toggle register map

Offset	Name	31	30	23	20	15	14	11	8	7	6	5	3	2	1
0x0	CR	OUTEN	DMAEN		DERDYCFG		ENABLE	EDM	RDYPOL		DEPOL	CKPOL
0x4	SR												RTT1B	RTT4B
0x8	RIS														OVR_RIS
0xc	IER														OVR_IE
0x10	MIS														OVR_MIS
0x14	ICR														OVR_ISC
0x28	DR	BYTE3		BYTE2		BYTE1				BYTE0

Toggle registers

CR

PSSI control register

Offset: 0x0, size: 32, reset: 0x40000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUTEN rw	DMAEN rw										DERDYCFG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	ENABLE rw			EDM rw			RDYPOL rw		DEPOL rw	CKPOL rw

Toggle fields

CKPOL

Bit 5: Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN..

DEPOL

Bit 6: Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface..

RDYPOL

Bit 8: Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface..

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time..

DERDYCFG

Bits 18-20: Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity..

DMAEN

Bit 30: DMA enable bit.

OUTEN

Bit 31: Data direction selection bit.

SR

PSSI status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												RTT1B r	RTT4B r

Toggle fields

RTT4B

Bit 2: RTT4B.

RTT1B

Bit 3: RTT1B.

RIS

PSSI raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_RIS r

Toggle fields

OVR_RIS

Bit 1: OVR_RIS.

IER

PSSI interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_IE rw

Toggle fields

OVR_IE

Bit 1: OVR_IE.

MIS

PSSI masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_MIS r

Toggle fields

OVR_MIS

Bit 1: OVR_MIS.

ICR

PSSI interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_ISC w

Toggle fields

OVR_ISC

Bit 1: OVR_ISC.

DR

PSSI data register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BYTE3 rw								BYTE2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BYTE1 rw								BYTE0 rw

Toggle fields

BYTE0

Bits 0-7: Data byte 0.

BYTE1

Bits 8-15: Data byte 1.

BYTE2

Bits 16-23: Data byte 2.

BYTE3

Bits 24-31: Data byte 3.

PWR

0x46020800: Power control

24/444 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	PWR_CR1																				SRAM5PD	SRAM4PD		SRAM2PD	SRAM1PD	ULPMEN	RRSB2	RRSB1			LPMS
0x4	PWR_CR2	SRDRUN																	FLASHFWU	SRAM4FWU		PRAMPDS		DC1RAMPDS	ICRAMPDS		SRAM4PDS	SRAM2PDS2	SRAM2PDS1		SRAM1PDS3	SRAM1PDS2	SRAM1PDS1
0x8	PWR_CR3																														FSTEN	REGSEL
0xc	PWR_VOSR												USBBOOSTEN	USBPWREN	BOOSTEN	VOS		VOSRDY	BOOSTRDY	USBBOOSTRDY
0x10	PWR_SVMCR		ASV	IO2SV	USV	AVM2EN	AVM1EN	IO2VMEN	UVMEN																	PVDLS			PVDE
0x14	PWR_WUCR1																									WUPEN8	WUPEN7	WUPEN6	WUPEN5	WUPEN4	WUPEN3	WUPEN2	WUPEN1
0x18	PWR_WUCR2																									WUPP8	WUPP7	WUPP6	WUPP5	WUPP4	WUPP3	WUPP2	WUPP1
0x1c	PWR_WUCR3																	WUSEL8		WUSEL7		WUSEL6		WUSEL5		WUSEL4		WUSEL3		WUSEL2		WUSEL1
0x20	PWR_BDCR1																												MONEN				BREN
0x24	PWR_BDCR2																															VBRS	VBE
0x28	PWR_DBPR																																DBP
0x2c	PWR_UCPDR																															UCPD_STBY	UCPD_DBDIS
0x30	PWR_SECCFGR																	APCSEC	VBSEC	VDMSEC	LPMSEC					WUP8SEC	WUP7SEC	WUP6SEC	WUP5SEC	WUP4SEC	WUP3SEC	WUP2SEC	WUP1SEC
0x34	PWR_PRIVCFGR																															NSPRIV	SPRIV
0x38	PWR_SR																														SBF	STOPF	CSSF
0x3c	PWR_SVMSR					VDDA2RDY	VDDA1RDY	VDDIO2RDY	VDDUSBRDY							ACTVOS		ACTVOSRDY											PVDO			REGS
0x40	PWR_BDSR																													TEMPH	TEMPL	VBATH
0x44	PWR_WUSR																									WUF8	WUF7	WUF6	WUF5	WUF4	WUF3	WUF2	WUF1
0x48	PWR_WUSCR																									CWUF8	CWUF7	CWUF6	CWUF5	CWUF4	CWUF3	CWUF2	CWUF1
0x4c	PWR_APCR																																APC
0x50	PWR_PUCRA																	PU15		PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x54	PWR_PDCRA																		PD14		PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x58	PWR_PUCRB																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x5c	PWR_PDCRB																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5		PD3	PD2	PD1	PD0
0x60	PWR_PUCRC																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x64	PWR_PDCRC																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x68	PWR_PUCRD																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x6c	PWR_PDCRD																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x70	PWR_PUCRE																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x74	PWR_PDCRE																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x78	PWR_PUCRF																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x7c	PWR_PDCRF																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x80	PWR_PUCRG																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x84	PWR_PDCRG																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x88	PWR_PUCRH																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x8c	PWR_PDCRH																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x90	PWR_PUCRI																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x94	PWR_PDCRI																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x98	PWR_PUCRJ																					PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x9c	PWR_PDCRJ																					PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0xa8	PWR_CR4				SRAM5PDS13	SRAM5PDS12	SRAM5PDS11	SRAM5PDS10	SRAM5PDS9	SRAM5PDS8	SRAM5PDS7	SRAM5PDS6	SRAM5PDS5	SRAM5PDS4	SRAM5PDS3	SRAM5PDS2	SRAM5PDS1								SRAM1PDS12	SRAM1PDS11	SRAM1PDS10	SRAM1PDS9	SRAM1PDS8	SRAM1PDS7	SRAM1PDS6	SRAM1PDS5	SRAM1PDS4

Toggle registers

PWR_CR1

PWR control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SRAM5PD rw	SRAM4PD rw		SRAM2PD rw	SRAM1PD rw	ULPMEN rw	RRSB2 rw	RRSB1 rw			LPMS rw

Toggle fields

LPMS

Bits 0-2: Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1.

RRSB1

Bit 5: SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode..

RRSB2

Bit 6: SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode..

ULPMEN

Bit 7: BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes..

SRAM1PD

Bit 8: SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1..

SRAM2PD

Bit 9: SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2..

SRAM4PD

Bit 11: SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4..

SRAM5PD

Bit 12: SRAM5 power down This bit is used to reduce the consumption by powering off the SRAM5. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

PWR_CR2

PWR control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRDRUN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FLASHFWU rw	SRAM4FWU rw		PRAMPDS rw		DC1RAMPDS rw	ICRAMPDS rw		SRAM4PDS rw	SRAM2PDS2 rw	SRAM2PDS1 rw		SRAM1PDS3 rw	SRAM1PDS2 rw	SRAM1PDS1 rw

Toggle fields

SRAM1PDS1

Bit 0: SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM1PDS2

Bit 1: SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM1PDS3

Bit 2: SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM2PDS1

Bit 4: SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1..

SRAM2PDS2

Bit 5: SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1..

SRAM4PDS

Bit 6: SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3).

ICRAMPDS

Bit 8: ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3).

DC1RAMPDS

Bit 9: DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3).

PRAMPDS

Bit 11: FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM4FWU

Bit 13: SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes..

FLASHFWU

Bit 14: Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption..

SRDRUN

Bit 31: SmartRun domain in Run mode.

PWR_CR3

PWR control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FSTEN rw	REGSEL rw

Toggle fields

REGSEL

Bit 1: Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS..

FSTEN

Bit 2: Fast soft start.

PWR_VOSR

PWR voltage scaling register

Offset: 0xc, size: 32, reset: 0x00008000, access: read-write

3/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											USBBOOSTEN rw	USBPWREN rw	BOOSTEN rw	VOS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VOSRDY r	BOOSTRDY r	USBBOOSTRDY r

Toggle fields

USBBOOSTRDY

Bit 13: USB EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The USB clock can be provided only after this bit is set. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

BOOSTRDY

Bit 14: EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set..

VOSRDY

Bit 15: Ready bit for VCORE voltage scaling output selection.

VOS

Bits 16-17: Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1..

BOOSTEN

Bit 18: EPOD booster enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. This bit must be set in range 1 and range 2 before increasing the system clock frequency above 50 MHz. This bit is reset when going into Stop modes (0, 1, 2, 3)..

USBPWREN

Bit 19: USB power enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

USBBOOSTEN

Bit 20: USB EPOD booster enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. This bit must be set in range 1 and range 2 before enabling the USB peripheral. This bit is reset when going into Stop modes (0, 1, 2, 3). Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

PWR_SVMCR

PWR supply voltage monitoring control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	ASV rw	IO2SV rw	USV rw	AVM2EN rw	AVM1EN rw	IO2VMEN rw	UVMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PVDLS rw			PVDE rw

Toggle fields

PVDE

Bit 4: Power voltage detector enable.

PVDLS

Bits 5-7: Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector:.

UVMEN

Bit 24: VDDUSB independent USB voltage monitor enable.

IO2VMEN

Bit 25: VDDIO2 independent I/Os voltage monitor enable.

AVM1EN

Bit 26: VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold).

AVM2EN

Bit 27: VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold).

USV

Bit 28: VDDUSB independent USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not..

IO2SV

Bit 29: VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not..

ASV

Bit 30: VDDA independent analog supply valid This bit is used to validate the VDDA supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the analog peripherals. If VDDA is not always present in the application, the VDDA voltage monitor can be used to determine whether this supply is ready or not..

PWR_WUCR1

PWR wakeup control register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUPEN8 rw	WUPEN7 rw	WUPEN6 rw	WUPEN5 rw	WUPEN4 rw	WUPEN3 rw	WUPEN2 rw	WUPEN1 rw

Toggle fields

WUPEN1

Bit 0: Wakeup pin WKUP1 enable.

WUPEN2

Bit 1: Wakeup pin WKUP2 enable.

WUPEN3

Bit 2: Wakeup pin WKUP3 enable.

WUPEN4

Bit 3: Wakeup pin WKUP4 enable.

WUPEN5

Bit 4: Wakeup pin WKUP5 enable.

WUPEN6

Bit 5: Wakeup pin WKUP6 enable.

WUPEN7

Bit 6: Wakeup pin WKUP7 enable.

WUPEN8

Bit 7: Wakeup pin WKUP8 enable.

PWR_WUCR2

PWR wakeup control register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUPP8 rw	WUPP7 rw	WUPP6 rw	WUPP5 rw	WUPP4 rw	WUPP3 rw	WUPP2 rw	WUPP1 rw

Toggle fields

WUPP1

Bit 0: Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0..

WUPP2

Bit 1: Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0..

WUPP3

Bit 2: Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0..

WUPP4

Bit 3: Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0..

WUPP5

Bit 4: Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0..

WUPP6

Bit 5: Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0..

WUPP7

Bit 6: Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0..

WUPP8

Bit 7: Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0..

PWR_WUCR3

PWR wakeup control register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUSEL8 rw		WUSEL7 rw		WUSEL6 rw		WUSEL5 rw		WUSEL4 rw		WUSEL3 rw		WUSEL2 rw		WUSEL1 rw

Toggle fields

WUSEL1

Bits 0-1: Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0..

WUSEL2

Bits 2-3: Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0..

WUSEL3

Bits 4-5: Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0..

WUSEL4

Bits 6-7: Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0..

WUSEL5

Bits 8-9: Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0..

WUSEL6

Bits 10-11: Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0..

WUSEL7

Bits 12-13: Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0..

WUSEL8

Bits 14-15: Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0..

PWR_BDCR1

PWR Backup domain control register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MONEN rw				BREN rw

Toggle fields

BREN

Bit 0: Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode..

MONEN

Bit 4: Backup domain voltage and temperature monitoring enable.

PWR_BDCR2

PWR Backup domain control register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														VBRS rw	VBE rw

Toggle fields

VBE

Bit 0: VBAT charging enable.

VBRS

Bit 1: VBAT charging resistor selection.

PWR_DBPR

PWR disable Backup domain register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															DBP rw

Toggle fields

DBP

Bit 0: Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers..

PWR_UCPDR

PWR USB Type-C™ and Power Delivery register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UCPD_STBY rw	UCPD_DBDIS rw

Toggle fields

UCPD_DBDIS

Bit 0: UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)..

UCPD_STBY

Bit 1: UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers..

PWR_SECCFGR

PWR security configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
APCSEC rw	VBSEC rw	VDMSEC rw	LPMSEC rw					WUP8SEC rw	WUP7SEC rw	WUP6SEC rw	WUP5SEC rw	WUP4SEC rw	WUP3SEC rw	WUP2SEC rw	WUP1SEC rw

Toggle fields

WUP1SEC

Bit 0: WUP1 secure protection.

WUP2SEC

Bit 1: WUP2 secure protection.

WUP3SEC

Bit 2: WUP3 secure protection.

WUP4SEC

Bit 3: WUP4 secure protection.

WUP5SEC

Bit 4: WUP5 secure protection.

WUP6SEC

Bit 5: WUP6 secure protection.

WUP7SEC

Bit 6: WUP7 secure protection.

WUP8SEC

Bit 7: WUP8 secure protection.

LPMSEC

Bit 12: Low-power modes secure protection.

VDMSEC

Bit 13: Voltage detection and monitoring secure protection.

VBSEC

Bit 14: Backup domain secure protection.

APCSEC

Bit 15: Pull-up/pull-down secure protection.

PWR_PRIVCFGR

PWR privilege control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														NSPRIV rw	SPRIV rw

Toggle fields

SPRIV

Bit 0: PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access..

NSPRIV

Bit 1: PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure..

PWR_SR

PWR status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													SBF r	STOPF r	CSSF w

Toggle fields

CSSF

Bit 0: Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. Writing 1 to this bit clears the STOPF and SBF flags..

STOPF

Bit 1: Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit..

SBF

Bit 2: Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset..

PWR_SVMSR

PWR supply voltage monitoring status register

Offset: 0x3c, size: 32, reset: 0x00008000, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				VDDA2RDY r	VDDA1RDY r	VDDIO2RDY r	VDDUSBRDY r							ACTVOS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTVOSRDY r											PVDO r			REGS r

Toggle fields

REGS

Bit 1: Regulator selection.

PVDO

Bit 4: VDD voltage detector output.

ACTVOSRDY

Bit 15: Voltage level ready for currently used VOS.

ACTVOS

Bits 16-17: VOS currently applied to VCORE This field provides the last VOS value..

VDDUSBRDY

Bit 24: VDDUSB ready.

VDDIO2RDY

Bit 25: VDDIO2 ready.

VDDA1RDY

Bit 26: VDDA ready versus 1.6V voltage monitor.

VDDA2RDY

Bit 27: VDDA ready versus 1.8 V voltage monitor.

PWR_BDSR

PWR Backup domain status register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TEMPH r	TEMPL r	VBATH r

Toggle fields

VBATH

Bit 1: Backup domain voltage level monitoring versus high threshold.

TEMPL

Bit 2: Temperature level monitoring versus low threshold.

TEMPH

Bit 3: Temperature level monitoring versus high threshold.

PWR_WUSR

PWR wakeup status register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUF8 r	WUF7 r	WUF6 r	WUF5 r	WUF4 r	WUF3 r	WUF2 r	WUF1 r

Toggle fields

WUF1

Bit 0: Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0..

WUF2

Bit 1: Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0..

WUF3

Bit 2: Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0..

WUF4

Bit 3: Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0..

WUF5

Bit 4: Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0..

WUF6

Bit 5: Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared..

WUF7

Bit 6: Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared..

WUF8

Bit 7: Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared..

PWR_WUSCR

PWR wakeup status clear register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CWUF8 w	CWUF7 w	CWUF6 w	CWUF5 w	CWUF4 w	CWUF3 w	CWUF2 w	CWUF1 w

Toggle fields

CWUF1

Bit 0: Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR..

CWUF2

Bit 1: Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR..

CWUF3

Bit 2: Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR..

CWUF4

Bit 3: Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR..

CWUF5

Bit 4: Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR..

CWUF6

Bit 5: Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR..

CWUF7

Bit 6: Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR..

CWUF8

Bit 7: Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR..

PWR_APCR

PWR apply pull configuration register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															APC rw

Toggle fields

APC

Bit 0: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os..

PWR_PUCRA

PWR port A pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw		PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU15

Bit 15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set..

PWR_PDCRA

PWR port A pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PD14 rw		PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD14

Bit 14: Port A pull-down bit 14 When set, this bit activates the pull-down on PA14 when the APC bit is set in PWR_APCR..

PWR_PUCRB

PWR port B pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRB

PWR port B pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw		PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRC

Power port C pull up control register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: PU0.

PU1

Bit 1: PU1.

PU2

Bit 2: PU2.

PU3

Bit 3: PU3.

PU4

Bit 4: PU4.

PU5

Bit 5: PU5.

PU6

Bit 6: PU6.

PU7

Bit 7: PU7.

PU8

Bit 8: PU8.

PU9

Bit 9: PU9.

PU10

Bit 10: PU10.

PU11

Bit 11: PU11.

PU12

Bit 12: PU12.

PU13

Bit 13: PU13.

PU14

Bit 14: PU14.

PU15

Bit 15: PU15.

PWR_PDCRC

PWR port C pull-down control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRD

PWR port D pull-up control register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRD

PWR port D pull-down control register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRE

PWR port E pull-up control register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRE

PWR port E pull-down control register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRF

PWR port F pull-up control register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRF

PWR port F pull-down control register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRG

PWR port G pull-up control register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRG

PWR port G pull-down control register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRH

PWR port H pull-up control register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRH

PWR port H pull-down control register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRI

PWR port I pull-up control register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRI

PWR port I pull-down control register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRJ

PWR port J pull-up control register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PWR_PDCRJ

PWR port J pull-down control register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PWR_CR4

PWR control register 4

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SRAM5PDS13 rw	SRAM5PDS12 rw	SRAM5PDS11 rw	SRAM5PDS10 rw	SRAM5PDS9 rw	SRAM5PDS8 rw	SRAM5PDS7 rw	SRAM5PDS6 rw	SRAM5PDS5 rw	SRAM5PDS4 rw	SRAM5PDS3 rw	SRAM5PDS2 rw	SRAM5PDS1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAM1PDS12 rw	SRAM1PDS11 rw	SRAM1PDS10 rw	SRAM1PDS9 rw	SRAM1PDS8 rw	SRAM1PDS7 rw	SRAM1PDS6 rw	SRAM1PDS5 rw	SRAM1PDS4 rw

Toggle fields

SRAM1PDS4

Bit 0: .

SRAM1PDS5

Bit 1: .

SRAM1PDS6

Bit 2: .

SRAM1PDS7

Bit 3: .

SRAM1PDS8

Bit 4: .

SRAM1PDS9

Bit 5: .

SRAM1PDS10

Bit 6: .

SRAM1PDS11

Bit 7: .

SRAM1PDS12

Bit 8: .

SRAM5PDS1

Bit 16: .

SRAM5PDS2

Bit 17: .

SRAM5PDS3

Bit 18: .

SRAM5PDS4

Bit 19: .

SRAM5PDS5

Bit 20: .

SRAM5PDS6

Bit 21: .

SRAM5PDS7

Bit 22: .

SRAM5PDS8

Bit 23: .

SRAM5PDS9

Bit 24: .

SRAM5PDS10

Bit 25: .

SRAM5PDS11

Bit 26: .

SRAM5PDS12

Bit 27: .

SRAM5PDS13

Bit 28: .

RAMCFG

0x40026000: RAMCFG

24/136 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	M1CR														WSC										SRAMER				ALE				ECCE
0x8	M1ISR																								SRAMBUSY							DED	SEDC
0x28	RAM1ERKEYR																									ERASEKEY
0x40	M2CR														WSC										SRAMER				ALE				ECCE
0x44	M2IER																													ECCNMI		DEIE	SEIE
0x48	M2ISR																								SRAMBUSY							DED	SEDC
0x4c	M2SEAR	ESEA																ESEA
0x50	M2DEAR	EDEA																EDEA
0x54	M2ICR																															CDED	CSEDC
0x58	M2WPR1	P31WP	P30WP	P29WP	P28WP	P27WP	P26WP	P25WP	P24WP	P23WP	P22WP	P21WP	P20WP	P19WP	P18WP	P17WP	P16WP	P15WP	P14WP	P13WP	P12WP	P11WP	P10WP	P9WP	P8WP	P7WP	P6WP	P5WP	P4WP	P3WP	P2WP	P1WP	P0WP
0x5c	M2WPR2	P63WP	P62WP	P61WP	P60WP	P59WP	P58WP	P57WP	P56WP	P55WP	P54WP	P53WP	P52WP	P51WP	P50WP	P49WP	P48WP	P47WP	P46WP	P45WP	P44WP	P43WP	P42WP	P41WP	P40WP	P39WP	P38WP	P37WP	P36WP	P35WP	P34WP	P33WP	P32WP
0x64	M2ECCKEYR																									ECCKEY
0x68	M2ERKEYR																									ERASEKEY
0x80	M3CR														WSC										SRAMER				ALE				ECCE
0x84	M3IER																													ECCNMI		DEIE	SEIE
0x88	M3ISR																								SRAMBUSY							DED	SEDC
0x8c	M3SEAR	ESEA																ESEA
0x90	M3DEAR	EDEA																EDEA
0x94	M3ICR																															CDED	CSEDC
0xa4	M3ECCKEYR																									ECCKEY
0xa8	M3ERKEYR																									ERASEKEY
0xc0	M4CR														WSC										SRAMER				ALE				ECCE
0xc8	M4ISR																								SRAMBUSY							DED	SEDC
0xe8	M4ERKEYR																									ERASEKEY
0x100	M5CR														WSC										SRAMER				ALE				ECCE
0x104	M5IER																													ECCNMI		DEIE	SEIE
0x108	M5ISR																								SRAMBUSY							DED	SEDC
0x10c	M5SEAR	ESEA																ESEA
0x110	M5DEAR	EDEA																EDEA
0x114	M5ICR																															CDED	CSEDC
0x124	M5ECCKEYR																									ECCKEY
0x128	M5ERKEYR																									ERASEKEY
0x140	M6CR														WSC										SRAMER				ALE				ECCE
0x148	M6ISR																								SRAMBUSY							DED	SEDC
0x168	M6ERKEYR																									ERASEKEY

Toggle registers

M1CR

RAMCFG SRAM x control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

Toggle fields

ECCE

Bit 0: ECCE.

ALE

Bit 4: ALE.

SRAMER

Bit 8: SRAMER.

WSC

Bits 16-18: WSC.

M1ISR

RAMCFG RAMx interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMBUSY r							DED r	SEDC r

Toggle fields

SEDC

Bit 0: SEDC.

DED

Bit 1: DED.

SRAMBUSY

Bit 8: SRAMBUSY.

RAM1ERKEYR

RAMCFG SRAM x erase key register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: ERASEKEY.

M2CR

RAMCFG SRAM x control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ESEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ESEA r

Toggle fields

ESEA

Bits 0-31: ESEA.

M2DEAR

RAMCFG RAM x ECC double error address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EDEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EDEA r

Toggle fields

EDEA

Bits 0-31: EDEA.

M2ICR

RAMCFG RAM x interrupt clear register x

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CDED rw	CSEDC rw

Toggle fields

CSEDC

Bit 0: CSEDC.

CDED

Bit 1: CDED.

M2WPR1

RAMCFG SRAM2 write protection register 1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P31WP rw	P30WP rw	P29WP rw	P28WP rw	P27WP rw	P26WP rw	P25WP rw	P24WP rw	P23WP rw	P22WP rw	P21WP rw	P20WP rw	P19WP rw	P18WP rw	P17WP rw	P16WP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P15WP rw	P14WP rw	P13WP rw	P12WP rw	P11WP rw	P10WP rw	P9WP rw	P8WP rw	P7WP rw	P6WP rw	P5WP rw	P4WP rw	P3WP rw	P2WP rw	P1WP rw	P0WP rw

Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: P31WP.

M2WPR2

RAMCFG SRAM2 write protection register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P63WP rw	P62WP rw	P61WP rw	P60WP rw	P59WP rw	P58WP rw	P57WP rw	P56WP rw	P55WP rw	P54WP rw	P53WP rw	P52WP rw	P51WP rw	P50WP rw	P49WP rw	P48WP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P47WP rw	P46WP rw	P45WP rw	P44WP rw	P43WP rw	P42WP rw	P41WP rw	P40WP rw	P39WP rw	P38WP rw	P37WP rw	P36WP rw	P35WP rw	P34WP rw	P33WP rw	P32WP rw

Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: P63WP.

M2ECCKEYR

RAMCFG SRAM x ECC key register

Offset: 0x64, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ECCKEY w

Toggle fields

ECCKEY

Bits 0-7: ECCKEY.

M2ERKEYR

RAMCFG SRAM x erase key register

Offset: 0x68, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: ERASEKEY.

M3CR

RAMCFG SRAM x control register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ESEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ESEA r

Toggle fields

ESEA

Bits 0-31: ESEA.

M3DEAR

RAMCFG RAM x ECC double error address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EDEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EDEA r

Toggle fields

EDEA

Bits 0-31: EDEA.

M3ICR

RAMCFG RAM x interrupt clear register x

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CDED rw	CSEDC rw

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

Toggle fields

ECCE

Bit 0: ECCE.

ALE

Bit 4: ALE.

SRAMER

Bit 8: SRAMER.

WSC

Bits 16-18: WSC.

M4ISR

RAMCFG RAMx interrupt status register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMBUSY r							DED r	SEDC r

Toggle fields

SEDC

Bit 0: SEDC.

DED

Bit 1: DED.

SRAMBUSY

Bit 8: SRAMBUSY.

M4ERKEYR

RAMCFG SRAM x erase key register

Offset: 0xe8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: ERASEKEY.

M5CR

RAMCFG SRAM x control register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ESEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ESEA r

Toggle fields

ESEA

Bits 0-31: ESEA.

M5DEAR

RAMCFG RAM x ECC double error address register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EDEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EDEA r

Toggle fields

EDEA

Bits 0-31: EDEA.

M5ICR

RAMCFG RAM x interrupt clear register x

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CDED rw	CSEDC rw

Toggle fields

CSEDC

Bit 0: CSEDC.

CDED

Bit 1: CDED.

M5ECCKEYR

RAMCFG RAM x interrupt clear register x

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ECCKEY rw

Toggle fields

ECCKEY

Bits 0-7: ECCKEY.

M5ERKEYR

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection..

M6CR

memory x control register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

Toggle fields

ECCE

Bit 0: ECCE.

ALE

Bit 4: ALE.

SRAMER

Bit 8: SRAMER.

WSC

Bits 16-18: WSC.

M6ISR

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMBUSY r							DED r	SEDC r

Toggle fields

SEDC

Bit 0: ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers..

DED

Bit 1: ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers..

SRAMBUSY

Bit 8: SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or readout protection regression. Refer to ..

M6ERKEYR

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection..

RCC

0x46020c00: Reset and clock control

38/520 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	RCC_CR			PLL3RDY	PLL3ON	PLL2RDY	PLL2ON	PLL1RDY	PLL1ON				HSEEXT	CSSON	HSEBYP	HSERDY	HSEON	SHSIRDY	SHSION	HSI48RDY	HSI48ON		HSIRDY	HSIKERON	HSION	MSIPLLFAST	MSIPLLSEL	MSIKRDY	MSIKON	MSIPLLEN	MSISRDY	MSIKERON	MSISON
0x8	RCC_ICSCR1	MSISRANGE				MSIKRANGE				MSIRGSEL	MSIBIAS			MSICAL0				MSICAL0	MSICAL1					MSICAL2					MSICAL3
0xc	RCC_ICSCR2													MSITRIM0				MSITRIM0	MSITRIM1					MSITRIM2					MSITRIM3
0x10	RCC_ICSCR3												HSITRIM									HSICAL
0x14	RCC_CRRCR																								HSI48CAL
0x1c	RCC_CFGR1		MCOPRE			MCOSEL																						STOPKERWUCK	STOPWUCK	SWS		SW
0x20	RCC_CFGR2												APB2DIS	APB1DIS	AHB2DIS2	AHB2DIS1	AHB1DIS		DPRE				PPRE2				PPRE1			HPRE
0x24	RCC_CFGR3															APB3DIS	AHB3DIS										PPRE3
0x28	RCC_PLL1CFGR														PLL1REN	PLL1QEN	PLL1PEN	PLL1MBOOST				PLL1M							PLL1FRACEN	PLL1RGE		PLL1SRC
0x2c	RCC_PLL2CFGR														PLL2REN	PLL2QEN	PLL2PEN					PLL2M							PLL2FRACEN	PLL2RGE		PLL2SRC
0x30	RCC_PLL3CFGR														PLL3REN	PLL3QEN	PLL3PEN					PLL3M							PLL3FRACEN	PLL3RGE		PLL3SRC
0x34	RCC_PLL1DIVR		PLL1R								PLL1Q							PLL1P							PLL1N
0x38	RCC_PLL1FRACR																	PLL1FRACN
0x3c	RCC_PLL2DIVR		PLL2R								PLL2Q							PLL2P							PLL2N
0x40	RCC_PLL2FRACR																	PLL2FRACN
0x44	RCC_PLL3DIVR		PLL3R								PLL3Q							PLL3P							PLL3N
0x48	RCC_PLL3FRACR																	PLL3FRACN
0x50	RCC_CIER																				SHSIRDYIE	MSIKRDYIE			PLL3RDYIE	PLL2RDYIE	PLL1RDYIE	HSI48RDYIE	HSERDYIE	HSIRDYIE	MSISRDYIE	LSERDYIE	LSIRDYIE
0x54	RCC_CIFR																				SHSIRDYF	MSIKRDYF	CSSF		PLL3RDYF	PLL2RDYF	PLL1RDYF	HSI48RDYF	HSERDYF	HSIRDYF	MSISRDYF	LSERDYF	LSIRDYF
0x58	RCC_CICR																				SHSIRDYC	MSIKRDYC	CSSC		PLL3RDYC	PLL2RDYC	PLL1RDYC	HSI48RDYC	HSERDYC	HSIRDYC	MSISRDYC	LSERDYC	LSIRDYC
0x60	RCC_AHB1RSTR												GPU2DRST	GFXMMURST	DMA2DRST	RAMCFGRST	TSCRST	JPEGRST			CRCRST									MDF1RST	FMACRST	CORDICRST	GPDMA1RST
0x64	RCC_AHB2RSTR1				SDMMC2RST	SDMMC1RST			OTFDEC2RST	OTFDEC1RST		OCTOSPIMRST	SAESRST	PKARST	RNGRST	HASHRST	AESRST		OTGRST		DCMI_PSSIRST		ADC12RST	GPIOJRST	GPIOIRST	GPIOHRST	GPIOGRST	GPIOFRST	GPIOERST	GPIODRST	GPIOCRST	GPIOBRST	GPIOARST
0x68	RCC_AHB2RSTR2																				HSPI1RST				OCTOSPI2RST				OCTOSPI1RST				FSMCRST
0x6c	RCC_AHB3RSTR																						ADF1RST	LPDMA1RST			DAC1RST	ADC4RST					LPGPIO1RST
0x74	RCC_APB1RSTR1							USART6RST	CRSRST		I2C2RST	I2C1RST	UART5RST	UART4RST	USART3RST	USART2RST			SPI2RST									TIM7RST	TIM6RST	TIM5RST	TIM4RST	TIM3RST	TIM2RST
0x78	RCC_APB1RSTR2									UCPD1RST														FDCAN1RST		I2C6RST	I2C5RST	LPTIM2RST				I2C4RST
0x7c	RCC_APB2RSTR					DSIRST	LTDCRST	GFXTIMRST	USBRST		SAI2RST	SAI1RST			TIM17RST	TIM16RST	TIM15RST		USART1RST	TIM8RST	SPI1RST	TIM1RST
0x80	RCC_APB3RSTR												VREFRST					COMPRST	OPAMPRST	LPTIM4RST	LPTIM3RST	LPTIM1RST				I2C3RST	LPUART1RST	SPI3RST				SYSCFGRST
0x88	RCC_AHB1ENR	SRAM1EN	DCACHE1EN		BKPSRAMEN				GTZC1EN			DCACHE2EN	GPU2DEN	GFXMMUEN	DMA2DEN	RAMCFGEN	TSCEN	JPEGEN			CRCEN				FLASHEN					MDF1EN	FMACEN	CORDICEN	GPDMA1EN
0x8c	RCC_AHB2ENR1	SRAM3EN	SRAM2EN		SDMMC2EN	SDMMC1EN			OTFDEC2EN	OTFDEC1EN		OCTOSPIMEN	SAESEN	PKAEN	RNGEN	HASHEN	AESEN	OTGHSPHYEN	OTGEN		DCMI_PSSIEN		ADC12EN	GPIOJEN	GPIOIEN	GPIOHEN	GPIOGEN	GPIOFEN	GPIOEEN	GPIODEN	GPIOCEN	GPIOBEN	GPIOAEN
0x90	RCC_AHB2ENR2	SRAM5EN	SRAM6EN																		HSPI1EN				OCTOSPI2EN				OCTOSPI1EN				FSMCEN
0x94	RCC_AHB3ENR	SRAM4EN																			GTZC2EN		ADF1EN	LPDMA1EN			DAC1EN	ADC4EN			PWREN		LPGPIO1EN
0x9c	RCC_APB1ENR1							USART6EN	CRSEN		I2C2EN	I2C1EN	UART5EN	UART4EN	USART3EN	USART2EN			SPI2EN			WWDGEN						TIM7EN	TIM6EN	TIM5EN	TIM4EN	TIM3EN	TIM2EN
0xa0	RCC_APB1ENR2									UCPD1EN														FDCAN1EN		I2C6EN	I2C5EN	LPTIM2EN				I2C4EN
0xa4	RCC_APB2ENR					DSIEN	LTDCEN	GFXTIMEN	USBEN		SAI2EN	SAI1EN			TIM17EN	TIM16EN	TIM15EN		USART1EN	TIM8EN	SPI1EN	TIM1EN
0xa8	RCC_APB3ENR											RTCAPBEN	VREFEN					COMPEN	OPAMPEN	LPTIM4EN	LPTIM3EN	LPTIM1EN				I2C3EN	LPUART1EN	SPI3EN				SYSCFGEN
0xb0	RCC_AHB1SMENR	SRAM1SMEN	DCACHE1SMEN	ICACHESMEN	BKPSRAMSMEN				GTZC1SMEN			DCACHE2SMEN	GPU2DSMEN	GFXMMUSMEN	DMA2DSMEN	RAMCFGSMEN	TSCSMEN	JPEGSMEN			CRCSMEN				FLASHSMEN					MDF1SMEN	FMACSMEN	CORDICSMEN	GPDMA1SMEN
0xb4	RCC_AHB2SMENR1	SRAM3SMEN	SRAM2SMEN		SDMMC2SMEN	SDMMC1SMEN			OTFDEC2SMEN	OTFDEC1SMEN		OCTOSPIMSMEN	SAESSMEN	PKASMEN	RNGSMEN	HASHSMEN	AESSMEN	OTGHSPHYSMEN	OTGSMEN		DCMI_PSSISMEN		ADC12SMEN	GPIOJSMEN	GPIOISMEN	GPIOHSMEN	GPIOGSMEN	GPIOFSMEN	GPIOESMEN	GPIODSMEN	GPIOCSMEN	GPIOBSMEN	GPIOASMEN
0xb8	RCC_AHB2SMENR2	SRAM5SMEN	SRAM6SMEN																		HSPI1SMEN				OCTOSPI2SMEN				OCTOSPI1SMEN				FSMCSMEN
0xbc	RCC_AHB3SMENR	SRAM4SMEN																			GTZC2SMEN		ADF1SMEN	LPDMA1SMEN			DAC1SMEN	ADC4SMEN			PWRSMEN		LPGPIO1SMEN
0xc4	RCC_APB1SMENR1							USART6SMEN	CRSSMEN		I2C2SMEN	I2C1SMEN	UART5SMEN	UART4SMEN	USART3SMEN	USART2SMEN			SPI2SMEN			WWDGSMEN						TIM7SMEN	TIM6SMEN	TIM5SMEN	TIM4SMEN	TIM3SMEN	TIM2SMEN
0xc8	RCC_APB1SMENR2									UCPD1SMEN														FDCAN1SMEN		I2C6SMEN	I2C5SMEN	LPTIM2SMEN				I2C4SMEN
0xcc	RCC_APB2SMENR					DSISMEN	LTDCSMEN	GFXTIMSMEN	USBSMEN		SAI2SMEN	SAI1SMEN			TIM17SMEN	TIM16SMEN	TIM15SMEN		USART1SMEN	TIM8SMEN	SPI1SMEN	TIM1SMEN
0xd0	RCC_APB3SMENR											RTCAPBSMEN	VREFSMEN					COMPSMEN	OPAMPSMEN	LPTIM4SMEN	LPTIM3SMEN	LPTIM1SMEN				I2C3SMEN	LPUART1SMEN	SPI3SMEN				SYSCFGSMEN
0xd8	RCC_SRDAMR	SRAM4AMEN		ADF1AMEN	LPDMA1AMEN	DAC1AMEN	LPGPIO1AMEN	ADC4AMEN				RTCAPBAMEN	VREFAMEN					COMPAMEN	OPAMPAMEN	LPTIM4AMEN	LPTIM3AMEN	LPTIM1AMEN				I2C3AMEN	LPUART1AMEN	SPI3AMEN
0xe0	RCC_CCIPR1	TIMICSEL				ICLKSEL		FDCAN1SEL		SYSTICKSEL		SPI1SEL		LPTIM2SEL		SPI2SEL		I2C4SEL		I2C2SEL		I2C1SEL		UART5SEL		UART4SEL		USART3SEL		USART2SEL		USART1SEL
0xe4	RCC_CCIPR2	OTGHSSEL				I2C6SEL		I2C5SEL		HSPI1SEL		OCTOSPISEL			LTDCSEL	USART6SEL		DSISEL	SDMMCSEL	RNGSEL		SAESSEL	SAI2SEL			SAI1SEL					MDF1SEL
0xe8	RCC_CCIPR3														ADF1SEL			DAC1SEL	ADCDACSEL			LPTIM1SEL		LPTIM34SEL		I2C3SEL			SPI3SEL		LPUART1SEL
0xf0	RCC_BDCR				LSIPREDIV	LSIRDY	LSION	LSCOSEL	LSCOEN								BDRST	RTCEN			LSEGFON	LSESYSRDY		RTCSEL		LSESYSEN	LSECSSD	LSECSSON	LSEDRV		LSEBYP	LSERDY	LSEON
0xf4	RCC_CSR	LPWRRSTF	WWDGRSTF	IWDGRSTF	SFTRSTF	BORRSTF	PINRSTF	OBLRSTF		RMVF								MSISSRANGE				MSIKSRANGE
0x110	RCC_SECCFGR																				RMVFSEC	HSI48SEC	ICLKSEC	PLL3SEC	PLL2SEC	PLL1SEC	PRESCSEC	SYSCLKSEC	LSESEC	LSISEC	MSISEC	HSESEC	HSISEC
0x114	RCC_PRIVCFGR																															NSPRIV	SPRIV

Toggle registers

RCC_CR

RCC clock control register

Offset: 0x0, size: 32, reset: 0x00000035, access: Unspecified

9/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		PLL3RDY r	PLL3ON rw	PLL2RDY r	PLL2ON rw	PLL1RDY r	PLL1ON rw				HSEEXT rw	CSSON rw	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SHSIRDY r	SHSION rw	HSI48RDY r	HSI48ON rw		HSIRDY r	HSIKERON rw	HSION rw	MSIPLLFAST rw	MSIPLLSEL rw	MSIKRDY r	MSIKON rw	MSIPLLEN rw	MSISRDY r	MSIKERON rw	MSISON rw

Toggle fields

MSISON

Bit 0: MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the�MSIS oscillator on when exiting Standby or Shutdown mode. It is set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes, or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock..

MSIKERON

Bit 1: MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI on in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see Section�11.4.24 for more details). This bit must be configured at 0 before entering Stop 3 mode..

MSISRDY

Bit 2: MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. It is set only when MSIS is enabled by software (by setting MSISON). Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles..

MSIPLLEN

Bit 3: MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)..

MSIKON

Bit 4: MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIK when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. It is set by hardware to force the MSIK oscillator on when STOPWUCK = 0 or STOPKERWUCK�=�0 when exiting Stop modes, or in case of a failure of the HSE oscillator..

MSIKRDY

Bit 5: MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles..

MSIPLLSEL

Bit 6: MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI output clock uses the PLL mode. It�can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to both clock outputs..

MSIPLLFAST

Bit 7: MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The�fast start-up is active when the MSI in PLL mode returns from switch off..

HSION

Bit 8: HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the�HSI16 oscillator on when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock..

HSIKERON

Bit 9: HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON even in Stop modes. Keeping HSI16 on in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to Section�11.4.24 for more details. This bit must be configured at 0 before entering Stop 3 mode..

HSIRDY

Bit 10: HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It is set only when HSI16 is enabled by software (by setting HSION). Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles..

HSI48ON

Bit 12: HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI48 when entering in Stop, Standby, or Shutdown modes..

HSI48RDY

Bit 13: HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Itis set only when HSI48 is enabled by software (by setting HSI48ON)..

SHSION

Bit 14: SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SHSI when entering in Stop, Standby, or Shutdown modes..

SHSIRDY

Bit 15: SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. It is set only when SHSI is enabled by software (by setting SHSION). Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles..

HSEON

Bit 16: HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock..

HSERDY

Bit 17: HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles..

HSEBYP

Bit 18: HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with an external clock. The�external clock must be enabled with the HSEON bit set, to be used by the device. This�bit can be written only if the HSE oscillator is disabled..

CSSON

Bit 19: Clock security system enable This bit is set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset..

HSEEXT

Bit 20: HSE external clock bypass mode This bit is set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled..

PLL1ON

Bit 24: PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock..

PLL1RDY

Bit 25: PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked..

PLL2ON

Bit 26: PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when entering Stop, Standby, or Shutdown mode..

PLL2RDY

Bit 27: PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked..

PLL3ON

Bit 28: PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when entering Stop, Standby, or Shutdown mode..

PLL3RDY

Bit 29: PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked..

RCC_ICSCR1

RCC internal clock sources calibration register 1

Offset: 0x8, size: 32, reset: 0x44000000, access: Unspecified

4/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSISRANGE rw				MSIKRANGE rw				MSIRGSEL rw	MSIBIAS rw			MSICAL0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSICAL0 r	MSICAL1 r					MSICAL2 r					MSICAL3 r

Toggle fields

MSICAL3

Bits 0-4: MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSICAL2

Bits 5-9: MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSICAL1

Bits 10-14: MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSICAL0

Bits 15-19: MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSIBIAS

Bit 22: MSI bias mode selection This bit is set by software to select the MSI bias mode. By default, the MSI bias is in�continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption when the regulator is in range 4, or when the device is in Stop 1 or Stop�2 mode, but it�decreases the MSI accuracy.

MSIRGSEL

Bit 23: MSI clock range selection This bit is set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR..

MSIKRANGE

Bits 24-27: MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is off (MSISON = 0) or when MSIK is ready (MSIKRDY�=�1). MSIKRANGE must NOT be modified when MSIK is on and NOT ready (MSIKON = 1 and MSIKRDY = 0) Note: MSIKRANGE is kept when the device wakes up from Stop mode, except when the�MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into�range 2 (24 MHz)..

MSISRANGE

Bits 28-31: MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is off (MSISON = 0) or when MSIS is ready (MSISRDY�=�1). MSISRANGE must NOT be modified when MSIS is on and NOT ready (MSISON�=�1 and MSISRDY�=�0) Note: MSISRANGE is kept when the device wakes up from Stop mode, except when the�MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into range 2 (24 MHz)..

RCC_ICSCR2

RCC internal clock sources calibration register 2

Offset: 0xc, size: 32, reset: 0x00084210, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												MSITRIM0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSITRIM0 rw	MSITRIM1 rw					MSITRIM2 rw					MSITRIM3 rw

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MSITRIM3

Bits 0-4: MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

MSITRIM2

Bits 5-9: MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

MSITRIM1

Bits 10-14: MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

MSITRIM0

Bits 15-19: MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

RCC_ICSCR3

RCC internal clock sources calibration register 3

Offset: 0x10, size: 32, reset: 0x00100000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											HSITRIM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				HSICAL r

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HSICAL

Bits 0-11: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value..

HSITRIM

Bits 16-20: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI..

RCC_CRRCR

RCC clock recovery RC register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							HSI48CAL r

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HSI48CAL

Bits 0-8: HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value..

RCC_CFGR1

RCC clock configuration register 1

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCOPRE rw			MCOSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										STOPKERWUCK rw	STOPWUCK rw	SWS r		SW rw

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SW

Bits 0-1: system clock switch This bitfield is set and cleared by software to select system clock source (SYSCLK). It is configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. This bitfield is configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK..

SWS

Bits 2-3: system clock switch status This bitfield is set and cleared by hardware to indicate which clock source is used as system clock..

STOPWUCK

Bit 4: wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on�HSE. STOPWUCK must not be modified when the CSS is enabled by HSECSSON in�RCC_CR, and the system clock is HSE (SWS = 10) or a switch on HSE is�requested (SW�=�10)..

STOPKERWUCK

Bit 5: wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals..

MCOSEL

Bits 24-27: microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching..

MCOPRE

Bits 28-30: microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed.

RCC_CFGR2

RCC clock configuration register 2

Offset: 0x20, size: 32, reset: 0x00006000, access: Unspecified

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											APB2DIS rw	APB1DIS rw	AHB2DIS2 rw	AHB2DIS1 rw	AHB1DIS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DPRE rw				PPRE2 rw				PPRE1 rw			HPRE rw

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HPRE

Bits 0-3: AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Table�118). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided.

PPRE1

Bits 4-6: APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1 clock (PCLK1). 0xx: PCLK1 not divided.

PPRE2

Bits 8-10: APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2 clock (PCLK2). 0xx: PCLK2 not divided.

DPRE

Bits 12-14: DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

AHB1DIS

Bit 16: AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1..

AHB2DIS1

Bit 17: AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3..

AHB2DIS2

Bit 18: AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR2 are off..

APB1DIS

Bit 19: APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG..

APB2DIS

Bit 20: APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all APB2 peripherals clocks are off..

RCC_CFGR3

RCC clock configuration register 3

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														APB3DIS rw	AHB3DIS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PPRE3 rw

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PPRE3

Bits 4-6: APB3 prescaler This bitfield is set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided.

AHB3DIS

Bit 16: AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4..

APB3DIS

Bit 17: APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off..

RCC_PLL1CFGR

RCC PLL1 configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PLL1REN rw	PLL1QEN rw	PLL1PEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL1MBOOST rw				PLL1M rw							PLL1FRACEN rw	PLL1RGE rw		PLL1SRC rw

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PLL1SRC

Bits 0-1: PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. It can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, this bitfield value must be zero..

PLL1RGE

Bits 2-3: PLL1 input frequency range This bit is set and reset by software to select the proper reference frequency range used for PLL1. It must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz.

PLL1FRACEN

Bit 4: PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRACN in the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL initialization phase for details)..

PLL1M

Bits 8-11: Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

PLL1MBOOST

Bits 12-15: Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1�input�clock�frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPODboost mode is disabled (see Section�10: Power control (PWR)). others: reserved.

PLL1PEN

Bit 16: PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when pll1_p_ck is not used..

PLL1QEN

Bit 17: PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when pll1_q_ck is not used..

PLL1REN

Bit 18: PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when pll1_r_ck is not used. This bit can be cleared only when the PLL1 is not used as SYSCLK..

RCC_PLL2CFGR

RCC PLL2 configuration register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PLL2REN rw	PLL2QEN rw	PLL2PEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PLL2M rw							PLL2FRACEN rw	PLL2RGE rw		PLL2SRC rw

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PLL2SRC

Bits 0-1: PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. It can be written only when the PLL2 is disabled. To save power, when no PLL2 is used, this bitfield value must be�zero..

PLL2RGE

Bits 2-3: PLL2 input frequency range This bitfield is set and reset by software to select the proper reference frequency range used for�PLL2. It must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz.

PLL2FRACEN

Bit 4: PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRACN in the ΣΔ modulator. In order to latch the PLL2FRACN value into the ΣΔ modulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see PLL initialization phase for details)..

PLL2M

Bits 8-11: Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

PLL2PEN

Bit 16: PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when pll2_p_ck is not used..

PLL2QEN

Bit 17: PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when pll2_q_ck is not used..

PLL2REN

Bit 18: PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when pll2_r_ck is not used..

RCC_PLL3CFGR

RCC PLL3 configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PLL3REN rw	PLL3QEN rw	PLL3PEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PLL3M rw							PLL3FRACEN rw	PLL3RGE rw		PLL3SRC rw

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PLL3SRC

Bits 0-1: PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. It can be written only when the PLL3 is disabled. To save power, when no PLL3 is used, this bitfield value must be�zero..

PLL3RGE

Bits 2-3: PLL3 input frequency range This bit is set and reset by software to select the proper reference frequency range used for�PLL3. It must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz.

PLL3FRACEN

Bit 4: PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRACN in the ΣΔ modulator. In order to latch the PLL3FRACN value into the ΣΔ modulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see PLL initialization phase for details)..

PLL3M

Bits 8-11: Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bitfield can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

PLL3PEN

Bit 16: PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when pll3_p_ck is not used..

PLL3QEN

Bit 17: PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when pll3_q_ck is not used..

PLL3REN

Bit 18: PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when pll3_r_ck is not used..

RCC_PLL1DIVR

RCC PLL1 dividers register

Offset: 0x34, size: 32, reset: 0x01010280, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLL1R rw								PLL1Q rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL1P rw							PLL1N rw

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PLL1N

Bits 0-8: Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded in PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16�MHz.

PLL1P

Bits 9-15: PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll1_p_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

PLL1Q

Bits 16-22: PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll1_q_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

PLL1R

Bits 24-30: PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed. ....

RCC_PLL1FRACR

RCC PLL1 fractional divider register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL1FRACN rw

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PLL1FRACN

Bits 3-15: Fractional part of the multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as�follows: Set PLL1FRACEN = 0. Write the new fractional value into PLL1FRACN. Set PLL1FRACEN = 1..

RCC_PLL2DIVR

RCC PLL2 dividers configuration register

Offset: 0x3c, size: 32, reset: 0x01010280, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLL2R rw								PLL2Q rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL2P rw							PLL2N rw

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PLL2N

Bits 0-8: Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded in PLL2FRACN, with: PLL2N between 4 and 512 input frequency Fref2_ck between 1MHz and 16MHz.

PLL2P

Bits 9-15: PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll2_p_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

PLL2Q

Bits 16-22: PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll2_q_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

PLL2R

Bits 24-30: PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll2_r_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

RCC_PLL2FRACR

RCC PLL2 fractional divider register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL2FRACN rw

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PLL2FRACN

Bits 3-15: Fractional part of the multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with PLL2N must be between 4 and 512. PLL2FRACN can be between 0 and 213 - 1. The input frequency Fref2_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into PLL2FRACN. Set the bit PLL2FRACEN to 1..

RCC_PLL3DIVR

RCC PLL3 dividers configuration register

Offset: 0x44, size: 32, reset: 0x01010280, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLL3R rw								PLL3Q rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL3P rw							PLL3N rw

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PLL3N

Bits 0-8: Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). ... ... Others: reserved VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded in PLL3FRACN, with: PLL3N between 4 and 512 input frequency Fref3_ck between 4 and 16MHz.

PLL3P

Bits 9-15: PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll3_p_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

PLL3Q

Bits 16-22: PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll3_q_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

PLL3R

Bits 24-30: PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll3_r_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

RCC_PLL3FRACR

RCC PLL3 fractional divider register

Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL3FRACN rw

Toggle fields

PLL3FRACN

Bits 3-15: Fractional part of the multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with: PLL3N must be between 4 and 512. PLL3FRACN can be between 0 and 213 - 1. The input frequency Fref3_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL3FRACEN to 0. Write the new fractional value into PLL3FRACN. Set the bit PLL3FRACEN to 1..

RCC_CIER

RCC clock interrupt enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SHSIRDYIE rw	MSIKRDYIE rw			PLL3RDYIE rw	PLL2RDYIE rw	PLL1RDYIE rw	HSI48RDYIE rw	HSERDYIE rw	HSIRDYIE rw	MSISRDYIE rw	LSERDYIE rw	LSIRDYIE rw

Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization..

LSERDYIE

Bit 1: LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization..

MSISRDYIE

Bit 2: MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization..

HSIRDYIE

Bit 3: HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization..

HSERDYIE

Bit 4: HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization..

HSI48RDYIE

Bit 5: HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization..

PLL1RDYIE

Bit 6: PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL1 lock..

PLL2RDYIE

Bit 7: PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL2 lock..

PLL3RDYIE

Bit 8: PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL3 lock..

MSIKRDYIE

Bit 11: MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization..

SHSIRDYIE

Bit 12: SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization..

RCC_CIFR

RCC clock interrupt flag register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SHSIRDYF r	MSIKRDYF r	CSSF r		PLL3RDYF r	PLL2RDYF r	PLL1RDYF r	HSI48RDYF r	HSERDYF r	HSIRDYF r	MSISRDYF r	LSERDYF r	LSIRDYF r

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE is set. It is cleared by software by�setting the LSIRDYC bit..

LSERDYF

Bit 1: LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE is set. It is cleared by software by setting the LSERDYC bit..

MSISRDYF

Bit 2: MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. It�is cleared by software by setting the MSISRDYC bit..

HSIRDYF

Bit 3: HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYIE = 1 in�response to setting the HSION (see RCC_CR). When HSION = 0 but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. This bit is cleared by software by setting the HSIRDYC bit..

HSERDYF

Bit 4: HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE is set. It is cleared by software by setting the HSERDYC bit..

HSI48RDYF

Bit 5: HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. it�is cleared by software by setting the HSI48RDYC bit..

PLL1RDYF

Bit 6: PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It is cleared by software by setting the PLL1RDYC bit..

PLL2RDYF

Bit 7: PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It is cleared by software by setting the PLL2RDYC bit..

PLL3RDYF

Bit 8: PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software by setting the PLL3RDYC bit..

CSSF

Bit 10: Clock security system interrupt flag This bit is set by hardware when a failure is detected in the HSE oscillator. It is cleared by software by setting the CSSC bit..

MSIKRDYF

Bit 11: MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. It is cleared by software by setting the MSIKRDYC bit..

SHSIRDYF

Bit 12: SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. It is cleared by software by setting the SHSIRDYC bit..

RCC_CICR

RCC clock interrupt clear register

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SHSIRDYC w	MSIKRDYC w	CSSC w		PLL3RDYC w	PLL2RDYC w	PLL1RDYC w	HSI48RDYC w	HSERDYC w	HSIRDYC w	MSISRDYC w	LSERDYC w	LSIRDYC w

Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect..

LSERDYC

Bit 1: LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect..

MSISRDYC

Bit 2: MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect..

HSIRDYC

Bit 3: HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect..

HSERDYC

Bit 4: HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect..

HSI48RDYC

Bit 5: HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect..

PLL1RDYC

Bit 6: PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect..

PLL2RDYC

Bit 7: PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect..

PLL3RDYC

Bit 8: PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect..

CSSC

Bit 10: Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect..

MSIKRDYC

Bit 11: MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect..

SHSIRDYC

Bit 12: SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect..

RCC_AHB1RSTR

RCC AHB1 peripheral reset register

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											GPU2DRST rw	GFXMMURST rw	DMA2DRST rw	RAMCFGRST rw	TSCRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JPEGRST rw			CRCRST rw									MDF1RST rw	FMACRST rw	CORDICRST rw	GPDMA1RST rw

Toggle fields

GPDMA1RST

Bit 0: GPDMA1 reset This bit is set and cleared by software..

CORDICRST

Bit 1: CORDIC reset This bit is set and cleared by software..

FMACRST

Bit 2: FMAC reset This bit is set and cleared by software..

MDF1RST

Bit 3: MDF1 reset This bit is set and cleared by software..

CRCRST

Bit 12: CRC reset This bit is set and cleared by software..

JPEGRST

Bit 15: JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

TSCRST

Bit 16: TSC reset This bit is set and cleared by software..

RAMCFGRST

Bit 17: RAMCFG reset This bit is set and cleared by software..

DMA2DRST

Bit 18: DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXMMURST

Bit 19: GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPU2DRST

Bit 20: GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2RSTR1

RCC AHB2 peripheral reset register 1

Offset: 0x64, size: 32, reset: 0x00000000, access: Unspecified

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SDMMC2RST rw	SDMMC1RST rw			OTFDEC2RST rw	OTFDEC1RST rw		OCTOSPIMRST rw	SAESRST rw	PKARST rw	RNGRST rw	HASHRST rw	AESRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OTGRST rw		DCMI_PSSIRST rw		ADC12RST rw	GPIOJRST rw	GPIOIRST rw	GPIOHRST rw	GPIOGRST rw	GPIOFRST rw	GPIOERST rw	GPIODRST rw	GPIOCRST rw	GPIOBRST rw	GPIOARST rw

Toggle fields

GPIOARST

Bit 0: I/O port A reset This bit is set and cleared by software..

GPIOBRST

Bit 1: I/O port B reset This bit is set and cleared by software..

GPIOCRST

Bit 2: I/O port C reset This bit is set and cleared by software..

GPIODRST

Bit 3: I/O port D reset This bit is set and cleared by software..

GPIOERST

Bit 4: I/O port E reset This bit is set and cleared by software..

GPIOFRST

Bit 5: I/O port F reset This bit is set and cleared by software. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value..

GPIOGRST

Bit 6: I/O port G reset This bit is set and cleared by software..

GPIOHRST

Bit 7: I/O port H reset This bit is set and cleared by software..

GPIOIRST

Bit 8: I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOJRST

Bit 9: I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

ADC12RST

Bit 10: ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx..

DCMI_PSSIRST

Bit 12: DCMI and PSSI reset This bit is set and cleared by software..

OTGRST

Bit 14: OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

AESRST

Bit 16: AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HASHRST

Bit 17: HASH reset This bit is set and cleared by software..

RNGRST

Bit 18: RNG reset This bit is set and cleared by software..

PKARST

Bit 19: PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SAESRST

Bit 20: SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPIMRST

Bit 21: OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC1RST

Bit 23: OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC2RST

Bit 24: OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SDMMC1RST

Bit 27: SDMMC1 reset This bit is set and cleared by software..

SDMMC2RST

Bit 28: SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2RSTR2

RCC AHB2 peripheral reset register 2

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSPI1RST rw				OCTOSPI2RST rw				OCTOSPI1RST rw				FSMCRST rw

Toggle fields

FSMCRST

Bit 0: Flexible memory controller reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPI1RST

Bit 4: OCTOSPI1 reset This bit is set and cleared by software..

OCTOSPI2RST

Bit 8: OCTOSPI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HSPI1RST

Bit 12: HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB3RSTR

RCC AHB3 peripheral reset register

Offset: 0x6c, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					ADF1RST rw	LPDMA1RST rw			DAC1RST rw	ADC4RST rw					LPGPIO1RST rw

Toggle fields

LPGPIO1RST

Bit 0: LPGPIO1 reset This bit is set and cleared by software..

ADC4RST

Bit 5: ADC4 reset This bit is set and cleared by software..

DAC1RST

Bit 6: DAC1 reset This bit is set and cleared by software..

LPDMA1RST

Bit 9: LPDMA1 reset This bit is set and cleared by software..

ADF1RST

Bit 10: ADF1 reset This bit is set and cleared by software..

RCC_APB1RSTR1

RCC APB1 peripheral reset register 1

Offset: 0x74, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						USART6RST rw	CRSRST rw		I2C2RST rw	I2C1RST rw	UART5RST rw	UART4RST rw	USART3RST rw	USART2RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2RST rw									TIM7RST rw	TIM6RST rw	TIM5RST rw	TIM4RST rw	TIM3RST rw	TIM2RST rw

Toggle fields

TIM2RST

Bit 0: TIM2 reset This bit is set and cleared by software..

TIM3RST

Bit 1: TIM3 reset This bit is set and cleared by software..

TIM4RST

Bit 2: TIM4 reset This bit is set and cleared by software..

TIM5RST

Bit 3: TIM5 reset This bit is set and cleared by software..

TIM6RST

Bit 4: TIM6 reset This bit is set and cleared by software..

TIM7RST

Bit 5: TIM7 reset This bit is set and cleared by software..

SPI2RST

Bit 14: SPI2 reset This bit is set and cleared by software..

USART2RST

Bit 17: USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USART3RST

Bit 18: USART3 reset This bit is set and cleared by software..

UART4RST

Bit 19: UART4 reset This bit is set and cleared by software..

UART5RST

Bit 20: UART5 reset This bit is set and cleared by software..

I2C1RST

Bit 21: I2C1 reset This bit is set and cleared by software..

I2C2RST

Bit 22: I2C2 reset This bit is set and cleared by software..

CRSRST

Bit 24: CRS reset This bit is set and cleared by software..

USART6RST

Bit 25: USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB1RSTR2

RCC APB1 peripheral reset register 2

Offset: 0x78, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UCPD1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FDCAN1RST rw		I2C6RST rw	I2C5RST rw	LPTIM2RST rw				I2C4RST rw

Toggle fields

I2C4RST

Bit 1: I2C4 reset This bit is set and cleared by software.

LPTIM2RST

Bit 5: LPTIM2 reset This bit is set and cleared by software..

I2C5RST

Bit 6: I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

I2C6RST

Bit 7: I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

FDCAN1RST

Bit 9: FDCAN1 reset This bit is set and cleared by software..

UCPD1RST

Bit 23: UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB2RSTR

RCC APB2 peripheral reset register

Offset: 0x7c, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DSIRST rw	LTDCRST rw	GFXTIMRST rw	USBRST rw		SAI2RST rw	SAI1RST rw			TIM17RST rw	TIM16RST rw	TIM15RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1RST rw	TIM8RST rw	SPI1RST rw	TIM1RST rw

Toggle fields

TIM1RST

Bit 11: TIM1 reset This bit is set and cleared by software..

SPI1RST

Bit 12: SPI1 reset This bit is set and cleared by software..

TIM8RST

Bit 13: TIM8 reset This bit is set and cleared by software..

USART1RST

Bit 14: USART1 reset This bit is set and cleared by software..

TIM15RST

Bit 16: TIM15 reset This bit is set and cleared by software..

TIM16RST

Bit 17: TIM16 reset This bit is set and cleared by software..

TIM17RST

Bit 18: TIM17 reset This bit is set and cleared by software..

SAI1RST

Bit 21: SAI1 reset This bit is set and cleared by software..

SAI2RST

Bit 22: SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USBRST

Bit 24: USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXTIMRST

Bit 25: GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

LTDCRST

Bit 26: LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DSIRST

Bit 27: DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB3RSTR

RCC APB3 peripheral reset register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											VREFRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPRST rw	OPAMPRST rw	LPTIM4RST rw	LPTIM3RST rw	LPTIM1RST rw				I2C3RST rw	LPUART1RST rw	SPI3RST rw				SYSCFGRST rw

Toggle fields

SYSCFGRST

Bit 1: SYSCFG reset This bit is set and cleared by software..

SPI3RST

Bit 5: SPI3 reset This bit is set and cleared by software..

LPUART1RST

Bit 6: LPUART1 reset This bit is set and cleared by software..

I2C3RST

Bit 7: I2C3 reset This bit is set and cleared by software..

LPTIM1RST

Bit 11: LPTIM1 reset This bit is set and cleared by software..

LPTIM3RST

Bit 12: LPTIM3 reset This bit is set and cleared by software..

LPTIM4RST

Bit 13: LPTIM4 reset This bit is set and cleared by software..

OPAMPRST

Bit 14: OPAMP reset This bit is set and cleared by software..

COMPRST

Bit 15: COMP reset This bit is set and cleared by software..

VREFRST

Bit 20: VREFBUF reset This bit is set and cleared by software..

RCC_AHB1ENR

RCC AHB1 peripheral clock enable register

Offset: 0x88, size: 32, reset: 0xD0200100, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM1EN rw	DCACHE1EN rw		BKPSRAMEN rw				GTZC1EN rw			DCACHE2EN rw	GPU2DEN rw	GFXMMUEN rw	DMA2DEN rw	RAMCFGEN rw	TSCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JPEGEN rw			CRCEN rw				FLASHEN rw					MDF1EN rw	FMACEN rw	CORDICEN rw	GPDMA1EN rw

Toggle fields

GPDMA1EN

Bit 0: GPDMA1 clock enable This bit is set and cleared by software..

CORDICEN

Bit 1: CORDIC clock enable This bit is set and cleared by software..

FMACEN

Bit 2: FMAC clock enable This bit is set and reset by software..

MDF1EN

Bit 3: MDF1 clock enable This bit is set and reset by software..

FLASHEN

Bit 8: FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the flash memory is in power-down mode..

CRCEN

Bit 12: CRC clock enable This bit is set and cleared by software..

JPEGEN

Bit 15: JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

TSCEN

Bit 16: Touch sensing controller clock enable This bit is set and cleared by software..

RAMCFGEN

Bit 17: RAMCFG clock enable This bit is set and cleared by software..

DMA2DEN

Bit 18: DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXMMUEN

Bit 19: GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPU2DEN

Bit 20: GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DCACHE2EN

Bit 21: DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GTZC1EN

Bit 24: GTZC1 clock enable This bit is set and reset by software..

BKPSRAMEN

Bit 28: BKPSRAM clock enable This bit is set and reset by software..

DCACHE1EN

Bit 30: DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2, HSPI1 or FSMC, even if the DCACHE1 is bypassed..

SRAM1EN

Bit 31: SRAM1 clock enable This bit is set and reset by software..

RCC_AHB2ENR1

RCC AHB2 peripheral clock enable register 1

Offset: 0x8c, size: 32, reset: 0xC0000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM3EN rw	SRAM2EN rw		SDMMC2EN rw	SDMMC1EN rw			OTFDEC2EN rw	OTFDEC1EN rw		OCTOSPIMEN rw	SAESEN rw	PKAEN rw	RNGEN rw	HASHEN rw	AESEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OTGHSPHYEN rw	OTGEN rw		DCMI_PSSIEN rw		ADC12EN rw	GPIOJEN rw	GPIOIEN rw	GPIOHEN rw	GPIOGEN rw	GPIOFEN rw	GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle fields

GPIOAEN

Bit 0: I/O port A clock enable This bit is set and cleared by software..

GPIOBEN

Bit 1: I/O port B clock enable This bit is set and cleared by software..

GPIOCEN

Bit 2: I/O port C clock enable This bit is set and cleared by software..

GPIODEN

Bit 3: I/O port D clock enable This bit is set and cleared by software..

GPIOEEN

Bit 4: I/O port E clock enable This bit is set and cleared by software..

GPIOFEN

Bit 5: I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOGEN

Bit 6: I/O port G clock enable This bit is set and cleared by software..

GPIOHEN

Bit 7: I/O port H clock enable This bit is set and cleared by software..

GPIOIEN

Bit 8: I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOJEN

Bit 9: I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

ADC12EN

Bit 10: ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx..

DCMI_PSSIEN

Bit 12: DCMI and PSSI clock enable This bit is set and cleared by software..

OTGEN

Bit 14: OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTGHSPHYEN

Bit 15: OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

AESEN

Bit 16: AES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HASHEN

Bit 17: HASH clock enable This bit is set and cleared by software.

RNGEN

Bit 18: RNG clock enable This bit is set and cleared by software..

PKAEN

Bit 19: PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SAESEN

Bit 20: SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPIMEN

Bit 21: OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC1EN

Bit 23: OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC2EN

Bit 24: OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SDMMC1EN

Bit 27: SDMMC1 clock enable This bit is set and cleared by software..

SDMMC2EN

Bit 28: SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM2EN

Bit 30: SRAM2 clock enable This bit is set and reset by software..

SRAM3EN

Bit 31: SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2ENR2

RCC AHB2 peripheral clock enable register 2

Offset: 0x90, size: 32, reset: 0x80000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM5EN rw	SRAM6EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSPI1EN rw				OCTOSPI2EN rw				OCTOSPI1EN rw				FSMCEN rw

Toggle fields

FSMCEN

Bit 0: FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPI1EN

Bit 4: OCTOSPI1 clock enable This bit is set and cleared by software..

OCTOSPI2EN

Bit 8: OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HSPI1EN

Bit 12: HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM6EN

Bit 30: SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM5EN

Bit 31: SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB3ENR

RCC AHB3 peripheral clock enable register

Offset: 0x94, size: 32, reset: 0x80000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM4EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			GTZC2EN rw		ADF1EN rw	LPDMA1EN rw			DAC1EN rw	ADC4EN rw			PWREN rw		LPGPIO1EN rw

Toggle fields

LPGPIO1EN

Bit 0: LPGPIO1 enable This bit is set and cleared by software..

PWREN

Bit 2: PWR clock enable This bit is set and cleared by software..

ADC4EN

Bit 5: ADC4 clock enable This bit is set and cleared by software..

DAC1EN

Bit 6: DAC1 clock enable This bit is set and cleared by software..

LPDMA1EN

Bit 9: LPDMA1 clock enable This bit is set and cleared by software..

ADF1EN

Bit 10: ADF1 clock enable This bit is set and cleared by software..

GTZC2EN

Bit 12: GTZC2 clock enable This bit is set and cleared by software..

SRAM4EN

Bit 31: SRAM4 clock enable This bit is set and reset by software..

RCC_APB1ENR1

RCC APB1 peripheral clock enable register 1

Offset: 0x9c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						USART6EN rw	CRSEN rw		I2C2EN rw	I2C1EN rw	UART5EN rw	UART4EN rw	USART3EN rw	USART2EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw			WWDGEN rw						TIM7EN rw	TIM6EN rw	TIM5EN rw	TIM4EN rw	TIM3EN rw	TIM2EN rw

Toggle fields

TIM2EN

Bit 0: TIM2 clock enable This bit is set and cleared by software..

TIM3EN

Bit 1: TIM3 clock enable This bit is set and cleared by software..

TIM4EN

Bit 2: TIM4 clock enable This bit is set and cleared by software..

TIM5EN

Bit 3: TIM5 clock enable This bit is set and cleared by software..

TIM6EN

Bit 4: TIM6 clock enable This bit is set and cleared by software..

TIM7EN

Bit 5: TIM7 clock enable This bit is set and cleared by software..

WWDGEN

Bit 11: WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset..

SPI2EN

Bit 14: SPI2 clock enable This bit is set and cleared by software..

USART2EN

Bit 17: USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USART3EN

Bit 18: USART3 clock enable This bit is set and cleared by software..

UART4EN

Bit 19: UART4 clock enable This bit is set and cleared by software..

UART5EN

Bit 20: UART5 clock enable This bit is set and cleared by software..

I2C1EN

Bit 21: I2C1 clock enable This bit is set and cleared by software..

I2C2EN

Bit 22: I2C2 clock enable This bit is set and cleared by software..

CRSEN

Bit 24: CRS clock enable This bit is set and cleared by software..

USART6EN

Bit 25: USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB1ENR2

RCC APB1 peripheral clock enable register 2

Offset: 0xa0, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UCPD1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FDCAN1EN rw		I2C6EN rw	I2C5EN rw	LPTIM2EN rw				I2C4EN rw

Toggle fields

I2C4EN

Bit 1: I2C4 clock enable This bit is set and cleared by software.

LPTIM2EN

Bit 5: LPTIM2 clock enable This bit is set and cleared by software..

I2C5EN

Bit 6: I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

I2C6EN

Bit 7: I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

FDCAN1EN

Bit 9: FDCAN1 clock enable This bit is set and cleared by software..

UCPD1EN

Bit 23: UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB2ENR

RCC APB2 peripheral clock enable register

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DSIEN rw	LTDCEN rw	GFXTIMEN rw	USBEN rw		SAI2EN rw	SAI1EN rw			TIM17EN rw	TIM16EN rw	TIM15EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw	TIM8EN rw	SPI1EN rw	TIM1EN rw

Toggle fields

TIM1EN

Bit 11: TIM1 clock enable This bit is set and cleared by software..

SPI1EN

Bit 12: SPI1 clock enable This bit is set and cleared by software..

TIM8EN

Bit 13: TIM8 clock enable This bit is set and cleared by software..

USART1EN

Bit 14: USART1clock enable This bit is set and cleared by software..

TIM15EN

Bit 16: TIM15 clock enable This bit is set and cleared by software..

TIM16EN

Bit 17: TIM16 clock enable This bit is set and cleared by software..

TIM17EN

Bit 18: TIM17 clock enable This bit is set and cleared by software..

SAI1EN

Bit 21: SAI1 clock enable This bit is set and cleared by software..

SAI2EN

Bit 22: SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USBEN

Bit 24: USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXTIMEN

Bit 25: GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

LTDCEN

Bit 26: LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DSIEN

Bit 27: DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB3ENR

RCC APB3 peripheral clock enable register

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										RTCAPBEN rw	VREFEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPEN rw	OPAMPEN rw	LPTIM4EN rw	LPTIM3EN rw	LPTIM1EN rw				I2C3EN rw	LPUART1EN rw	SPI3EN rw				SYSCFGEN rw

Toggle fields

SYSCFGEN

Bit 1: SYSCFG clock enable This bit is set and cleared by software..

SPI3EN

Bit 5: SPI3 clock enable This bit is set and cleared by software..

LPUART1EN

Bit 6: LPUART1 clock enable This bit is set and cleared by software..

I2C3EN

Bit 7: I2C3 clock enable This bit is set and cleared by software..

LPTIM1EN

Bit 11: LPTIM1 clock enable This bit is set and cleared by software..

LPTIM3EN

Bit 12: LPTIM3 clock enable This bit is set and cleared by software..

LPTIM4EN

Bit 13: LPTIM4 clock enable This bit is set and cleared by software..

OPAMPEN

Bit 14: OPAMP clock enable This bit is set and cleared by software..

COMPEN

Bit 15: COMP clock enable This bit is set and cleared by software..

VREFEN

Bit 20: VREFBUF clock enable This bit is set and cleared by software..

RTCAPBEN

Bit 21: RTC and TAMP APB clock enable This bit is set and cleared by software..

RCC_AHB1SMENR

RCC AHB1 peripheral clock enable in Sleep and Stop modes register

Offset: 0xb0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM1SMEN rw	DCACHE1SMEN rw	ICACHESMEN rw	BKPSRAMSMEN rw				GTZC1SMEN rw			DCACHE2SMEN rw	GPU2DSMEN rw	GFXMMUSMEN rw	DMA2DSMEN rw	RAMCFGSMEN rw	TSCSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JPEGSMEN rw			CRCSMEN rw				FLASHSMEN rw					MDF1SMEN rw	FMACSMEN rw	CORDICSMEN rw	GPDMA1SMEN rw

Toggle fields

GPDMA1SMEN

Bit 0: GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

CORDICSMEN

Bit 1: CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sleep mode..

FMACSMEN

Bit 2: FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software..

MDF1SMEN

Bit 3: MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

FLASHSMEN

Bit 8: FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software..

CRCSMEN

Bit 12: CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software..

JPEGSMEN

Bit 15: JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

TSCSMEN

Bit 16: TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software..

RAMCFGSMEN

Bit 17: RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software..

DMA2DSMEN

Bit 18: DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXMMUSMEN

Bit 19: GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPU2DSMEN

Bit 20: GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DCACHE2SMEN

Bit 21: DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GTZC1SMEN

Bit 24: GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

BKPSRAMSMEN

Bit 28: BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software.

ICACHESMEN

Bit 29: ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software..

DCACHE1SMEN

Bit 30: DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SRAM1SMEN

Bit 31: SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

RCC_AHB2SMENR1

RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1

Offset: 0xb4, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM3SMEN rw	SRAM2SMEN rw		SDMMC2SMEN rw	SDMMC1SMEN rw			OTFDEC2SMEN rw	OTFDEC1SMEN rw		OCTOSPIMSMEN rw	SAESSMEN rw	PKASMEN rw	RNGSMEN rw	HASHSMEN rw	AESSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OTGHSPHYSMEN rw	OTGSMEN rw		DCMI_PSSISMEN rw		ADC12SMEN rw	GPIOJSMEN rw	GPIOISMEN rw	GPIOHSMEN rw	GPIOGSMEN rw	GPIOFSMEN rw	GPIOESMEN rw	GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle fields

GPIOASMEN

Bit 0: I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOBSMEN

Bit 1: I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOCSMEN

Bit 2: I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIODSMEN

Bit 3: I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOESMEN

Bit 4: I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOFSMEN

Bit 5: I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOGSMEN

Bit 6: I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOHSMEN

Bit 7: I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOISMEN

Bit 8: I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOJSMEN

Bit 9: I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

ADC12SMEN

Bit 10: ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx..

DCMI_PSSISMEN

Bit 12: DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software..

OTGSMEN

Bit 14: OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTGHSPHYSMEN

Bit 15: OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

AESSMEN

Bit 16: AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes This bit is set and cleared by software.

RNGSMEN

Bit 18: RNG clock enable during Sleep and Stop modes This bit is set and cleared by software..

PKASMEN

Bit 19: PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SAESSMEN

Bit 20: SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPIMSMEN

Bit 21: OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC1SMEN

Bit 23: OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC2SMEN

Bit 24: OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SDMMC1SMEN

Bit 27: SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SDMMC2SMEN

Bit 28: SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM2SMEN

Bit 30: SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SRAM3SMEN

Bit 31: SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2SMENR2

RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2

Offset: 0xb8, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM5SMEN rw	SRAM6SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSPI1SMEN rw				OCTOSPI2SMEN rw				OCTOSPI1SMEN rw				FSMCSMEN rw

Toggle fields

FSMCSMEN

Bit 0: FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPI1SMEN

Bit 4: OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

OCTOSPI2SMEN

Bit 8: OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HSPI1SMEN

Bit 12: HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM6SMEN

Bit 30: SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM5SMEN

Bit 31: SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB3SMENR

RCC AHB3 peripheral clock enable in Sleep and Stop modes register

Offset: 0xbc, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM4SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			GTZC2SMEN rw		ADF1SMEN rw	LPDMA1SMEN rw			DAC1SMEN rw	ADC4SMEN rw			PWRSMEN rw		LPGPIO1SMEN rw

Toggle fields

LPGPIO1SMEN

Bit 0: LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software..

PWRSMEN

Bit 2: PWR clock enable during Sleep and Stop modes This bit is set and cleared by software..

ADC4SMEN

Bit 5: ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

DAC1SMEN

Bit 6: DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPDMA1SMEN

Bit 9: LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

ADF1SMEN

Bit 10: ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

GTZC2SMEN

Bit 12: GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SRAM4SMEN

Bit 31: SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software..

RCC_APB1SMENR1

RCC APB1 peripheral clock enable in Sleep and Stop modes register 1

Offset: 0xc4, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						USART6SMEN rw	CRSSMEN rw		I2C2SMEN rw	I2C1SMEN rw	UART5SMEN rw	UART4SMEN rw	USART3SMEN rw	USART2SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw			WWDGSMEN rw						TIM7SMEN rw	TIM6SMEN rw	TIM5SMEN rw	TIM4SMEN rw	TIM3SMEN rw	TIM2SMEN rw

Toggle fields

TIM2SMEN

Bit 0: TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM3SMEN

Bit 1: TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM4SMEN

Bit 2: TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM5SMEN

Bit 3: TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM6SMEN

Bit 4: TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM7SMEN

Bit 5: TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software..

WWDGSMEN

Bit 11: Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. It is forced to one by hardware when the hardware WWDG option is activated..

SPI2SMEN

Bit 14: SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

USART2SMEN

Bit 17: USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USART3SMEN

Bit 18: USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

UART4SMEN

Bit 19: UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

UART5SMEN

Bit 20: UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C1SMEN

Bit 21: I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C2SMEN

Bit 22: I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes This bit is set and cleared by software..

USART6SMEN

Bit 25: USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB1SMENR2

RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0xc8, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UCPD1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FDCAN1SMEN rw		I2C6SMEN rw	I2C5SMEN rw	LPTIM2SMEN rw				I2C4SMEN rw

Toggle fields

I2C4SMEN

Bit 1: I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM2SMEN

Bit 5: LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C5SMEN

Bit 6: I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

I2C6SMEN

Bit 7: I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

FDCAN1SMEN

Bit 9: FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

UCPD1SMEN

Bit 23: UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB2SMENR

RCC APB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0xcc, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DSISMEN rw	LTDCSMEN rw	GFXTIMSMEN rw	USBSMEN rw		SAI2SMEN rw	SAI1SMEN rw			TIM17SMEN rw	TIM16SMEN rw	TIM15SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1SMEN rw	TIM8SMEN rw	SPI1SMEN rw	TIM1SMEN rw

Toggle fields

TIM1SMEN

Bit 11: TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SPI1SMEN

Bit 12: SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

TIM8SMEN

Bit 13: TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software..

USART1SMEN

Bit 14: USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

TIM15SMEN

Bit 16: TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM16SMEN

Bit 17: TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM17SMEN

Bit 18: TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SAI1SMEN

Bit 21: SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SAI2SMEN

Bit 22: SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USBSMEN

Bit 24: USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXTIMSMEN

Bit 25: GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

LTDCSMEN

Bit 26: LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DSISMEN

Bit 27: DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB3SMENR

RCC APB3 peripheral clock enable in Sleep and Stop modes register

Offset: 0xd0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										RTCAPBSMEN rw	VREFSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPSMEN rw	OPAMPSMEN rw	LPTIM4SMEN rw	LPTIM3SMEN rw	LPTIM1SMEN rw				I2C3SMEN rw	LPUART1SMEN rw	SPI3SMEN rw				SYSCFGSMEN rw

Toggle fields

SYSCFGSMEN

Bit 1: SYSCFG clock enable during Sleep and Stop modes This bit is set and cleared by software..

SPI3SMEN

Bit 5: SPI3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPUART1SMEN

Bit 6: LPUART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C3SMEN

Bit 7: I2C3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM1SMEN

Bit 11: LPTIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM3SMEN

Bit 12: LPTIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM4SMEN

Bit 13: LPTIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

OPAMPSMEN

Bit 14: OPAMP clock enable during Sleep and Stop modes This bit is set and cleared by software..

COMPSMEN

Bit 15: COMP clock enable during Sleep and Stop modes This bit is set and cleared by software..

VREFSMEN

Bit 20: VREFBUF clock enable during Sleep and Stop modes This bit is set and cleared by software..

RTCAPBSMEN

Bit 21: RTC and TAMP APB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

RCC_SRDAMR

RCC SmartRun domain peripheral autonomous mode register

Offset: 0xd8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM4AMEN rw		ADF1AMEN rw	LPDMA1AMEN rw	DAC1AMEN rw	LPGPIO1AMEN rw	ADC4AMEN rw				RTCAPBAMEN rw	VREFAMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPAMEN rw	OPAMPAMEN rw	LPTIM4AMEN rw	LPTIM3AMEN rw	LPTIM1AMEN rw				I2C3AMEN rw	LPUART1AMEN rw	SPI3AMEN rw

Toggle fields

SPI3AMEN

Bit 5: SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPUART1AMEN

Bit 6: LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C3AMEN

Bit 7: I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM1AMEN

Bit 11: LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM3AMEN

Bit 12: LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM4AMEN

Bit 13: LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

OPAMPAMEN

Bit 14: OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

COMPAMEN

Bit 15: COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

VREFAMEN

Bit 20: VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

RTCAPBAMEN

Bit 21: RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

ADC4AMEN

Bit 25: ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPGPIO1AMEN

Bit 26: LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

DAC1AMEN

Bit 27: DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPDMA1AMEN

Bit 28: LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

ADF1AMEN

Bit 29: ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

SRAM4AMEN

Bit 31: SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

RCC_CCIPR1

RCC peripherals independent clock configuration register 1

Offset: 0xe0, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIMICSEL rw				ICLKSEL rw		FDCAN1SEL rw		SYSTICKSEL rw		SPI1SEL rw		LPTIM2SEL rw		SPI2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I2C4SEL rw		I2C2SEL rw		I2C1SEL rw		UART5SEL rw		UART4SEL rw		USART3SEL rw		USART2SEL rw		USART1SEL rw

Toggle fields

USART1SEL

Bits 0-1: USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

USART2SEL

Bits 2-3: USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source. The USART2 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

USART3SEL

Bits 4-5: USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

UART4SEL

Bits 6-7: UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

UART5SEL

Bits 8-9: UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

I2C1SEL

Bits 10-11: I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK..

I2C2SEL

Bits 12-13: I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK..

I2C4SEL

Bits 14-15: I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK..

SPI2SEL

Bits 16-17: SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK..

LPTIM2SEL

Bits 18-19: Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1..

SPI1SEL

Bits 20-21: SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK..

SYSTICKSEL

Bits 22-23: SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry..

FDCAN1SEL

Bits 24-25: FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source..

ICLKSEL

Bits 26-27: Intermediate clock source selection These bits are used to select the clock source for the OTG_FS, the USB, and the SDMMC..

TIMICSEL

Bits 29-31: Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16, TIM17, and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4, or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK, and MSIS clock sources cannot be selected as�TIM16, TIM17, or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division..

RCC_CCIPR2

RCC peripherals independent clock configuration register 2

Offset: 0xe4, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OTGHSSEL rw				I2C6SEL rw		I2C5SEL rw		HSPI1SEL rw		OCTOSPISEL rw			LTDCSEL rw	USART6SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DSISEL rw	SDMMCSEL rw	RNGSEL rw		SAESSEL rw	SAI2SEL rw			SAI1SEL rw					MDF1SEL rw

Toggle fields

MDF1SEL

Bits 0-2: MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved.

SAI1SEL

Bits 5-7: SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible..

SAI2SEL

Bits 8-10: SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

SAESSEL

Bit 11: SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RNGSEL

Bits 12-13: RNG kernel clock source selection These bits are used to select the RNG kernel clock source..

SDMMCSEL

Bit 14: SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change it only after reset and before enabling the SDMMC..

DSISEL

Bit 15: DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value..

USART6SEL

Bits 16-17: USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

LTDCSEL

Bit 18: LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPISEL

Bits 20-21: OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source..

HSPI1SEL

Bits 22-23: HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

I2C5SEL

Bits 24-25: I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

I2C6SEL

Bits 26-27: I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

OTGHSSEL

Bits 30-31: OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

RCC_CCIPR3

RCC peripherals independent clock configuration register 3

Offset: 0xe8, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													ADF1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DAC1SEL rw	ADCDACSEL rw			LPTIM1SEL rw		LPTIM34SEL rw		I2C3SEL rw			SPI3SEL rw		LPUART1SEL rw

Toggle fields

LPUART1SEL

Bits 0-2: LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16, LSE, or MSIK..

SPI3SEL

Bits 3-4: SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK..

I2C3SEL

Bits 6-7: I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK..

LPTIM34SEL

Bits 8-9: LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON�=�1..

LPTIM1SEL

Bits 10-11: LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON = 1..

ADCDACSEL

Bits 12-14: ADC1, ADC2, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC2, ADC4, and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC2, ADC4, and DAC1 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in�Stop 2 mode)..

DAC1SEL

Bit 15: DAC1 sample-and-hold clock source selection This bit is used to select the DAC1 sample-and-hold clock source..

ADF1SEL

Bits 16-18: ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK..

RCC_BDCR

RCC backup domain control register

Offset: 0xf0, size: 32, reset: 0x00000000, access: Unspecified

3/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			LSIPREDIV rw	LSIRDY rw	LSION rw	LSCOSEL rw	LSCOEN rw								BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw			LSEGFON rw	LSESYSRDY r		RTCSEL rw		LSESYSEN rw	LSECSSD r	LSECSSON rw	LSEDRV rw		LSEBYP rw	LSERDY r	LSEON rw

Toggle fields

LSEON

Bit 0: LSE oscillator enable This bit is set and cleared by software..

LSERDY

Bit 1: LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After LSEON is cleared, this LSERDY bit goes low after six external low-speed oscillator clock cycles..

LSEBYP

Bit 2: LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. It can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)..

LSEDRV

Bits 3-4: LSE oscillator drive capability This bitfield is set by software to modulate the drive capability of the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode..

LSECSSON

Bit 5: CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable this LSECSSON bit..

LSECSSD

Bit 6: CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by the CCS on the external 32�kHz oscillator (LSE)..

LSESYSEN

Bit 7: LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock generated by RCC, which can be used by any peripheral when its source clock is the LSE, or at system level if one of LSCOSEL, MCO, or MSI PLL mode is needed..

RTCSEL

Bits 8-9: RTC and TAMP clock source selection This bit is set by software to select the clock source for the RTC and TAMP. Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the�backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). BDRST bit can be used to reset them..

LSESYSRDY

Bit 11: LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE system clock is stable.When LSESYSEN is set, this LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles..

LSEGFON

Bit 12: LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch filter. It can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)..

RTCEN

Bit 15: RTC and TAMP clock enable This bit is set and cleared by software..

BDRST

Bit 16: Backup domain software reset This bit is set and cleared by software..

LSCOEN

Bit 24: Low-speed clock output (LSCO) enable This bit is set and cleared by software..

LSCOSEL

Bit 25: Low-speed clock output selection This bit is set and cleared by software..

LSION

Bit 26: LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60��s maximum after the LSION bit is cleared..

LSIRDY

Bit 27: LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After�LSION is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0..

LSIPREDIV

Bit 28: Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI division. It can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC..

RCC_CSR

RCC control/status register

Offset: 0xf4, size: 32, reset: 0x0C004400, access: Unspecified

7/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF r	WWDGRSTF r	IWDGRSTF r	SFTRSTF r	BORRSTF r	PINRSTF r	OBLRSTF r		RMVF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSISSRANGE rw				MSIKSRANGE rw

Toggle fields

MSIKSRANGE

Bits 8-11: MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIK frequency..

MSISSRANGE

Bits 12-15: MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIS frequency..

RMVF

Bit 23: Remove reset flag This bit is set by software to clear the reset flags..

OBLRSTF

Bit 25: Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading occurs. It is cleared by�writing to the RMVF bit..

PINRSTF

Bit 26: NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to�the RMVF bit..

BORRSTF

Bit 27: Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout reset or an exit from Shutdown mode reset occurs. It is cleared by writing to the RMVF bit..

SFTRSTF

Bit 28: Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writing to RMVF..

IWDGRSTF

Bit 29: Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared by writing to the RMVF bit..

WWDGRSTF

Bit 30: Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to�the RMVF bit..

LPWRRSTF

Bit 31: Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shutdown mode entry, whereas the corresponding NRST_STOP, NRST_STBY, or NRST_SHDW option bit is cleared. This bit is cleared by writing to the RMVF bit..

RCC_SECCFGR

RCC secure configuration register

Offset: 0x110, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			RMVFSEC rw	HSI48SEC rw	ICLKSEC rw	PLL3SEC rw	PLL2SEC rw	PLL1SEC rw	PRESCSEC rw	SYSCLKSEC rw	LSESEC rw	LSISEC rw	MSISEC rw	HSESEC rw	HSISEC rw

Toggle fields

HSISEC

Bit 0: HSI clock configuration and status bit security This bit is set and reset by software..

HSESEC

Bit 1: HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software..

MSISEC

Bit 2: MSI clock configuration and status bit security This bit is set and reset by software..

LSISEC

Bit 3: LSI clock configuration and status bit security This bit is set and reset by software..

LSESEC

Bit 4: LSE clock configuration and status bit security This bit is set and reset by software..

SYSCLKSEC

Bit 5: SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set and reset by software..

PRESCSEC

Bit 6: AHBx/APBx prescaler configuration bits security This bit is set and reset by software..

PLL1SEC

Bit 7: PLL1 clock configuration and status bit security This bit is set and reset by software..

PLL2SEC

Bit 8: PLL2 clock configuration and status bit security Set and reset by software..

PLL3SEC

Bit 9: PLL3 clock configuration and status bit security This bit is set and reset by software..

ICLKSEC

Bit 10: Intermediate clock source selection security This bit is set and reset by software..

HSI48SEC

Bit 11: HSI48 clock configuration and status bit security This bit is set and reset by software..

RMVFSEC

Bit 12: Remove reset flag security This bit is set and reset by software..

RCC_PRIVCFGR

RCC privilege configuration register

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														NSPRIV rw	SPRIV rw

Toggle fields

SPRIV

Bit 0: RCC secure function privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access..

NSPRIV

Bit 1: RCC non-secure function privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure..

RNG

0x420c0800: Random number generator

4/18 fields covered.

Toggle register map

Offset	Name	31	30	25	19	15	12	11	7	6	5	3	2	1	0
0x0	CR	CONFIGLOCK	CONDRST	RNG_CONFIG1	CLKDIV	RNG_CONFIG2	NISTC	RNG_CONFIG3	ARDIS		CED	IE	RNGEN
0x4	SR									SEIS	CEIS		SECS	CECS	DRDY
0x8	DR	RNDATA				RNDATA
0x10	HTCR	HTCFG				HTCFG

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CONFIGLOCK rw	CONDRST rw					RNG_CONFIG1 rw						CLKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNG_CONFIG2 rw			NISTC rw	RNG_CONFIG3 rw				ARDIS rw		CED rw		IE rw	RNGEN rw

Toggle fields

RNGEN

Bit 2: True random number generator enable.

IE

Bit 3: Interrupt Enable.

CED

Bit 5: Clock error detection.

ARDIS

Bit 7: Auto reset disable.

RNG_CONFIG3

Bits 8-11: RNG configuration 3.

NISTC

Bit 12: Non NIST compliant.

RNG_CONFIG2

Bits 13-15: RNG configuration 2.

CLKDIV

Bits 16-19: Clock divider factor.

RNG_CONFIG1

Bits 20-25: RNG configuration 1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: RNG Config Lock.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SEIS rw	CEIS rw			SECS r	CECS r	DRDY r

Toggle fields

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNDATA r

Toggle fields

RNDATA

Bits 0-31: Random data.

HTCR

health test control register

Offset: 0x10, size: 32, reset: 0x00006274, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HTCFG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HTCFG rw

Toggle fields

HTCFG

Bits 0-31: health test configuration.

RTC

0x46007800: Real-time clock

40/156 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TR										PM	HT		HU					MNT			MNU					ST			SU
0x4	DR									YT				YU				WDU			MT	MU						DT		DU
0x8	SSR	SS																SS
0xc	ICSR																RECALPF				BCDU			BIN		INIT	INITF	RSF	INITS	SHPF	WUTWF
0x10	PRER										PREDIV_A								PREDIV_S
0x14	WUTR	WUTOCLR																WUT
0x18	CR	OUT2EN	TAMPALRM_TYPE	TAMPALRM_PU	ALRBFCLR	ALRAFCLR	TAMPOE	TAMPTS	ITSE	COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE	WUTIE	ALRBIE	ALRAIE	TSE	WUTE	ALRBE	ALRAE	SSRUIE	FMT	BYPSHAD	REFCKON	TSEDGE	WUCKSEL
0x1c	PRIVCR																	PRIV	INITPRIV	CALPRIV										TSPRIV	WUTPRIV	ALRBPRIV	ALRAPRIV
0x20	SECCFGR																	SEC	INITSEC	CALSEC										TSSEC	WUTSEC	ALRBSEC	ALRASEC
0x24	WPR																									KEY
0x28	CALR																	CALP	CALW8	CALW16	LPCAL				CALM
0x2c	SHIFTR	ADD1S																	SUBFS
0x30	TSTR										PM	HT		HU					MNT			MNU					ST			SU
0x34	TSDR																	WDU			MT	MU						DT		DU
0x38	TSSSR	SS																SS
0x40	ALRMAR	MSK4	WDSEL	DT		DU				MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x44	ALRMASSR	SSCLR		MASKSS															SS
0x48	ALRMBR	MSK4	WDSEL	DT		DU				MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x4c	ALRMBSSR	SSCLR		MASKSS															SS
0x50	SR																										SSRUF	ITSF	TSOVF	TSF	WUTF	ALRBF	ALRAF
0x54	MISR																										SSRUMF	ITSMF	TSOVMF	TSMF	WUTMF	ALRBMF	ALRAMF
0x58	SMISR																										SSRUMF	ITSMF	TSOVMF	TSMF	WUTMF	ALRBMF	ALRAMF
0x5c	SCR																										CSSRUF	CITSF	CTSOVF	CTSF	CWUTF	CALRBF	CALRAF
0x70	ALRABINR	SS																SS
0x74	ALRBBINR	SS																SS

Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-31: SS.

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

5/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			BCDU rw			BIN rw		INIT rw	INITF r	RSF rw	INITS r	SHPF r	WUTWF r

Toggle fields

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

BIN

Bits 8-9: BIN.

BCDU

Bits 10-12: BCDU.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WUTOCLR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

WUTOCLR

Bits 16-31: WUTOCLR.

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/29 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUT2EN rw	TAMPALRM_TYPE rw	TAMPALRM_PU rw	ALRBFCLR rw	ALRAFCLR rw	TAMPOE rw	TAMPTS rw	ITSE rw	COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H w	ADD1H w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw	ALRBIE rw	ALRAIE rw	TSE rw	WUTE rw	ALRBE rw	ALRAE rw	SSRUIE rw	FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw	WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

TSEDGE

Bit 3: TSEDGE.

REFCKON

Bit 4: REFCKON.

BYPSHAD

Bit 5: BYPSHAD.

FMT

Bit 6: FMT.

SSRUIE

Bit 7: SSRUIE.

ALRAE

Bit 8: ALRAE.

ALRBE

Bit 9: ALRBE.

WUTE

Bit 10: WUTE.

TSE

Bit 11: TSE.

ALRAIE

Bit 12: ALRAIE.

ALRBIE

Bit 13: ALRBIE.

WUTIE

Bit 14: WUTIE.

TSIE

Bit 15: TSIE.

ADD1H

Bit 16: ADD1H.

SUB1H

Bit 17: SUB1H.

BKP

Bit 18: BKP.

COSEL

Bit 19: COSEL.

POL

Bit 20: POL.

OSEL

Bits 21-22: OSEL.

COE

Bit 23: COE.

ITSE

Bit 24: ITSE.

TAMPTS

Bit 25: TAMPTS.

TAMPOE

Bit 26: TAMPOE.

ALRAFCLR

Bit 27: ALRAFCLR.

ALRBFCLR

Bit 28: ALRBFCLR.

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

OUT2EN

Bit 31: OUT2EN.

PRIVCR

RTC privilege mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV rw	INITPRIV rw	CALPRIV rw										TSPRIV rw	WUTPRIV rw	ALRBPRIV rw	ALRAPRIV rw

Toggle fields

ALRAPRIV

Bit 0: ALRAPRIV.

ALRBPRIV

Bit 1: ALRBPRIV.

WUTPRIV

Bit 2: WUTPRIV.

TSPRIV

Bit 3: TSPRIV.

CALPRIV

Bit 13: CALPRIV.

INITPRIV

Bit 14: INITPRIV.

PRIV

Bit 15: PRIV.

SECCFGR

RTC secure mode control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC rw	INITSEC rw	CALSEC rw										TSSEC rw	WUTSEC rw	ALRBSEC rw	ALRASEC rw

Toggle fields

ALRASEC

Bit 0: ALRASEC.

ALRBSEC

Bit 1: ALRBSEC.

WUTSEC

Bit 2: WUTSEC.

TSSEC

Bit 3: TSSEC.

CALSEC

Bit 13: CALSEC.

INITSEC

Bit 14: INITSEC.

SEC

Bit 15: SEC.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle fields

KEY

Bits 0-7: Write protection key.

CALR

calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw	LPCAL rw				CALM rw

Toggle fields

CALM

Bits 0-8: Calibration minus.

LPCAL

Bit 12: LPCAL.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM r	HT r		HU r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT r			MNU r					ST r			SU r

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU r			MT r	MU r						DT r		DU r

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-31: Sub second value.

ALRMAR

alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMASSR

alarm A sub second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SSCLR rw		MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

SSCLR

Bit 31: SSCLR.

ALRMBR

alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

ALRMBSSR

alarm B sub second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SSCLR rw		MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

SSCLR

Bit 31: SSCLR.

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SSRUF r	ITSF r	TSOVF r	TSF r	WUTF r	ALRBF r	ALRAF r

Toggle fields

ALRAF

Bit 0: ALRAF.

ALRBF

Bit 1: ALRBF.

WUTF

Bit 2: WUTF.

TSF

Bit 3: TSF.

TSOVF

Bit 4: TSOVF.

ITSF

Bit 5: ITSF.

SSRUF

Bit 6: SSRUF.

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SSRUMF r	ITSMF r	TSOVMF r	TSMF r	WUTMF r	ALRBMF r	ALRAMF r

Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SSRUMF

Bit 6: SSRUMF.

SMISR

RTC secure masked interrupt status register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SSRUMF r	ITSMF r	TSOVMF r	TSMF r	WUTMF r	ALRBMF r	ALRAMF r

Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SSRUMF

Bit 6: SSRUMF.

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CSSRUF w	CITSF w	CTSOVF w	CTSF w	CWUTF w	CALRBF w	CALRAF w

Toggle fields

CALRAF

Bit 0: CALRAF.

CALRBF

Bit 1: CALRBF.

CWUTF

Bit 2: CWUTF.

CTSF

Bit 3: CTSF.

CTSOVF

Bit 4: CTSOVF.

CITSF

Bit 5: CITSF.

CSSRUF

Bit 6: CSSRUF.

ALRABINR

RTC alarm A binary mode register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS rw

Toggle fields

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

ALRBBINR

RTC alarm B binary mode register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS rw

Toggle fields

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

SAI1

0x40015400: Serial audio interface

18/122 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	22	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GCR																					SYNCOUT				SYNCIN
0x4	ACR1			MCKEN	OSR	MCKDIV		NODIV		DMAEN	SAIAEN			OUTDRIV	MONO	SYNCEN		CKSTR	LSBFIRST	DS				PRTCFG		MODE
0x8	ACR2											COMP		CPL	MUTECN						MUTEVAL	MUTE	TRIS	FFLUSH	FTH
0xc	AFRCR								FSOFF	FSPOL	FSDEF		FSALL							FRL
0x10	ASLOTR	SLOTEN														NBSLOT				SLOTSZ			FBOFF
0x14	AIM																				LFSDETIE	AFSDETIE	CNRDYIE	FREQIE	WCKCFGIE	MUTEDETIE	OVRUDRIE
0x18	ASR								FLVL												LFSDET	AFSDET	CNRDY	FREQ	WCKCFG	MUTEDET	OVRUDR
0x1c	ACLRFR																				CLFSDET	CAFSDET	CCNRDY		CWCKCFG	CMUTEDET	COVRUDR
0x20	ADR	DATA										DATA
0x24	BCR1			MCKEN	OSR	MCKDIV		NODIV		DMAEN	SAIAEN			OUTDRIV	MONO	SYNCEN		CKSTR	LSBFIRST	DS				PRTCFG		MODE
0x28	BCR2											COMP		CPL	MUTECN						MUTEVAL	MUTE	TRIS	FFLUSH	FTH
0x2c	BFRCR								FSOFF	FSPOL	FSDEF		FSALL							FRL
0x30	BSLOTR	SLOTEN														NBSLOT				SLOTSZ			FBOFF
0x34	BIM																				LFSDETIE	AFSDETIE	CNRDYIE	FREQIE	WCKCFGIE	MUTEDETIE	OVRUDRIE
0x38	BSR								FLVL												LFSDET	AFSDET	CNRDY	FREQ	WCKCFG	MUTEDET	OVRUDR
0x3c	BCLRFR																				CLFSDET	CAFSDET	CCNRDY		CWCKCFG	CMUTEDET	COVRUDR
0x40	BDR	DATA										DATA
0x44	PDMCR															CKEN4	CKEN3	CKEN2	CKEN1			MICNBR					PDMEN
0x48	PDMDLY		DLYM4R		DLYM4L		DLYM3R		DLYM3L				DLYM2R				DLYM2L				DLYM1R				DLYM1L

Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SYNCOUT rw				SYNCIN rw

Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

ACR1

A Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCKDIV rw						NODIV rw		DMAEN rw	SAIAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OUTDRIV rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle fields

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OUTDRIV

Bit 13: Output drive.

SAIAEN

Bit 16: Audio block A enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCKDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

ACR2

A Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECN rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUSH rw	FTH rw

Toggle fields

FTH

Bits 0-2: FIFO threshold.

FFLUSH

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

AFRCR

A frame configuration register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

ASLOTR

A Slot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

AIM

A Interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFGIE rw	MUTEDETIE rw	OVRUDRIE rw

Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDETIE

Bit 1: Mute detection interrupt enable.

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

ASR

A Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

ACLRFR

A Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CLFSDET w	CAFSDET w	CCNRDY w		CWCKCFG w	CMUTEDET w	COVRUDR w

Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

CMUTEDET

Bit 1: Mute detection flag.

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

CCNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

ADR

A Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

BCR1

B Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCKDIV rw						NODIV rw		DMAEN rw	SAIAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OUTDRIV rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle fields

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OUTDRIV

Bit 13: Output drive.

SAIAEN

Bit 16: Audio block A enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCKDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

BCR2

B Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECN rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUSH rw	FTH rw

Toggle fields

FTH

Bits 0-2: FIFO threshold.

FFLUSH

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

BFRCR

B frame configuration register

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

BSLOTR

B Slot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

BIM

B Interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFGIE rw	MUTEDETIE rw	OVRUDRIE rw

Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDETIE

Bit 1: Mute detection interrupt enable.

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

BSR

B Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

BCLRFR

B Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CLFSDET w	CAFSDET w	CCNRDY w		CWCKCFG w	CMUTEDET w	COVRUDR w

Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

CMUTEDET

Bit 1: Mute detection flag.

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

CCNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

BDR

B Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CKEN4 rw	CKEN3 rw	CKEN2 rw	CKEN1 rw			MICNBR rw					PDMEN rw

Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

CKEN3

Bit 10: CKEN3.

CKEN4

Bit 11: CKEN4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DLYM4R rw				DLYM4L rw				DLYM3R rw				DLYM3L rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DLYM2R rw				DLYM2L rw				DLYM1R rw				DLYM1L rw

Toggle fields

DLYM1L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM1R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM2L

Bits 8-10: Delay line for first microphone of pair 2.

DLYM2R

Bits 12-14: Delay line for second microphone of pair 2.

DLYM3L

Bits 16-18: DLYM3L.

DLYM3R

Bits 20-22: DLYM3R.

DLYM4L

Bits 24-26: DLYM4L.

DLYM4R

Bits 28-30: DLYM4R.

SDMMC

0x420c8000: Secure digital input/output MultiMediaCard interface

35/140 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	POWER																												DIRPOL	VSWITCHEN	VSWITCH	PWRCTRL
0x4	CLKCR											SELCLKRX		BUSSPEED	DDR	HWFC_EN	NEGEDGE	WIDBUS			PWRSAV			CLKDIV
0x8	ARGR	CMDARG																CMDARG
0xc	CMDR																CMDSUSPEND	BOOTEN	BOOTMODE	DTHOLD	CPSMEN	WAITPEND	WAITINT	WAITRESP		CMDSTOP	CMDTRANS	CMDINDEX
0x10	RESPCMDR																											RESPCMD
0x14	RESP1	CARDSTATUS1																CARDSTATUS1
0x18	RESP2	CARDSTATUS2																CARDSTATUS2
0x1c	RESP3	CARDSTATUS3																CARDSTATUS3
0x20	RESP4	CARDSTATUS4																CARDSTATUS4
0x24	DTIMER	DATATIME																DATATIME
0x28	DLENR								DATALENGTH									DATALENGTH
0x2c	DCTRL																			FIFORST	BOOTACKEN	SDIOEN	RWMOD	RWSTOP	RWSTART	DBLOCKSIZE				DTMODE		DTDIR	DTEN
0x30	DCNTR								DATACOUNT									DATACOUNT
0x34	STAR				IDMABTC	IDMATE	CKSTOP	VSWEND	ACKTIMEOUT	ACKFAIL	SDIOIT	BUSYD0END	BUSYD0	RXFIFOE	TXFIFOE	RXFIFOF	TXFIFOF	RXFIFOHF	TXFIFOHE	CPSMACT	DPSMACT	DABORT	DBCKEND	DHOLD	DATAEND	CMDSENT	CMDREND	RXOVERR	TXUNDERR	DTIMEOUT	CTIMEOUT	DCRCFAIL	CCRCFAIL
0x38	ICR				IDMABTCC	IDMATEC	CKSTOPC	VSWENDC	ACKTIMEOUTC	ACKFAILC	SDIOITC	BUSYD0ENDC										DABORTC	DBCKENDC	DHOLDC	DATAENDC	CMDSENTC	CMDRENDC	RXOVERRC	TXUNDERRC	DTIMEOUTC	CTIMEOUTC	DCRCFAILC	CCRCFAILC
0x3c	MASKR				IDMABTCIE		CKSTOPIE	VSWENDIE	ACKTIMEOUTIE	ACKFAILIE	SDIOITIE	BUSYD0ENDIE			TXFIFOEIE	RXFIFOFIE		RXFIFOHFIE	TXFIFOHEIE			DABORTIE	DBCKENDIE	DHOLDIE	DATAENDIE	CMDSENTIE	CMDRENDIE	RXOVERRIE	TXUNDERRIE	DTIMEOUTIE	CTIMEOUTIE	DCRCFAILIE	CCRCFAILIE
0x40	ACKTIMER								ACKTIME									ACKTIME
0x50	SDMMC_IDMACTRLR																															IDMABMODE	IDMAEN
0x54	SDMMC_IDMABSIZER																IDMABNDT	IDMABNDT
0x58	SDMMC_IDMABASER	IDMABASE																IDMABASE
0x64	SDMMC_IDMALAR	ULA	ULS	ABR														IDMALA
0x68	SDMMC_IDMABAR	IDMABA																IDMABA
0x80	FIFOR0	FIFODATA																FIFODATA
0x84	FIFOR1	FIFODATA																FIFODATA
0x88	FIFOR2	FIFODATA																FIFODATA
0x8c	FIFOR3	FIFODATA																FIFODATA
0x90	FIFOR4	FIFODATA																FIFODATA
0x94	FIFOR5	FIFODATA																FIFODATA
0x98	FIFOR6	FIFODATA																FIFODATA
0x9c	FIFOR7	FIFODATA																FIFODATA
0xa0	FIFOR8	FIFODATA																FIFODATA
0xa4	FIFOR9	FIFODATA																FIFODATA
0xa8	FIFOR10	FIFODATA																FIFODATA
0xac	FIFOR11	FIFODATA																FIFODATA
0xb0	FIFOR12	FIFODATA																FIFODATA
0xb4	FIFOR13	FIFODATA																FIFODATA
0xb8	FIFOR14	FIFODATA																FIFODATA
0xbc	FIFOR15	FIFODATA																FIFODATA

Toggle registers

POWER

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DIRPOL rw	VSWITCHEN rw	VSWITCH rw	PWRCTRL rw

Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits.

VSWITCH

Bit 2: Voltage switch sequence start.

VSWITCHEN

Bit 3: Voltage switch procedure enable.

DIRPOL

Bit 4: Data and command direction signals polarity selection.

CLKCR

clock control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SELCLKRX rw		BUSSPEED rw	DDR rw	HWFC_EN rw	NEGEDGE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WIDBUS rw			PWRSAV rw			CLKDIV rw

Toggle fields

CLKDIV

Bits 0-9: Clock divide factor.

PWRSAV

Bit 12: Power saving configuration bit.

WIDBUS

Bits 14-15: Wide bus mode enable bit.

NEGEDGE

Bit 16: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 17: HW Flow Control enable.

DDR

Bit 18: Data rate signaling selection.

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104.

SELCLKRX

Bits 20-21: Receive clock selection.

ARGR

argument register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDARG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDARG rw

Toggle fields

CMDARG

Bits 0-31: Command argument.

CMDR

command register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															CMDSUSPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BOOTEN rw	BOOTMODE rw	DTHOLD rw	CPSMEN rw	WAITPEND rw	WAITINT rw	WAITRESP rw		CMDSTOP rw	CMDTRANS rw	CMDINDEX rw

Toggle fields

CMDINDEX

Bits 0-5: Command index.

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM.

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM.

WAITRESP

Bits 8-9: Wait for response bits.

WAITINT

Bit 10: CPSM waits for interrupt request.

WAITPEND

Bit 11: CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM.

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit.

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM.

BOOTMODE

Bit 14: Select the boot mode procedure to be used.

BOOTEN

Bit 15: Enable boot mode procedure.

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end.

RESPCMDR

command response register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RESPCMD r

Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS1 r

Toggle fields

CARDSTATUS1

Bits 0-31: CARDSTATUS1.

RESP2

response 2 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS2 r

Toggle fields

CARDSTATUS2

Bits 0-31: CARDSTATUS2.

RESP3

response 3 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS3 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS3 r

Toggle fields

CARDSTATUS3

Bits 0-31: CARDSTATUS3.

RESP4

response 4 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS4 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS4 r

Toggle fields

CARDSTATUS4

Bits 0-31: CARDSTATUS4.

DTIMER

data timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATATIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATATIME rw

Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period.

DLENR

data length register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DATALENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATALENGTH rw

Toggle fields

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		FIFORST rw	BOOTACKEN rw	SDIOEN rw	RWMOD rw	RWSTOP rw	RWSTART rw	DBLOCKSIZE rw				DTMODE rw		DTDIR rw	DTEN rw

Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bits 2-3: Data transfer mode selection.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment.

FIFORST

Bit 13: FIFO reset, will flush any remaining data.

DCNTR

data counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DATACOUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATACOUNT r

Toggle fields

DATACOUNT

Bits 0-24: Data count value.

STAR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			IDMABTC r	IDMATE r	CKSTOP r	VSWEND r	ACKTIMEOUT r	ACKFAIL r	SDIOIT r	BUSYD0END r	BUSYD0 r	RXFIFOE r	TXFIFOE r	RXFIFOF r	TXFIFOF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFIFOHF r	TXFIFOHE r	CPSMACT r	DPSMACT r	DABORT r	DBCKEND r	DHOLD r	DATAEND r	CMDSENT r	CMDREND r	RXOVERR r	TXUNDERR r	DTIMEOUT r	CTIMEOUT r	DCRCFAIL r	CCRCFAIL r

Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error (masked by hardware when IDMA is enabled).

RXOVERR

Bit 5: Received FIFO overrun error (masked by hardware when IDMA is enabled).

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data transfer ended correctly.

DHOLD

Bit 9: Data transfer Hold.

DBCKEND

Bit 10: Data block sent/received.

DABORT

Bit 11: Data transfer aborted by CMD12.

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state.

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state.

TXFIFOHE

Bit 14: Transmit FIFO half empty.

RXFIFOHF

Bit 15: Receive FIFO half full.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response.

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected.

SDIOIT

Bit 22: SDIO interrupt received.

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail).

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout.

VSWEND

Bit 25: Voltage switch critical timing section completion.

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure.

IDMATE

Bit 27: IDMA transfer error.

IDMABTC

Bit 28: IDMA buffer transfer complete.

ICR

interrupt clear register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			IDMABTCC rw	IDMATEC rw	CKSTOPC rw	VSWENDC rw	ACKTIMEOUTC rw	ACKFAILC rw	SDIOITC rw	BUSYD0ENDC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DABORTC rw	DBCKENDC rw	DHOLDC rw	DATAENDC rw	CMDSENTC rw	CMDRENDC rw	RXOVERRC rw	TXUNDERRC rw	DTIMEOUTC rw	CTIMEOUTC rw	DCRCFAILC rw	CCRCFAILC rw

Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

DHOLDC

Bit 9: DHOLD flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

DABORTC

Bit 11: DABORT flag clear bit.

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

ACKFAILC

Bit 23: ACKFAIL flag clear bit.

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit.

VSWENDC

Bit 25: VSWEND flag clear bit.

CKSTOPC

Bit 26: CKSTOP flag clear bit.

IDMATEC

Bit 27: IDMA transfer error clear bit.

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit.

MASKR

mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			IDMABTCIE rw		CKSTOPIE rw	VSWENDIE rw	ACKTIMEOUTIE rw	ACKFAILIE rw	SDIOITIE rw	BUSYD0ENDIE rw			TXFIFOEIE rw	RXFIFOFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFIFOHFIE rw	TXFIFOHEIE rw			DABORTIE rw	DBCKENDIE rw	DHOLDIE rw	DATAENDIE rw	CMDSENTIE rw	CMDRENDIE rw	RXOVERRIE rw	TXUNDERRIE rw	DTIMEOUTIE rw	CTIMEOUTIE rw	DCRCFAILIE rw	CCRCFAILIE rw

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

DHOLDIE

Bit 9: Data hold interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

DABORTIE

Bit 11: Data transfer aborted interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable.

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable.

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable.

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable.

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable.

ACKTIMER

acknowledgment timer register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ACKTIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACKTIME rw

Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period.

SDMMC_IDMACTRLR

DMA control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														IDMABMODE rw	IDMAEN rw

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ULA rw	ULS rw	ABR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDMALA rw

Toggle fields

IDMALA

Bits 2-15: Acknowledge linked list buffer ready.

ABR

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ADC_ISR																			LDORDY			AWD3	AWD2	AWD1	JEOS	JEOC	OVR	EOS	EOC	EOSMP	ADRDY
0x4	ADC_IER																						AWD3IE	AWD2IE	AWD1IE	JEOSIE	JEOCIE	OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	ADC_CR	ADCAL		DEEPPWD	ADVREGEN	CALINDEX										ADCALLIN											JADSTP	ADSTP	JADSTART	ADSTART	ADDIS	ADEN
0xc	ADC_CFGR1		AWD1CH					JAUTO	JAWD1EN	AWD1EN	AWD1SGL	JDISCEN	DISCNUM			DISCEN		AUTDLY	CONT	OVRMOD	EXTEN		EXTSEL						RES		DMNGT
0x10	ADC_CFGR2	LSHIFT				LFTRIG		OSR									SMPTRIG	SWTRIG	BULB			ROVSM	TROVS	OVSS							JOVSE	ROVSE
0x14	ADC_SMPR1			SMP9			SMP8			SMP7		SMP6			SMP5		SMP5	SMP4			SMP3			SMP2			SMP1			SMP0
0x18	ADC_SMPR2			SMP19			SMP18			SMP17		SMP16			SMP15		SMP15	SMP14			SMP13			SMP12			SMP11			SMP10
0x1c	ADC_PCSEL												PCSEL19	PCSEL18	PCSEL17	PCSEL16	PCSEL15	PCSEL14	PCSEL13	PCSEL12	PCSEL11	PCSEL10	PCSEL9	PCSEL8	PCSEL7	PCSEL6	PCSEL5	PCSEL4	PCSEL3	PCSEL2	PCSEL1	PCSEL0
0x30	ADC_SQR1				SQ4						SQ3					SQ2	SQ2					SQ1							L
0x34	ADC_SQR2				SQ9						SQ8					SQ7	SQ7					SQ6						SQ5
0x38	ADC_SQR3				SQ14						SQ13					SQ12	SQ12					SQ11						SQ10
0x3c	ADC_SQR4																					SQ16						SQ15
0x40	ADC_DR	RDATA															RDATA
0x4c	ADC_JSQR	JSQ4						JSQ3					JSQ2				JSQ2		JSQ1					JEXTEN		JEXTSEL					JL
0x60	ADC_OFR1	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x64	ADC_OFR2	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x68	ADC_OFR3	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x6c	ADC_OFR4	OFFSET_CH					SSAT	USAT	POSOFF	OFFSET							OFFSET
0x70	ADC_GCOMP	GCOMP																	GCOMPCOEFF
0x80	ADC_JDR1	JDATA															JDATA
0x84	ADC_JDR2	JDATA															JDATA
0x88	ADC_JDR3	JDATA															JDATA
0x8c	ADC_JDR4	JDATA															JDATA
0xa0	ADC_AWD2CR												AWD2CH				AWD2CH
0xa4	ADC_AWD3CR												AWD3CH				AWD3CH
0xa8	ADC_LTR1								LTR1								LTR1
0xac	ADC_HTR1	AWDFILT1							HTR1								HTR1
0xb0	ADC_LTR2								LTR2								LTR2
0xb4	ADC_HTR2								HTR2								HTR2
0xb8	ADC_LTR3								LTR3								LTR3
0xbc	ADC_HTR3								HTR3								HTR3
0xc0	ADC_DIFSEL												DIFSEL				DIFSEL
0xc4	ADC_CALFACT							CAPTURE_COEF	LATCH_COEF							VALIDITY	I_APB_DATA								I_APB_ADDR
0xc8	ADC_CALFACT2	CALFACT															CALFACT

Toggle registers

ADC_ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDY r			AWD3 rw	AWD2 rw	AWD1 rw	JEOS rw	JEOC rw	OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

LDORDY

Bit 12: LDORDY.

ADC_IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						AWD3IE rw	AWD2IE rw	AWD1IE rw	JEOSIE rw	JEOCIE rw	OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

ADC_CR

ADC control register

Offset: 0x8, size: 32, reset: 0x20000000, access: Unspecified

7/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL r		DEEPPWD rw	ADVREGEN rw	CALINDEX rw											ADCALLIN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										JADSTP r	ADSTP r	JADSTART r	ADSTART r	ADDIS r	ADEN r

Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADCALLIN

Bit 16: ADCALLIN.

CALINDEX

Bits 24-27: CALINDEX.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCAL

Bit 31: ADCAL.

ADC_CFGR1

ADC configuration register

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	AWD1CH rw					JAUTO rw	JAWD1EN rw	AWD1EN rw	AWD1SGL rw		JDISCEN rw	DISCNUM rw			DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	AUTDLY rw	CONT rw	OVRMOD rw	EXTEN rw		EXTSEL rw						RES rw		DMNGT rw

Toggle fields

DMNGT

Bits 0-1: DMNGT.

RES

Bits 2-3: RES.

EXTSEL

Bits 5-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWD1CH

Bits 26-30: AWD1CH.

ADC_CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LSHIFT rw				LFTRIG rw		OSR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPTRIG rw	SWTRIG rw	BULB rw			ROVSM rw	TROVS rw	OVSS rw							JOVSE rw	ROVSE rw

Toggle fields

ROVSE

Bit 0: ROVSE.

JOVSE

Bit 1: JOVSE.

OVSS

Bits 5-8: OVSS.

TROVS

Bit 9: TROVS.

ROVSM

Bit 10: ROVSM.

BULB

Bit 13: BULB.

SWTRIG

Bit 14: SWTRIG.

SMPTRIG

Bit 15: SMPTRIG.

OSR

Bits 16-25: OSR.

LFTRIG

Bit 27: LFTRIG.

LSHIFT

Bits 28-31: LSHIFT.

ADC_SMPR1

ADC sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP9 rw			SMP8 rw			SMP7 rw			SMP6 rw			SMP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5 rw	SMP4 rw			SMP3 rw			SMP2 rw			SMP1 rw			SMP0 rw

Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

ADC_SMPR2

ADC sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP19 rw			SMP18 rw			SMP17 rw			SMP16 rw			SMP15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15 rw	SMP14 rw			SMP13 rw			SMP12 rw			SMP11 rw			SMP10 rw

Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

SMP19

Bits 27-29: SMP19.

ADC_PCSEL

ADC channel preselection register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												PCSEL19 rw	PCSEL18 rw	PCSEL17 rw	PCSEL16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCSEL15 rw	PCSEL14 rw	PCSEL13 rw	PCSEL12 rw	PCSEL11 rw	PCSEL10 rw	PCSEL9 rw	PCSEL8 rw	PCSEL7 rw	PCSEL6 rw	PCSEL5 rw	PCSEL4 rw	PCSEL3 rw	PCSEL2 rw	PCSEL1 rw	PCSEL0 rw

Toggle fields

PCSEL0

Bit 0: PCSEL0.

PCSEL1

Bit 1: PCSEL1.

PCSEL2

Bit 2: PCSEL2.

PCSEL3

Bit 3: PCSEL3.

PCSEL4

Bit 4: PCSEL4.

PCSEL5

Bit 5: PCSEL5.

PCSEL6

Bit 6: PCSEL6.

PCSEL7

Bit 7: PCSEL7.

PCSEL8

Bit 8: PCSEL8.

PCSEL9

Bit 9: PCSEL9.

PCSEL10

Bit 10: PCSEL10.

PCSEL11

Bit 11: PCSEL11.

PCSEL12

Bit 12: PCSEL12.

PCSEL13

Bit 13: PCSEL13.

PCSEL14

Bit 14: PCSEL14.

PCSEL15

Bit 15: PCSEL15.

PCSEL16

Bit 16: PCSEL16.

PCSEL17

Bit 17: PCSEL17.

PCSEL18

Bit 18: PCSEL18.

PCSEL19

Bit 19: PCSEL19.

ADC_SQR1

ADC regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ4 rw						SQ3 rw						SQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ2 rw					SQ1 rw							L rw

Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

ADC_SQR2

ADC regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ9 rw						SQ8 rw						SQ7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ7 rw					SQ6 rw						SQ5 rw

Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

ADC_SQR3

ADC regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ14 rw						SQ13 rw						SQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ12 rw					SQ11 rw						SQ10 rw

Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

ADC_SQR4

ADC regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SQ16 rw						SQ15 rw

Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

ADC_DR

ADC regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA r

Toggle fields

RDATA

Bits 0-31: RDATA.

ADC_JSQR

ADC injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JSQ4 rw						JSQ3 rw						JSQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ2 rw		JSQ1 rw					JEXTEN rw		JEXTSEL rw					JL rw

Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-6: JEXTSEL.

JEXTEN

Bits 7-8: JEXTEN.

JSQ1

Bits 9-13: JSQ1.

JSQ2

Bits 15-19: JSQ2.

JSQ3

Bits 21-25: JSQ3.

JSQ4

Bits 27-31: JSQ4.

ADC_OFR1

ADC offset register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_OFR2

ADC offset register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_OFR3

ADC offset register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_OFR4

ADC offset register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET_CH rw					SSAT rw	USAT rw	POSOFF rw	OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-23: OFFSET.

POSOFF

Bit 24: POSOFF.

USAT

Bit 25: USAT.

SSAT

Bit 26: SSAT.

OFFSET_CH

Bits 27-31: OFFSET_CH.

ADC_GCOMP

ADC gain compensation register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GCOMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		GCOMPCOEFF rw

Toggle fields

GCOMPCOEFF

Bits 0-13: GCOMPCOEFF.

GCOMP

Bit 31: GCOMP.

ADC_JDR1

ADC injected data register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_JDR2

ADC injected data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_JDR3

ADC injected data register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_JDR4

ADC injected data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-31: JDATA.

ADC_AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AWD2CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH rw

Toggle fields

AWD2CH

Bits 0-19: AWD2CH.

ADC_AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AWD3CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH rw

Toggle fields

AWD3CH

Bits 0-19: AWD3CH.

ADC_LTR1

ADC watchdog threshold register 1

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							LTR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LTR1 rw

Toggle fields

LTR1

Bits 0-24: LTR1.

ADC_HTR1

ADC watchdog threshold register 1

Offset: 0xac, size: 32, reset: 0x01FFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AWDFILT1 rw							HTR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HTR1 rw

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CAPTURE_COEF rw	LATCH_COEF rw								VALIDITY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I_APB_DATA r								I_APB_ADDR r

Toggle fields

I_APB_ADDR

Bits 0-7: I_APB_ADDR.

I_APB_DATA

Bits 8-15: I_APB_DATA.

VALIDITY

Bit 16: VALIDITY.

LATCH_COEF

Bit 24: LATCH_COEF.

CAPTURE_COEF

Bit 25: CAPTURE_COEF.

ADC_CALFACT2

ADC calibration factor register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALFACT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALFACT rw

Toggle fields

CALFACT

Bits 0-31: CALFACT.

SEC_ADC12_Common

0x52028300: Analog-to-Digital Converter

25/32 fields covered.

Toggle register map

Offset	Name	31	28	25	24	23	22	21	20	19	18	17	16	15	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ADC12_CSR		LDORDY_SLV	AWD3_SLV	AWD2_SLV	AWD1_SLV	JEOS_SLV	JEOC_SLV	OVR_SLV	EOS_SLV	EOC_SLV	EOSMP_SLV	ADRDY_SLV		LDORDY_MST		AWD3_MST	AWD2_MST	AWD1_MST	JEOS_MST	JEOC_MST	OVR_MST	EOS_MST	EOC_MST	EOSMP_MST	ADRDY_MST
0x8	ADC12_CCR				VBATEN	VSENSESEL	VREFEN	PRESC						DAMDF		DELAY						DUAL
0xc	ADC12_CDR	RDATA_SLV												RDATA_MST
0x10	ADC12_CDR2	RDATA_ALT												RDATA_ALT

Toggle registers

ADC12_CSR

ADC common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			LDORDY_SLV r			AWD3_SLV r	AWD2_SLV r	AWD1_SLV r	JEOS_SLV r	JEOC_SLV r	OVR_SLV r	EOS_SLV r	EOC_SLV r	EOSMP_SLV r	ADRDY_SLV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDY_MST r			AWD3_MST r	AWD2_MST r	AWD1_MST r	JEOS_MST r	JEOC_MST r	OVR_MST r	EOS_MST r	EOC_MST r	EOSMP_MST r	ADRDY_MST r

Toggle fields

ADRDY_MST

Bit 0: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register..

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register..

EOC_MST

Bit 2: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register..

EOS_MST

Bit 3: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register..

OVR_MST

Bit 4: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register..

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register..

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register..

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register..

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register..

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register..

LDORDY_MST

Bit 12: ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register..

ADRDY_SLV

Bit 16: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register..

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register..

EOC_SLV

Bit 18: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register..

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register..

OVR_SLV

Bit 20: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register..

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register..

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register..

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register..

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register..

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register..

LDORDY_SLV

Bit 28: ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register..

ADC12_CCR

ADC_CCR system control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							VBATEN rw	VSENSESEL rw	VREFEN rw	PRESC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DAMDF rw				DELAY rw							DUAL rw

Toggle fields

DUAL

Bits 0-4: Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

DELAY

Bits 8-11: Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

DAMDF

Bits 14-15: Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register ADC12_CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

PRESC

Bits 18-21: ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VREFEN

Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VSENSESEL

Bit 23: Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VBATEN

Bit 24: VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

ADC12_CDR

ADC common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA_SLV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_MST r

Toggle fields

RDATA_MST

Bits 0-15: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF[1:0] = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]..

RDATA_SLV

Bits 16-31: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)).

ADC12_CDR2

ADC common regular data register for 32-bit dual mode

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA_ALT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_ALT r

Toggle fields

RDATA_ALT

Bits 0-31: Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)..

SEC_ADC4

0x56021000: ADC4

6/146 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ADC_ISR																				LDORDY	EOCAL		AWD3	AWD2	AWD1			OVR	EOS	EOC	EOSMP	ADRDY
0x4	ADC_IER																				LDORDYIE	EOCALIE		AWD3IE	AWD2IE	AWD1IE			OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	ADC_CR	ADCAL			ADVREGEN																								ADSTP		ADSTART	ADDIS	ADEN
0xc	ADC_CFGR1		AWD1CH							AWD1EN	AWD1SGL	CHSELRMOD					DISCEN		WAIT	CONT	OVRMOD	EXTEN			EXTSEL			ALIGN	SCANDIR	RES		DMACFG	DMAEN
0x10	ADC_CFGR2			LFTRIG																				TOVS	OVSS				OVSR				OVSE
0x14	ADC_SMPR	SMPSEL23	SMPSEL22	SMPSEL21	SMPSEL20	SMPSEL19	SMPSEL18	SMPSEL17	SMPSEL16	SMPSEL15	SMPSEL14	SMPSEL13	SMPSEL12	SMPSEL11	SMPSEL10	SMPSEL9	SMPSEL8	SMPSEL7	SMPSEL6	SMPSEL5	SMPSEL4	SMPSEL3	SMPSEL2	SMPSEL1	SMPSEL0		SMP2				SMP1
0x20	ADC_AWD1TR					HT1																LT1
0x24	ADC_AWD2TR					HT2																LT2
0x28	ADC_CHSELRMOD0									CHSEL								CHSEL
0x28	ADC_CHSELRMOD1	SQ8				SQ7				SQ6				SQ5				SQ4				SQ3				SQ2				SQ1
0x2c	ADC_AWD3TR					HT3																LT3
0x40	ADC_DR																	DATA
0x44	ADC_PWR																													VREFSECSMP	VREFPROT	DPD	AUTOFF
0xa0	ADC_AWD2CR									AWD2CH23	AWD2CH22	AWD2CH21	AWD2CH20	AWD2CH19	AWD2CH18	AWD2CH17	AWD2CH16	AWD2CH15	AWD2CH14	AWD2CH13	AWD2CH12	AWD2CH11	AWD2CH10	AWD2CH9	AWD2CH8	AWD2CH7	AWD2CH6	AWD2CH5	AWD2CH4	AWD2CH3	AWD2CH2	AWD2CH1	AWD2CH0
0xa4	ADC_AWD3CR									AWD3CH23	AWD3CH22	AWD3CH21	AWD3CH20	AWD3CH19	AWD3CH18	AWD3CH17	AWD3CH16	AWD3CH15	AWD3CH14	AWD3CH13	AWD3CH12	AWD3CH11	AWD3CH10	AWD3CH9	AWD3CH8	AWD3CH7	AWD3CH6	AWD3CH5	AWD3CH4	AWD3CH3	AWD3CH2	AWD3CH1	AWD3CH0
0xb4	ADC_CALFACT																										CALFACT
0xd0	ADC_OR																																CHN21SEL
0x308	ADC_CCR								VBATEN	TSEN	VREFEN	PRESC

Toggle registers

ADC_ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDY rw	EOCAL rw		AWD3 rw	AWD2 rw	AWD1 rw			OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

EOCAL

Bit 11: EOCAL.

LDORDY

Bit 12: LDORDY.

ADC_IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LDORDYIE rw	EOCALIE rw		AWD3IE rw	AWD2IE rw	AWD1IE rw			OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

EOCALIE

Bit 11: EOCALIE.

LDORDYIE

Bit 12: LDORDYIE.

ADC_CR

ADC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL r			ADVREGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ADSTP r		ADSTART r	ADDIS r	ADEN r

Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

ADSTP

Bit 4: ADSTP.

ADVREGEN

Bit 28: ADVREGEN.

ADCAL

Bit 31: ADCAL.

ADC_CFGR1

ADC configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	AWD1CH rw							AWD1EN rw	AWD1SGL rw	CHSELRMOD rw					DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WAIT rw	CONT rw	OVRMOD rw	EXTEN rw			EXTSEL rw			ALIGN rw	SCANDIR rw	RES rw		DMACFG rw	DMAEN rw

Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 2-3: RES.

SCANDIR

Bit 4: SCANDIR.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-8: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

WAIT

Bit 14: WAIT.

DISCEN

Bit 16: DISCEN.

CHSELRMOD

Bit 21: CHSELRMOD.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

AWD1CH

Bits 26-30: AWD1CH.

ADC_CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		LFTRIG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TOVS rw	OVSS rw				OVSR rw				OVSE rw

Toggle fields

OVSE

Bit 0: OVSE.

OVSR

Bits 2-4: OVSR.

OVSS

Bits 5-8: OVSS.

TOVS

Bit 9: TOVS.

LFTRIG

Bit 29: LFTRIG.

ADC_SMPR

ADC sample time register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SMPSEL23 rw	SMPSEL22 rw	SMPSEL21 rw	SMPSEL20 rw	SMPSEL19 rw	SMPSEL18 rw	SMPSEL17 rw	SMPSEL16 rw	SMPSEL15 rw	SMPSEL14 rw	SMPSEL13 rw	SMPSEL12 rw	SMPSEL11 rw	SMPSEL10 rw	SMPSEL9 rw	SMPSEL8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPSEL7 rw	SMPSEL6 rw	SMPSEL5 rw	SMPSEL4 rw	SMPSEL3 rw	SMPSEL2 rw	SMPSEL1 rw	SMPSEL0 rw		SMP2 rw				SMP1 rw

Toggle fields

SMP1

Bits 0-2: SMP1.

SMP2

Bits 4-6: SMP2.

SMPSEL0

Bit 8: SMPSEL0.

SMPSEL1

Bit 9: SMPSEL1.

SMPSEL2

Bit 10: SMPSEL2.

SMPSEL3

Bit 11: SMPSEL3.

SMPSEL4

Bit 12: SMPSEL4.

SMPSEL5

Bit 13: SMPSEL5.

SMPSEL6

Bit 14: SMPSEL6.

SMPSEL7

Bit 15: SMPSEL7.

SMPSEL8

Bit 16: SMPSEL8.

SMPSEL9

Bit 17: SMPSEL9.

SMPSEL10

Bit 18: SMPSEL10.

SMPSEL11

Bit 19: SMPSEL11.

SMPSEL12

Bit 20: SMPSEL12.

SMPSEL13

Bit 21: SMPSEL13.

SMPSEL14

Bit 22: SMPSEL14.

SMPSEL15

Bit 23: SMPSEL15.

SMPSEL16

Bit 24: SMPSEL16.

SMPSEL17

Bit 25: SMPSEL17.

SMPSEL18

Bit 26: SMPSEL18.

SMPSEL19

Bit 27: SMPSEL19.

SMPSEL20

Bit 28: SMPSEL20.

SMPSEL21

Bit 29: SMPSEL21.

SMPSEL22

Bit 30: SMPSEL22.

SMPSEL23

Bit 31: SMPSEL23.

ADC_AWD1TR

ADC watchdog threshold register

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT1 rw

Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

ADC_AWD2TR

ADC watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT2 rw

Toggle fields

LT2

Bits 0-11: LT2.

HT2

Bits 16-27: HT2.

ADC_CHSELRMOD0

ADC channel selection register [alternate]

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CHSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CHSEL rw

Toggle fields

CHSEL

Bits 0-23: CHSEL.

ADC_CHSELRMOD1

ADC channel selection register [alternate]

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SQ8 rw				SQ7 rw				SQ6 rw				SQ5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4 rw				SQ3 rw				SQ2 rw				SQ1 rw

Toggle fields

SQ1

Bits 0-3: SQ1.

SQ2

Bits 4-7: SQ2.

SQ3

Bits 8-11: SQ3.

SQ4

Bits 12-15: SQ4.

SQ5

Bits 16-19: SQ5.

SQ6

Bits 20-23: SQ6.

SQ7

Bits 24-27: SQ7.

SQ8

Bits 28-31: SQ8.

ADC_AWD3TR

ADC watchdog threshold register

Offset: 0x2c, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT3 rw

Toggle fields

LT3

Bits 0-11: LT3.

HT3

Bits 16-27: HT3.

ADC_DR

ADC data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA r

Toggle fields

DATA

Bits 0-15: DATA.

ADC_PWR

ADC data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VREFSECSMP rw	VREFPROT rw	DPD rw	AUTOFF rw

Toggle fields

AUTOFF

Bit 0: AUTOFF.

DPD

Bit 1: DPD.

VREFPROT

Bit 2: VREFPROT.

VREFSECSMP

Bit 3: VREFSECSMP.

ADC_AWD2CR

ADC Analog Watchdog 2 Configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								AWD2CH23 rw	AWD2CH22 rw	AWD2CH21 rw	AWD2CH20 rw	AWD2CH19 rw	AWD2CH18 rw	AWD2CH17 rw	AWD2CH16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH15 rw	AWD2CH14 rw	AWD2CH13 rw	AWD2CH12 rw	AWD2CH11 rw	AWD2CH10 rw	AWD2CH9 rw	AWD2CH8 rw	AWD2CH7 rw	AWD2CH6 rw	AWD2CH5 rw	AWD2CH4 rw	AWD2CH3 rw	AWD2CH2 rw	AWD2CH1 rw	AWD2CH0 rw

Toggle fields

AWD2CH0

Bit 0: AWD2CH0.

AWD2CH1

Bit 1: AWD2CH1.

AWD2CH2

Bit 2: AWD2CH2.

AWD2CH3

Bit 3: AWD2CH3.

AWD2CH4

Bit 4: AWD2CH4.

AWD2CH5

Bit 5: AWD2CH5.

AWD2CH6

Bit 6: AWD2CH6.

AWD2CH7

Bit 7: AWD2CH7.

AWD2CH8

Bit 8: AWD2CH8.

AWD2CH9

Bit 9: AWD2CH9.

AWD2CH10

Bit 10: AWD2CH10.

AWD2CH11

Bit 11: AWD2CH11.

AWD2CH12

Bit 12: AWD2CH12.

AWD2CH13

Bit 13: AWD2CH13.

AWD2CH14

Bit 14: AWD2CH14.

AWD2CH15

Bit 15: AWD2CH15.

AWD2CH16

Bit 16: AWD2CH16.

AWD2CH17

Bit 17: AWD2CH17.

AWD2CH18

Bit 18: AWD2CH18.

AWD2CH19

Bit 19: AWD2CH19.

AWD2CH20

Bit 20: AWD2CH20.

AWD2CH21

Bit 21: AWD2CH21.

AWD2CH22

Bit 22: AWD2CH22.

AWD2CH23

Bit 23: AWD2CH23.

ADC_AWD3CR

ADC Analog Watchdog 3 Configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								AWD3CH23 rw	AWD3CH22 rw	AWD3CH21 rw	AWD3CH20 rw	AWD3CH19 rw	AWD3CH18 rw	AWD3CH17 rw	AWD3CH16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH15 rw	AWD3CH14 rw	AWD3CH13 rw	AWD3CH12 rw	AWD3CH11 rw	AWD3CH10 rw	AWD3CH9 rw	AWD3CH8 rw	AWD3CH7 rw	AWD3CH6 rw	AWD3CH5 rw	AWD3CH4 rw	AWD3CH3 rw	AWD3CH2 rw	AWD3CH1 rw	AWD3CH0 rw

Toggle fields

AWD3CH0

Bit 0: AWD3CH0.

AWD3CH1

Bit 1: AWD3CH1.

AWD3CH2

Bit 2: AWD3CH2.

AWD3CH3

Bit 3: AWD3CH3.

AWD3CH4

Bit 4: AWD3CH4.

AWD3CH5

Bit 5: AWD3CH5.

AWD3CH6

Bit 6: AWD3CH6.

AWD3CH7

Bit 7: AWD3CH7.

AWD3CH8

Bit 8: AWD3CH8.

AWD3CH9

Bit 9: AWD3CH9.

AWD3CH10

Bit 10: AWD3CH10.

AWD3CH11

Bit 11: AWD3CH11.

AWD3CH12

Bit 12: AWD3CH12.

AWD3CH13

Bit 13: AWD3CH13.

AWD3CH14

Bit 14: AWD3CH14.

AWD3CH15

Bit 15: AWD3CH15.

AWD3CH16

Bit 16: AWD3CH16.

AWD3CH17

Bit 17: AWD3CH17.

AWD3CH18

Bit 18: AWD3CH18.

AWD3CH19

Bit 19: AWD3CH19.

AWD3CH20

Bit 20: AWD3CH20.

AWD3CH21

Bit 21: AWD3CH21.

AWD3CH22

Bit 22: AWD3CH22.

AWD3CH23

Bit 23: AWD3CH23.

ADC_CALFACT

ADC Calibration factor

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CALFACT rw

Toggle fields

CALFACT

Bits 0-6: CALFACT.

ADC_OR

ADC option register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															CHN21SEL rw

Toggle fields

CHN21SEL

Bit 0: CHN21SEL.

ADC_CCR

ADC common configuration register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							VBATEN rw	TSEN rw	VREFEN rw	PRESC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRESC

Bits 18-21: PRESC.

VREFEN

Bit 22: VREFEN.

TSEN

Bit 23: TSEN.

VBATEN

Bit 24: VBATEN.

SEC_ADF1

0x56024000: ADF1

7/68 fields covered.

Toggle register map

Offset	Name	31	30	28	27	25	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ADF_GCR																							TRGO
0x4	ADF_CKGCR	CKGACTIVE	PROCDIV				CCKDIV		TRGSRC							TRGSENS		CCK1DIR	CCK0DIR	CKGMOD		CCK1EN	CCK0EN	CKGDEN
0x80	ADF_SITF0CR	SITFACTIVE										STH							SITFMOD			SCKSRC		SITFEN
0x84	ADF_BSMX0CR	BSMXACTIVE																		BSSEL
0x88	ADF_DFLT0CR	DFLTACTIVE	DFLTRUN		NBDIS				TRGSRC									ACQMOD				FTH	DMAEN	DFLTEN
0x8c	ADF_DFLT0CICR					SCALE		MCICD	MCICD									CICMOD					DATSRC
0x90	ADF_DFLT0RSFR														HPFC		HPFBYP			RSFLTD				RSFLTBYP
0xa4	ADF_DLY0CR	SKPBF																SKPDLY
0xac	ADF_DFLT0IER										SDLVLIE	SDDETIE	RFOVRIE	CKABIE	SATIE								DOVRIE	FTHIE
0xb0	ADF_DFLT0ISR										SDLVLF	SDDETF	RFOVRF	CKABF	SATF						RXNEF		DOVRF	FTHF
0xb8	ADF_SADCR	SADACTIVE									SADMOD			FRSIZE			HYSTEN		SADST		DETCFG	DATCAP		SADEN
0xbc	ADF_SADCFGR			ANMIN						HGOVR				LFRNB				ANSLP			SNTHR
0xc0	ADF_SADSDLVR									SDLVL
0xc4	ADF_SADANLVR									ANLVL
0xf0	ADF_DFLT0DR	DR							DR

Toggle registers

ADF_GCR

ADF Global Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TRGO rw

Toggle fields

TRGO

Bit 0: Trigger output control Set by software and reset by.

ADF_CKGCR

ADF clock generator control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKGACTIVE rw	PROCDIV rw											CCKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		CCK1DIR rw	CCK0DIR rw	CKGMOD rw		CCK1EN rw	CCK0EN rw	CKGDEN rw

Toggle fields

CKGDEN

Bit 0: CKGEN dividers enable.

CCK0EN

Bit 1: ADF_CCK0 clock enable.

CCK1EN

Bit 2: ADF_CCK1 clock enable.

CKGMOD

Bit 4: Clock generator mode.

CCK0DIR

Bit 5: ADF_CCK0 direction.

CCK1DIR

Bit 6: ADF_CCK1 direction.

TRGSENS

Bit 8: CKGEN trigger sensitivity selection.

TRGSRC

Bits 12-15: Digital filter trigger signal selection.

CCKDIV

Bits 16-19: Divider to control the ADF_CCK clock.

PROCDIV

Bits 24-30: Divider to control the serial interface clock.

CKGACTIVE

Bit 31: Clock generator active flag.

ADF_SITF0CR

ADF serial interface control register 0

Offset: 0x80, size: 32, reset: 0x00001F00, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: SITFEN.

SCKSRC

Bits 1-2: SCKSRC.

SITFMOD

Bits 4-5: SITFMOD.

STH

Bits 8-12: STH.

SITFACTIVE

Bit 31: SITFACTIVE.

ADF_BSMX0CR

ADF bitstream matrix control register 0

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream selection.

BSMXACTIVE

Bit 31: BSMX active flag.

ADF_DFLT0CR

ADF digital filter control register 0

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE rw	DFLTRUN rw			NBDIS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw									ACQMOD rw				FTH rw	DMAEN rw	DFLTEN rw

Toggle fields

DFLTEN

Bit 0: DFLT0 enable.

DMAEN

Bit 1: DMA requests enable.

FTH

Bit 2: RXFIFO threshold selection.

ACQMOD

Bits 4-6: DFLT0 trigger mode.

TRGSRC

Bits 12-15: DFLT0 trigger signal selection.

NBDIS

Bits 20-27: Number of samples to be discarded.

DFLTRUN

Bit 30: DFLT0 run status flag.

DFLTACTIVE

Bit 31: DFLT0 active flag.

ADF_DFLT0CICR

ADF digital filer configuration register 0

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter.

CICMOD

Bits 4-6: Select the CIC order.

MCICD

Bits 8-16: CIC decimation ratio selection.

SCALE

Bits 20-25: Scaling factor selection.

ADF_DFLT0RSFR

ADF reshape filter configuration register 0

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass.

RSFLTD

Bit 4: Reshaper filter decimation ratio.

HPFBYP

Bit 7: High-pass filter bypass.

HPFC

Bits 8-9: High-pass filter cut-off frequency.

ADF_DLY0CR

ADF delay control register 0

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream.

SKPBF

Bit 31: Skip busy flag.

ADF_DFLT0IER

ADF DFLT0 interrupt enable register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SDLVLIE rw	SDDETIE rw	RFOVRIE rw	CKABIE rw	SATIE rw								DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable.

DOVRIE

Bit 1: Data overflow interrupt enable.

SATIE

Bit 9: Saturation detection interrupt enable.

CKABIE

Bit 10: Clock absence detection interrupt enable.

RFOVRIE

Bit 11: Reshape filter overrun interrupt enable.

SDDETIE

Bit 12: Sound activity detection interrupt enable.

SDLVLIE

Bit 13: SAD sound-level value ready enable.

ADF_DFLT0ISR

ADF DFLT0 interrupt status register 0

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SDLVLF rw	SDDETF rw	RFOVRF rw	CKABF rw	SATF rw						RXNEF r		DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag.

DOVRF

Bit 1: Data overflow flag.

RXNEF

Bit 3: RXFIFO not empty flag.

SATF

Bit 9: Saturation detection flag.

CKABF

Bit 10: Clock absence detection flag.

RFOVRF

Bit 11: Reshape filter overrun detection flag.

SDDETF

Bit 12: Sound activity detection flag.

SDLVLF

Bit 13: Sound level value ready flag.

ADF_SADCR

ADF SAD control register

Offset: 0xb8, size: 32, reset: 0x00000000, access: Unspecified

2/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SADACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SADMOD rw			FRSIZE rw			HYSTEN rw		SADST r		DETCFG rw	DATCAP rw		SADEN rw

Toggle fields

SADEN

Bit 0: Sound activity detector enable.

DATCAP

Bits 1-2: Data capture mode.

DETCFG

Bit 3: Sound trigger event configuration.

SADST

Bits 4-5: SAD state.

HYSTEN

Bit 7: Hysteresis enable.

FRSIZE

Bits 8-10: Frame size.

SADMOD

Bits 12-13: SAD working mode.

SADACTIVE

Bit 31: SAD Active flag.

ADF_SADCFGR

ADF SAD configuration register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ANMIN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	HGOVR rw				LFRNB rw				ANSLP rw			SNTHR rw

Toggle fields

SNTHR

Bits 0-3: SNTHR.

ANSLP

Bits 4-6: ANSLP.

LFRNB

Bits 8-10: LFRNB.

HGOVR

Bits 12-14: Hangover time window.

ANMIN

Bits 16-28: ANMIN.

ADF_SADSDLVR

ADF SAD sound level register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SDLVL r

Toggle fields

SDLVL

Bits 0-14: SDLVL.

ADF_SADANLVR

ADF SAD ambient noise level register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	ANLVL r

Toggle fields

ANLVL

Bits 0-14: ANLVL.

ADF_DFLT0DR

ADF digital filter data register 0

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: DR.

SEC_COMP

0x56005400: Comparator

2/22 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	COMP1_CSR	COMP1_LOCK	COMP1_VALUE						COMP1_BLANKSEL					COMP1_PWRMODE		COMP1_HYST		COMP1_POLARITY	COMP1_WINOUT			COMP1_WINMODE		COMP1_INPSEL		COMP1_INMSEL							COMP1_EN
0x4	COMP2_CSR	COM2_LOCK	COM2_VALUE						COM2_BLANKSEL					COM2_PWRMODE		COM2_HYST		COM2_POLARITY	COM2_WINOUT			COM2_WINMODE		COM2_INPSEL		COM2_INMSEL							COM2_EN

Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP1_LOCK rw	COMP1_VALUE r						COMP1_BLANKSEL rw					COMP1_PWRMODE rw		COMP1_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP1_POLARITY rw	COMP1_WINOUT rw			COMP1_WINMODE rw		COMP1_INPSEL rw		COMP1_INMSEL rw							COMP1_EN rw

Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_INMSEL

Bits 4-7: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bits 8-9: Comparator1 input plus selection bit.

COMP1_WINMODE

Bit 11: COMP1_WINMODE.

COMP1_WINOUT

Bit 14: COMP1_WINOUT.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_PWRMODE

Bits 18-19: COMP1_PWRMODE.

COMP1_BLANKSEL

Bits 20-24: COMP1_BLANKSEL.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COM2_LOCK rw	COM2_VALUE r						COM2_BLANKSEL rw					COM2_PWRMODE rw		COM2_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COM2_POLARITY rw	COM2_WINOUT rw			COM2_WINMODE rw		COM2_INPSEL rw		COM2_INMSEL rw							COM2_EN rw

Toggle fields

COM2_EN

Bit 0: Comparator 2 enable bit.

COM2_INMSEL

Bits 4-7: Comparator 2 Input Minus connection configuration bit.

COM2_INPSEL

Bits 8-9: Comparator 2 input plus selection bit.

COM2_WINMODE

Bit 11: COM2_WINMODE.

COM2_WINOUT

Bit 14: COM2_WINOUT.

COM2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COM2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COM2_PWRMODE

Bits 18-19: COM2_PWRMODE.

COM2_BLANKSEL

Bits 20-24: COM2_BLANKSEL.

COM2_VALUE

Bit 30: Comparator 2 output status bit.

COM2_LOCK

Bit 31: COMP2_CSR register lock bit.

SEC_CORDIC

0x50021000: CORDIC Co-processor

2/13 fields covered.

Toggle register map

Offset	Name	31	22	21	20	19	18	17	16	15	10	7	3
0x0	CSR	RRDY	ARGSIZE	RESSIZE	NARGS	NRES	DMAWEN	DMAREN	IEN		SCALE	PRECISION	FUNC
0x4	WDATA	ARG								ARG
0x8	RDATA	RES								RES

Toggle registers

CSR

CORDIC Control Status register

Offset: 0x0, size: 32, reset: 0x00000050, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RRDY r									ARGSIZE rw	RESSIZE rw	NARGS rw	NRES rw	DMAWEN rw	DMAREN rw	IEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SCALE rw			PRECISION rw				FUNC rw

Toggle fields

FUNC

Bits 0-3: Function.

PRECISION

Bits 4-7: Precision required (number of iterations).

SCALE

Bits 8-10: Scaling factor.

IEN

Bit 16: Enable interrupt.

DMAREN

Bit 17: Enable DMA read channel.

DMAWEN

Bit 18: Enable DMA write channel.

NRES

Bit 19: Number of results in the CORDIC_RDATA register.

NARGS

Bit 20: Number of arguments expected by the CORDIC_WDATA register.

RESSIZE

Bit 21: Width of output data.

ARGSIZE

Bit 22: Width of input data.

RRDY

Bit 31: Result ready flag.

WDATA

FMAC Write Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARG w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARG w

Toggle fields

ARG

Bits 0-31: Function input arguments.

RDATA

FMAC Read Data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES r

Toggle fields

RES

Bits 0-31: Function result.

SEC_CRC

0x50023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	CRC_INIT	CRC_INIT
0x14	POL	POL	POL

Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle fields

IDR

Bits 0-31: General-purpose 8-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT rw

Toggle fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle fields

POL

Bits 0-31: Programmable polynomial.

SEC_CRS

0x50006000: Clock recovery system

9/26 fields covered.

Toggle register map

Offset	Name	31	29	26	23	15	14	10	9	8	7	6	5	3	2	1	0
0x0	CR						TRIM				SWSYNC	AUTOTRIMEN	CEN	ESYNCIE	ERRIE	SYNCWARNIE	SYNCOKIE
0x4	CFGR	SYNCPOL	SYNCSRC	SYNCDIV	FELIM	RELOAD
0x8	ISR	FECAP				FEDIR		TRIMOVF	SYNCMISS	SYNCERR				ESYNCF	ERRF	SYNCWARNF	SYNCOKF
0xc	ICR													ESYNCC	ERRC	SYNCWARNC	SYNCOKC

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00004000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TRIM rw							SWSYNC rw	AUTOTRIMEN rw	CEN rw		ESYNCIE rw	ERRIE rw	SYNCWARNIE rw	SYNCOKIE rw

Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-14: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SYNCPOL rw		SYNCSRC rw			SYNCDIV rw			FELIM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FECAP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FEDIR r					TRIMOVF r	SYNCMISS r	SYNCERR r					ESYNCF r	ERRF r	SYNCWARNF r	SYNCOKF r

Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ESYNCC rw	ERRC rw	SYNCWARNC rw	SYNCOKC rw

Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

SEC_DAC1

0x56021800: Digital-to-analog converter

12/66 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	25	24	23	22	21	20	18	17	16	15	14	13	12	11	9	8	7	5	4	2	1	0
0x0	DAC_CR		CEN2	DMAUDRIE2	DMAEN2	MAMP2			WAVE2		TSEL2			TEN2	EN2		CEN1	DMAUDRIE1	DMAEN1	MAMP1			WAVE1	TSEL1			TEN1	EN1
0x4	DAC_SWTRGR																										SWTRIG2	SWTRIG1
0x8	DAC_DHR12R1					DACC1DHRB														DACC1DHR
0xc	DAC_DHR12L1	DACC1DHRB														DACC1DHR
0x10	DAC_DHR8R1															DACC1DHRB							DACC1DHR
0x14	DAC_DHR12R2					DACC2DHRB														DACC2DHR
0x18	DAC_DHR12L2	DACC2DHRB														DACC2DHR
0x1c	DAC_DHR8R2															DACC2DHRB							DACC2DHR
0x20	DAC_DHR12RD					DACC2DHR														DACC1DHR
0x24	DAC_DHR12LD	DACC2DHR														DACC1DHR
0x28	DAC_DHR8RD															DACC2DHR							DACC1DHR
0x2c	DAC_DOR1					DACC1DORB														DACC1DOR
0x30	DAC_DOR2					DACC2DORB														DACC2DOR
0x34	DAC_SR	BWST2	CAL_FLAG2	DMAUDR2	DORSTAT2	DAC2RDY										BWST1	CAL_FLAG1	DMAUDR1	DORSTAT1	DAC1RDY
0x38	DAC_CCR											OTRIM2													OTRIM1
0x3c	DAC_MCR						SINFORMAT2	DMADOUBLE2					MODE2			HFSEL					SINFORMAT1	DMADOUBLE1				MODE1
0x40	DAC_SHSR1																				TSAMPLE1
0x44	DAC_SHSR2																				TSAMPLE2
0x48	DAC_SHHR						THOLD2														THOLD1
0x4c	DAC_SHRR								TREFRESH2														TREFRESH1
0x54	DAC_AUTOCR									AUTOMODE

Toggle registers

DAC_CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CEN2 rw	DMAUDRIE2 rw	DMAEN2 rw	MAMP2 rw				WAVE2 rw		TSEL2 rw				TEN2 rw	EN2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CEN1 rw	DMAUDRIE1 rw	DMAEN1 rw	MAMP1 rw				WAVE1 rw		TSEL1 rw				TEN1 rw	EN1 rw

Toggle fields

EN1

Bit 0: DAC channel1 enable.

TEN1

Bit 1: DAC channel1 trigger enable.

TSEL1

Bits 2-5: DAC channel1 trigger selection.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

CEN1

Bit 14: DAC channel1 calibration enable.

EN2

Bit 16: DAC channel2 enable.

TEN2

Bit 17: DAC channel2 trigger enable.

TSEL2

Bits 18-21: DAC channel2 trigger selection.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

DMAEN2

Bit 28: DAC channel2 DMA enable.

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

CEN2

Bit 30: DAC channel2 calibration enable.

DAC_SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SWTRIG2 w	SWTRIG1 w

Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

SWTRIG2

Bit 1: DAC channel2 software trigger.

DAC_DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC1DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC1DHRB

Bits 16-27: DAC channel1 12-bit right-aligned data B.

DAC_DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC1DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC1DHRB

Bits 20-31: DAC channel1 12-bit left-aligned data B.

DAC_DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHRB rw								DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC1DHRB

Bits 8-15: DAC channel1 8-bit right-aligned Sdata.

DAC_DHR12R2

DAC channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DHR rw

Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

DACC2DHRB

Bits 16-27: DAC channel2 12-bit right-aligned data.

DAC_DHR12L2

DAC channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC2DHRB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw

Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

DACC2DHRB

Bits 20-31: DAC channel2 12-bit left-aligned data B.

DAC_DHR8R2

DAC channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHRB rw								DACC2DHR rw

Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

DACC2DHRB

Bits 8-15: DAC channel2 8-bit right-aligned data.

DAC_DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

DAC_DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

DAC_DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw								DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

DAC_DOR1

DAC channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC1DORB r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DOR r

Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DACC1DORB

Bits 16-27: DAC channel1 data output.

DAC_DOR2

DAC channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DORB r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DOR r

Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

DACC2DORB

Bits 16-27: DAC channel2 data output.

DAC_SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

8/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BWST2 r	CAL_FLAG2 r	DMAUDR2 rw	DORSTAT2 r	DAC2RDY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BWST1 r	CAL_FLAG1 r	DMAUDR1 rw	DORSTAT1 r	DAC1RDY r

Toggle fields

DAC1RDY

Bit 11: DAC channel1 ready status bit.

DORSTAT1

Bit 12: DAC channel1 output register status bit.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag.

DAC2RDY

Bit 27: DAC channel 2 ready status bit.

DORSTAT2

Bit 28: DAC channel 2 output register status bit.

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag.

DAC_CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											OTRIM2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											OTRIM1 rw

Toggle fields

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

DAC_MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SINFORMAT2 rw	DMADOUBLE2 rw						MODE2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HFSEL rw						SINFORMAT1 rw	DMADOUBLE1 rw						MODE1 rw

Toggle fields

MODE1

Bits 0-2: DAC Channel 1 mode.

DMADOUBLE1

Bit 8: DAC Channel1 DMA double data mode.

SINFORMAT1

Bit 9: Enable signed format for DAC channel1.

HFSEL

Bits 14-15: High frequency interface mode selection.

MODE2

Bits 16-18: DAC Channel 2 mode.

DMADOUBLE2

Bit 24: DAC Channel2 DMA double data mode.

SINFORMAT2

Bit 25: Enable signed format for DAC channel2.

DAC_SHSR1

DAC Sample and Hold sample time register 1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TSAMPLE1 rw

Toggle fields

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode).

DAC_SHSR2

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TSAMPLE2 rw

Toggle fields

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time (only valid in sample and hold mode).

DAC_SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						THOLD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						THOLD1 rw

Toggle fields

THOLD1

Bits 0-9: DAC Channel 1 hold Time (only valid in sample and hold mode).

THOLD2

Bits 16-25: DAC Channel 2 hold time (only valid in sample and hold mode).

DAC_SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TREFRESH2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TREFRESH1 rw

Toggle fields

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time (only valid in sample and hold mode).

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time (only valid in sample and hold mode).

DAC_AUTOCR

Autonomous mode control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									AUTOMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

AUTOMODE

Bit 22: DAC Autonomous mode.

SEC_DCACHE

0x50031400: DCACHE

9/30 fields covered.

Toggle register map

Offset	Name	31	23	22	21	20	19	18	17	16	15	11	10	4	3	2	1	0
0x0	DCACHE_CR	HBURST	WMISSMRST	WHITMRST	WMISSMEN	WHITMEN	RMISSMRST	RHITMRST	RMISSMEN	RHITMEN		STARTCMD	CACHECMD				CACHEINV	EN
0x4	DCACHE_SR													CMDENDF	BUSYCMDF	ERRF	BSYENDF	BUSYF
0x8	DCACHE_IER													CMDENDIE		ERRIE	BSYENDIE
0xc	DCACHE_FCR													CCMDENDF		CERRF	CBSYENDF
0x10	DCACHE_RHMONR	RHITMON									RHITMON
0x14	DCACHE_RMMONR										MRISSMON
0x20	DCACHE_WHMONR	WHITMON									WHITMON
0x24	DCACHE_WMMONR										WMISSMON
0x28	DCACHE_CMDRSADDRR	CMDSTARTADDR									CMDSTARTADDR
0x2c	DCACHE_CMDREADDRR	CMDENDADDR									CMDENDADDR

Toggle registers

DCACHE_CR

DCACHE control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw								WMISSMRST rw	WHITMRST rw	WMISSMEN rw	WHITMEN rw	RMISSMRST rw	RHITMRST rw	RMISSMEN rw	RHITMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				STARTCMD w	CACHECMD rw									CACHEINV w	EN rw

Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

CACHECMD

Bits 8-10: CACHECMD.

STARTCMD

Bit 11: STARTCMD.

RHITMEN

Bit 16: RHITMEN.

RMISSMEN

Bit 17: RMISSMEN.

RHITMRST

Bit 18: RHITMRST.

RMISSMRST

Bit 19: RMISSMRST.

WHITMEN

Bit 20: WHITMEN.

WMISSMEN

Bit 21: WMISSMEN.

WHITMRST

Bit 22: WHITMRST.

WMISSMRST

Bit 23: WMISSMRST.

HBURST

Bit 31: HBURST.

DCACHE_SR

DCACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMDENDF r	BUSYCMDF r	ERRF r	BSYENDF r	BUSYF r

Toggle fields

BUSYF

Bit 0: BUSYF.

BSYENDF

Bit 1: BSYENDF.

ERRF

Bit 2: ERRF.

BUSYCMDF

Bit 3: BUSYCMDF.

CMDENDF

Bit 4: CMDENDF.

DCACHE_IER

DCACHE interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMDENDIE rw		ERRIE rw	BSYENDIE rw

Toggle fields

BSYENDIE

Bit 1: BSYENDIE.

ERRIE

Bit 2: ERRIE.

CMDENDIE

Bit 4: CMDENDIE.

DCACHE_FCR

DCACHE flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CCMDENDF w		CERRF w	CBSYENDF w

Toggle fields

CBSYENDF

Bit 1: CBSYENDF.

CERRF

Bit 2: CERRF.

CCMDENDF

Bit 4: CCMDENDF.

DCACHE_RHMONR

DCACHE read-hit monitor register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RHITMON r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RHITMON r

Toggle fields

RHITMON

Bits 0-31: RHITMON.

DCACHE_RMMONR

DCACHE read-miss monitor register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRISSMON r

Toggle fields

MRISSMON

Bits 0-15: RMISSMON.

DCACHE_WHMONR

write-hit monitor register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WHITMON r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WHITMON r

Toggle fields

WHITMON

Bits 0-31: WHITMON.

DCACHE_WMMONR

write-miss monitor register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WMISSMON r

Toggle fields

WMISSMON

Bits 0-15: WMISSMON.

DCACHE_CMDRSADDRR

command range start address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDSTARTADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDSTARTADDR rw

Toggle fields

CMDSTARTADDR

Bits 4-31: CMDSTARTADDR.

DCACHE_CMDREADDRR

command range start address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDENDADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDENDADDR rw

Toggle fields

CMDENDADDR

Bits 4-31: CMDENDADDR.

SEC_DCMI

0x5202c000: Digital camera interface

17/54 fields covered.

Toggle register map

Offset	Name	31	29	28	23	20	19	18	17	15	14	13	11	9	7	6	5	4	3	2	1	0
0x0	CR					OELS	LSM	OEBS	BSM		ENABLE		EDM	FCRC	VSPOL	HSPOL	PCKPOL	ESS	JPEG	CROP	CM	CAPTURE
0x4	SR																			FNE	VSYNC	HSYNC
0x8	RIS																	LINE_RIS	VSYNC_RIS	ERR_RIS	OVR_RIS	FRAME_RIS
0xc	IER																	LINE_IE	VSYNC_IE	ERR_IE	OVR_IE	FRAME_IE
0x10	MIS																	LINE_MIS	VSYNC_MIS	ERR_MIS	OVR_MIS	FRAME_MIS
0x14	ICR																	LINE_ISC	VSYNC_ISC	ERR_ISC	OVR_ISC	FRAME_ISC
0x18	ESCR	FEC			LEC					LSC					FSC
0x1c	ESUR	FEU			LEU					LSU					FSU
0x20	CWSTRT			VST								HOFFCNT
0x24	CWSIZE		VLINE									CAPCNT
0x28	DR	BYTE3			BYTE2					BYTE1					BYTE0

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											OELS rw	LSM rw	OEBS rw	BSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	ENABLE rw			EDM rw		FCRC rw		VSPOL rw	HSPOL rw	PCKPOL rw	ESS rw	JPEG rw	CROP rw	CM rw	CAPTURE rw

Toggle fields

CAPTURE

Bit 0: Capture enable.

CM

Bit 1: Capture mode.

CROP

Bit 2: Crop feature.

JPEG

Bit 3: JPEG format.

ESS

Bit 4: Embedded synchronization select.

PCKPOL

Bit 5: Pixel clock polarity.

HSPOL

Bit 6: Horizontal synchronization polarity.

VSPOL

Bit 7: Vertical synchronization polarity.

FCRC

Bits 8-9: Frame capture rate control.

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: DCMI enable.

BSM

Bits 16-17: Byte Select mode.

OEBS

Bit 18: Odd/Even Byte Select (Byte Select Start).

LSM

Bit 19: Line Select mode.

OELS

Bit 20: Odd/Even Line Select (Line Select Start).

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FNE r	VSYNC r	HSYNC r

Toggle fields

HSYNC

Bit 0: Horizontal synchronization.

VSYNC

Bit 1: Vertical synchronization.

FNE

Bit 2: FIFO not empty.

RIS

raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_RIS r	VSYNC_RIS r	ERR_RIS r	OVR_RIS r	FRAME_RIS r

Toggle fields

FRAME_RIS

Bit 0: Capture complete raw interrupt status.

OVR_RIS

Bit 1: Overrun raw interrupt status.

ERR_RIS

Bit 2: Synchronization error raw interrupt status.

VSYNC_RIS

Bit 3: DCMI_VSYNC raw interrupt status.

LINE_RIS

Bit 4: Line raw interrupt status.

IER

interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_IE rw	VSYNC_IE rw	ERR_IE rw	OVR_IE rw	FRAME_IE rw

Toggle fields

FRAME_IE

Bit 0: Capture complete interrupt enable.

OVR_IE

Bit 1: Overrun interrupt enable.

ERR_IE

Bit 2: Synchronization error interrupt enable.

VSYNC_IE

Bit 3: DCMI_VSYNC interrupt enable.

LINE_IE

Bit 4: Line interrupt enable.

MIS

masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_MIS r	VSYNC_MIS r	ERR_MIS r	OVR_MIS r	FRAME_MIS r

Toggle fields

FRAME_MIS

Bit 0: Capture complete masked interrupt status.

OVR_MIS

Bit 1: Overrun masked interrupt status.

ERR_MIS

Bit 2: Synchronization error masked interrupt status.

VSYNC_MIS

Bit 3: VSYNC masked interrupt status.

LINE_MIS

Bit 4: Line masked interrupt status.

ICR

interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LINE_ISC w	VSYNC_ISC w	ERR_ISC w	OVR_ISC w	FRAME_ISC w

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			VST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		HOFFCNT rw

Toggle fields

HOFFCNT

Bits 0-13: Horizontal offset count.

VST

Bits 16-28: Vertical start line count.

CWSIZE

crop window size

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		VLINE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CAPCNT rw

Toggle fields

CAPCNT

Bits 0-13: Capture count.

VLINE

Bits 16-29: Vertical line count.

DR

data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BYTE3 r								BYTE2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BYTE1 r								BYTE0 r

Toggle fields

BYTE0

Bits 0-7: Data byte 0.

BYTE1

Bits 8-15: Data byte 1.

BYTE2

Bits 16-23: Data byte 2.

BYTE3

Bits 24-31: Data byte 3.

SEC_DLYBOS

0x520cf000: The delay block (DLYB) is used to generate an output clock that is dephased from the input clock

2/6 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DLYB_CR																															SEN	DEN
0x4	DLYB_CFGR	LNGF				LNG													UNIT											SEL

Toggle registers

DLYB_CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SEN rw	DEN rw

Toggle fields

DEN

Bit 0: Operational amplifier Enable.

SEN

Bit 1: OPALPM.

DLYB_CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LNGF r				LNG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	UNIT rw											SEL rw

Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

SEC_DLYBSD

0x520c8400: The delay block (DLYB) is used to generate an output clock that is dephased from the input clock

2/6 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DLYB_CR																															SEN	DEN
0x4	DLYB_CFGR	LNGF				LNG													UNIT											SEL

Toggle registers

DLYB_CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SEN rw	DEN rw

Toggle fields

DEN

Bit 0: Operational amplifier Enable.

SEN

Bit 1: OPALPM.

DLYB_CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LNGF r				LNG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	UNIT rw											SEL rw

Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

SEC_EXTI

0x56022000: External interrupt/event controller

0/251 fields covered.

Toggle register map

Offset	Name	31	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	EXTI_RTSR1		RT25	RT24	RT23	RT22	RT21	RT20	RT19	RT18	RT17	RT16	RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
0x4	EXTI_FTSR1		FT25	FT24	FT23	FT22	FT21	FT20	FT19	FT18	FT17	FT16	FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
0x8	EXTI_SWIER1		SWI25	SWI24	SWI23	SWI22	SWI21	SWI20	SWI19	SWI18	SWI17	SWI16	SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
0xc	EXTI_RPR1		RPIF25	RPIF24	RPIF23	RPIF22	RPIF21	RPIF20	RPIF19	RPIF18	RPIF17	RPIF16	RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
0x10	EXTI_FPR1		FPIF25	FPIF24	FPIF23	FPIF22	FPIF21	FPIF20	FPIF19	FPIF18	FPIF17	FPIF16	FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
0x14	EXTI_SECCFGR1		SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x18	EXTI_PRIVCFGR1		PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x60	EXTI_EXTICR1	EXTI3			EXTI2								EXTI1								EXTI0
0x64	EXTI_EXTICR2	EXTI7			EXTI6								EXTI5								EXTI4
0x68	EXTI_EXTICR3	EXTI11			EXTI10								EXTI9								EXTI8
0x6c	EXTI_EXTICR4	EXTI15			EXTI14								EXTI13								EXTI12
0x70	EXTI_LOCKR																											LOCK
0x80	EXTI_IMR1		IM25	IM24	IM23	IM22	IM21	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x84	EXTI_EMR1		EM25	EM24	EM23	EM22	EM21	EM20	EM19	EM18	EM17	EM16	EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0

Toggle registers

EXTI_RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RT25 rw	RT24 rw	RT23 rw	RT22 rw	RT21 rw	RT20 rw	RT19 rw	RT18 rw	RT17 rw	RT16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15 rw	RT14 rw	RT13 rw	RT12 rw	RT11 rw	RT10 rw	RT9 rw	RT8 rw	RT7 rw	RT6 rw	RT5 rw	RT4 rw	RT3 rw	RT2 rw	RT1 rw	RT0 rw

Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT1

Bit 1: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT2

Bit 2: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT3

Bit 3: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT4

Bit 4: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT5

Bit 5: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT6

Bit 6: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT7

Bit 7: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT8

Bit 8: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT9

Bit 9: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT10

Bit 10: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT11

Bit 11: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT12

Bit 12: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT13

Bit 13: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT14

Bit 14: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT15

Bit 15: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT16

Bit 16: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT17

Bit 17: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT18

Bit 18: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT19

Bit 19: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT20

Bit 20: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT21

Bit 21: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT22

Bit 22: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT23

Bit 23: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT24

Bit 24: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

RT25

Bit 25: Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FT25 rw	FT24 rw	FT23 rw	FT22 rw	FT21 rw	FT20 rw	FT19 rw	FT18 rw	FT17 rw	FT16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15 rw	FT14 rw	FT13 rw	FT12 rw	FT11 rw	FT10 rw	FT9 rw	FT8 rw	FT7 rw	FT6 rw	FT5 rw	FT4 rw	FT3 rw	FT2 rw	FT1 rw	FT0 rw

Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT1

Bit 1: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT2

Bit 2: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT3

Bit 3: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT4

Bit 4: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT5

Bit 5: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT6

Bit 6: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT7

Bit 7: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT8

Bit 8: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT9

Bit 9: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT10

Bit 10: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT11

Bit 11: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT12

Bit 12: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT13

Bit 13: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT14

Bit 14: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT15

Bit 15: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT16

Bit 16: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT17

Bit 17: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT18

Bit 18: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT19

Bit 19: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT20

Bit 20: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT21

Bit 21: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT22

Bit 22: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT23

Bit 23: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT24

Bit 24: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FT25

Bit 25: Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SWI25 rw	SWI24 rw	SWI23 rw	SWI22 rw	SWI21 rw	SWI20 rw	SWI19 rw	SWI18 rw	SWI17 rw	SWI16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15 rw	SWI14 rw	SWI13 rw	SWI12 rw	SWI11 rw	SWI10 rw	SWI9 rw	SWI8 rw	SWI7 rw	SWI6 rw	SWI5 rw	SWI4 rw	SWI3 rw	SWI2 rw	SWI1 rw	SWI0 rw

Toggle fields

SWI0

Bit 0: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI1

Bit 1: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI2

Bit 2: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI3

Bit 3: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI4

Bit 4: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI5

Bit 5: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI6

Bit 6: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI7

Bit 7: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI8

Bit 8: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI9

Bit 9: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI10

Bit 10: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI11

Bit 11: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI12

Bit 12: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI13

Bit 13: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI14

Bit 14: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI15

Bit 15: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI16

Bit 16: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI17

Bit 17: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI18

Bit 18: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI19

Bit 19: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI20

Bit 20: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI21

Bit 21: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI22

Bit 22: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI23

Bit 23: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI24

Bit 24: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SWI25

Bit 25: Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_RPR1

EXTI rising edge pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RPIF25 rw	RPIF24 rw	RPIF23 rw	RPIF22 rw	RPIF21 rw	RPIF20 rw	RPIF19 rw	RPIF18 rw	RPIF17 rw	RPIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15 rw	RPIF14 rw	RPIF13 rw	RPIF12 rw	RPIF11 rw	RPIF10 rw	RPIF9 rw	RPIF8 rw	RPIF7 rw	RPIF6 rw	RPIF5 rw	RPIF4 rw	RPIF3 rw	RPIF2 rw	RPIF1 rw	RPIF0 rw

Toggle fields

RPIF0

Bit 0: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF1

Bit 1: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF2

Bit 2: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF3

Bit 3: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF4

Bit 4: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF5

Bit 5: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF6

Bit 6: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF7

Bit 7: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF8

Bit 8: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF9

Bit 9: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF10

Bit 10: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF11

Bit 11: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF12

Bit 12: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF13

Bit 13: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF14

Bit 14: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF15

Bit 15: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF16

Bit 16: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF17

Bit 17: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF18

Bit 18: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF19

Bit 19: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF20

Bit 20: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF21

Bit 21: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF22

Bit 22: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF23

Bit 23: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF24

Bit 24: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

RPIF25

Bit 25: configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value..

EXTI_FPR1

EXTI falling edge pending register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FPIF25 rw	FPIF24 rw	FPIF23 rw	FPIF22 rw	FPIF21 rw	FPIF20 rw	FPIF19 rw	FPIF18 rw	FPIF17 rw	FPIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15 rw	FPIF14 rw	FPIF13 rw	FPIF12 rw	FPIF11 rw	FPIF10 rw	FPIF9 rw	FPIF8 rw	FPIF7 rw	FPIF6 rw	FPIF5 rw	FPIF4 rw	FPIF3 rw	FPIF2 rw	FPIF1 rw	FPIF0 rw

Toggle fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF1

Bit 1: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF2

Bit 2: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF3

Bit 3: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF4

Bit 4: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF5

Bit 5: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF6

Bit 6: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF7

Bit 7: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF8

Bit 8: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF9

Bit 9: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF10

Bit 10: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF11

Bit 11: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF12

Bit 12: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF13

Bit 13: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF14

Bit 14: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF15

Bit 15: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF16

Bit 16: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF17

Bit 17: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF18

Bit 18: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF19

Bit 19: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF20

Bit 20: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF21

Bit 21: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF22

Bit 22: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF23

Bit 23: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF24

Bit 24: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

FPIF25

Bit 25: configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_SECCFGR1

EXTI security configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC1

Bit 1: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC2

Bit 2: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC3

Bit 3: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC4

Bit 4: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC5

Bit 5: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC6

Bit 6: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC7

Bit 7: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC8

Bit 8: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC9

Bit 9: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC10

Bit 10: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC11

Bit 11: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC12

Bit 12: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC13

Bit 13: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC14

Bit 14: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC15

Bit 15: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC16

Bit 16: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC17

Bit 17: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC18

Bit 18: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC19

Bit 19: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC20

Bit 20: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC21

Bit 21: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC22

Bit 22: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC23

Bit 23: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC24

Bit 24: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC25

Bit 25: Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_PRIVCFGR1

EXTI privilege configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV1

Bit 1: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV2

Bit 2: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV3

Bit 3: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV4

Bit 4: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV5

Bit 5: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV6

Bit 6: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV7

Bit 7: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV8

Bit 8: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV9

Bit 9: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV10

Bit 10: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV11

Bit 11: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV12

Bit 12: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV13

Bit 13: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV14

Bit 14: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV15

Bit 15: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV16

Bit 16: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV17

Bit 17: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV18

Bit 18: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV19

Bit 19: Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

PRIV20

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LOCK rw

Toggle fields

LOCK

Bit 0: Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset..

EXTI_IMR1

EXTI CPU wake-up with interrupt mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						IM25 rw	IM24 rw	IM23 rw	IM22 rw	IM21 rw	IM20 rw	IM19 rw	IM18 rw	IM17 rw	IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle fields

IM0

Bit 0: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM1

Bit 1: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM2

Bit 2: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM3

Bit 3: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM4

Bit 4: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM5

Bit 5: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM6

Bit 6: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM7

Bit 7: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM8

Bit 8: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM9

Bit 9: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM10

Bit 10: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM11

Bit 11: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM12

Bit 12: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM13

Bit 13: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM14

Bit 14: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM15

Bit 15: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM16

Bit 16: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM17

Bit 17: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM18

Bit 18: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM19

Bit 19: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM20

Bit 20: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM21

Bit 21: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM22

Bit 22: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM23

Bit 23: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM24

Bit 24: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

IM25

Bit 25: CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EXTI_EMR1

EXTI CPU wake-up with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						EM25 rw	EM24 rw	EM23 rw	EM22 rw	EM21 rw	EM20 rw	EM19 rw	EM18 rw	EM17 rw	EM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM15 rw	EM14 rw	EM13 rw	EM12 rw	EM11 rw	EM10 rw	EM9 rw	EM8 rw	EM7 rw	EM6 rw	EM5 rw	EM4 rw	EM3 rw	EM2 rw	EM1 rw	EM0 rw

Toggle fields

EM0

Bit 0: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM1

Bit 1: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM2

Bit 2: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM3

Bit 3: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM4

Bit 4: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM5

Bit 5: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM6

Bit 6: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM7

Bit 7: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM8

Bit 8: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM9

Bit 9: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM10

Bit 10: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM11

Bit 11: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM12

Bit 12: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM13

Bit 13: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM14

Bit 14: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM15

Bit 15: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM16

Bit 16: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM17

Bit 17: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM18

Bit 18: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM19

Bit 19: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM20

Bit 20: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM21

Bit 21: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM22

Bit 22: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM23

Bit 23: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM24

Bit 24: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

EM25

Bit 25: CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value..

SEC_FDCAN1

0x5000a400: FDCAN1_RAM

43/160 fields covered.

Toggle register map

Offset	Name	31	28	27	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	FDCAN_CREL	REL		STEP			SUBSTEP				YEAR				MON								DAY
0x4	FDCAN_ENDN	ETV													ETV
0xc	FDCAN_DBTP						TDC			DBRP								DTSEG1					DTSEG2				DSJW
0x10	FDCAN_TEST																						RX	TX		LBCK
0x14	FDCAN_RWD														WDV								WDC
0x18	FDCAN_CCCR														NISO	TXP	EFBI	PXHD			BRSE	FDOE	TEST	DAR	MON	CSR	CSA	ASM	CCE	INIT
0x1c	FDCAN_NBTP	NSJW				NBRP									NTSEG1									NTSEG2
0x20	FDCAN_TSCC										TCP																		TSS
0x24	FDCAN_TSCV														TSC
0x28	FDCAN_TOCC	TOP																										TOS		ETOC
0x2c	FDCAN_TOCV														TOC
0x40	FDCAN_ECR						CEL								RP	REC							TEC
0x44	FDCAN_PSR							TDCV								PXE	REDL	RBRS	RESI	DLEC			BO	EW	EP	ACT		LEC
0x48	FDCAN_TDCR															TDCO								TDCF
0x50	FDCAN_IR						ARA	PED	PEA	WDI	BO	EW	EP	ELO	TOO	MRAF	TSW	TEFL	TEFF	TEFN	TFE	TCF	TC	HPM	RF1L	RF1F	RF1N	RF0L	RF0F	RF0N
0x54	FDCAN_IE						ARAE	PEDE	PEAE	WDIE	BOE	EWE	EPE	ELOE	TOOE	MRAFE	TSWE	TEFLE	TEFFE	TEFNE	TEFE	TCFE	TCE	HPME	RF1LE	RF1FE	RF1NE	RF0LE	RF0FE	RF0NE
0x58	FDCAN_ILS																							PERR	BERR	MISC	TFERR	SMSG	RxFIFO1	RxFIFO0
0x5c	FDCAN_ILE																												EINT1	EINT0
0x80	FDCAN_RXGFC			LSE						LSS											F0OM	F1OM			ANFS		ANFE		RRFS	RRFE
0x84	FDCAN_XIDAM		EIDM												EIDM
0x88	FDCAN_HPMS														FLST			FIDX					MSI					BIDX
0x90	FDCAN_RXF0S				RF0L	F0F							F0PI								F0GI						F0FL
0x94	FDCAN_RXF0A																											F0AI
0x98	FDCAN_RXF1S				RF1L	F1F							F1PI								F1GI						F1FL
0x9c	FDCAN_RXF1A																											F1AI
0xc0	FDCAN_TXBC					TFQM
0xc4	FDCAN_TXFQS								TFQF				TFQPI								TFGI							TFFL
0xc8	FDCAN_TXBRP																											TRP
0xcc	FDCAN_TXBAR																											AR
0xd0	FDCAN_TXBCR																											CR
0xd4	FDCAN_TXBTO																											TO
0xd8	FDCAN_TXBCF																											CF
0xdc	FDCAN_TXBTIE																											TIE
0xe0	FDCAN_TXBCIE																											CFIE
0xe4	FDCAN_TXEFS				TEFL	EFF							EFPI								EFGI							EFFL
0xe8	FDCAN_TXEFA																												EFAI
0x100	FDCAN_CKDIV																										PDIV

Toggle registers

FDCAN_CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REL r				STEP r				SUBSTEP r				YEAR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MON r								DAY r

Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

FDCAN_ENDN

FDCAN endian register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETV r

Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TDC rw			DBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DTSEG1 rw					DTSEG2 rw				DSJW rw

Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

FDCAN_TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RX r	TX rw		LBCK rw

Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

FDCAN_RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDV r								WDC rw

Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

FDCAN_CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NISO rw	TXP rw	EFBI rw	PXHD rw			BRSE rw	FDOE rw	TEST rw	DAR rw	MON rw	CSR rw	CSA rw	ASM rw	CCE rw	INIT rw

Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BRSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSJW rw							NBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NTSEG1 rw									NTSEG2 rw

Toggle fields

NTSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: Nominal (Re)Synchronization Jump Width.

FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TCP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TSS rw

Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

FDCAN_TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSC rw

Toggle fields

TSC

Bits 0-15: Timestamp Counter.

FDCAN_TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TOS rw		ETOC rw

Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

FDCAN_TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOC rw

Toggle fields

FDCAN_ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RP r	REC r							TEC r

Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

FDCAN_PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TDCV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PXE rw	REDL rw	RBRS rw	RESI rw	DLEC rw			BO r	EW r	EP r	ACT r		LEC rw

Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDCO rw								TDCF rw

Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

FDCAN_IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARA rw	PED rw	PEA rw	WDI rw	BO rw	EW rw	EP rw	ELO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOO rw	MRAF rw	TSW rw	TEFL rw	TEFF rw	TEFN rw	TFE rw	TCF rw	TC rw	HPM rw	RF1L rw	RF1F rw	RF1N rw	RF0L rw	RF0F rw	RF0N rw

Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

FDCAN_IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARAE rw	PEDE rw	PEAE rw	WDIE rw	BOE rw	EWE rw	EPE rw	ELOE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOOE rw	MRAFE rw	TSWE rw	TEFLE rw	TEFFE rw	TEFNE rw	TEFE rw	TCFE rw	TCE rw	HPME rw	RF1LE rw	RF1FE rw	RF1NE rw	RF0LE rw	RF0FE rw	RF0NE rw

Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

TSWE

Bit 13: TSWE.

MRAFE

Bit 14: Message RAM Access Failure Enable.

TOOE

Bit 15: Timeout Occurred Enable.

ELOE

Bit 16: Error Logging Overflow Enable.

EPE

Bit 17: Error Passive Enable.

EWE

Bit 18: Warning Status Enable.

BOE

Bit 19: Bus_Off Status Enable.

WDIE

Bit 20: Watchdog Interrupt Enable.

PEAE

Bit 21: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 22: Protocol Error in Data Phase Enable.

ARAE

Bit 23: Access to Reserved Address Enable.

FDCAN_ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PERR rw	BERR rw	MISC rw	TFERR rw	SMSG rw	RxFIFO1 rw	RxFIFO0 rw

Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

FDCAN_ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EINT1 rw	EINT0 rw

Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

FDCAN_RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				LSE rw							LSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0OM rw	F1OM rw			ANFS rw		ANFE rw		RRFS rw	RRFE rw

Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

FDCAN_XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			EIDM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIDM rw

Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

FDCAN_HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLST r			FIDX r					MSI r					BIDX r

Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF0L r	F0F r							F0PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0GI r						F0FL r

Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F0AI rw

Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF1L r	F1F r							F1PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F1GI r						F1FL r

Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F1AI rw

Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

FDCAN_TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TFQM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TFQF r				TFQPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TFGI r							TFFL r

Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TRP r

Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													AR rw

Toggle fields

AR

Bits 0-2: Add Request.

FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CR rw

Toggle fields

CR

Bits 0-2: Cancellation Request.

FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TO r

Toggle fields

TO

Bits 0-2: Transmission Occurred..

FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CF r

Toggle fields

CF

Bits 0-2: Cancellation Finished.

FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TIE rw

Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CFIE rw

Toggle fields

CFIE

Bits 0-2: Cancellation Finished Interrupt Enable.

FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TEFL r	EFF r							EFPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EFGI r							EFFL r

Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EFAI rw

Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

FDCAN_CKDIV

FDCAN CFG clock divider register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PDIV rw

Toggle fields

PDIV

Bits 0-3: PDIV.

SEC_FDCAN1_RAM

0x5000ac00: FDCAN1_RAM

43/160 fields covered.

Toggle register map

Offset	Name	31	28	27	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	FDCAN_CREL	REL		STEP			SUBSTEP				YEAR				MON								DAY
0x4	FDCAN_ENDN	ETV													ETV
0xc	FDCAN_DBTP						TDC			DBRP								DTSEG1					DTSEG2				DSJW
0x10	FDCAN_TEST																						RX	TX		LBCK
0x14	FDCAN_RWD														WDV								WDC
0x18	FDCAN_CCCR														NISO	TXP	EFBI	PXHD			BRSE	FDOE	TEST	DAR	MON	CSR	CSA	ASM	CCE	INIT
0x1c	FDCAN_NBTP	NSJW				NBRP									NTSEG1									NTSEG2
0x20	FDCAN_TSCC										TCP																		TSS
0x24	FDCAN_TSCV														TSC
0x28	FDCAN_TOCC	TOP																										TOS		ETOC
0x2c	FDCAN_TOCV														TOC
0x40	FDCAN_ECR						CEL								RP	REC							TEC
0x44	FDCAN_PSR							TDCV								PXE	REDL	RBRS	RESI	DLEC			BO	EW	EP	ACT		LEC
0x48	FDCAN_TDCR															TDCO								TDCF
0x50	FDCAN_IR						ARA	PED	PEA	WDI	BO	EW	EP	ELO	TOO	MRAF	TSW	TEFL	TEFF	TEFN	TFE	TCF	TC	HPM	RF1L	RF1F	RF1N	RF0L	RF0F	RF0N
0x54	FDCAN_IE						ARAE	PEDE	PEAE	WDIE	BOE	EWE	EPE	ELOE	TOOE	MRAFE	TSWE	TEFLE	TEFFE	TEFNE	TEFE	TCFE	TCE	HPME	RF1LE	RF1FE	RF1NE	RF0LE	RF0FE	RF0NE
0x58	FDCAN_ILS																							PERR	BERR	MISC	TFERR	SMSG	RxFIFO1	RxFIFO0
0x5c	FDCAN_ILE																												EINT1	EINT0
0x80	FDCAN_RXGFC			LSE						LSS											F0OM	F1OM			ANFS		ANFE		RRFS	RRFE
0x84	FDCAN_XIDAM		EIDM												EIDM
0x88	FDCAN_HPMS														FLST			FIDX					MSI					BIDX
0x90	FDCAN_RXF0S				RF0L	F0F							F0PI								F0GI						F0FL
0x94	FDCAN_RXF0A																											F0AI
0x98	FDCAN_RXF1S				RF1L	F1F							F1PI								F1GI						F1FL
0x9c	FDCAN_RXF1A																											F1AI
0xc0	FDCAN_TXBC					TFQM
0xc4	FDCAN_TXFQS								TFQF				TFQPI								TFGI							TFFL
0xc8	FDCAN_TXBRP																											TRP
0xcc	FDCAN_TXBAR																											AR
0xd0	FDCAN_TXBCR																											CR
0xd4	FDCAN_TXBTO																											TO
0xd8	FDCAN_TXBCF																											CF
0xdc	FDCAN_TXBTIE																											TIE
0xe0	FDCAN_TXBCIE																											CFIE
0xe4	FDCAN_TXEFS				TEFL	EFF							EFPI								EFGI							EFFL
0xe8	FDCAN_TXEFA																												EFAI
0x100	FDCAN_CKDIV																										PDIV

Toggle registers

FDCAN_CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REL r				STEP r				SUBSTEP r				YEAR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MON r								DAY r

Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

FDCAN_ENDN

FDCAN endian register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETV r

Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TDC rw			DBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DTSEG1 rw					DTSEG2 rw				DSJW rw

Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

FDCAN_TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RX r	TX rw		LBCK rw

Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

FDCAN_RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDV r								WDC rw

Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

FDCAN_CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NISO rw	TXP rw	EFBI rw	PXHD rw			BRSE rw	FDOE rw	TEST rw	DAR rw	MON rw	CSR rw	CSA rw	ASM rw	CCE rw	INIT rw

Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BRSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSJW rw							NBRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NTSEG1 rw									NTSEG2 rw

Toggle fields

NTSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: Nominal (Re)Synchronization Jump Width.

FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TCP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TSS rw

Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

FDCAN_TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSC rw

Toggle fields

TSC

Bits 0-15: Timestamp Counter.

FDCAN_TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TOS rw		ETOC rw

Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

FDCAN_TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOC rw

Toggle fields

FDCAN_ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RP r	REC r							TEC r

Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

FDCAN_PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TDCV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PXE rw	REDL rw	RBRS rw	RESI rw	DLEC rw			BO r	EW r	EP r	ACT r		LEC rw

Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDCO rw								TDCF rw

Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

FDCAN_IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARA rw	PED rw	PEA rw	WDI rw	BO rw	EW rw	EP rw	ELO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOO rw	MRAF rw	TSW rw	TEFL rw	TEFF rw	TEFN rw	TFE rw	TCF rw	TC rw	HPM rw	RF1L rw	RF1F rw	RF1N rw	RF0L rw	RF0F rw	RF0N rw

Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

FDCAN_IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ARAE rw	PEDE rw	PEAE rw	WDIE rw	BOE rw	EWE rw	EPE rw	ELOE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOOE rw	MRAFE rw	TSWE rw	TEFLE rw	TEFFE rw	TEFNE rw	TEFE rw	TCFE rw	TCE rw	HPME rw	RF1LE rw	RF1FE rw	RF1NE rw	RF0LE rw	RF0FE rw	RF0NE rw

Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

TSWE

Bit 13: TSWE.

MRAFE

Bit 14: Message RAM Access Failure Enable.

TOOE

Bit 15: Timeout Occurred Enable.

ELOE

Bit 16: Error Logging Overflow Enable.

EPE

Bit 17: Error Passive Enable.

EWE

Bit 18: Warning Status Enable.

BOE

Bit 19: Bus_Off Status Enable.

WDIE

Bit 20: Watchdog Interrupt Enable.

PEAE

Bit 21: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 22: Protocol Error in Data Phase Enable.

ARAE

Bit 23: Access to Reserved Address Enable.

FDCAN_ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PERR rw	BERR rw	MISC rw	TFERR rw	SMSG rw	RxFIFO1 rw	RxFIFO0 rw

Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

FDCAN_ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EINT1 rw	EINT0 rw

Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

FDCAN_RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				LSE rw							LSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0OM rw	F1OM rw			ANFS rw		ANFE rw		RRFS rw	RRFE rw

Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

FDCAN_XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			EIDM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIDM rw

Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

FDCAN_HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLST r			FIDX r					MSI r					BIDX r

Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF0L r	F0F r							F0PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F0GI r						F0FL r

Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F0AI rw

Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						RF1L r	F1F r							F1PI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						F1GI r						F1FL r

Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													F1AI rw

Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

FDCAN_TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TFQM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TFQF r				TFQPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TFGI r							TFFL r

Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TRP r

Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													AR rw

Toggle fields

AR

Bits 0-2: Add Request.

FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CR rw

Toggle fields

CR

Bits 0-2: Cancellation Request.

FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TO r

Toggle fields

TO

Bits 0-2: Transmission Occurred..

FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CF r

Toggle fields

CF

Bits 0-2: Cancellation Finished.

FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TIE rw

Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CFIE rw

Toggle fields

CFIE

Bits 0-2: Cancellation Finished Interrupt Enable.

FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TEFL r	EFF r							EFPI r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EFGI r							EFFL r

Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EFAI rw

Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

FDCAN_CKDIV

FDCAN CFG clock divider register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PDIV rw

Toggle fields

PDIV

Bits 0-3: PDIV.

SEC_FLASH

0x50022000: Flash

15/1153 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	FLASH_ACR																		SLEEP_PD	PDREQ2	PDREQ1	LPM			PRFTEN					LATENCY
0x8	FLASH_NSKEYR	NSKEY																NSKEY
0xc	FLASH_SECKEYR	SECKEY																SECKEY
0x10	FLASH_OPTKEYR	OPTKEY																OPTKEY
0x18	FLASH_PDKEY1R	PDKEY1																PDKEY1
0x1c	FLASH_PDKEY2R	PDKEY2																PDKEY2
0x20	FLASH_NSSR											PD2	PD1	OEM2LOCK	OEM1LOCK	WDW	BSY			OPTWERR						PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x24	FLASH_SECSR															WDW	BSY		RDERR							PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x28	FLASH_NSCR	LOCK	OPTLOCK			OBL_LAUNCH		ERRIE	EOPIE							OPTSTRT	STRT	MER2	BWR			BKER	PNB								MER1	PER	PG
0x2c	FLASH_SECCR	LOCK		INV			RDERRIE	ERRIE	EOPIE								STRT	MER2	BWR			BKER	PNB								MER1	PER	PG
0x30	FLASH_ECCR	ECCD	ECCC						ECCIE		SYSF_ECC	BK_ECC	ADDR_ECC					ADDR_ECC
0x34	FLASH_OPSR	CODE_OP									SYSF_OP	BK_OP	ADDR_OP					ADDR_OP
0x40	FLASH_OPTR	TZEN	IO_VDDIO2_HSLV	IO_VDD_HSLV	PA15_PUPEN	nBOOT0	nSWBOOT0	SRAM2_RST	SRAM2_ECC		BKPRAM_ECC	DUALBANK	SWAP_BANK	WWDG_SW	IWDG_STDBY	IWDG_STOP	IWDG_SW	SRAM1345_RST	nRST_SHDW	nRST_STDBY	nRST_STOP		BOR_LEV			RDP
0x44	FLASH_NSBOOTADD0R	NSBOOTADD0																NSBOOTADD0
0x48	FLASH_NSBOOTADD1R	NSBOOTADD1																NSBOOTADD1
0x4c	FLASH_SECBOOTADD0R	SECBOOTADD0																SECBOOTADD0															BOOT_LOCK
0x50	FLASH_SECWM1R1									SECWM1_PEND																SECWM1_PSTRT
0x54	FLASH_SECWM1R2	HDP1EN								HDP1_PEND								PCROP1EN								PCROP1_PSTRT
0x58	FLASH_WRP1AR	UNLOCK								WRP1A_PEND																WRP1A_PSTRT
0x5c	FLASH_WRP1BR	UNLOCK								WRP1B_PEND																WRP1B_PSTRT
0x60	FLASH_SECWM2R1									SECWM2_PEND																SECWM2_PSTRT
0x64	FLASH_SECWM2R2	HDP2EN								HDP2_PEND								PCROP2EN								PCROP2_PSTRT
0x68	FLASH_WRP2AR	UNLOCK								WRP2A_PEND																WRP2A_PSTRT
0x6c	FLASH_WRP2BR	UNLOCK								WRP2B_PEND																WRP2B_PSTRT
0x70	FLASH_OEM1KEYR1	OEM1KEY																OEM1KEY
0x74	FLASH_OEM1KEYR2	OEM1KEY																OEM1KEY
0x78	FLASH_OEM2KEYR1	OEM2KEY																OEM2KEY
0x7c	FLASH_OEM2KEYR2	OEM2KEY																OEM2KEY
0x80	FLASH_SEC1BBR1	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x84	FLASH_SEC1BBR2	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x88	FLASH_SEC1BBR3	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x8c	FLASH_SEC1BBR4	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x90	FLASH_SEC1BBR5	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x94	FLASH_SEC1BBR6	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x98	FLASH_SEC1BBR7	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0x9c	FLASH_SEC1BBR8	SEC1BB31	SEC1BB30	SEC1BB29	SEC1BB28	SEC1BB27	SEC1BB26	SEC1BB25	SEC1BB24	SEC1BB23	SEC1BB22	SEC1BB21	SEC1BB20	SEC1BB19	SEC1BB18	SEC1BB17	SEC1BB16	SEC1BB15	SEC1BB14	SEC1BB13	SEC1BB12	SEC1BB11	SEC1BB10	SEC1BB9	SEC1BB8	SEC1BB7	SEC1BB6	SEC1BB5	SEC1BB4	SEC1BB3	SEC1BB2	SEC1BB1	SEC1BB0
0xa0	FLASH_SEC2BBR1	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xa4	FLASH_SEC2BBR2	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xa8	FLASH_SEC2BBR3	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xac	FLASH_SEC2BBR4	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xb0	FLASH_SEC2BBR5	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xb4	FLASH_SEC2BBR6	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xb8	FLASH_SEC2BBR7	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xbc	FLASH_SEC2BBR8	SEC2BB31	SEC2BB30	SEC2BB29	SEC2BB28	SEC2BB27	SEC2BB26	SEC2BB25	SEC2BB24	SEC2BB23	SEC2BB22	SEC2BB21	SEC2BB20	SEC2BB19	SEC2BB18	SEC2BB17	SEC2BB16	SEC2BB15	SEC2BB14	SEC2BB13	SEC2BB12	SEC2BB11	SEC2BB10	SEC2BB9	SEC2BB8	SEC2BB7	SEC2BB6	SEC2BB5	SEC2BB4	SEC2BB3	SEC2BB2	SEC2BB1	SEC2BB0
0xc0	FLASH_SECHDPCR																															HDP2_ACCDIS	HDP1_ACCDIS
0xc4	FLASH_PRIVCFGR																															NSPRIV	SPRIV
0xd0	FLASH_PRIV1BBR1	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xd4	FLASH_PRIV1BBR2	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xd8	FLASH_PRIV1BBR3	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xdc	FLASH_PRIV1BBR4	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xe0	FLASH_PRIV1BBR5	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xe4	FLASH_PRIV1BBR6	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xe8	FLASH_PRIV1BBR7	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xec	FLASH_PRIV1BBR8	PRIV1BB31	PRIV1BB30	PRIV1BB29	PRIV1BB28	PRIV1BB27	PRIV1BB26	PRIV1BB25	PRIV1BB24	PRIV1BB23	PRIV1BB22	PRIV1BB21	PRIV1BB20	PRIV1BB19	PRIV1BB18	PRIV1BB17	PRIV1BB16	PRIV1BB15	PRIV1BB14	PRIV1BB13	PRIV1BB12	PRIV1BB11	PRIV1BB10	PRIV1BB9	PRIV1BB8	PRIV1BB7	PRIV1BB6	PRIV1BB5	PRIV1BB4	PRIV1BB3	PRIV1BB2	PRIV1BB1	PRIV1BB0
0xf0	FLASH_PRIV2BBR1	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0xf4	FLASH_PRIV2BBR2	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0xf8	FLASH_PRIV2BBR3	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0xfc	FLASH_PRIV2BBR4	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x100	FLASH_PRIV2BBR5	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x104	FLASH_PRIV2BBR6	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x108	FLASH_PRIV2BBR7	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0
0x10c	FLASH_PRIV2BBR8	PRIV2BB31	PRIV2BB30	PRIV2BB29	PRIV2BB28	PRIV2BB27	PRIV2BB26	PRIV2BB25	PRIV2BB24	PRIV2BB23	PRIV2BB22	PRIV2BB21	PRIV2BB20	PRIV2BB19	PRIV2BB18	PRIV2BB17	PRIV2BB16	PRIV2BB15	PRIV2BB14	PRIV2BB13	PRIV2BB12	PRIV2BB11	PRIV2BB10	PRIV2BB9	PRIV2BB8	PRIV2BB7	PRIV2BB6	PRIV2BB5	PRIV2BB4	PRIV2BB3	PRIV2BB2	PRIV2BB1	PRIV2BB0

Toggle registers

FLASH_ACR

FLASH access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SLEEP_PD rw	PDREQ2 rw	PDREQ1 rw	LPM rw			PRFTEN rw					LATENCY rw

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LATENCY

Bits 0-3: Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. ....

PRFTEN

Bit 8: Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory..

LPM

Bit 11: Low-power read mode This bit puts the Flash memory in low-power read mode..

PDREQ1

6/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										PD2 r	PD1 r	OEM2LOCK r	OEM1LOCK r	WDW r	BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OPTWERR rw						PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

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EOP

Bit 0: Non-secure end of operation This bit is set by hardware when one or more Flash memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_NSCR). This bit is cleared by writing 1..

OPERR

Bit 1: Non-secure operation error This bit is set by hardware when a Flash memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1..

PROGERR

Bit 3: Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1..

WRPERR

Bit 4: Non-secure write protection error This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. Refer to for full conditions of error flag setting..

PGAERR

Bit 5: Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1..

SIZERR

Bit 6: Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1..

PGSERR

Bit 7: Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting..

OPTWERR

Bit 13: Option write error This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. Refer to for full conditions of error flag setting..

BSY

Bit 16: Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs..

WDW

Bit 17: Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory..

OEM1LOCK

Bit 18: OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active..

OEM2LOCK

Bit 19: OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active..

PD1

Bit 20: Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken..

PD2

Bit 21: Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken..

FLASH_SECSR

FLASH secure status register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														WDW r	BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	RDERR rw							PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

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EOP

Bit 0: Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1..

OPERR

Bit 1: Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1..

PROGERR

Bit 3: Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1..

WRPERR

Bit 4: Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. Refer to for full conditions of error flag setting..

PGAERR

Bit 5: Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1..

SIZERR

Bit 6: Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1..

PGSERR

Bit 7: Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting..

RDERR

Bit 14: Secure readout protection error This bit is set by hardware when a read access is performed to a secure PCROP area and when a cacheable fetch access is performed to a secure PCROP area. An interrupt is generated if RDERRIE is set in FLASH_SECCR register. This bit is cleared by writing 1..

BSY

Bit 16: Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs..

WDW

Bit 17: Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory..

FLASH_NSCR

FLASH non-secure control register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	OPTLOCK rw			OBL_LAUNCH rw		ERRIE rw	EOPIE rw							OPTSTRT rw	STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MER2 rw	BWR rw			BKER rw	PNB rw								MER1 rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Non-secure programming.

PER

Bit 1: Non-secure page erase.

MER1

Bit 2: Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set..

PNB

Bits 3-10: Non-secure page number selection These bits select the page to erase. ... ....

BKER

Bit 11: Non-secure bank selection for page erase.

BWR

Bit 14: Non-secure burst write programming mode When set, this bit selects the burst write programming mode..

MER2

Bit 15: Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set..

STRT

Bit 16: Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR..

OPTSTRT

Bit 17: Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR..

EOPIE

Bit 24: Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1..

ERRIE

Bit 25: Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1..

OBL_LAUNCH

Bit 27: Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set..

OPTLOCK

Bit 30: Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset..

LOCK

Bit 31: Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset..

FLASH_SECCR

FLASH secure control register

Offset: 0x2c, size: 32, reset: 0x80000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw		INV rw			RDERRIE rw	ERRIE rw	EOPIE rw								STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MER2 rw	BWR rw			BKER rw	PNB rw								MER1 rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Secure programming.

PER

Bit 1: Secure page erase.

MER1

Bit 2: Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set..

PNB

Bits 3-10: Secure page number selection These bits select the page to erase. ... ....

BKER

Bit 11: Secure bank selection for page erase.

BWR

Bit 14: Secure burst write programming mode When set, this bit selects the burst write programming mode..

MER2

Bit 15: Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set..

STRT

Bit 16: Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR..

EOPIE

Bit 24: Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1..

ERRIE

Bit 25: Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_SECSR is set to 1..

RDERRIE

Bit 26: Secure PCROP read error interrupt enable This bit enables the interrupt generation when the RDERR bit in the FLASH_SECSR is set to 1..

INV

Bit 29: Flash memory security state invert This bit inverts the Flash memory security state..

LOCK

Bit 31: Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset..

FLASH_ECCR

FLASH ECC register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

3/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECCD rw	ECCC rw						ECCIE rw		SYSF_ECC r	BK_ECC r	ADDR_ECC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_ECC r

Toggle fields

ADDR_ECC

Bits 0-20: ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given by bank from address 0x0 0000 to 0x1F FFF0..

BK_ECC

Bit 21: ECC fail bank This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection..

SYSF_ECC

Bit 22: System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory..

ECCIE

Bit 24: ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set..

ECCC

Bit 30: ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1..

ECCD

Bit 31: ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1..

FLASH_OPSR

FLASH operation status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CODE_OP r									SYSF_OP r	BK_OP r	ADDR_OP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_OP r

Toggle fields

ADDR_OP

Bits 0-20: Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0x1F FFF0..

BK_OP

Bit 21: Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred.

SYSF_OP

Bit 22: Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory..

CODE_OP

Bits 29-31: Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset:.

FLASH_OPTR

FLASH option register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TZEN rw	IO_VDDIO2_HSLV rw	IO_VDD_HSLV rw	PA15_PUPEN rw	nBOOT0 rw	nSWBOOT0 rw	SRAM2_RST rw	SRAM2_ECC rw		BKPRAM_ECC rw	DUALBANK rw	SWAP_BANK rw	WWDG_SW rw	IWDG_STDBY rw	IWDG_STOP rw	IWDG_SW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRAM1345_RST rw	nRST_SHDW rw	nRST_STDBY rw	nRST_STOP rw		BOR_LEV rw			RDP rw

Toggle fields

RDP

Bits 0-7: Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details..

BOR_LEV

Bits 8-10: BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset..

nRST_STOP

Bit 12: Reset generation in Stop mode.

nRST_STDBY

Bit 13: Reset generation in Standby mode.

nRST_SHDW

Bit 14: Reset generation in Shutdown mode.

SRAM1345_RST

Bit 15: SRAM1, SRAM4 and SRAM5 erase upon system reset.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

SWAP_BANK

Bit 20: Swap banks.

DUALBANK

Bit 21: Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices.

BKPRAM_ECC

Bit 22: Backup RAM ECC detection and correction enable.

SRAM2_ECC

Bit 24: SRAM2 ECC detection and correction enable.

SRAM2_RST

Bit 25: SRAM2 erase when system reset.

nSWBOOT0

Bit 26: Software BOOT0.

nBOOT0

Bit 27: nBOOT0 option bit.

PA15_PUPEN

Bit 28: PA15 pull-up enable.

IO_VDD_HSLV

Bit 29: High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V.

IO_VDDIO2_HSLV

Bit 30: High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V..

TZEN

Bit 31: Global TrustZone security enable.

FLASH_NSBOOTADD0R

FLASH non-secure boot address 0 register

Offset: 0x44, size: 32, reset: 0x0000000F, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSBOOTADD0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NSBOOTADD0 rw

Toggle fields

NSBOOTADD0

Bits 7-31: Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000).

FLASH_NSBOOTADD1R

FLASH non-secure boot address 1 register

Offset: 0x48, size: 32, reset: 0x0000000F, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NSBOOTADD1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NSBOOTADD1 rw

Toggle fields

NSBOOTADD1

Bits 7-31: Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000).

FLASH_SECBOOTADD0R

FLASH secure boot address 0 register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SECBOOTADD0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SECBOOTADD0 rw															BOOT_LOCK rw

Toggle fields

BOOT_LOCK

Bit 0: Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0..

SECBOOTADD0

Bits 7-31: Secure boot base address 0 The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000).

FLASH_SECWM1R1

FLASH secure watermark1 register 1

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SECWM1_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SECWM1_PSTRT rw

Toggle fields

SECWM1_PSTRT

Bits 0-7: Start page of first secure area This field contains the first page of the secure area in bank 1..

SECWM1_PEND

Bits 16-23: End page of first secure area This field contains the last page of the secure area in bank 1..

FLASH_SECWM1R2

FLASH secure watermark1 register 2

Offset: 0x54, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HDP1EN rw								HDP1_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCROP1EN rw								PCROP1_PSTRT rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SECWM2_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SECWM2_PSTRT rw

Toggle fields

SECWM2_PSTRT

Bits 0-7: Start page of second secure area This field contains the first page of the secure area in bank 2..

SECWM2_PEND

Bits 16-23: End page of second secure area This field contains the last page of the secure area in bank 2..

FLASH_SECWM2R2

FLASH secure watermark2 register 2

Offset: 0x64, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HDP2EN rw								HDP2_PEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCROP2EN rw								PCROP2_PSTRT rw

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

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SEC1BB0

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SEC1BB1

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SEC1BB2

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SEC1BB3

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SEC1BB4

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SEC1BB5

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SEC1BB10

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SEC1BB12

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SEC1BB15

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SEC1BB21

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SEC1BB22

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SEC1BB24

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SEC1BB27

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SEC1BB28

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SEC1BB29

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SEC1BB30

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SEC1BB31

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FLASH_SEC1BBR2

FLASH secure block based bank 1 register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

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SEC1BB0

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SEC1BB1

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SEC1BB2

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SEC1BB3

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SEC1BB4

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SEC1BB5

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SEC1BB6

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SEC1BB7

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SEC1BB8

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SEC1BB9

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SEC1BB10

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SEC1BB11

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SEC1BB12

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SEC1BB13

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SEC1BB14

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SEC1BB15

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SEC1BB16

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SEC1BB17

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SEC1BB18

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SEC1BB19

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

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SEC1BB29

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SEC1BB30

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SEC1BB31

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FLASH_SEC1BBR3

FLASH secure block based bank 1 register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

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SEC1BB0

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SEC1BB1

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SEC1BB2

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SEC1BB3

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SEC1BB4

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SEC1BB5

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SEC1BB7

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SEC1BB10

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SEC1BB12

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SEC1BB15

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SEC1BB18

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

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SEC1BB29

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SEC1BB30

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SEC1BB31

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FLASH_SEC1BBR4

FLASH secure block based bank 1 register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

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SEC1BB0

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SEC1BB1

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SEC1BB2

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SEC1BB3

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SEC1BB4

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SEC1BB5

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SEC1BB15

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SEC1BB17

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SEC1BB18

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SEC1BB20

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SEC1BB21

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SEC1BB22

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SEC1BB23

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

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SEC1BB29

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SEC1BB30

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SEC1BB31

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FLASH_SEC1BBR5

FLASH secure block based bank 1 register 5

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

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SEC1BB1

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SEC1BB2

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SEC1BB3

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SEC1BB4

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SEC1BB10

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SEC1BB20

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SEC1BB22

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SEC1BB24

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SEC1BB25

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SEC1BB26

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SEC1BB27

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SEC1BB28

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SEC1BB29

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SEC1BB30

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SEC1BB31

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FLASH_SEC1BBR6

FLASH secure block based bank 1 register 6

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

Bit 9: .

SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

Bit 13: .

SEC1BB14

Bit 14: .

SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

Bit 17: .

SEC1BB18

Bit 18: .

SEC1BB19

Bit 19: .

SEC1BB20

Bit 20: .

SEC1BB21

Bit 21: .

SEC1BB22

Bit 22: .

SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR7

FLASH secure block based bank 1 register 7

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

Bit 9: .

SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

Bit 13: .

SEC1BB14

Bit 14: .

SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

Bit 17: .

SEC1BB18

Bit 18: .

SEC1BB19

Bit 19: .

SEC1BB20

Bit 20: .

SEC1BB21

Bit 21: .

SEC1BB22

Bit 22: .

SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC1BBR8

FLASH secure block based bank 1 register 8

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC1BB31 rw	SEC1BB30 rw	SEC1BB29 rw	SEC1BB28 rw	SEC1BB27 rw	SEC1BB26 rw	SEC1BB25 rw	SEC1BB24 rw	SEC1BB23 rw	SEC1BB22 rw	SEC1BB21 rw	SEC1BB20 rw	SEC1BB19 rw	SEC1BB18 rw	SEC1BB17 rw	SEC1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC1BB15 rw	SEC1BB14 rw	SEC1BB13 rw	SEC1BB12 rw	SEC1BB11 rw	SEC1BB10 rw	SEC1BB9 rw	SEC1BB8 rw	SEC1BB7 rw	SEC1BB6 rw	SEC1BB5 rw	SEC1BB4 rw	SEC1BB3 rw	SEC1BB2 rw	SEC1BB1 rw	SEC1BB0 rw

Toggle fields

SEC1BB0

Bit 0: .

SEC1BB1

Bit 1: .

SEC1BB2

Bit 2: .

SEC1BB3

Bit 3: .

SEC1BB4

Bit 4: .

SEC1BB5

Bit 5: .

SEC1BB6

Bit 6: .

SEC1BB7

Bit 7: .

SEC1BB8

Bit 8: .

SEC1BB9

Bit 9: .

SEC1BB10

Bit 10: .

SEC1BB11

Bit 11: .

SEC1BB12

Bit 12: .

SEC1BB13

Bit 13: .

SEC1BB14

Bit 14: .

SEC1BB15

Bit 15: .

SEC1BB16

Bit 16: .

SEC1BB17

Bit 17: .

SEC1BB18

Bit 18: .

SEC1BB19

Bit 19: .

SEC1BB20

Bit 20: .

SEC1BB21

Bit 21: .

SEC1BB22

Bit 22: .

SEC1BB23

Bit 23: .

SEC1BB24

Bit 24: .

SEC1BB25

Bit 25: .

SEC1BB26

Bit 26: .

SEC1BB27

Bit 27: .

SEC1BB28

Bit 28: .

SEC1BB29

Bit 29: .

SEC1BB30

Bit 30: .

SEC1BB31

Bit 31: .

FLASH_SEC2BBR1

FLASH secure block based bank 2 register 1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR2

FLASH secure block based bank 2 register 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR3

FLASH secure block based bank 2 register 3

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR4

FLASH secure block based bank 2 register 4

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR5

FLASH secure block based bank 2 register 5

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR6

FLASH secure block based bank 2 register 6

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR7

FLASH secure block based bank 2 register 7

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SEC2BBR8

FLASH secure block based bank 2 register 8

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC2BB31 rw	SEC2BB30 rw	SEC2BB29 rw	SEC2BB28 rw	SEC2BB27 rw	SEC2BB26 rw	SEC2BB25 rw	SEC2BB24 rw	SEC2BB23 rw	SEC2BB22 rw	SEC2BB21 rw	SEC2BB20 rw	SEC2BB19 rw	SEC2BB18 rw	SEC2BB17 rw	SEC2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC2BB15 rw	SEC2BB14 rw	SEC2BB13 rw	SEC2BB12 rw	SEC2BB11 rw	SEC2BB10 rw	SEC2BB9 rw	SEC2BB8 rw	SEC2BB7 rw	SEC2BB6 rw	SEC2BB5 rw	SEC2BB4 rw	SEC2BB3 rw	SEC2BB2 rw	SEC2BB1 rw	SEC2BB0 rw

Toggle fields

SEC2BB0

Bit 0: .

SEC2BB1

Bit 1: .

SEC2BB2

Bit 2: .

SEC2BB3

Bit 3: .

SEC2BB4

Bit 4: .

SEC2BB5

Bit 5: .

SEC2BB6

Bit 6: .

SEC2BB7

Bit 7: .

SEC2BB8

Bit 8: .

SEC2BB9

Bit 9: .

SEC2BB10

Bit 10: .

SEC2BB11

Bit 11: .

SEC2BB12

Bit 12: .

SEC2BB13

Bit 13: .

SEC2BB14

Bit 14: .

SEC2BB15

Bit 15: .

SEC2BB16

Bit 16: .

SEC2BB17

Bit 17: .

SEC2BB18

Bit 18: .

SEC2BB19

Bit 19: .

SEC2BB20

Bit 20: .

SEC2BB21

Bit 21: .

SEC2BB22

Bit 22: .

SEC2BB23

Bit 23: .

SEC2BB24

Bit 24: .

SEC2BB25

Bit 25: .

SEC2BB26

Bit 26: .

SEC2BB27

Bit 27: .

SEC2BB28

Bit 28: .

SEC2BB29

Bit 29: .

SEC2BB30

Bit 30: .

SEC2BB31

Bit 31: .

FLASH_SECHDPCR

FLASH secure HDP control register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														HDP2_ACCDIS rw	HDP1_ACCDIS rw

Toggle fields

HDP1_ACCDIS

Bit 0: HDP1 area access disable When set, this bit is only cleared by a system reset..

HDP2_ACCDIS

Bit 1: HDP2 area access disable When set, this bit is only cleared by a system reset..

FLASH_PRIVCFGR

FLASH privilege configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														NSPRIV rw	SPRIV rw

Toggle fields

SPRIV

Bit 0: Privileged protection for secure registers.

NSPRIV

Bit 1: Privileged protection for non-secure registers.

FLASH_PRIV1BBR1

FLASH privilege block based bank 1 register 1

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR2

FLASH privilege block based bank 1 register 2

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR3

FLASH privilege block based bank 1 register 3

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR4

FLASH privilege block based bank 1 register 4

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR5

FLASH privilege block based bank 1 register 5

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR6

FLASH privilege block based bank 1 register 6

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR7

FLASH privilege block based bank 1 register 7

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV1BBR8

FLASH privilege block based bank 1 register 8

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV1BB31 rw	PRIV1BB30 rw	PRIV1BB29 rw	PRIV1BB28 rw	PRIV1BB27 rw	PRIV1BB26 rw	PRIV1BB25 rw	PRIV1BB24 rw	PRIV1BB23 rw	PRIV1BB22 rw	PRIV1BB21 rw	PRIV1BB20 rw	PRIV1BB19 rw	PRIV1BB18 rw	PRIV1BB17 rw	PRIV1BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV1BB15 rw	PRIV1BB14 rw	PRIV1BB13 rw	PRIV1BB12 rw	PRIV1BB11 rw	PRIV1BB10 rw	PRIV1BB9 rw	PRIV1BB8 rw	PRIV1BB7 rw	PRIV1BB6 rw	PRIV1BB5 rw	PRIV1BB4 rw	PRIV1BB3 rw	PRIV1BB2 rw	PRIV1BB1 rw	PRIV1BB0 rw

Toggle fields

PRIV1BB0

Bit 0: .

PRIV1BB1

Bit 1: .

PRIV1BB2

Bit 2: .

PRIV1BB3

Bit 3: .

PRIV1BB4

Bit 4: .

PRIV1BB5

Bit 5: .

PRIV1BB6

Bit 6: .

PRIV1BB7

Bit 7: .

PRIV1BB8

Bit 8: .

PRIV1BB9

Bit 9: .

PRIV1BB10

Bit 10: .

PRIV1BB11

Bit 11: .

PRIV1BB12

Bit 12: .

PRIV1BB13

Bit 13: .

PRIV1BB14

Bit 14: .

PRIV1BB15

Bit 15: .

PRIV1BB16

Bit 16: .

PRIV1BB17

Bit 17: .

PRIV1BB18

Bit 18: .

PRIV1BB19

Bit 19: .

PRIV1BB20

Bit 20: .

PRIV1BB21

Bit 21: .

PRIV1BB22

Bit 22: .

PRIV1BB23

Bit 23: .

PRIV1BB24

Bit 24: .

PRIV1BB25

Bit 25: .

PRIV1BB26

Bit 26: .

PRIV1BB27

Bit 27: .

PRIV1BB28

Bit 28: .

PRIV1BB29

Bit 29: .

PRIV1BB30

Bit 30: .

PRIV1BB31

Bit 31: .

FLASH_PRIV2BBR1

FLASH privilege block based bank 2 register 1

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR2

FLASH privilege block based bank 2 register 2

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR3

FLASH privilege block based bank 2 register 3

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR4

FLASH privilege block based bank 2 register 4

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR5

FLASH privilege block based bank 2 register 5

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR6

FLASH privilege block based bank 2 register 6

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR7

FLASH privilege block based bank 2 register 7

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

FLASH_PRIV2BBR8

FLASH privilege block based bank 2 register 8

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV2BB31 rw	PRIV2BB30 rw	PRIV2BB29 rw	PRIV2BB28 rw	PRIV2BB27 rw	PRIV2BB26 rw	PRIV2BB25 rw	PRIV2BB24 rw	PRIV2BB23 rw	PRIV2BB22 rw	PRIV2BB21 rw	PRIV2BB20 rw	PRIV2BB19 rw	PRIV2BB18 rw	PRIV2BB17 rw	PRIV2BB16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV2BB15 rw	PRIV2BB14 rw	PRIV2BB13 rw	PRIV2BB12 rw	PRIV2BB11 rw	PRIV2BB10 rw	PRIV2BB9 rw	PRIV2BB8 rw	PRIV2BB7 rw	PRIV2BB6 rw	PRIV2BB5 rw	PRIV2BB4 rw	PRIV2BB3 rw	PRIV2BB2 rw	PRIV2BB1 rw	PRIV2BB0 rw

Toggle fields

PRIV2BB0

Bit 0: .

PRIV2BB1

Bit 1: .

PRIV2BB2

Bit 2: .

PRIV2BB3

Bit 3: .

PRIV2BB4

Bit 4: .

PRIV2BB5

Bit 5: .

PRIV2BB6

Bit 6: .

PRIV2BB7

Bit 7: .

PRIV2BB8

Bit 8: .

PRIV2BB9

Bit 9: .

PRIV2BB10

Bit 10: .

PRIV2BB11

Bit 11: .

PRIV2BB12

Bit 12: .

PRIV2BB13

Bit 13: .

PRIV2BB14

Bit 14: .

PRIV2BB15

Bit 15: .

PRIV2BB16

Bit 16: .

PRIV2BB17

Bit 17: .

PRIV2BB18

Bit 18: .

PRIV2BB19

Bit 19: .

PRIV2BB20

Bit 20: .

PRIV2BB21

Bit 21: .

PRIV2BB22

Bit 22: .

PRIV2BB23

Bit 23: .

PRIV2BB24

Bit 24: .

PRIV2BB25

Bit 25: .

PRIV2BB26

Bit 26: .

PRIV2BB27

Bit 27: .

PRIV2BB28

Bit 28: .

PRIV2BB29

Bit 29: .

PRIV2BB30

Bit 30: .

PRIV2BB31

Bit 31: .

SEC_FMAC

0x50021400: Filter Math Accelerator

6/29 fields covered.

Toggle register map

Offset	Name	31	30	25	23	16	15	10	9	8	7	4	3	2	1	0
0x0	X1BUFCFG			FULL_WM			X1_BUF_SIZE				X1_BASE
0x4	X2BUFCFG						X2_BUF_SIZE				X2_BASE
0x8	YBUFCFG			EMPTY_WM			Y_BUF_SIZE				Y_BASE
0xc	PARAM	START	FUNC		R		Q				P
0x10	CR					RESET	CLIPEN		DMAWEN	DMAREN		SATIEN	UNFLIEN	OVFLIEN	WIEN	RIEN
0x14	SR							SAT	UNFL	OVFL					X1FULL	YEMPTY
0x18	WDATA						WDATA
0x1c	RDATA						RDATA

Toggle registers

X1BUFCFG

FMAC X1 Buffer Configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FULL_WM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
X1_BUF_SIZE rw								X1_BASE rw

Toggle fields

X1_BASE

Bits 0-7: Base address of X1 buffer.

X1_BUF_SIZE

Bits 8-15: Allocated size of X1 buffer in 16-bit words.

FULL_WM

Bits 24-25: Watermark for buffer full flag.

X2BUFCFG

FMAC X2 Buffer Configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
X2_BUF_SIZE rw								X2_BASE rw

Toggle fields

X2_BASE

Bits 0-7: Base address of X2 buffer.

X2_BUF_SIZE

Bits 8-15: Size of X2 buffer in 16-bit words.

YBUFCFG

FMAC Y Buffer Configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						EMPTY_WM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Y_BUF_SIZE rw								Y_BASE rw

Toggle fields

Y_BASE

Bits 0-7: Base address of Y buffer.

Y_BUF_SIZE

Bits 8-15: Size of Y buffer in 16-bit words.

EMPTY_WM

Bits 24-25: Watermark for buffer empty flag.

PARAM

FMAC Parameter register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
START rw	FUNC rw							R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Q rw								P rw

Toggle fields

P

Bits 0-7: Input parameter P.

Q

Bits 8-15: Input parameter Q.

R

Bits 16-23: Input parameter R.

FUNC

Bits 24-30: Function.

START

Bit 31: Enable execution.

CR

FMAC Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RESET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLIPEN rw						DMAWEN rw	DMAREN rw				SATIEN rw	UNFLIEN rw	OVFLIEN rw	WIEN rw	RIEN rw

Toggle fields

RIEN

Bit 0: Enable read interrupt.

WIEN

Bit 1: Enable write interrupt.

OVFLIEN

Bit 2: Enable overflow error interrupts.

UNFLIEN

Bit 3: Enable underflow error interrupts.

SATIEN

Bit 4: Enable saturation error interrupts.

DMAREN

Bit 8: Enable DMA read channel requests.

DMAWEN

Bit 9: Enable DMA write channel requests.

CLIPEN

Bit 15: Enable clipping.

RESET

Bit 16: Reset FMAC unit.

SR

FMAC Status register

Offset: 0x14, size: 32, reset: 0x00000001, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SAT r	UNFL r	OVFL r							X1FULL r	YEMPTY r

Toggle fields

YEMPTY

Bit 0: Y buffer empty flag.

X1FULL

Bit 1: X1 buffer full flag.

OVFL

Bit 8: Overflow error flag.

UNFL

Bit 9: Underflow error flag.

SAT

Bit 10: Saturation error flag.

WDATA

FMAC Write Data register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDATA w

Toggle fields

WDATA

Bits 0-15: Write data.

RDATA

FMAC Read Data register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA r

Toggle fields

RDATA

Bits 0-15: Read data.

SEC_GPDMA1

0x50020000: GPDMA1

160/900 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	21	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPDMA_SECCFGR													SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x4	GPDMA_PRIVCFGR													PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0xc	MISR													MIS15	MIS14	MIS13	MIS12	MIS11	MIS10	MIS9	MIS8	MIS7	MIS6	MIS5	MIS4	MIS3	MIS2	MIS1	MIS0
0x10	SMISR													MIS15	MIS14	MIS13	MIS12	MIS11	MIS10	MIS9	MIS8	MIS7	MIS6	MIS5	MIS4	MIS3	MIS2	MIS1	MIS0
0x50	GPDMA_C0LBAR	LBA
0x5c	GPDMA_C0FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x60	GPDMA_C0SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x64	GPDMA_C0CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x90	GPDMA_C0TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x94	GPDMA_C0TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x98	GPDMA_C0BR1													BNDT
0x9c	GPDMA_C0SAR	SA												SA
0xa0	GPDMA_C0DAR	DA												DA
0xcc	GPDMA_C0LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0xd0	GPDMA_C1LBAR	LBA
0xdc	GPDMA_C1FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0xe0	GPDMA_C1SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0xe4	GPDMA_C1CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x110	GPDMA_C1TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x114	GPDMA_C1TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x118	GPDMA_C1BR1													BNDT
0x11c	GPDMA_C1SAR	SA												SA
0x120	GPDMA_C1DAR	DA												DA
0x14c	GPDMA_C1LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x150	GPDMA_C2LBAR	LBA
0x15c	GPDMA_C2FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x160	GPDMA_C2SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x164	GPDMA_C2CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x190	GPDMA_C2TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x194	GPDMA_C2TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x198	GPDMA_C2BR1													BNDT
0x19c	GPDMA_C2SAR	SA												SA
0x1a0	GPDMA_C2DAR	DA												DA
0x1cc	GPDMA_C2LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x1d0	GPDMA_C3LBAR	LBA
0x1dc	GPDMA_C3FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x1e0	GPDMA_C3SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x1e4	GPDMA_C3CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x210	GPDMA_C3TR1	DSEC	DAP			DHX	DBX	DBL_1			DINC	DDW_LOG2		SSEC	SAP	SBX	PAM			SBL_1						SINC		SDW_LOG2
0x214	GPDMA_C3TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x218	GPDMA_C3BR1													BNDT
0x21c	GPDMA_C3SAR	SA												SA
0x220	GPDMA_C3DAR	DA												DA
0x24c	GPDMA_C3LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x250	GPDMA_C4LBAR	LBA
0x25c	GPDMA_C4FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x260	GPDMA_C4SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x264	GPDMA_C4CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x294	GPDMA_C4TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x298	GPDMA_C4BR1													BNDT
0x29c	GPDMA_C4SAR	SA												SA
0x2a0	GPDMA_C4DAR	DA												DA
0x2cc	GPDMA_C4LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x2d0	GPDMA_C5LBAR	LBA
0x2dc	GPDMA_C5FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x2e0	GPDMA_C5SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x2e4	GPDMA_C5CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x314	GPDMA_C5TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x318	GPDMA_C5BR1													BNDT
0x31c	GPDMA_C5SAR	SA												SA
0x320	GPDMA_C5DAR	DA												DA
0x34c	GPDMA_C5LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x350	GPDMA_C6LBAR	LBA
0x35c	GPDMA_C6FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x360	GPDMA_C6SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x364	GPDMA_C6CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x394	GPDMA_C6TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x398	GPDMA_C6BR1													BNDT
0x39c	GPDMA_C6SAR	SA												SA
0x3a0	GPDMA_C6DAR	DA												DA
0x3cc	GPDMA_C6LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x3d0	GPDMA_C7LBAR	LBA
0x3dc	GPDMA_C7FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x3e0	GPDMA_C7SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x3e4	GPDMA_C7CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x414	GPDMA_C7TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x418	GPDMA_C7BR1													BNDT
0x41c	GPDMA_C7SAR	SA												SA
0x420	GPDMA_C7DAR	DA												DA
0x44c	GPDMA_C7LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x450	GPDMA_C8LBAR	LBA
0x45c	GPDMA_C8FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x460	GPDMA_C8SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x464	GPDMA_C8CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x494	GPDMA_C8TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x498	GPDMA_C8BR1													BNDT
0x49c	GPDMA_C8SAR	SA												SA
0x4a0	GPDMA_C8DAR	DA												DA
0x4cc	GPDMA_C8LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x4d0	GPDMA_C9LBAR	LBA
0x4dc	GPDMA_C9FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x4e0	GPDMA_C9SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x4e4	GPDMA_C9CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x514	GPDMA_C9TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x518	GPDMA_C9BR1													BNDT
0x51c	GPDMA_C9SAR	SA												SA
0x520	GPDMA_C9DAR	DA												DA
0x54c	GPDMA_C9LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x550	GPDMA_C10LBAR	LBA
0x55c	GPDMA_C10FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x560	GPDMA_C10SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x564	GPDMA_C10CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x594	GPDMA_C10TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x598	GPDMA_C10BR1													BNDT
0x59c	GPDMA_C10SAR	SA												SA
0x5a0	GPDMA_C10DAR	DA												DA
0x5cc	GPDMA_C10LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x5d0	GPDMA_C11LBAR	LBA
0x5dc	GPDMA_C11FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x5e0	GPDMA_C11SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x5e4	GPDMA_C11CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x614	GPDMA_C11TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x618	GPDMA_C11BR1													BNDT
0x61c	GPDMA_C11SAR	SA												SA
0x620	GPDMA_C11DAR	DA												DA
0x64c	GPDMA_C11LLR	UT1	UT2	UB1	USA	UDA							ULL	LA
0x650	GPDMA_C12LBAR	LBA
0x65c	GPDMA_C12FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x660	GPDMA_C12SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x664	GPDMA_C12CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x694	GPDMA_C12TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x698	GPDMA_C12BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x69c	GPDMA_C12SAR	SA												SA
0x6a0	GPDMA_C12DAR	DA												DA
0x6a4	GPDMA_C12TR3				DAO												SAO
0x6a8	GPDMA_C12BR2	BRDAO												BRSAO
0x6cc	GPDMA_C12LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA
0x6d0	GPDMA_C13LBAR	LBA
0x6dc	GPDMA_C13FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x6e0	GPDMA_C13SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x6e4	GPDMA_C13CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x714	GPDMA_C13TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x718	GPDMA_C13BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x71c	GPDMA_C13SAR	SA												SA
0x720	GPDMA_C13DAR	DA												DA
0x724	GPDMA_C13TR3				DAO												SAO
0x728	GPDMA_C13BR2	BRDAO												BRSAO
0x74c	GPDMA_C13LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA
0x750	GPDMA_C14LBAR	LBA
0x75c	GPDMA_C14FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x760	GPDMA_C14SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x764	GPDMA_C14CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x794	GPDMA_C14TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x798	GPDMA_C14BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x79c	GPDMA_C14SAR	SA												SA
0x7a0	GPDMA_C14DAR	DA												DA
0x7a4	GPDMA_C14TR3				DAO												SAO
0x7a8	GPDMA_C14BR2	BRDAO												BRSAO
0x7cc	GPDMA_C14LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA
0x7d0	GPDMA_C15LBAR	LBA
0x7dc	GPDMA_C15FCR														TOF	SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x7e0	GPDMA_C15SR								FIFOL							SUSPF	USEF	ULEF	DTEF	HTF	TCF								IDLEF
0x7e4	GPDMA_C15CR								PRIO			LAP	LSM			SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE						SUSP	RESET	EN
0x814	GPDMA_C15TR2	TCEM						TRIGPOL		TRIGSEL				TRIGM				BREQ	DREQ	SWREQ			REQSEL
0x818	GPDMA_C15BR1	BRDDEC	BRSDEC	DDEC	SDEC		BRC							BNDT
0x81c	GPDMA_C15SAR	SA												SA
0x820	GPDMA_C15DAR	DA												DA
0x824	GPDMA_C15TR3				DAO												SAO
0x828	GPDMA_C15BR2	BRDAO												BRSAO
0x84c	GPDMA_C15LLR	UT1	UT2	UB1	USA	UDA	UT3	UB2					ULL	LA

Toggle registers

GPDMA_SECCFGR

GPDMA secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

GPDMA_PRIVCFGR

GPDMA privileged configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

MISR

non-secure masked interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MIS15 r	MIS14 r	MIS13 r	MIS12 r	MIS11 r	MIS10 r	MIS9 r	MIS8 r	MIS7 r	MIS6 r	MIS5 r	MIS4 r	MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

MIS4

Bit 4: MIS4.

MIS5

Bit 5: MIS5.

MIS6

Bit 6: MIS6.

MIS7

Bit 7: MIS7.

MIS8

Bit 8: MIS8.

MIS9

Bit 9: MIS9.

MIS10

Bit 10: MIS10.

MIS11

Bit 11: MIS11.

MIS12

Bit 12: MIS12.

MIS13

Bit 13: MIS13.

MIS14

Bit 14: MIS14.

MIS15

Bit 15: MIS15.

SMISR

secure masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MIS15 r	MIS14 r	MIS13 r	MIS12 r	MIS11 r	MIS10 r	MIS9 r	MIS8 r	MIS7 r	MIS6 r	MIS5 r	MIS4 r	MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

MIS4

Bit 4: MIS4.

MIS5

Bit 5: MIS5.

MIS6

Bit 6: MIS6.

MIS7

Bit 7: MIS7.

MIS8

Bit 8: MIS8.

MIS9

Bit 9: MIS9.

MIS10

Bit 10: MIS10.

MIS11

Bit 11: MIS11.

MIS12

Bit 12: MIS12.

MIS13

Bit 13: MIS13.

MIS14

Bit 14: MIS14.

MIS15

Bit 15: MIS15.

GPDMA_C0LBAR

channel x linked-list base address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C0FCR

GPDMA channel x flag clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C0SR

channel x status register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C0CR

channel x control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C0TR1

GPDMA channel x transfer register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

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SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C0TR2

GPDMA channel x transfer register 2

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

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REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C0BR1

GPDMA channel x block register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

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BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C0SAR

GPDMA channel x source address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

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SA

Bits 0-31: source address.

GPDMA_C0DAR

GPDMA channel x destination address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

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DA

Bits 0-31: destination address.

GPDMA_C0LLR

GPDMA channel x linked-list address register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

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LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C1LBAR

channel x linked-list base address register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C1FCR

GPDMA channel x flag clear register

Offset: 0xdc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C1SR

channel x status register

Offset: 0xe0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

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IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C1CR

channel x control register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C1TR1

GPDMA channel x transfer register 1

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C1TR2

GPDMA channel x transfer register 2

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: TRIGM mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C1BR1

GPDMA channel x block register 1

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C1SAR

GPDMA channel x source address register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C1DAR

GPDMA channel x destination address register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C1LLR

GPDMA channel x linked-list address register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C2LBAR

channel x linked-list base address register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C2FCR

GPDMA channel x flag clear register

Offset: 0x15c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C2SR

channel x status register

Offset: 0x160, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C2CR

channel x control register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C2TR1

GPDMA channel x transfer register 1

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C2TR2

GPDMA channel x transfer register 2

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C2BR1

GPDMA channel x block register 1

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C2SAR

GPDMA channel x source address register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C2DAR

GPDMA channel x destination address register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C2LLR

GPDMA channel x linked-list address register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C3LBAR

channel x linked-list base address register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C3FCR

GPDMA channel x flag clear register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C3SR

channel x status register

Offset: 0x1e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C3CR

channel x control register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel. i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C3TR1

GPDMA channel x transfer register 1

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw	DAP rw			DHX rw	DBX rw	DBL_1 rw						DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw	SAP rw	SBX rw	PAM rw			SBL_1 rw						SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

SBL_1

Bits 4-9: source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

PAM

Bits 11-12: PAM.

SBX

Bit 13: source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

Bit 14: source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DBL_1

Bits 20-25: destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed..

DBX

Bit 26: destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

Bit 27: destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word.

DAP

Bit 30: destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

GPDMA_C3TR2

GPDMA channel x transfer register 2

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C3BR1

GPDMA channel x block register 1

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C3SAR

GPDMA channel x source address register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C3DAR

GPDMA channel x destination address register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C3LLR

GPDMA channel x linked-list address register

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C4LBAR

channel x linked-list base address register

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C4FCR

GPDMA channel x flag clear register

Offset: 0x25c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C4SR

channel x status register

Offset: 0x260, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C4CR

channel x control register

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C4TR2

GPDMA channel x transfer register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode.

GPDMA_C4BR1

GPDMA channel x block register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C4SAR

GPDMA channel x source address register

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C4DAR

GPDMA channel x destination address register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C4LLR

GPDMA channel x linked-list address register

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C5LBAR

channel x linked-list base address register

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C5FCR

GPDMA channel x flag clear register

Offset: 0x2dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C5SR

channel x status register

Offset: 0x2e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C5CR

channel x control register

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C5TR2

GPDMA channel x transfer register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C5BR1

GPDMA channel x block register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C5SAR

GPDMA channel x source address register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C5DAR

GPDMA channel x destination address register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C5LLR

GPDMA channel x linked-list address register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C6LBAR

channel x linked-list base address register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C6FCR

GPDMA channel x flag clear register

Offset: 0x35c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C6SR

channel x status register

Offset: 0x360, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C6CR

channel x control register

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C6TR2

GPDMA channel x transfer register 2

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11.

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C6BR1

GPDMA channel x block register 1

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C6SAR

GPDMA channel x source address register

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C6DAR

GPDMA channel x destination address register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C6LLR

GPDMA channel x linked-list address register

Offset: 0x3cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C7LBAR

channel x linked-list base address register

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C7FCR

GPDMA channel x flag clear register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C7SR

channel x status register

Offset: 0x3e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C7CR

channel x control register

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset.

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C7TR2

GPDMA channel x transfer register 2

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C7BR1

GPDMA channel x block register 1

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C7SAR

GPDMA channel x source address register

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C7DAR

GPDMA channel x destination address register

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C7LLR

GPDMA channel x linked-list address register

Offset: 0x44c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C8LBAR

channel x linked-list base address register

Offset: 0x450, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C8FCR

GPDMA channel x flag clear register

Offset: 0x45c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C8SR

channel x status register

Offset: 0x460, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C8CR

channel x control register

Offset: 0x464, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C8TR2

GPDMA channel x transfer register 2

Offset: 0x494, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C8BR1

GPDMA channel x block register 1

Offset: 0x498, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C8SAR

GPDMA channel x source address register

Offset: 0x49c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C8DAR

GPDMA channel x destination address register

Offset: 0x4a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C8LLR

GPDMA channel x linked-list address register

Offset: 0x4cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C9LBAR

channel x linked-list base address register

Offset: 0x4d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C9FCR

GPDMA channel x flag clear register

Offset: 0x4dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C9SR

channel x status register

Offset: 0x4e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C9CR

channel x control register

Offset: 0x4e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C9TR2

GPDMA channel x transfer register 2

Offset: 0x514, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C9BR1

GPDMA channel x block register 1

Offset: 0x518, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C9SAR

GPDMA channel x source address register

Offset: 0x51c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C9DAR

GPDMA channel x destination address register

Offset: 0x520, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C9LLR

GPDMA channel x linked-list address register

Offset: 0x54c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C10LBAR

channel x linked-list base address register

Offset: 0x550, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C10FCR

GPDMA channel x flag clear register

Offset: 0x55c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C10SR

channel x status register

Offset: 0x560, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C10CR

channel x control register

Offset: 0x564, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C10TR2

GPDMA channel x transfer register 2

Offset: 0x594, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C10BR1

GPDMA channel x block register 1

Offset: 0x598, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C10SAR

GPDMA channel x source address register

Offset: 0x59c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C10DAR

GPDMA channel x destination address register

Offset: 0x5a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C10LLR

GPDMA channel x linked-list address register

Offset: 0x5cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C11LBAR

channel x linked-list base address register

Offset: 0x5d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C11FCR

GPDMA channel x flag clear register

Offset: 0x5dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C11SR

channel x status register

Offset: 0x5e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C11CR

channel x control register

Offset: 0x5e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C11TR2

GPDMA channel x transfer register 2

Offset: 0x614, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C11BR1

GPDMA channel x block register 1

Offset: 0x618, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

GPDMA_C11SAR

GPDMA channel x source address register

Offset: 0x61c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C11DAR

GPDMA channel x destination address register

Offset: 0x620, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C11LLR

GPDMA channel x linked-list address register

Offset: 0x64c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C12LBAR

channel x linked-list base address register

Offset: 0x650, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C12FCR

GPDMA channel x flag clear register

Offset: 0x65c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C12SR

channel x status register

Offset: 0x660, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C12CR

channel x control register

Offset: 0x664, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C12TR2

GPDMA channel x transfer register 2

Offset: 0x694, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C12BR1

GPDMA channel x block register 1

Offset: 0x698, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C12SAR

GPDMA channel x source address register

Offset: 0x69c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C12DAR

GPDMA channel x destination address register

Offset: 0x6a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C12TR3

GPDMA channel x transfer register 3

Offset: 0x6a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C12BR2

GPDMA channel x block register 2

Offset: 0x6a8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C12LLR

GPDMA channel x linked-list address register

Offset: 0x6cc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C13LBAR

channel x linked-list base address register

Offset: 0x6d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C13FCR

GPDMA channel x flag clear register

Offset: 0x6dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C13SR

channel x status register

Offset: 0x6e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

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IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C13CR

channel x control register

Offset: 0x6e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C13TR2

GPDMA channel x transfer register 2

Offset: 0x714, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C13BR1

GPDMA channel x block register 1

Offset: 0x718, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C13SAR

GPDMA channel x source address register

Offset: 0x71c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C13DAR

GPDMA channel x destination address register

Offset: 0x720, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C13TR3

GPDMA channel x transfer register 3

Offset: 0x724, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C13BR2

GPDMA channel x block register 2

Offset: 0x728, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C13LLR

GPDMA channel x linked-list address register

Offset: 0x74c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C14LBAR

channel x linked-list base address register

Offset: 0x750, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C14FCR

GPDMA channel x flag clear register

Offset: 0x75c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C14SR

channel x status register

Offset: 0x760, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C14CR

channel x control register

Offset: 0x764, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C14TR2

GPDMA channel x transfer register 2

Offset: 0x794, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C14BR1

GPDMA channel x block register 1

Offset: 0x798, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C14SAR

GPDMA channel x source address register

Offset: 0x79c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C14DAR

GPDMA channel x destination address register

Offset: 0x7a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C14TR3

GPDMA channel x transfer register 3

Offset: 0x7a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C14BR2

GPDMA channel x block register 2

Offset: 0x7a8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C14LLR

GPDMA channel x linked-list address register

Offset: 0x7cc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

GPDMA_C15LBAR

channel x linked-list base address register

Offset: 0x7d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

GPDMA_C15FCR

GPDMA channel x flag clear register

Offset: 0x7dc, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TOF w	SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

TOF

Bit 14: trigger overrun flag clear.

GPDMA_C15SR

channel x status register

Offset: 0x7e0, size: 32, reset: 0x00000001, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

FIFOL

Bits 16-23: monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1..

GPDMA_C15CR

channel x control register

Offset: 0x7e4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw						LAP rw	LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

LAP

Bit 17: linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

GPDMA_C15TR2

GPDMA channel x transfer register 2

Offset: 0x814, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw				TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw	DREQ rw	SWREQ rw			REQSEL rw

Toggle fields

REQSEL

Bits 0-6: DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

DREQ

Bit 10: Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port).

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger..

TRIGSEL

Bits 16-21: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

GPDMA_C15BR1

GPDMA channel x block register 1

Offset: 0x818, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDDEC rw	BRSDEC rw	DDEC rw	SDEC rw		BRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

BRC

Bits 16-26: BRC.

SDEC

Bit 28: SDEC.

DDEC

Bit 29: DDEC.

BRSDEC

Bit 30: BRSDEC.

BRDDEC

Bit 31: BRDDEC.

GPDMA_C15SAR

GPDMA channel x source address register

Offset: 0x81c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

GPDMA_C15DAR

GPDMA channel x destination address register

Offset: 0x820, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

GPDMA_C15TR3

GPDMA channel x transfer register 3

Offset: 0x824, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			DAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SAO rw

Toggle fields

SAO

Bits 0-12: source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DAO

Bits 16-28: destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied..

GPDMA_C15BR2

GPDMA channel x block register 2

Offset: 0x828, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BRDAO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRSAO rw

Toggle fields

BRSAO

Bits 0-15: Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

BRDAO

Bits 16-31: Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

GPDMA_C15LLR

GPDMA channel x linked-list address register

Offset: 0x84c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw	UT3 rw	UB2 rw									ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update.

UB2

Bit 25: Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update.

UT3

Bit 26: Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update.

UDA

Bit 27: Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update.

USA

Bit 28: Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update.

UB1

Bit 29: Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update.

UT2

Bit 30: Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update.

UT1

Bit 31: Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update.

SEC_GPIOA

0x52020000: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GPIOB

0x52020400: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GPIOC

0x52020800: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GPIOD

0x52020c00: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GPIOE

0x52021000: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GPIOG

0x52021800: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GPIOH

0x52021c00: General-purpose I/Os

16/209 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GPIO_MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	GPIO_OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	GPIO_OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	GPIO_PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	GPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	GPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	GPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	GPIO_LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	GPIO_AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	GPIO_AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	GPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0
0x2c	GPIO_HSLVR																	HSLV15	HSLV14	HSLV13	HSLV12	HSLV11	HSLV10	HSLV9	HSLV8	HSLV7	HSLV6	HSLV5	HSLV4	HSLV3	HSLV2	HSLV1	HSLV0
0x30	GPIO_SECCFGR																	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0

Toggle registers

GPIO_MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

MODE15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT1

Bit 1: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT2

Bit 2: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT3

Bit 3: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT4

Bit 4: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT5

Bit 5: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT6

Bit 6: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT7

Bit 7: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT8

Bit 8: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT9

Bit 9: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT10

Bit 10: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT11

Bit 11: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT12

Bit 12: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT13

Bit 13: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT14

Bit 14: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OT15

Bit 15: Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OSPEED15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD1

Bits 2-3: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD2

Bits 4-5: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD3

Bits 6-7: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD4

Bits 8-9: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD5

Bits 10-11: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD6

Bits 12-13: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD7

Bits 14-15: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD8

Bits 16-17: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD9

Bits 18-19: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD10

Bits 20-21: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD11

Bits 22-23: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD12

Bits 24-25: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD13

Bits 26-27: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD14

Bits 28-29: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

PUPD15

Bits 30-31: Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID1

Bit 1: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID2

Bit 2: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID3

Bit 3: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID4

Bit 4: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID5

Bit 5: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID6

Bit 6: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID7

Bit 7: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID8

Bit 8: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID9

Bit 9: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID10

Bit 10: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID11

Bit 11: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID12

Bit 12: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID13

Bit 13: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID14

Bit 14: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

ID15

Bit 15: Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD1

Bit 1: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD2

Bit 2: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD3

Bit 3: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD4

Bit 4: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD5

Bit 5: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD6

Bit 6: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD7

Bit 7: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD8

Bit 8: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD9

Bit 9: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD10

Bit 10: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD11

Bit 11: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD12

Bit 12: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD13

Bit 13: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD14

Bit 14: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

OD15

Bit 15: Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS1

Bit 1: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS2

Bit 2: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS3

Bit 3: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS4

Bit 4: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS5

Bit 5: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS6

Bit 6: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS7

Bit 7: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS8

Bit 8: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS9

Bit 9: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS10

Bit 10: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS11

Bit 11: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS12

Bit 12: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS13

Bit 13: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS14

Bit 14: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BS15

Bit 15: Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR0

Bit 16: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 17: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 18: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 19: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 20: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 21: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 22: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 23: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 24: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 25: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 26: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 27: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 28: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 29: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 30: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 31: Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK1

Bit 1: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK2

Bit 2: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK3

Bit 3: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK4

Bit 4: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK5

Bit 5: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK6

Bit 6: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK7

Bit 7: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK8

Bit 8: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK9

Bit 9: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK10

Bit 10: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK11

Bit 11: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK12

Bit 12: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK13

Bit 13: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK14

Bit 14: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCK15

Bit 15: Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

GPIO_AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL1

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL2

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL3

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL4

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL5

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL6

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL7

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL9

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL10

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL11

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL12

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL13

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL14

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

AFSEL15

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR1

Bit 1: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR2

Bit 2: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR3

Bit 3: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR4

Bit 4: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR5

Bit 5: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR6

Bit 6: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR7

Bit 7: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR8

Bit 8: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR9

Bit 9: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR10

Bit 10: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR11

Bit 11: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR12

Bit 12: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR13

Bit 13: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR14

Bit 14: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

BR15

Bit 15: Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_HSLVR

GPIO high-speed low-voltage register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSLV15 rw	HSLV14 rw	HSLV13 rw	HSLV12 rw	HSLV11 rw	HSLV10 rw	HSLV9 rw	HSLV8 rw	HSLV7 rw	HSLV6 rw	HSLV5 rw	HSLV4 rw	HSLV3 rw	HSLV2 rw	HSLV1 rw	HSLV0 rw

Toggle fields

HSLV0

Bit 0: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV1

Bit 1: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV2

Bit 2: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV3

Bit 3: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV4

Bit 4: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV5

Bit 5: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV6

Bit 6: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV7

Bit 7: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV8

Bit 8: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV9

Bit 9: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV10

Bit 10: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV11

Bit 11: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV12

Bit 12: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV13

Bit 13: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV14

Bit 14: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

HSLV15

Bit 15: Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package..

GPIO_SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x0000FFFF, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC1

Bit 1: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC2

Bit 2: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC3

Bit 3: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC4

Bit 4: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC5

Bit 5: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC6

Bit 6: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC7

Bit 7: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC8

Bit 8: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC9

Bit 9: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC10

Bit 10: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC11

Bit 11: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC12

Bit 12: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC13

Bit 13: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC14

Bit 14: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC15

Bit 15: I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package..

SEC_GTZC1_MPCBB1

0x50032c00: GTZC1_MPCBB1

0/3383 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MPCBB1_CR	SRWILADIS	INVSECSTATE																														GLOCK
0x10	MPCBB1_CFGLOCK1	SPLCK31	SPLCK30	SPLCK29	SPLCK28	SPLCK27	SPLCK26	SPLCK25	SPLCK24	SPLCK23	SPLCK22	SPLCK21	SPLCK20	SPLCK19	SPLCK18	SPLCK17	SPLCK16	SPLCK15	SPLCK14	SPLCK13	SPLCK12	SPLCK11	SPLCK10	SPLCK9	SPLCK8	SPLCK7	SPLCK6	SPLCK5	SPLCK4	SPLCK3	SPLCK2	SPLCK1	SPLCK0
0x14	MPCBB1_CFGLOCK2													SPLCK51	SPLCK50	SPLCK49	SPLCK48	SPLCK47	SPLCK46	SPLCK45	SPLCK44	SPLCK43	SPLCK42	SPLCK41	SPLCK40	SPLCK39	SPLCK38	SPLCK37	SPLCK36	SPLCK35	SPLCK34	SPLCK33	SPLCK32
0x100	MPCBB1_SECCFGR0	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x104	MPCBB1_SECCFGR1	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x108	MPCBB1_SECCFGR2	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x10c	MPCBB1_SECCFGR3	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x110	MPCBB1_SECCFGR4	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x114	MPCBB1_SECCFGR5	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x118	MPCBB1_SECCFGR6	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x11c	MPCBB1_SECCFGR7	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x120	MPCBB1_SECCFGR8	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x124	MPCBB1_SECCFGR9	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x128	MPCBB1_SECCFGR10	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x12c	MPCBB1_SECCFGR11	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x130	MPCBB1_SECCFGR12	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x134	MPCBB1_SECCFGR13	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x138	MPCBB1_SECCFGR14	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x13c	MPCBB1_SECCFGR15	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x140	MPCBB1_SECCFGR16	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x144	MPCBB1_SECCFGR17	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x148	MPCBB1_SECCFGR18	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x14c	MPCBB1_SECCFGR19	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x150	MPCBB1_SECCFGR20	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x154	MPCBB1_SECCFGR21	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x158	MPCBB1_SECCFGR22	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x15c	MPCBB1_SECCFGR23	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x160	MPCBB1_SECCFGR24	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x164	MPCBB1_SECCFGR25	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x168	MPCBB1_SECCFGR26	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x16c	MPCBB1_SECCFGR27	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x170	MPCBB1_SECCFGR28	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x174	MPCBB1_SECCFGR29	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x178	MPCBB1_SECCFGR30	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x17c	MPCBB1_SECCFGR31	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x180	MPCBB1_SECCFGR32	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x184	MPCBB1_SECCFGR33	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x188	MPCBB1_SECCFGR34	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x18c	MPCBB1_SECCFGR35	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x190	MPCBB1_SECCFGR36	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x194	MPCBB1_SECCFGR37	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x198	MPCBB1_SECCFGR38	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x19c	MPCBB1_SECCFGR39	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a0	MPCBB1_SECCFGR40	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a4	MPCBB1_SECCFGR41	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a8	MPCBB1_SECCFGR42	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1ac	MPCBB1_SECCFGR43	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b0	MPCBB1_SECCFGR44	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b4	MPCBB1_SECCFGR45	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b8	MPCBB1_SECCFGR46	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1bc	MPCBB1_SECCFGR47	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c0	MPCBB1_SECCFGR48	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c4	MPCBB1_SECCFGR49	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c8	MPCBB1_SECCFGR50	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1cc	MPCBB1_SECCFGR51	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x200	MPCBB1_PRIVCFGR0	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x204	MPCBB1_PRIVCFGR1	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x208	MPCBB1_PRIVCFGR2	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x20c	MPCBB1_PRIVCFGR3	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x210	MPCBB1_PRIVCFGR4	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x214	MPCBB1_PRIVCFGR5	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x218	MPCBB1_PRIVCFGR6	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x21c	MPCBB1_PRIVCFGR7	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x220	MPCBB1_PRIVCFGR8	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x224	MPCBB1_PRIVCFGR9	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x228	MPCBB1_PRIVCFGR10	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x22c	MPCBB1_PRIVCFGR11	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x230	MPCBB1_PRIVCFGR12	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x234	MPCBB1_PRIVCFGR13	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x238	MPCBB1_PRIVCFGR14	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x23c	MPCBB1_PRIVCFGR15	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x240	MPCBB1_PRIVCFGR16	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x244	MPCBB1_PRIVCFGR17	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x248	MPCBB1_PRIVCFGR18	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x24c	MPCBB1_PRIVCFGR19	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x250	MPCBB1_PRIVCFGR20	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x254	MPCBB1_PRIVCFGR21	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x258	MPCBB1_PRIVCFGR22	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x25c	MPCBB1_PRIVCFGR23	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x260	MPCBB1_PRIVCFGR24	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x264	MPCBB1_PRIVCFGR25	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x268	MPCBB1_PRIVCFGR26	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x26c	MPCBB1_PRIVCFGR27	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x270	MPCBB1_PRIVCFGR28	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x274	MPCBB1_PRIVCFGR29	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x278	MPCBB1_PRIVCFGR30	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x27c	MPCBB1_PRIVCFGR31	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x280	MPCBB1_PRIVCFGR32	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x284	MPCBB1_PRIVCFGR33	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x288	MPCBB1_PRIVCFGR34	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x28c	MPCBB1_PRIVCFGR35	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x290	MPCBB1_PRIVCFGR36	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x294	MPCBB1_PRIVCFGR37	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x298	MPCBB1_PRIVCFGR38	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x29c	MPCBB1_PRIVCFGR39	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a0	MPCBB1_PRIVCFGR40	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a4	MPCBB1_PRIVCFGR41	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a8	MPCBB1_PRIVCFGR42	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2ac	MPCBB1_PRIVCFGR43	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b0	MPCBB1_PRIVCFGR44	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b4	MPCBB1_PRIVCFGR45	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b8	MPCBB1_PRIVCFGR46	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2bc	MPCBB1_PRIVCFGR47	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c0	MPCBB1_PRIVCFGR48	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c4	MPCBB1_PRIVCFGR49	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c8	MPCBB1_PRIVCFGR50	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2cc	MPCBB1_PRIVCFGR51	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0

Toggle registers

MPCBB1_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRWILADIS rw	INVSECSTATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															GLOCK rw

Toggle fields

GLOCK

Bit 0: lock the control register of the MPCBB until next reset.

INVSECSTATE

Bit 30: SRAMx clocks security state.

SRWILADIS

Bit 31: secure read/write illegal access disable.

MPCBB1_CFGLOCK1

GTZC1 SRAMz MPCBB configuration lock register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SPLCK31 rw	SPLCK30 rw	SPLCK29 rw	SPLCK28 rw	SPLCK27 rw	SPLCK26 rw	SPLCK25 rw	SPLCK24 rw	SPLCK23 rw	SPLCK22 rw	SPLCK21 rw	SPLCK20 rw	SPLCK19 rw	SPLCK18 rw	SPLCK17 rw	SPLCK16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK15 rw	SPLCK14 rw	SPLCK13 rw	SPLCK12 rw	SPLCK11 rw	SPLCK10 rw	SPLCK9 rw	SPLCK8 rw	SPLCK7 rw	SPLCK6 rw	SPLCK5 rw	SPLCK4 rw	SPLCK3 rw	SPLCK2 rw	SPLCK1 rw	SPLCK0 rw

Toggle fields

SPLCK0

Bit 0: SPLCK0.

SPLCK1

Bit 1: SPLCK1.

SPLCK2

Bit 2: SPLCK2.

SPLCK3

Bit 3: SPLCK3.

SPLCK4

Bit 4: SPLCK4.

SPLCK5

Bit 5: SPLCK5.

SPLCK6

Bit 6: SPLCK6.

SPLCK7

Bit 7: SPLCK7.

SPLCK8

Bit 8: SPLCK8.

SPLCK9

Bit 9: SPLCK9.

SPLCK10

Bit 10: SPLCK10.

SPLCK11

Bit 11: SPLCK11.

SPLCK12

Bit 12: SPLCK12.

SPLCK13

Bit 13: SPLCK13.

SPLCK14

Bit 14: SPLCK14.

SPLCK15

Bit 15: SPLCK15.

SPLCK16

Bit 16: SPLCK16.

SPLCK17

Bit 17: SPLCK17.

SPLCK18

Bit 18: SPLCK18.

SPLCK19

Bit 19: SPLCK19.

SPLCK20

Bit 20: SPLCK20.

SPLCK21

Bit 21: SPLCK21.

SPLCK22

Bit 22: SPLCK22.

SPLCK23

Bit 23: SPLCK23.

SPLCK24

Bit 24: SPLCK24.

SPLCK25

Bit 25: SPLCK25.

SPLCK26

Bit 26: SPLCK26.

SPLCK27

Bit 27: SPLCK27.

SPLCK28

Bit 28: SPLCK28.

SPLCK29

Bit 29: SPLCK29.

SPLCK30

Bit 30: SPLCK30.

SPLCK31

Bit 31: SPLCK31.

MPCBB1_CFGLOCK2

GTZC1 SRAMz MPCBB configuration lock register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												SPLCK51 rw	SPLCK50 rw	SPLCK49 rw	SPLCK48 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK47 rw	SPLCK46 rw	SPLCK45 rw	SPLCK44 rw	SPLCK43 rw	SPLCK42 rw	SPLCK41 rw	SPLCK40 rw	SPLCK39 rw	SPLCK38 rw	SPLCK37 rw	SPLCK36 rw	SPLCK35 rw	SPLCK34 rw	SPLCK33 rw	SPLCK32 rw

Toggle fields

SPLCK32

Bit 0: SPLCK32.

SPLCK33

Bit 1: SPLCK33.

SPLCK34

Bit 2: SPLCK34.

SPLCK35

Bit 3: SPLCK35.

SPLCK36

Bit 4: SPLCK36.

SPLCK37

Bit 5: SPLCK37.

SPLCK38

Bit 6: SPLCK38.

SPLCK39

Bit 7: SPLCK39.

SPLCK40

Bit 8: SPLCK40.

SPLCK41

Bit 9: SPLCK41.

SPLCK42

Bit 10: SPLCK42.

SPLCK43

Bit 11: SPLCK43.

SPLCK44

Bit 12: SPLCK44.

SPLCK45

Bit 13: SPLCK45.

SPLCK46

Bit 14: SPLCK46.

SPLCK47

Bit 15: SPLCK47.

SPLCK48

Bit 16: SPLCK48.

SPLCK49

Bit 17: SPLCK49.

SPLCK50

Bit 18: SPLCK50.

SPLCK51

Bit 19: SPLCK51.

MPCBB1_SECCFGR0

MPCBBx security configuration for super-block x register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR1

MPCBBx security configuration for super-block x register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR2

MPCBBx security configuration for super-block x register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR3

MPCBBx security configuration for super-block x register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR4

MPCBBx security configuration for super-block x register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR5

MPCBBx security configuration for super-block x register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR6

MPCBBx security configuration for super-block x register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR7

MPCBBx security configuration for super-block x register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR8

MPCBBx security configuration for super-block x register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR9

MPCBBx security configuration for super-block x register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR10

MPCBBx security configuration for super-block x register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR11

MPCBBx security configuration for super-block x register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR12

MPCBBx security configuration for super-block x register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR13

MPCBBx security configuration for super-block x register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR14

MPCBBx security configuration for super-block x register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR15

MPCBBx security configuration for super-block x register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR16

MPCBBx security configuration for super-block x register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR17

MPCBBx security configuration for super-block x register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR18

MPCBBx security configuration for super-block x register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR19

MPCBBx security configuration for super-block x register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR20

MPCBBx security configuration for super-block x register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR21

MPCBBx security configuration for super-block x register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR22

MPCBBx security configuration for super-block x register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR23

MPCBBx security configuration for super-block x register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR24

MPCBBx security configuration for super-block x register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR25

MPCBBx security configuration for super-block x register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR26

MPCBBx security configuration for super-block x register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR27

MPCBBx security configuration for super-block x register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR28

MPCBBx security configuration for super-block x register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR29

MPCBBx security configuration for super-block x register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR30

MPCBBx security configuration for super-block x register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR31

MPCBBx security configuration for super-block x register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR32

MPCBBx security configuration for super-block x register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR33

MPCBBx security configuration for super-block x register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR34

MPCBBx security configuration for super-block x register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR35

MPCBBx security configuration for super-block x register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR36

MPCBBx security configuration for super-block x register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR37

MPCBBx security configuration for super-block x register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR38

MPCBBx security configuration for super-block x register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR39

MPCBBx security configuration for super-block x register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR40

MPCBBx security configuration for super-block x register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR41

MPCBBx security configuration for super-block x register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR42

MPCBBx security configuration for super-block x register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR43

MPCBBx security configuration for super-block x register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR44

MPCBBx security configuration for super-block x register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR45

MPCBBx security configuration for super-block x register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR46

MPCBBx security configuration for super-block x register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR47

MPCBBx security configuration for super-block x register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR48

MPCBBx security configuration for super-block x register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR49

MPCBBx security configuration for super-block x register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR50

MPCBBx security configuration for super-block x register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_SECCFGR51

MPCBBx security configuration for super-block x register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB1_PRIVCFGR0

MPCBB privileged configuration for super-block x register

Offset: 0x200, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR1

MPCBB privileged configuration for super-block x register

Offset: 0x204, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR2

MPCBB privileged configuration for super-block x register

Offset: 0x208, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR3

MPCBB privileged configuration for super-block x register

Offset: 0x20c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR4

MPCBB privileged configuration for super-block x register

Offset: 0x210, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR5

MPCBB privileged configuration for super-block x register

Offset: 0x214, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR6

MPCBB privileged configuration for super-block x register

Offset: 0x218, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR7

MPCBB privileged configuration for super-block x register

Offset: 0x21c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR8

MPCBB privileged configuration for super-block x register

Offset: 0x220, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR9

MPCBB privileged configuration for super-block x register

Offset: 0x224, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR10

MPCBB privileged configuration for super-block x register

Offset: 0x228, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR11

MPCBB privileged configuration for super-block x register

Offset: 0x22c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR12

MPCBB privileged configuration for super-block x register

Offset: 0x230, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR13

MPCBB privileged configuration for super-block x register

Offset: 0x234, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR14

MPCBB privileged configuration for super-block x register

Offset: 0x238, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR15

MPCBB privileged configuration for super-block x register

Offset: 0x23c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR16

MPCBB privileged configuration for super-block x register

Offset: 0x240, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR17

MPCBB privileged configuration for super-block x register

Offset: 0x244, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR18

MPCBB privileged configuration for super-block x register

Offset: 0x248, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR19

MPCBB privileged configuration for super-block x register

Offset: 0x24c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR20

MPCBB privileged configuration for super-block x register

Offset: 0x250, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR21

MPCBB privileged configuration for super-block x register

Offset: 0x254, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR22

MPCBB privileged configuration for super-block x register

Offset: 0x258, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR23

MPCBB privileged configuration for super-block x register

Offset: 0x25c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR24

MPCBB privileged configuration for super-block x register

Offset: 0x260, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR25

MPCBB privileged configuration for super-block x register

Offset: 0x264, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR26

MPCBB privileged configuration for super-block x register

Offset: 0x268, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR27

MPCBB privileged configuration for super-block x register

Offset: 0x26c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR28

MPCBB privileged configuration for super-block x register

Offset: 0x270, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR29

MPCBB privileged configuration for super-block x register

Offset: 0x274, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR30

MPCBB privileged configuration for super-block x register

Offset: 0x278, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR31

MPCBB privileged configuration for super-block x register

Offset: 0x27c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR32

MPCBB privileged configuration for super-block x register

Offset: 0x280, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR33

MPCBB privileged configuration for super-block x register

Offset: 0x284, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR34

MPCBB privileged configuration for super-block x register

Offset: 0x288, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR35

MPCBB privileged configuration for super-block x register

Offset: 0x28c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR36

MPCBB privileged configuration for super-block x register

Offset: 0x290, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR37

MPCBB privileged configuration for super-block x register

Offset: 0x294, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR38

MPCBB privileged configuration for super-block x register

Offset: 0x298, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR39

MPCBB privileged configuration for super-block x register

Offset: 0x29c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR40

MPCBB privileged configuration for super-block x register

Offset: 0x2a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR41

MPCBB privileged configuration for super-block x register

Offset: 0x2a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR42

MPCBB privileged configuration for super-block x register

Offset: 0x2a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR43

MPCBB privileged configuration for super-block x register

Offset: 0x2ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR44

MPCBB privileged configuration for super-block x register

Offset: 0x2b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR45

MPCBB privileged configuration for super-block x register

Offset: 0x2b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR46

MPCBB privileged configuration for super-block x register

Offset: 0x2b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR47

MPCBB privileged configuration for super-block x register

Offset: 0x2bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR48

MPCBB privileged configuration for super-block x register

Offset: 0x2c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR49

MPCBB privileged configuration for super-block x register

Offset: 0x2c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR50

MPCBB privileged configuration for super-block x register

Offset: 0x2c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB1_PRIVCFGR51

MPCBB privileged configuration for super-block x register

Offset: 0x2cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

SEC_GTZC1_MPCBB2

0x50033000: GTZC1_MPCBB2

0/3383 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MPCBB2_CR	SRWILADIS	INVSECSTATE																														GLOCK
0x10	MPCBB2_CFGLOCK1	SPLCK31	SPLCK30	SPLCK29	SPLCK28	SPLCK27	SPLCK26	SPLCK25	SPLCK24	SPLCK23	SPLCK22	SPLCK21	SPLCK20	SPLCK19	SPLCK18	SPLCK17	SPLCK16	SPLCK15	SPLCK14	SPLCK13	SPLCK12	SPLCK11	SPLCK10	SPLCK9	SPLCK8	SPLCK7	SPLCK6	SPLCK5	SPLCK4	SPLCK3	SPLCK2	SPLCK1	SPLCK0
0x14	MPCBB2_CFGLOCK2													SPLCK51	SPLCK50	SPLCK49	SPLCK48	SPLCK47	SPLCK46	SPLCK45	SPLCK44	SPLCK43	SPLCK42	SPLCK41	SPLCK40	SPLCK39	SPLCK38	SPLCK37	SPLCK36	SPLCK35	SPLCK34	SPLCK33	SPLCK32
0x100	MPCBB2_SECCFGR0	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x104	MPCBB2_SECCFGR1	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x108	MPCBB2_SECCFGR2	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x10c	MPCBB2_SECCFGR3	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x110	MPCBB2_SECCFGR4	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x114	MPCBB2_SECCFGR5	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x118	MPCBB2_SECCFGR6	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x11c	MPCBB2_SECCFGR7	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x120	MPCBB2_SECCFGR8	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x124	MPCBB2_SECCFGR9	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x128	MPCBB2_SECCFGR10	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x12c	MPCBB2_SECCFGR11	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x130	MPCBB2_SECCFGR12	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x134	MPCBB2_SECCFGR13	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x138	MPCBB2_SECCFGR14	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x13c	MPCBB2_SECCFGR15	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x140	MPCBB2_SECCFGR16	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x144	MPCBB2_SECCFGR17	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x148	MPCBB2_SECCFGR18	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x14c	MPCBB2_SECCFGR19	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x150	MPCBB2_SECCFGR20	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x154	MPCBB2_SECCFGR21	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x158	MPCBB2_SECCFGR22	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x15c	MPCBB2_SECCFGR23	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x160	MPCBB2_SECCFGR24	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x164	MPCBB2_SECCFGR25	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x168	MPCBB2_SECCFGR26	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x16c	MPCBB2_SECCFGR27	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x170	MPCBB2_SECCFGR28	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x174	MPCBB2_SECCFGR29	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x178	MPCBB2_SECCFGR30	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x17c	MPCBB2_SECCFGR31	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x180	MPCBB2_SECCFGR32	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x184	MPCBB2_SECCFGR33	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x188	MPCBB2_SECCFGR34	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x18c	MPCBB2_SECCFGR35	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x190	MPCBB2_SECCFGR36	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x194	MPCBB2_SECCFGR37	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x198	MPCBB2_SECCFGR38	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x19c	MPCBB2_SECCFGR39	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a0	MPCBB2_SECCFGR40	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a4	MPCBB2_SECCFGR41	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1a8	MPCBB2_SECCFGR42	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1ac	MPCBB2_SECCFGR43	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b0	MPCBB2_SECCFGR44	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b4	MPCBB2_SECCFGR45	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1b8	MPCBB2_SECCFGR46	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1bc	MPCBB2_SECCFGR47	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c0	MPCBB2_SECCFGR48	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c4	MPCBB2_SECCFGR49	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1c8	MPCBB2_SECCFGR50	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x1cc	MPCBB2_SECCFGR51	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x200	MPCBB2_PRIVCFGR0	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x204	MPCBB2_PRIVCFGR1	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x208	MPCBB2_PRIVCFGR2	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x20c	MPCBB2_PRIVCFGR3	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x210	MPCBB2_PRIVCFGR4	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x214	MPCBB2_PRIVCFGR5	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x218	MPCBB2_PRIVCFGR6	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x21c	MPCBB2_PRIVCFGR7	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x220	MPCBB2_PRIVCFGR8	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x224	MPCBB2_PRIVCFGR9	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x228	MPCBB2_PRIVCFGR10	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x22c	MPCBB2_PRIVCFGR11	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x230	MPCBB2_PRIVCFGR12	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x234	MPCBB2_PRIVCFGR13	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x238	MPCBB2_PRIVCFGR14	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x23c	MPCBB2_PRIVCFGR15	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x240	MPCBB2_PRIVCFGR16	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x244	MPCBB2_PRIVCFGR17	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x248	MPCBB2_PRIVCFGR18	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x24c	MPCBB2_PRIVCFGR19	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x250	MPCBB2_PRIVCFGR20	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x254	MPCBB2_PRIVCFGR21	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x258	MPCBB2_PRIVCFGR22	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x25c	MPCBB2_PRIVCFGR23	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x260	MPCBB2_PRIVCFGR24	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x264	MPCBB2_PRIVCFGR25	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x268	MPCBB2_PRIVCFGR26	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x26c	MPCBB2_PRIVCFGR27	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x270	MPCBB2_PRIVCFGR28	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x274	MPCBB2_PRIVCFGR29	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x278	MPCBB2_PRIVCFGR30	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x27c	MPCBB2_PRIVCFGR31	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x280	MPCBB2_PRIVCFGR32	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x284	MPCBB2_PRIVCFGR33	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x288	MPCBB2_PRIVCFGR34	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x28c	MPCBB2_PRIVCFGR35	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x290	MPCBB2_PRIVCFGR36	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x294	MPCBB2_PRIVCFGR37	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x298	MPCBB2_PRIVCFGR38	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x29c	MPCBB2_PRIVCFGR39	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a0	MPCBB2_PRIVCFGR40	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a4	MPCBB2_PRIVCFGR41	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2a8	MPCBB2_PRIVCFGR42	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2ac	MPCBB2_PRIVCFGR43	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b0	MPCBB2_PRIVCFGR44	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b4	MPCBB2_PRIVCFGR45	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2b8	MPCBB2_PRIVCFGR46	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2bc	MPCBB2_PRIVCFGR47	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c0	MPCBB2_PRIVCFGR48	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c4	MPCBB2_PRIVCFGR49	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2c8	MPCBB2_PRIVCFGR50	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x2cc	MPCBB2_PRIVCFGR51	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0

Toggle registers

MPCBB2_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRWILADIS rw	INVSECSTATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															GLOCK rw

Toggle fields

GLOCK

Bit 0: lock the control register of the MPCBB until next reset.

INVSECSTATE

Bit 30: SRAMx clocks security state.

SRWILADIS

Bit 31: secure read/write illegal access disable.

MPCBB2_CFGLOCK1

GTZC1 SRAMz MPCBB configuration lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SPLCK31 rw	SPLCK30 rw	SPLCK29 rw	SPLCK28 rw	SPLCK27 rw	SPLCK26 rw	SPLCK25 rw	SPLCK24 rw	SPLCK23 rw	SPLCK22 rw	SPLCK21 rw	SPLCK20 rw	SPLCK19 rw	SPLCK18 rw	SPLCK17 rw	SPLCK16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK15 rw	SPLCK14 rw	SPLCK13 rw	SPLCK12 rw	SPLCK11 rw	SPLCK10 rw	SPLCK9 rw	SPLCK8 rw	SPLCK7 rw	SPLCK6 rw	SPLCK5 rw	SPLCK4 rw	SPLCK3 rw	SPLCK2 rw	SPLCK1 rw	SPLCK0 rw

Toggle fields

SPLCK0

Bit 0: SPLCK0.

SPLCK1

Bit 1: SPLCK1.

SPLCK2

Bit 2: SPLCK2.

SPLCK3

Bit 3: SPLCK3.

SPLCK4

Bit 4: SPLCK4.

SPLCK5

Bit 5: SPLCK5.

SPLCK6

Bit 6: SPLCK6.

SPLCK7

Bit 7: SPLCK7.

SPLCK8

Bit 8: SPLCK8.

SPLCK9

Bit 9: SPLCK9.

SPLCK10

Bit 10: SPLCK10.

SPLCK11

Bit 11: SPLCK11.

SPLCK12

Bit 12: SPLCK12.

SPLCK13

Bit 13: SPLCK13.

SPLCK14

Bit 14: SPLCK14.

SPLCK15

Bit 15: SPLCK15.

SPLCK16

Bit 16: SPLCK16.

SPLCK17

Bit 17: SPLCK17.

SPLCK18

Bit 18: SPLCK18.

SPLCK19

Bit 19: SPLCK19.

SPLCK20

Bit 20: SPLCK20.

SPLCK21

Bit 21: SPLCK21.

SPLCK22

Bit 22: SPLCK22.

SPLCK23

Bit 23: SPLCK23.

SPLCK24

Bit 24: SPLCK24.

SPLCK25

Bit 25: SPLCK25.

SPLCK26

Bit 26: SPLCK26.

SPLCK27

Bit 27: SPLCK27.

SPLCK28

Bit 28: SPLCK28.

SPLCK29

Bit 29: SPLCK29.

SPLCK30

Bit 30: SPLCK30.

SPLCK31

Bit 31: SPLCK31.

MPCBB2_CFGLOCK2

GTZC1 SRAMz MPCBB configuration lock register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												SPLCK51 rw	SPLCK50 rw	SPLCK49 rw	SPLCK48 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPLCK47 rw	SPLCK46 rw	SPLCK45 rw	SPLCK44 rw	SPLCK43 rw	SPLCK42 rw	SPLCK41 rw	SPLCK40 rw	SPLCK39 rw	SPLCK38 rw	SPLCK37 rw	SPLCK36 rw	SPLCK35 rw	SPLCK34 rw	SPLCK33 rw	SPLCK32 rw

Toggle fields

SPLCK32

Bit 0: SPLCK32.

SPLCK33

Bit 1: SPLCK33.

SPLCK34

Bit 2: SPLCK34.

SPLCK35

Bit 3: SPLCK35.

SPLCK36

Bit 4: SPLCK36.

SPLCK37

Bit 5: SPLCK37.

SPLCK38

Bit 6: SPLCK38.

SPLCK39

Bit 7: SPLCK39.

SPLCK40

Bit 8: SPLCK40.

SPLCK41

Bit 9: SPLCK41.

SPLCK42

Bit 10: SPLCK42.

SPLCK43

Bit 11: SPLCK43.

SPLCK44

Bit 12: SPLCK44.

SPLCK45

Bit 13: SPLCK45.

SPLCK46

Bit 14: SPLCK46.

SPLCK47

Bit 15: SPLCK47.

SPLCK48

Bit 16: SPLCK48.

SPLCK49

Bit 17: SPLCK49.

SPLCK50

Bit 18: SPLCK50.

SPLCK51

Bit 19: SPLCK51.

MPCBB2_SECCFGR0

MPCBBx security configuration for super-block x register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR1

MPCBBx security configuration for super-block x register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR2

MPCBBx security configuration for super-block x register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR3

MPCBBx security configuration for super-block x register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR4

MPCBBx security configuration for super-block x register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR5

MPCBBx security configuration for super-block x register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR6

MPCBBx security configuration for super-block x register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR7

MPCBBx security configuration for super-block x register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR8

MPCBBx security configuration for super-block x register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR9

MPCBBx security configuration for super-block x register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR10

MPCBBx security configuration for super-block x register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR11

MPCBBx security configuration for super-block x register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR12

MPCBBx security configuration for super-block x register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR13

MPCBBx security configuration for super-block x register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR14

MPCBBx security configuration for super-block x register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR15

MPCBBx security configuration for super-block x register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR16

MPCBBx security configuration for super-block x register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR17

MPCBBx security configuration for super-block x register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR18

MPCBBx security configuration for super-block x register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR19

MPCBBx security configuration for super-block x register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR20

MPCBBx security configuration for super-block x register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR21

MPCBBx security configuration for super-block x register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR22

MPCBBx security configuration for super-block x register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR23

MPCBBx security configuration for super-block x register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR24

MPCBBx security configuration for super-block x register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR25

MPCBBx security configuration for super-block x register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR26

MPCBBx security configuration for super-block x register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR27

MPCBBx security configuration for super-block x register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR28

MPCBBx security configuration for super-block x register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR29

MPCBBx security configuration for super-block x register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR30

MPCBBx security configuration for super-block x register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR31

MPCBBx security configuration for super-block x register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR32

MPCBBx security configuration for super-block x register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR33

MPCBBx security configuration for super-block x register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR34

MPCBBx security configuration for super-block x register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR35

MPCBBx security configuration for super-block x register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR36

MPCBBx security configuration for super-block x register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR37

MPCBBx security configuration for super-block x register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR38

MPCBBx security configuration for super-block x register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR39

MPCBBx security configuration for super-block x register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR40

MPCBBx security configuration for super-block x register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR41

MPCBBx security configuration for super-block x register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR42

MPCBBx security configuration for super-block x register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR43

MPCBBx security configuration for super-block x register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR44

MPCBBx security configuration for super-block x register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR45

MPCBBx security configuration for super-block x register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR46

MPCBBx security configuration for super-block x register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR47

MPCBBx security configuration for super-block x register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR48

MPCBBx security configuration for super-block x register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR49

MPCBBx security configuration for super-block x register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR50

MPCBBx security configuration for super-block x register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_SECCFGR51

MPCBBx security configuration for super-block x register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB2_PRIVCFGR0

MPCBB privileged configuration for super-block x register

Offset: 0x200, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR1

MPCBB privileged configuration for super-block x register

Offset: 0x204, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR2

MPCBB privileged configuration for super-block x register

Offset: 0x208, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR3

MPCBB privileged configuration for super-block x register

Offset: 0x20c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR4

MPCBB privileged configuration for super-block x register

Offset: 0x210, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR5

MPCBB privileged configuration for super-block x register

Offset: 0x214, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR6

MPCBB privileged configuration for super-block x register

Offset: 0x218, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR7

MPCBB privileged configuration for super-block x register

Offset: 0x21c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR8

MPCBB privileged configuration for super-block x register

Offset: 0x220, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR9

MPCBB privileged configuration for super-block x register

Offset: 0x224, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR10

MPCBB privileged configuration for super-block x register

Offset: 0x228, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR11

MPCBB privileged configuration for super-block x register

Offset: 0x22c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR12

MPCBB privileged configuration for super-block x register

Offset: 0x230, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR13

MPCBB privileged configuration for super-block x register

Offset: 0x234, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR14

MPCBB privileged configuration for super-block x register

Offset: 0x238, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR15

MPCBB privileged configuration for super-block x register

Offset: 0x23c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR16

MPCBB privileged configuration for super-block x register

Offset: 0x240, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR17

MPCBB privileged configuration for super-block x register

Offset: 0x244, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR18

MPCBB privileged configuration for super-block x register

Offset: 0x248, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR19

MPCBB privileged configuration for super-block x register

Offset: 0x24c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR20

MPCBB privileged configuration for super-block x register

Offset: 0x250, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR21

MPCBB privileged configuration for super-block x register

Offset: 0x254, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR22

MPCBB privileged configuration for super-block x register

Offset: 0x258, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR23

MPCBB privileged configuration for super-block x register

Offset: 0x25c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR24

MPCBB privileged configuration for super-block x register

Offset: 0x260, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR25

MPCBB privileged configuration for super-block x register

Offset: 0x264, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR26

MPCBB privileged configuration for super-block x register

Offset: 0x268, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR27

MPCBB privileged configuration for super-block x register

Offset: 0x26c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR28

MPCBB privileged configuration for super-block x register

Offset: 0x270, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR29

MPCBB privileged configuration for super-block x register

Offset: 0x274, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR30

MPCBB privileged configuration for super-block x register

Offset: 0x278, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR31

MPCBB privileged configuration for super-block x register

Offset: 0x27c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR32

MPCBB privileged configuration for super-block x register

Offset: 0x280, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR33

MPCBB privileged configuration for super-block x register

Offset: 0x284, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR34

MPCBB privileged configuration for super-block x register

Offset: 0x288, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR35

MPCBB privileged configuration for super-block x register

Offset: 0x28c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR36

MPCBB privileged configuration for super-block x register

Offset: 0x290, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR37

MPCBB privileged configuration for super-block x register

Offset: 0x294, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR38

MPCBB privileged configuration for super-block x register

Offset: 0x298, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR39

MPCBB privileged configuration for super-block x register

Offset: 0x29c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR40

MPCBB privileged configuration for super-block x register

Offset: 0x2a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR41

MPCBB privileged configuration for super-block x register

Offset: 0x2a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR42

MPCBB privileged configuration for super-block x register

Offset: 0x2a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR43

MPCBB privileged configuration for super-block x register

Offset: 0x2ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR44

MPCBB privileged configuration for super-block x register

Offset: 0x2b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR45

MPCBB privileged configuration for super-block x register

Offset: 0x2b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR46

MPCBB privileged configuration for super-block x register

Offset: 0x2b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR47

MPCBB privileged configuration for super-block x register

Offset: 0x2bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR48

MPCBB privileged configuration for super-block x register

Offset: 0x2c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR49

MPCBB privileged configuration for super-block x register

Offset: 0x2c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR50

MPCBB privileged configuration for super-block x register

Offset: 0x2c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

MPCBB2_PRIVCFGR51

MPCBB privileged configuration for super-block x register

Offset: 0x2cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

SEC_GTZC1_TZIC

0x50032800: GTZC1_TZIC

55/164 fields covered.

Toggle register map

Offset	Name	30	27	26	25	24	23	22	20	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IER1									FDCAN1IE	LPTIM2IE	I2C4IE	CRSIE	I2C2IE	I2C1IE	UART5IE	USART4IE	USART3IE		SPI2IE	IWDGIE	WWDGIE	TIM7IE	TIM6IE	TIM5IE	TIM4IE	TIM3IE	TIM2IE
0x4	IER2																				SAI1IE	TIM17IE	TIM16IE	TIM15IE	USART1IE	TIM8IE	SPI1IE	TIM1IE
0x8	IER3			HSPI1_REGIE			GPU2DIE	RAMCFGIE	OCTOSPI1_REGIE		SDMMC1IE				RNGIE	HASHIE			DCMIIE	ADC1I2E	DCACHE1_REGIE	ICACHE_REGIE		TSCIE	CRCIE	FMACIE	CORDICIE	MDF1IE
0xc	IER4	SRAM5IE	MPCBB2_REGIE	SRAM2IE	MPCBB1_REGIE	SRAM1IE			HSPI1_MEMIE	BKPSRAMIE		OCTOSPI1_MEMIE	TZIC1IE	TZSC1IE												FLASHIE	FLASH_REGIE	GPDMA1IE
0x10	SR1									FDCAN1F	LPTIM2F	I2C4F	CRSF	I2C2F	I2C1F	UART5F	UART4F	USART3F		SPI2F	IWDGF	WWDGF	TIM7F	TIM6F	TIM5F	TIM4F	TIM3F	TIM2F
0x14	SR2																				SAI1F	TIM17F	TIM16F	TIM15F	USART1F	TIM8F	SPI1F	TIM1F
0x18	SR3			HSPI1_REGF			GPU2DF	RAMCFGF	OCTOSPI1_REGF		SDMMC1F				RNGF	HASHF			DCMIF	ADC12F	DCACHE1_REGF	ICACHE_REGF		TSCF	CRCF	FMACF	CORDICF	MDF1F
0x1c	SR4	SRAM5F	MPCBB2_REGF	SRAM2F	MPCBB1_REGF	SRAM1F			HSPI1_MEMF	BKPSRAMF		OCTOSPI1_MEMF	TZIC1F	TZSC1F												FLASHF	FLASH_REGF	GPDMA1F
0x20	FCR1									CFDCAN1F	CLPTIM2F	CI2C4F	CCRSF	CI2C2F	CI2C1F	CUART5F	CUART4F	CUSART3F		CSPI2F	CIWDGF	CWWDGF	CTIM7F	CTIM6F	CTIM5F	CTIM4F	CTIM3F	CTIM2F
0x24	FCR2																				CSAI1F	CTIM17F	CTIM16F	CTIM15F	CUSART1F	CTIM8F	CSPI1F	CTIM1F
0x28	FCR3						CGPU2DF	CRAMCFGF	COCTOSPI1_REGF		CSDMMC1F				CRNGF	CHASHF			CDCMIF	CADC12F	CDCACHE1_REGF	CICACHE_REGF		CTSCF	CCRCF	CFMACF	CCORDICF	CMDF1F
0x2c	FCR4	CSRAM5F	CMPCBB2_REGF	CSRAM2F	CMPCBB1_REGF	CSRAM1F			CHSPI1_MEMF	CBKPSRAMF		COCTOSPI1_MEMF	CTZIC1F	CTZSC1F												CFLASHF	CFLASH_REGF	CGPDMA1F

Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1IE rw	LPTIM2IE rw	I2C4IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSIE rw	I2C2IE rw	I2C1IE rw	UART5IE rw	USART4IE rw	USART3IE rw		SPI2IE rw	IWDGIE rw	WWDGIE rw	TIM7IE rw	TIM6IE rw	TIM5IE rw	TIM4IE rw	TIM3IE rw	TIM2IE rw

Toggle fields

TIM2IE

Bit 0: TIM2IE.

TIM3IE

Bit 1: TIM3IE.

TIM4IE

Bit 2: TIM4IE.

TIM5IE

Bit 3: TIM5IE.

TIM6IE

Bit 4: TIM6IE.

TIM7IE

Bit 5: TIM7IE.

WWDGIE

Bit 6: WWDGIE.

IWDGIE

Bit 7: IWDGIE.

SPI2IE

Bit 8: SPI2IE.

USART3IE

Bit 10: illegal access interrupt enable for USART3.

USART4IE

Bit 11: illegal access interrupt enable for UART4.

UART5IE

Bit 12: illegal access interrupt enable for UART5.

I2C1IE

Bit 13: illegal access interrupt enable for I2C1.

I2C2IE

Bit 14: illegal access interrupt enable for I2C2.

CRSIE

Bit 15: illegal access interrupt enable for CRS.

I2C4IE

Bit 16: illegal access interrupt enable for I2C4.

LPTIM2IE

Bit 17: illegal access interrupt enable for LPTIM2.

FDCAN1IE

Bit 18: illegal access interrupt enable for FDCAN1.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1IE rw	TIM17IE rw	TIM16IE rw	TIM15IE rw	USART1IE rw	TIM8IE rw	SPI1IE rw	TIM1IE rw

Toggle fields

TIM1IE

Bit 0: illegal access interrupt enable for TIM1.

SPI1IE

Bit 1: illegal access interrupt enable for SPI1.

TIM8IE

Bit 2: illegal access interrupt enable for TIM8.

USART1IE

Bit 3: illegal access interrupt enable for USART1.

TIM15IE

Bit 4: illegal access interrupt enable for TIM5.

TIM16IE

Bit 5: illegal access interrupt enable for TIM6.

TIM17IE

Bit 6: illegal access interrupt enable for TIM7.

SAI1IE

Bit 7: illegal access interrupt enable for SAI1.

IER3

TZIC interrupt enable register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGIE rw			GPU2DIE rw	RAMCFGIE rw		OCTOSPI1_REGIE rw			SDMMC1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGIE rw	HASHIE rw			DCMIIE rw	ADC1I2E rw	DCACHE1_REGIE rw	ICACHE_REGIE rw		TSCIE rw	CRCIE rw	FMACIE rw	CORDICIE rw	MDF1IE rw

Toggle fields

MDF1IE

Bit 0: illegal access interrupt enable for MDF1.

CORDICIE

Bit 1: illegal access interrupt enable for CORDIC.

FMACIE

Bit 2: illegal access interrupt enable for FMAC.

CRCIE

Bit 3: illegal access interrupt enable for CRC.

TSCIE

Bit 4: illegal access interrupt enable for TSC.

ICACHE_REGIE

Bit 6: illegal access interrupt enable for ICACHE registers.

DCACHE1_REGIE

Bit 7: illegal access interrupt enable for DCACHE registers.

ADC1I2E

Bit 8: illegal access interrupt enable for ADC1 or ADC2.

DCMIIE

Bit 9: illegal access interrupt enable for DCMI.

HASHIE

Bit 12: illegal access interrupt enable for HASH.

RNGIE

Bit 13: illegal access interrupt enable for RNG.

SDMMC1IE

Bit 17: illegal access interrupt enable.

OCTOSPI1_REGIE

Bit 20: illegal access interrupt enable for OCTOSPI1 registers.

RAMCFGIE

Bit 22: illegal access interrupt enable for RAMCFG.

GPU2DIE

Bit 23: GPU2DIE.

HSPI1_REGIE

Bit 26: HSPI1_REGIE.

IER4

TZIC interrupt enable register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SRAM5IE rw			MPCBB2_REGIE rw	SRAM2IE rw	MPCBB1_REGIE rw	SRAM1IE rw				HSPI1_MEMIE rw		BKPSRAMIE rw		OCTOSPI1_MEMIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC1IE rw	TZSC1IE rw												FLASHIE rw	FLASH_REGIE rw	GPDMA1IE rw

Toggle fields

GPDMA1IE

Bit 0: illegal access interrupt enable for GPDMA1.

FLASH_REGIE

Bit 1: illegal access interrupt enable for FLASH registers.

FLASHIE

Bit 2: illegal access interrupt enable for FLASH memory.

TZSC1IE

Bit 14: illegal access interrupt enable for GTZC1 TZSC registers.

TZIC1IE

Bit 15: illegal access interrupt enable for GTZC1 TZIC registers.

OCTOSPI1_MEMIE

Bit 16: illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank.

BKPSRAMIE

Bit 18: illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank.

HSPI1_MEMIE

Bit 20: illegal access interrupt enable for HSPI1 memory bank.

SRAM1IE

Bit 24: illegal access interrupt enable for SRAM1.

MPCBB1_REGIE

Bit 25: illegal access interrupt enable for MPCBB1 registers.

SRAM2IE

Bit 26: illegal access interrupt enable for SRAM2.

MPCBB2_REGIE

Bit 27: illegal access interrupt enable for MPCBB2 registers.

SRAM5IE

Bit 30: illegal access interrupt enable for SRAM5.

SR1

TZIC status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1F r	LPTIM2F r	I2C4F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSF r	I2C2F r	I2C1F r	UART5F r	UART4F r	USART3F r		SPI2F r	IWDGF r	WWDGF r	TIM7F r	TIM6F r	TIM5F r	TIM4F r	TIM3F r	TIM2F r

Toggle fields

TIM2F

Bit 0: illegal access flag for TIM2.

TIM3F

Bit 1: illegal access flag for TIM3.

TIM4F

Bit 2: illegal access flag for TIM4.

TIM5F

Bit 3: illegal access flag for TIM5.

TIM6F

Bit 4: illegal access flag for TIM6.

TIM7F

Bit 5: illegal access flag for TIM7.

WWDGF

Bit 6: illegal access flag for WWDG.

IWDGF

Bit 7: illegal access flag for IWDG.

SPI2F

Bit 8: illegal access flag for SPI2.

USART3F

Bit 10: illegal access flag for USART3.

UART4F

Bit 11: illegal access flag for UART4.

UART5F

Bit 12: illegal access flag for UART5.

I2C1F

Bit 13: illegal access flag for I2C1.

I2C2F

Bit 14: illegal access flag for I2C2.

CRSF

Bit 15: illegal access flag for CRS.

I2C4F

Bit 16: illegal access flag for I2C4.

LPTIM2F

Bit 17: illegal access flag for LPTIM2.

FDCAN1F

Bit 18: illegal access flag for FDCAN1.

SR2

TZIC status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1F r	TIM17F r	TIM16F r	TIM15F r	USART1F r	TIM8F r	SPI1F r	TIM1F r

Toggle fields

TIM1F

Bit 0: illegal access flag for TIM1.

SPI1F

Bit 1: illegal access flag for SPI1.

TIM8F

Bit 2: illegal access flag for TIM8.

USART1F

Bit 3: illegal access flag for USART1.

TIM15F

Bit 4: illegal access flag for TIM5.

TIM16F

Bit 5: illegal access flag for TIM6.

TIM17F

Bit 6: illegal access flag for TIM7.

SAI1F

Bit 7: illegal access flag for SAI1.

SR3

TZIC status register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGF r			GPU2DF r	RAMCFGF r		OCTOSPI1_REGF r			SDMMC1F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGF r	HASHF r			DCMIF r	ADC12F r	DCACHE1_REGF r	ICACHE_REGF r		TSCF r	CRCF r	FMACF r	CORDICF r	MDF1F r

Toggle fields

MDF1F

Bit 0: illegal access flag for MDF1.

CORDICF

Bit 1: illegal access flag for CORDIC.

FMACF

Bit 2: illegal access flag for FMAC.

CRCF

Bit 3: illegal access flag for CRC.

TSCF

Bit 4: illegal access flag for TSC.

ICACHE_REGF

Bit 6: illegal access flag for ICACHE registers.

DCACHE1_REGF

Bit 7: illegal access flag for DCACHE registers.

ADC12F

Bit 8: illegal access flag for ADC1 and ADC2.

DCMIF

Bit 9: illegal access flag for DCMI.

HASHF

Bit 12: illegal access flag for HASH.

RNGF

Bit 13: illegal access flag for RNG.

SDMMC1F

Bit 17: illegal access flag.

OCTOSPI1_REGF

Bit 20: illegal access flag for OCTOSPI1 registers.

RAMCFGF

Bit 22: illegal access flag for RAMCFG.

GPU2DF

Bit 23: illegal access flag for GPU2D.

HSPI1_REGF

Bit 26: illegal access flag for HSPI1 registers.

SR4

TZIC status register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SRAM5F r			MPCBB2_REGF r	SRAM2F r	MPCBB1_REGF r	SRAM1F r				HSPI1_MEMF r		BKPSRAMF r		OCTOSPI1_MEMF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC1F r	TZSC1F r												FLASHF r	FLASH_REGF r	GPDMA1F r

Toggle fields

GPDMA1F

Bit 0: illegal access flag for GPDMA1.

FLASH_REGF

Bit 1: illegal access flag for FLASH registers.

FLASHF

Bit 2: illegal access flag for FLASH memory.

TZSC1F

Bit 14: illegal access flag for GTZC1 TZSC registers.

TZIC1F

Bit 15: illegal access flag for GTZC1 TZIC registers.

OCTOSPI1_MEMF

Bit 16: illegal access flag for MPCWM1 (OCTOSPI1) memory bank.

BKPSRAMF

Bit 18: illegal access flag for MPCWM3 (BKPSRAM) memory bank.

HSPI1_MEMF

Bit 20: illegal access flag for HSPI1 memory bank.

SRAM1F

Bit 24: illegal access flag for SRAM1.

MPCBB1_REGF

Bit 25: illegal access flag for MPCBB1 registers.

SRAM2F

Bit 26: illegal access flag for SRAM2.

MPCBB2_REGF

Bit 27: illegal access flag for MPCBB2 registers.

SRAM5F

Bit 30: illegal access flag for SRAM5.

FCR1

TZIC flag clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													CFDCAN1F w	CLPTIM2F w	CI2C4F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCRSF w	CI2C2F w	CI2C1F w	CUART5F w	CUART4F w	CUSART3F w		CSPI2F w	CIWDGF w	CWWDGF w	CTIM7F w	CTIM6F w	CTIM5F w	CTIM4F w	CTIM3F w	CTIM2F w

Toggle fields

CTIM2F

Bit 0: clear the illegal access flag for TIM2.

CTIM3F

Bit 1: clear the illegal access flag for TIM3.

CTIM4F

Bit 2: clear the illegal access flag for TIM4.

CTIM5F

Bit 3: clear the illegal access flag for TIM5.

CTIM6F

Bit 4: clear the illegal access flag for TIM6.

CTIM7F

Bit 5: clear the illegal access flag for TIM7.

CWWDGF

Bit 6: clear the illegal access flag for WWDG.

CIWDGF

Bit 7: clear the illegal access flag for IWDG.

CSPI2F

Bit 8: clear the illegal access flag for SPI2.

CUSART3F

Bit 10: clear the illegal access flag for USART3.

CUART4F

Bit 11: clear the illegal access flag for UART4.

CUART5F

Bit 12: clear the illegal access flag for UART5.

CI2C1F

Bit 13: clear the illegal access flag for I2C1.

CI2C2F

Bit 14: clear the illegal access flag for I2C2.

CCRSF

Bit 15: clear the illegal access flag for CRS.

CI2C4F

Bit 16: clear the illegal access flag for I2C4.

CLPTIM2F

Bit 17: clear the illegal access flag for LPTIM2.

CFDCAN1F

Bit 18: clear the illegal access flag for FDCAN1.

FCR2

TZIC flag clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CSAI1F w	CTIM17F w	CTIM16F w	CTIM15F w	CUSART1F w	CTIM8F w	CSPI1F w	CTIM1F w

Toggle fields

CTIM1F

Bit 0: clear the illegal access flag for TIM1.

CSPI1F

Bit 1: clear the illegal access flag for SPI1.

CTIM8F

Bit 2: clear the illegal access flag for TIM8.

CUSART1F

Bit 3: clear the illegal access flag for USART1.

CTIM15F

Bit 4: clear the illegal access flag for TIM5.

CTIM16F

Bit 5: clear the illegal access flag for TIM6.

CTIM17F

Bit 6: clear the illegal access flag for TIM7.

CSAI1F

Bit 7: clear the illegal access flag for SAI1.

FCR3

TZIC flag clear register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CGPU2DF w	CRAMCFGF w		COCTOSPI1_REGF w			CSDMMC1F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CRNGF w	CHASHF w			CDCMIF w	CADC12F w	CDCACHE1_REGF w	CICACHE_REGF w		CTSCF w	CCRCF w	CFMACF w	CCORDICF w	CMDF1F w

Toggle fields

CMDF1F

Bit 0: clear the illegal access flag for MDF1.

CCORDICF

Bit 1: clear the illegal access flag for CORDIC.

CFMACF

Bit 2: clear the illegal access flag for FMAC.

CCRCF

Bit 3: clear the illegal access flag for CRC.

CTSCF

Bit 4: clear the illegal access flag for TSC.

CICACHE_REGF

Bit 6: clear the illegal access flag for ICACHE registers.

CDCACHE1_REGF

Bit 7: clear the illegal access flag for DCACHE1 registers.

CADC12F

Bit 8: clear the illegal access flag for ADC1 and ADC2.

CDCMIF

Bit 9: clear the illegal access flag for DCMI.

CHASHF

Bit 12: clear the illegal access flag for HASH.

CRNGF

Bit 13: clear the illegal access flag for RNG.

CSDMMC1F

Bit 17: clear the illegal access flag.

COCTOSPI1_REGF

Bit 20: clear the illegal access flag for OCTOSPI1 registers.

CRAMCFGF

Bit 22: clear the illegal access flag for RAMCFG.

CGPU2DF

Bit 23: clear the illegal access flag for GPU2D.

FCR4

TZIC flag clear register 4

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CSRAM5F w			CMPCBB2_REGF w	CSRAM2F w	CMPCBB1_REGF w	CSRAM1F w				CHSPI1_MEMF w		CBKPSRAMF w		COCTOSPI1_MEMF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTZIC1F w	CTZSC1F w												CFLASHF w	CFLASH_REGF w	CGPDMA1F w

Toggle fields

CGPDMA1F

Bit 0: clear the illegal access flag for GPDMA1.

CFLASH_REGF

Bit 1: clear the illegal access flag for FLASH registers.

CFLASHF

Bit 2: clear the illegal access flag for FLASH memory.

CTZSC1F

Bit 14: clear the illegal access flag for GTZC1 TZSC registers.

CTZIC1F

Bit 15: clear the illegal access flag for GTZC1 TZIC registers.

COCTOSPI1_MEMF

Bit 16: clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank.

CBKPSRAMF

Bit 18: clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank.

CHSPI1_MEMF

Bit 20: clear the illegal access flag for HSPI1 memory bank.

CSRAM1F

Bit 24: clear the illegal access flag for SRAM1.

CMPCBB1_REGF

Bit 25: clear the illegal access flag for MPCBB1 registers.

CSRAM2F

Bit 26: clear the illegal access flag for SRAM2.

CMPCBB2_REGF

Bit 27: clear the illegal access flag for MPCBB2 registers.

CSRAM5F

Bit 30: clear the illegal access flag for SRAM5.

SEC_GTZC1_TZSC

0x50032400: GTZC1_TZSC

0/145 fields covered.

Toggle register map

Offset	Name	27	26	23	22	20	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TZSC_CR																								LCK
0x10	TZSC_SECCFGR1						FDCAN1SEC	LPTIM2SEC	I2C4SEC	CRSSEC	I2C2SEC	I2C1SEC	UART5SEC	UART4SEC	USART3SEC		SPI2SEC	IWDGSEC	WWDGSEC	TIM7SEC	TIM6SEC	TIM5SEC	TIM4SEC	TIM3SEC	TIM2SEC
0x14	TZSC_SECCFGR2																	SAI1SEC	TIM17SEC	TIM16SEC	TIM15SEC	USART1SEC	TIM8SEC	SPI1SEC	TIM1SEC
0x18	TZSC_SECCFGR3		HSPI1_REGSEC	GPU2DSEC	RAMCFGSEC	OCTOSPI1_REGSEC		SDMMC1SEC				RNGSEC	HASHSEC			DCMISEC	ADC1SEC	DCACHE1_REGSEC	ICACHE_REGSEC		TSCSEC	CRCSEC	FMACSEC	CORDICSEC	MDF1SEC
0x20	TZSC_PRIVCFGR1						FDCAN1PRIV	LPTIM2PRIV	I2C4PRIV	CRSPRIV	I2C2PRIV	I2C1PRIV	UART5PRIV	UART4PRIV	USART3PRIV		SPI2PRIV	IWDGPRIV	WWDGPRIV	TIM7PRIV	TIM6PRIV	TIM5PRIV	TIM4PRIV	TIM3PRIV	TIM2PRIV
0x24	TZSC_PRIVCFGR2																	SAI1PRIV	TIM17PRIV	TIM16PRIV	TIM15PRIV	USART1PRIV	TIM8PRIV	SPI1PRIV	TIM1PRIV
0x28	TZSC_PRIVCFGR3		HSPI1_REGPRIV	GPU2DPRIV	RAMCFGPRIV	OCTOSPI1_REGPRIV		SDMMC1PRIV				RNGPRIV	HASHPRIV			DCMIPRIV	ADC1PRIV	DCACHE1_REGPRIV	ICACHE_REGPRIV		TSCPRIV	CRCPRIV	FMACPRIV	CORDICPRIV	MDF1PRIV
0x40	TZSC_MPCWM1ACFGR															PRIV	SEC							SRLOCK	SREN
0x44	TZSC_MPCWM1AR	SUBA_LENGTH													SUBA_START
0x48	TZSC_MPCWM1BCFGR															PRIV	SEC							SRLOCK	SREN
0x4c	TZSC_MPCWM1BR	SUBB_LENGTH													SUBB_START
0x50	TZSC_MPCWM2ACFGR															PRIV	SEC							SRLOCK	SREN
0x54	TZSC_MPCWM2AR	SUBA_LENGTH													SUBA_START
0x58	TZSC_MPCWM2BCFGR															PRIV	SEC							SRLOCK	SREN
0x5c	TZSC_MPCWM2BR	SUBB_LENGTH													SUBB_START
0x60	TZSC_MPCWM3ACFGR															PRIV	SEC							SRLOCK	SREN
0x64	TZSC_MPCWM3AR	SUBA_LENGTH													SUBA_START
0x70	TZSC_MPCWM4ACFGR															PRIV	SEC							SRLOCK	SREN
0x74	TZSC_MPCWM4AR	SUBA_LENGTH													SUBA_START
0x80	TZSC_MPCWM5ACFGR															PRIV	SEC							SRLOCK	SREN
0x84	TZSC_MPCWM5AR	SUBA_LENGTH													SUBA_START
0x88	TZSC_MPCWM5BCFGR															PRIV	SEC							SRLOCK	SREN
0x8c	TZSC_MPCWM5BR	SUBB_LENGTH													SUBB_START
0x90	TZSC_MPCWM6ACFGR															PRIV	SEC							SRLOCK	SREN
0x94	TZSC_MPCWM6AR	SUBA_LENGTH													SUBA_START
0x98	TZSC_MPCWM6BCFGR															PRIV	SEC							SRLOCK	SREN
0x9c	TZSC_MPCWM6BR	SUBB_LENGTH													SUBB_START

Toggle registers

TZSC_CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LCK rw

Toggle fields

LCK

Bit 0: lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset.

TZSC_SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1SEC rw	LPTIM2SEC rw	I2C4SEC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSSEC rw	I2C2SEC rw	I2C1SEC rw	UART5SEC rw	UART4SEC rw	USART3SEC rw		SPI2SEC rw	IWDGSEC rw	WWDGSEC rw	TIM7SEC rw	TIM6SEC rw	TIM5SEC rw	TIM4SEC rw	TIM3SEC rw	TIM2SEC rw

Toggle fields

TIM2SEC

Bit 0: secure access mode for TIM2.

TIM3SEC

Bit 1: secure access mode for TIM3.

TIM4SEC

Bit 2: secure access mode for TIM4.

TIM5SEC

Bit 3: secure access mode for TIM5.

TIM6SEC

Bit 4: secure access mode for TIM6.

TIM7SEC

Bit 5: secure access mode for TIM7.

WWDGSEC

Bit 6: secure access mode for WWDG.

IWDGSEC

Bit 7: secure access mode for IWDG.

SPI2SEC

Bit 8: secure access mode for SPI2.

USART3SEC

Bit 10: secure access mode for USART3.

UART4SEC

Bit 11: secure access mode for UART4.

UART5SEC

Bit 12: secure access mode for UART5.

I2C1SEC

Bit 13: secure access mode for I2C1.

I2C2SEC

Bit 14: secure access mode for I2C2.

CRSSEC

Bit 15: secure access mode for CRS.

I2C4SEC

Bit 16: secure access mode for I2C4.

LPTIM2SEC

Bit 17: secure access mode for LPTIM2.

FDCAN1SEC

Bit 18: secure access mode for FDCAN1.

TZSC_SECCFGR2

TZSC secure configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1SEC rw	TIM17SEC rw	TIM16SEC rw	TIM15SEC rw	USART1SEC rw	TIM8SEC rw	SPI1SEC rw	TIM1SEC rw

Toggle fields

TIM1SEC

Bit 0: secure access mode for TIM1.

SPI1SEC

Bit 1: secure access mode for SPI1.

TIM8SEC

Bit 2: secure access mode for TIM8.

USART1SEC

Bit 3: secure access mode for USART1.

TIM15SEC

Bit 4: secure access mode for TIM5.

TIM16SEC

Bit 5: secure access mode for TIM6.

TIM17SEC

Bit 6: secure access mode for TIM7.

SAI1SEC

Bit 7: secure access mode for SAI1.

TZSC_SECCFGR3

TZSC secure configuration register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGSEC rw			GPU2DSEC rw	RAMCFGSEC rw		OCTOSPI1_REGSEC rw			SDMMC1SEC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGSEC rw	HASHSEC rw			DCMISEC rw	ADC1SEC rw	DCACHE1_REGSEC rw	ICACHE_REGSEC rw		TSCSEC rw	CRCSEC rw	FMACSEC rw	CORDICSEC rw	MDF1SEC rw

Toggle fields

MDF1SEC

Bit 0: secure access mode for MDF1.

CORDICSEC

Bit 1: secure access mode for CORDIC.

FMACSEC

Bit 2: secure access mode for FMAC.

CRCSEC

Bit 3: secure access mode for CRC.

TSCSEC

Bit 4: secure access mode for TSC.

ICACHE_REGSEC

Bit 6: secure access mode for ICACHE registers.

DCACHE1_REGSEC

Bit 7: secure access mode for DCACHE1 registers.

ADC1SEC

Bit 8: secure access mode for ADC1.

DCMISEC

Bit 9: secure access mode for DCMI.

HASHSEC

Bit 12: secure access mode for HASH.

RNGSEC

Bit 13: secure access mode for RNG.

SDMMC1SEC

Bit 17: secure access mode.

OCTOSPI1_REGSEC

Bit 20: secure access mode for OCTOSPI1 registers.

RAMCFGSEC

Bit 22: secure access mode for RAMCFG.

GPU2DSEC

Bit 23: GPU2DSEC.

HSPI1_REGSEC

Bit 26: HSPI1_REGSEC.

TZSC_PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FDCAN1PRIV rw	LPTIM2PRIV rw	I2C4PRIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRSPRIV rw	I2C2PRIV rw	I2C1PRIV rw	UART5PRIV rw	UART4PRIV rw	USART3PRIV rw		SPI2PRIV rw	IWDGPRIV rw	WWDGPRIV rw	TIM7PRIV rw	TIM6PRIV rw	TIM5PRIV rw	TIM4PRIV rw	TIM3PRIV rw	TIM2PRIV rw

Toggle fields

TIM2PRIV

Bit 0: privileged access mode for TIM2.

TIM3PRIV

Bit 1: privileged access mode for TIM3.

TIM4PRIV

Bit 2: privileged access mode for TIM4.

TIM5PRIV

Bit 3: privileged access mode for TIM5.

TIM6PRIV

Bit 4: privileged access mode for TIM6.

TIM7PRIV

Bit 5: privileged access mode for TIM7.

WWDGPRIV

Bit 6: privileged access mode for WWDG.

IWDGPRIV

Bit 7: privileged access mode for IWDG.

SPI2PRIV

Bit 8: privileged access mode for SPI2.

USART3PRIV

Bit 10: privileged access mode for USART3.

UART4PRIV

Bit 11: privileged access mode for UART4.

UART5PRIV

Bit 12: privileged access mode for UART5.

I2C1PRIV

Bit 13: privileged access mode for I2C1.

I2C2PRIV

Bit 14: privileged access mode for I2C2.

CRSPRIV

Bit 15: privileged access mode for CRS.

I2C4PRIV

Bit 16: privileged access mode for I2C4.

LPTIM2PRIV

Bit 17: privileged access mode for LPTIM2.

FDCAN1PRIV

Bit 18: privileged access mode for FDCAN1.

TZSC_PRIVCFGR2

TZSC privilege configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SAI1PRIV rw	TIM17PRIV rw	TIM16PRIV rw	TIM15PRIV rw	USART1PRIV rw	TIM8PRIV rw	SPI1PRIV rw	TIM1PRIV rw

Toggle fields

TIM1PRIV

Bit 0: privileged access mode for TIM1.

SPI1PRIV

Bit 1: privileged access mode for SPI1PRIV.

TIM8PRIV

Bit 2: privileged access mode for TIM8.

USART1PRIV

Bit 3: privileged access mode for USART1.

TIM15PRIV

Bit 4: privileged access mode for TIM15.

TIM16PRIV

Bit 5: privileged access mode for TIM16.

TIM17PRIV

Bit 6: privileged access mode for TIM17.

SAI1PRIV

Bit 7: privileged access mode for SAI1.

TZSC_PRIVCFGR3

TZSC privilege configuration register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					HSPI1_REGPRIV rw			GPU2DPRIV rw	RAMCFGPRIV rw		OCTOSPI1_REGPRIV rw			SDMMC1PRIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RNGPRIV rw	HASHPRIV rw			DCMIPRIV rw	ADC1PRIV rw	DCACHE1_REGPRIV rw	ICACHE_REGPRIV rw		TSCPRIV rw	CRCPRIV rw	FMACPRIV rw	CORDICPRIV rw	MDF1PRIV rw

Toggle fields

MDF1PRIV

Bit 0: privileged access mode for MDF1.

CORDICPRIV

Bit 1: privileged access mode for CORDIC.

FMACPRIV

Bit 2: privileged access mode for FMAC.

CRCPRIV

Bit 3: privileged access mode for CRC.

TSCPRIV

Bit 4: privileged access mode for TSC.

ICACHE_REGPRIV

Bit 6: privileged access mode for ICACHE registers.

DCACHE1_REGPRIV

Bit 7: privileged access mode for DCACHE1 registers.

ADC1PRIV

Bit 8: privileged access mode for ADC1.

DCMIPRIV

Bit 9: privileged access mode for DCMI.

HASHPRIV

Bit 12: privileged access mode for HASH.

RNGPRIV

Bit 13: privileged access mode for RNG.

SDMMC1PRIV

Bit 17: privileged access mode.

OCTOSPI1_REGPRIV

Bit 20: privileged access mode for OCTOSPI1.

RAMCFGPRIV

Bit 22: privileged access mode for RAMCFG.

GPU2DPRIV

Bit 23: GPU2DPRIV.

HSPI1_REGPRIV

Bit 26: HSPI1_REGPRIV.

TZSC_MPCWM1ACFGR

TZSC memory 1 sub-region A watermark configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM1AR

TZSC memory 1 sub-region A watermark register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM1BCFGR

TZSC memory 1 sub-region B watermark configuration register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM1BR

TZSC memory 1 sub-region B watermark register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM2ACFGR

TZSC memory 2 sub-region A watermark configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM2AR

TZSC memory 2 sub-region A watermark register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM2BCFGR

TZSC memory 2 sub-region B watermark configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM2BR

TZSC memory 2 sub-region B watermark register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM3ACFGR

TZSC memory 3 sub-region A watermark configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM3AR

TZSC memory 3 sub-region A watermark register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM4ACFGR

TZSC memory 4 sub-region A watermark configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM4AR

TZSC memory 4 sub-region A watermark register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM5ACFGR

TZSC memory 5 sub-region A watermark configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM5AR

TZSC memory 5 sub-region A watermark register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM5BCFGR

TZSC memory 5 sub-region B watermark configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM5BR

TZSC memory 5 sub-region B watermark register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM6ACFGR

TZSC memory 6 sub-region B watermark configuration register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM6AR

TZSC memory 6 sub-region B watermark register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBA_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBA_START rw

Toggle fields

SUBA_START

Bits 0-10: Start of sub-region A.

SUBA_LENGTH

Bits 16-27: Length of sub-region A.

TZSC_MPCWM6BCFGR

TZSC memory 6 sub-region B watermark configuration register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PRIV rw	SEC rw							SRLOCK rw	SREN rw

Toggle fields

SREN

Bit 0: Sub-region enable.

SRLOCK

Bit 1: Sub-region lock.

SEC

Bit 8: Secure sub-region.

PRIV

Bit 9: Privileged sub-region.

TZSC_MPCWM6BR

TZSC memory 6 sub-region B watermark register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				SUBB_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SUBB_START rw

Toggle fields

SUBB_START

Bits 0-10: Start of sub-region A.

SUBB_LENGTH

Bits 16-27: Length of sub-region A.

SEC_GTZC2_MPCBB4

0x56023800: GTZC2_MPCBB4

0/68 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MPCBB4_CR	SRWILADIS	INVSECSTATE																														GLOCK
0x10	MPCBB4_CFGLOCK																																SPLCK0
0x100	MPCBB4_SECCFGR0	SEC31	SEC30	SEC29	SEC28	SEC27	SEC26	SEC25	SEC24	SEC23	SEC22	SEC21	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x200	MPCBB4_PRIVCFGR0	PRIV31	PRIV30	PRIV29	PRIV28	PRIV27	PRIV26	PRIV25	PRIV24	PRIV23	PRIV22	PRIV21	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0

Toggle registers

MPCBB4_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRWILADIS rw	INVSECSTATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															GLOCK rw

Toggle fields

GLOCK

Bit 0: lock the control register of the MPCBB until next reset.

INVSECSTATE

Bit 30: SRAMx clocks security state.

SRWILADIS

Bit 31: secure read/write illegal access disable.

MPCBB4_CFGLOCK

GTZC2 SRAM4 MPCBB configuration lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															SPLCK0 rw

Toggle fields

SPLCK0

Bit 0: Security/privilege configuration lock for super-block 0.

MPCBB4_SECCFGR0

MPCBB security configuration for super-block 0 register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC31 rw	SEC30 rw	SEC29 rw	SEC28 rw	SEC27 rw	SEC26 rw	SEC25 rw	SEC24 rw	SEC23 rw	SEC22 rw	SEC21 rw	SEC20 rw	SEC19 rw	SEC18 rw	SEC17 rw	SEC16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15 rw	SEC14 rw	SEC13 rw	SEC12 rw	SEC11 rw	SEC10 rw	SEC9 rw	SEC8 rw	SEC7 rw	SEC6 rw	SEC5 rw	SEC4 rw	SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

SEC8

Bit 8: SEC8.

SEC9

Bit 9: SEC9.

SEC10

Bit 10: SEC10.

SEC11

Bit 11: SEC11.

SEC12

Bit 12: SEC12.

SEC13

Bit 13: SEC13.

SEC14

Bit 14: SEC14.

SEC15

Bit 15: SEC15.

SEC16

Bit 16: SEC16.

SEC17

Bit 17: SEC17.

SEC18

Bit 18: SEC18.

SEC19

Bit 19: SEC19.

SEC20

Bit 20: SEC20.

SEC21

Bit 21: SEC21.

SEC22

Bit 22: SEC22.

SEC23

Bit 23: SEC23.

SEC24

Bit 24: SEC24.

SEC25

Bit 25: SEC25.

SEC26

Bit 26: SEC26.

SEC27

Bit 27: SEC27.

SEC28

Bit 28: SEC28.

SEC29

Bit 29: SEC29.

SEC30

Bit 30: SEC30.

SEC31

Bit 31: SEC31.

MPCBB4_PRIVCFGR0

MPCBB privileged configuration for super-block 0 register

Offset: 0x200, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRIV31 rw	PRIV30 rw	PRIV29 rw	PRIV28 rw	PRIV27 rw	PRIV26 rw	PRIV25 rw	PRIV24 rw	PRIV23 rw	PRIV22 rw	PRIV21 rw	PRIV20 rw	PRIV19 rw	PRIV18 rw	PRIV17 rw	PRIV16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15 rw	PRIV14 rw	PRIV13 rw	PRIV12 rw	PRIV11 rw	PRIV10 rw	PRIV9 rw	PRIV8 rw	PRIV7 rw	PRIV6 rw	PRIV5 rw	PRIV4 rw	PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

PRIV4

Bit 4: PRIV4.

PRIV5

Bit 5: PRIV5.

PRIV6

Bit 6: PRIV6.

PRIV7

Bit 7: PRIV7.

PRIV8

Bit 8: PRIV8.

PRIV9

Bit 9: PRIV9.

PRIV10

Bit 10: PRIV10.

PRIV11

Bit 11: PRIV11.

PRIV12

Bit 12: PRIV12.

PRIV13

Bit 13: PRIV13.

PRIV14

Bit 14: PRIV14.

PRIV15

Bit 15: PRIV15.

PRIV16

Bit 16: PRIV16.

PRIV17

Bit 17: PRIV17.

PRIV18

Bit 18: PRIV18.

PRIV19

Bit 19: PRIV19.

PRIV20

Bit 20: PRIV20.

PRIV21

Bit 21: PRIV21.

PRIV22

Bit 22: PRIV22.

PRIV23

Bit 23: PRIV23.

PRIV24

Bit 24: PRIV24.

PRIV25

Bit 25: PRIV25.

PRIV26

Bit 26: PRIV26.

PRIV27

Bit 27: PRIV27.

PRIV28

Bit 28: PRIV28.

PRIV29

Bit 29: PRIV29.

PRIV30

Bit 30: PRIV30.

PRIV31

Bit 31: PRIV31.

SEC_GTZC2_TZIC

0x56023400: GTZC2_TZIC

22/67 fields covered.

Toggle register map

Offset	Name	25	24	15	14	12	11	9	8	7	6	5	4	3	2	1	0
0x0	IER1					ADF1IE	DAC1IE	VREFBUFIE		COMPIE	OPAMPIE	LPTIM4IE	LPTIM3IE	LPTIM1IE	I2C3IE	LPUART1IE	SPI3IE
0x4	IER2	MPCBB4_REGIE	SRAM4IE	TZIC2IE	TZSC2IE						EXTIIE	LPDMA1IE	RCCIE	PWRIE	TAMPIE	RTCIE	SYSCFGIE
0x10	SR1					ADF1F	DAC1F	VREFBUFF		COMPF	OPAMPF	LPTIM4F	LPTIM3F	LPTIM1F	I2C3F	LPUART1F	SPI3F
0x14	SR2	MPCBB4_REGF	SRAM4F	TZIC2F	TZSC2F						EXTIF	LPDMA1F	RCCF	PWRF	TAMPF	RTCF	SYSCFGF
0x20	FCR1					CADF1F	CDAC1F	CVREFBUFF	CADC2F	CCOMPF	COPAMPF	CLPTIM4F	CLPTIM3F	CLPTIM1F	CI2C3F	CLPUART1F	CSPI3F
0x24	FCR2	CMPCBB4_REGF	CSRAM4F	CTZIC2F	CTZSC2F						CEXTIF	CLPDMA1F	CRCCF	CPWRF	CTAMPF	CRTCF	CSYSCFGF

Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1IE rw	DAC1IE rw		VREFBUFIE rw		COMPIE rw	OPAMPIE rw	LPTIM4IE rw	LPTIM3IE rw	LPTIM1IE rw	I2C3IE rw	LPUART1IE rw	SPI3IE rw

Toggle fields

SPI3IE

Bit 0: illegal access interrupt enable for SPI3.

LPUART1IE

Bit 1: illegal access interrupt enable for LPUART1.

I2C3IE

Bit 2: illegal access interrupt enable for I2C3.

LPTIM1IE

Bit 3: illegal access interrupt enable for LPTIM1.

LPTIM3IE

Bit 4: illegal access interrupt enable for LPTIM3.

LPTIM4IE

Bit 5: illegal access interrupt enable for LPTIM4.

OPAMPIE

Bit 6: illegal access interrupt enable for OPAMP.

COMPIE

Bit 7: illegal access interrupt enable for COMP.

VREFBUFIE

Bit 9: illegal access interrupt enable for VREFBUF.

DAC1IE

Bit 11: illegal access interrupt enable for DAC1.

ADF1IE

Bit 12: illegal access interrupt enable for ADF1.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MPCBB4_REGIE rw	SRAM4IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC2IE rw	TZSC2IE rw								EXTIIE rw	LPDMA1IE rw	RCCIE rw	PWRIE rw	TAMPIE rw	RTCIE rw	SYSCFGIE rw

Toggle fields

SYSCFGIE

Bit 0: illegal access interrupt enable for SYSCFG.

RTCIE

Bit 1: illegal access interrupt enable for RTC.

TAMPIE

Bit 2: illegal access interrupt enable for TAMP.

PWRIE

Bit 3: illegal access interrupt enable for PWR.

RCCIE

Bit 4: illegal access interrupt enable for RCC.

LPDMA1IE

Bit 5: illegal access interrupt enable for LPDMA.

EXTIIE

Bit 6: illegal access interrupt enable for EXTI.

TZSC2IE

Bit 14: illegal access interrupt enable for GTZC2 TZSC registers.

TZIC2IE

Bit 15: illegal access interrupt enable for GTZC2 TZIC registers.

SRAM4IE

Bit 24: illegal access interrupt enable for SRAM4.

MPCBB4_REGIE

Bit 25: illegal access interrupt enable for MPCBB4 registers.

SR1

TZIC status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1F r	DAC1F r		VREFBUFF r		COMPF r	OPAMPF r	LPTIM4F r	LPTIM3F r	LPTIM1F r	I2C3F r	LPUART1F r	SPI3F r

Toggle fields

SPI3F

Bit 0: illegal access flag for SPI3.

LPUART1F

Bit 1: illegal access flag for LPUART1.

I2C3F

Bit 2: illegal access flag for I2C3.

LPTIM1F

Bit 3: illegal access flag for LPTIM1.

LPTIM3F

Bit 4: illegal access flag for LPTIM3.

LPTIM4F

Bit 5: illegal access flag for LPTIM4.

OPAMPF

Bit 6: illegal access flag for OPAMP.

COMPF

Bit 7: illegal access flag for COMP.

VREFBUFF

Bit 9: illegal access flag for VREFBUF.

DAC1F

Bit 11: illegal access flag for DAC1.

ADF1F

Bit 12: illegal access flag for ADF1.

SR2

TZIC status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MPCBB4_REGF r	SRAM4F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TZIC2F r	TZSC2F r								EXTIF r	LPDMA1F r	RCCF r	PWRF r	TAMPF r	RTCF r	SYSCFGF r

Toggle fields

SYSCFGF

Bit 0: illegal access flag for SYSCFG.

RTCF

Bit 1: illegal access flag for RTC.

TAMPF

Bit 2: illegal access flag for TAMP.

PWRF

Bit 3: illegal access flag for PWRUSART1F.

RCCF

Bit 4: illegal access flag for RCC.

LPDMA1F

Bit 5: illegal access flag for LPDMA.

EXTIF

Bit 6: illegal access flag for EXTI.

TZSC2F

Bit 14: illegal access flag for GTZC2 TZSC registers.

TZIC2F

Bit 15: illegal access flag for GTZC2 TZIC registers.

SRAM4F

Bit 24: illegal access flag for SRAM4.

MPCBB4_REGF

Bit 25: illegal access flag for MPCBB4 registers.

FCR1

TZIC flag clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CADF1F w	CDAC1F w		CVREFBUFF w	CADC2F w	CCOMPF w	COPAMPF w	CLPTIM4F w	CLPTIM3F w	CLPTIM1F w	CI2C3F w	CLPUART1F w	CSPI3F w

Toggle fields

CSPI3F

Bit 0: clear the illegal access flag for SPI3.

CLPUART1F

Bit 1: clear the illegal access flag for LPUART1.

CI2C3F

Bit 2: clear the illegal access flag for I2C3.

CLPTIM1F

Bit 3: clear the illegal access flag for LPTIM1.

CLPTIM3F

Bit 4: clear the illegal access flag for LPTIM3.

CLPTIM4F

Bit 5: clear the illegal access flag for LPTIM4.

COPAMPF

Bit 6: clear the illegal access flag for OPAMP.

CCOMPF

Bit 7: clear the illegal access flag for COMP.

CADC2F

Bit 8: clear the illegal access flag for ADC2.

CVREFBUFF

Bit 9: clear the illegal access flag for VREFBUF.

CDAC1F

Bit 11: clear the illegal access flag for DAC1.

CADF1F

Bit 12: clear the illegal access flag for ADF1.

FCR2

TZIC flag clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CMPCBB4_REGF w	CSRAM4F w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTZIC2F w	CTZSC2F w								CEXTIF w	CLPDMA1F w	CRCCF w	CPWRF w	CTAMPF w	CRTCF w	CSYSCFGF w

Toggle fields

CSYSCFGF

Bit 0: clear the illegal access flag for SYSCFG.

CRTCF

Bit 1: clear the illegal access flag for RTC.

CTAMPF

Bit 2: clear the illegal access flag for TAMP.

CPWRF

Bit 3: clear the illegal access flag for PWR.

CRCCF

Bit 4: clear the illegal access flag for RCC.

CLPDMA1F

Bit 5: clear the illegal access flag for LPDMA.

CEXTIF

Bit 6: clear the illegal access flag for EXTI.

CTZSC2F

Bit 14: clear the illegal access flag for GTZC2 TZSC registers.

CTZIC2F

Bit 15: clear the illegal access flag for GTZC2 TZIC registers.

CSRAM4F

Bit 24: clear the illegal access flag for SRAM4.

CMPCBB4_REGF

Bit 25: clear the illegal access flag for MPCBB4 registers.

SEC_GTZC2_TZSC

0x56023000: GTZC2_TZSC

0/23 fields covered.

Toggle register map

Offset	Name	12	11	9	7	6	5	4	3	2	1	0
0x0	TZSC_CR											LCK
0x10	TZSC_SECCFGR1	ADF1SEC	DAC1SEC	VREFBUFSEC	COMPSEC	OPAMPSEC	LPTIM4SEC	LPTIM3SEC	LPTIM1SEC	I2C3SEC	LPUART1SEC	SPI3SEC
0x20	TZSC_PRIVCFGR1	ADF1PRIV	DAC1PRIV	VREFBUFPRIV	COMPPRIV	OPAMPPRIV	LPTIM4PRIV	LPTIM3PRIV	LPTIM1PRIV	I2C3PRIV	LPUART1PRIV	SPI3PRIV

Toggle registers

TZSC_CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LCK rw

Toggle fields

LCK

Bit 0: lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset.

TZSC_SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1SEC rw	DAC1SEC rw		VREFBUFSEC rw		COMPSEC rw	OPAMPSEC rw	LPTIM4SEC rw	LPTIM3SEC rw	LPTIM1SEC rw	I2C3SEC rw	LPUART1SEC rw	SPI3SEC rw

Toggle fields

SPI3SEC

Bit 0: secure access mode for SPI3.

LPUART1SEC

Bit 1: secure access mode for LPUART1.

I2C3SEC

Bit 2: secure access mode for I2C3.

LPTIM1SEC

Bit 3: secure access mode for LPTIM1.

LPTIM3SEC

Bit 4: secure access mode for LPTIM3.

LPTIM4SEC

Bit 5: secure access mode for LPTIM4.

OPAMPSEC

Bit 6: secure access mode for OPAMP.

COMPSEC

Bit 7: secure access mode for COMP.

VREFBUFSEC

Bit 9: secure access mode for VREFBUF.

DAC1SEC

Bit 11: secure access mode for DAC1.

ADF1SEC

Bit 12: secure access mode for ADF1.

TZSC_PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADF1PRIV rw	DAC1PRIV rw		VREFBUFPRIV rw		COMPPRIV rw	OPAMPPRIV rw	LPTIM4PRIV rw	LPTIM3PRIV rw	LPTIM1PRIV rw	I2C3PRIV rw	LPUART1PRIV rw	SPI3PRIV rw

Toggle fields

SPI3PRIV

Bit 0: privileged access mode for SPI3.

LPUART1PRIV

Bit 1: privileged access mode for LPUART1.

I2C3PRIV

Bit 2: privileged access mode for I2C3.

LPTIM1PRIV

Bit 3: privileged access mode for LPTIM1.

LPTIM3PRIV

Bit 4: privileged access mode for LPTIM3.

LPTIM4PRIV

Bit 5: privileged access mode for LPTIM4.

OPAMPPRIV

Bit 6: privileged access mode for OPAMP.

COMPPRIV

Bit 7: privileged access mode for COMP.

VREFBUFPRIV

Bit 9: privileged access mode for VREFBUF.

DAC1PRIV

Bit 11: privileged access mode for DAC1.

ADF1PRIV

Bit 12: privileged access mode for ADF1.

SEC_HASH

0x520c0400: Hash processor

20/88 fields covered.

Toggle register map

Offset	Name	31	20	18	16	15	13	12	11	8	6	5	4	3	2	1	0
0x0	CR			ALGO	LKEY		MDMAT	DINNE	NBW		MODE	DATATYPE		DMAE	INIT
0x4	DIN	DATAIN				DATAIN
0x8	STR									DCAL			NBLW
0xc	HRA0	H0				H0
0x10	HRA1	H1				H1
0x14	HRA2	H2				H2
0x18	HRA3	H3				H3
0x1c	HRA4	H4				H4
0x20	IMR															DCIE	DINIE
0x24	SR		NBWE			DINNE	NBWP							BUSY	DMAS	DCIS	DINIS
0xf8	CSR0	CS0				CS0
0xfc	CSR1	CS1				CS1
0x100	CSR2	CS2				CS2
0x104	CSR3	CS3				CS3
0x108	CSR4	CS4				CS4
0x10c	CSR5	CS5				CS5
0x110	CSR6	CS6				CS6
0x114	CSR7	CS7				CS7
0x118	CSR8	CS8				CS8
0x11c	CSR9	CS9				CS9
0x120	CSR10	CS10				CS10
0x124	CSR11	CS11				CS11
0x128	CSR12	CS12				CS12
0x12c	CSR13	CS13				CS13
0x130	CSR14	CS14				CS14
0x134	CSR15	CS15				CS15
0x138	CSR16	CS16				CS16
0x13c	CSR17	CS17				CS17
0x140	CSR18	CS18				CS18
0x144	CSR19	CS19				CS19
0x148	CSR20	CS20				CS20
0x14c	CSR21	CS21				CS21
0x150	CSR22	CS22				CS22
0x154	CSR23	CS23				CS23
0x158	CSR24	CS24				CS24
0x15c	CSR25	CS25				CS25
0x160	CSR26	CS26				CS26
0x164	CSR27	CS27				CS27
0x168	CSR28	CS28				CS28
0x16c	CSR29	CS29				CS29
0x170	CSR30	CS30				CS30
0x174	CSR31	CS31				CS31
0x178	CSR32	CS32				CS32
0x17c	CSR33	CS33				CS33
0x180	CSR34	CS34				CS34
0x184	CSR35	CS35				CS35
0x188	CSR36	CS36				CS36
0x18c	CSR37	CS37				CS37
0x190	CSR38	CS38				CS38
0x194	CSR39	CS39				CS39
0x198	CSR40	CS40				CS40
0x19c	CSR41	CS41				CS41
0x1a0	CSR42	CS42				CS42
0x1a4	CSR43	CS43				CS43
0x1a8	CSR44	CS44				CS44
0x1ac	CSR45	CS45				CS45
0x1b0	CSR46	CS46				CS46
0x1b4	CSR47	CS47				CS47
0x1b8	CSR48	CS48				CS48
0x1bc	CSR49	CS49				CS49
0x1c0	CSR50	CS50				CS50
0x1c4	CSR51	CS51				CS51
0x1c8	CSR52	CS52				CS52
0x1cc	CSR53	CS53				CS53
0x310	HR0	H0				H0
0x314	HR1	H1				H1
0x318	HR2	H2				H2
0x31c	HR3	H3				H3
0x320	HR4	H4				H4
0x324	HR5	H5				H5
0x328	HR6	H6				H6
0x32c	HR7	H7				H7

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													ALGO rw		LKEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MDMAT rw	DINNE r	NBW r					MODE rw	DATATYPE rw		DMAE rw	INIT w

Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO

Bits 17-18: Algorithm selection.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATAIN w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAIN w

Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DCAL w				NBLW rw

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DCIE rw	DINIE rw

Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											NBWE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DINNE r		NBWP r										BUSY r	DMAS r	DCIS rw	DINIS rw

Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

NBWP

Bits 9-13: Number of words already pushed.

DINNE

Bit 15: DIN not empty.

NBWE

Bits 16-20: Number of words expected.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS0 rw

Toggle fields

CS0

Bits 0-31: CS0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS1 rw

Toggle fields

CS1

Bits 0-31: CS1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS2 rw

Toggle fields

CS2

Bits 0-31: CS2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS3 rw

Toggle fields

CS3

Bits 0-31: CS3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS4 rw

Toggle fields

CS4

Bits 0-31: CS4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS5 rw

Toggle fields

CS5

Bits 0-31: CS5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS6 rw

Toggle fields

CS6

Bits 0-31: CS6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS7 rw

Toggle fields

CS7

Bits 0-31: CS7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS8 rw

Toggle fields

CS8

Bits 0-31: CS8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS9 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS9 rw

Toggle fields

CS9

Bits 0-31: CS9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS10 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS10 rw

Toggle fields

CS10

Bits 0-31: CS10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS11 rw

Toggle fields

CS11

Bits 0-31: CS11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS12 rw

Toggle fields

CS12

Bits 0-31: CS12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS13 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS13 rw

Toggle fields

CS13

Bits 0-31: CS13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS14 rw

Toggle fields

CS14

Bits 0-31: CS14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS15 rw

Toggle fields

CS15

Bits 0-31: CS15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS16 rw

Toggle fields

CS16

Bits 0-31: CS16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS17 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS17 rw

Toggle fields

CS17

Bits 0-31: CS17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS18 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS18 rw

Toggle fields

CS18

Bits 0-31: CS18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS19 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS19 rw

Toggle fields

CS19

Bits 0-31: CS19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS20 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS20 rw

Toggle fields

CS20

Bits 0-31: CS20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS21 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS21 rw

Toggle fields

CS21

Bits 0-31: CS21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS22 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS22 rw

Toggle fields

CS22

Bits 0-31: CS22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS23 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS23 rw

Toggle fields

CS23

Bits 0-31: CS23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS24 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS24 rw

Toggle fields

CS24

Bits 0-31: CS24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS25 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS25 rw

Toggle fields

CS25

Bits 0-31: CS25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS26 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS26 rw

Toggle fields

CS26

Bits 0-31: CS26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS27 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS27 rw

Toggle fields

CS27

Bits 0-31: CS27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS28 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS28 rw

Toggle fields

CS28

Bits 0-31: CS28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS29 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS29 rw

Toggle fields

CS29

Bits 0-31: CS29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS30 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS30 rw

Toggle fields

CS30

Bits 0-31: CS30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS31 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS31 rw

Toggle fields

CS31

Bits 0-31: CS31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS32 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS32 rw

Toggle fields

CS32

Bits 0-31: CS32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS33 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS33 rw

Toggle fields

CS33

Bits 0-31: CS33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS34 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS34 rw

Toggle fields

CS34

Bits 0-31: CS34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS35 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS35 rw

Toggle fields

CS35

Bits 0-31: CS35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS36 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS36 rw

Toggle fields

CS36

Bits 0-31: CS36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS37 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS37 rw

Toggle fields

CS37

Bits 0-31: CS37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS38 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS38 rw

Toggle fields

CS38

Bits 0-31: CS38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS39 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS39 rw

Toggle fields

CS39

Bits 0-31: CS39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS40 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS40 rw

Toggle fields

CS40

Bits 0-31: CS40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS41 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS41 rw

Toggle fields

CS41

Bits 0-31: CS41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS42 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS42 rw

Toggle fields

CS42

Bits 0-31: CS42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS43 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS43 rw

Toggle fields

CS43

Bits 0-31: CS43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS44 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS44 rw

Toggle fields

CS44

Bits 0-31: CS44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS45 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS45 rw

Toggle fields

CS45

Bits 0-31: CS45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS46 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS46 rw

Toggle fields

CS46

Bits 0-31: CS46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS47 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS47 rw

Toggle fields

CS47

Bits 0-31: CS47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS48 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS48 rw

Toggle fields

CS48

Bits 0-31: CS48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS49 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS49 rw

Toggle fields

CS49

Bits 0-31: CS49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS50 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS50 rw

Toggle fields

CS50

Bits 0-31: CS50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS51 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS51 rw

Toggle fields

CS51

Bits 0-31: CS51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS52 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS52 rw

Toggle fields

CS52

Bits 0-31: CS52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS53 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS53 rw

Toggle fields

CS53

Bits 0-31: CS53.

HR0

digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H0 r

Toggle fields

H0

Bits 0-31: H0.

HR1

digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H1 r

Toggle fields

H1

Bits 0-31: H1.

HR2

digest register 4

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H2 r

Toggle fields

H2

Bits 0-31: H2.

HR3

digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H3 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H3 r

Toggle fields

H3

Bits 0-31: H3.

HR4

digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H4 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H4 r

Toggle fields

H4

Bits 0-31: H4.

HR5

supplementary digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H5 r

Toggle fields

H5

Bits 0-31: H5.

HR6

supplementary digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H6 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H6 r

Toggle fields

H6

Bits 0-31: H6.

HR7

supplementary digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
H7 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
H7 r

Toggle fields

H7

Bits 0-31: H7.

SEC_I2C1

0x50005400: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

SEC_I2C2

0x50005800: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

SEC_I2C3

0x56002800: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

SEC_I2C4

0x50008400: Inter-integrated circuit

17/84 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	STOPFACLR	ADDRACLR				FMP	PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2				PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1															OA1EN					OA1MODE	OA1
0xc	OAR2															OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC						SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN		TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR							ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																	ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																							PEC
0x24	RXDR																							RXDATA
0x28	TXDR																							TXDATA
0x2c	I2C_AUTOCR									TRIGEN	TRIGPOL	TRIGSEL												TCRDMAEN	TCDMAEN

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
STOPFACLR rw	ADDRACLR rw						FMP rw	PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

FMP

Bit 24: Fast-mode Plus 20 mA drive enable.

ADDRACLR

Bit 30: Address match flag (ADDR) automatic clear.

STOPFACLR

Bit 31: STOP detection flag (STOPF) automatic clear.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C_AUTOCR

I2C Autonomous mode control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TCRDMAEN rw	TCDMAEN rw

Toggle fields

TCDMAEN

Bit 6: DMA request enable on Transfer Complete event.

TCRDMAEN

Bit 7: DMA request enable on Transfer Complete Reload event.

TRIGSEL

Bits 16-19: Trigger selection.

TRIGPOL

Bit 20: Trigger polarity.

TRIGEN

Bit 21: Trigger enable.

SEC_ICache

0x50030400: ICache

5/40 fields covered.

Toggle register map

Offset	Name	31	28	26	19	18	17	16	15	11	7	2	1	0
0x0	ICACHE_CR				MISSMRST	HITMRST	MISSMEN	HITMEN				WAYSEL	CACHEINV	EN
0x4	ICACHE_SR											ERRF	BSYENDF	BUSYF
0x8	ICACHE_IER											ERRIE	BSYENDIE
0xc	ICACHE_FCR											CERRF	CBSYENDF
0x10	ICACHE_HMONR	HITMON							HITMON
0x14	ICACHE_MMONR								MISSMON
0x20	ICACHE_CRR0	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR
0x24	ICACHE_CRR1	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR
0x28	ICACHE_CRR2	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR
0x2c	ICACHE_CRR3	HBURST	MSTSEL	REMAPADDR					REN	RSIZE	BASEADDR

Toggle registers

ICACHE_CR

ICACHE control register

Offset: 0x0, size: 32, reset: 0x00000004, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												MISSMRST rw	HITMRST rw	MISSMEN rw	HITMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WAYSEL rw	CACHEINV w	EN rw

Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

WAYSEL

Bit 2: WAYSEL.

HITMEN

Bit 16: HITMEN.

MISSMEN

Bit 17: MISSMEN.

HITMRST

Bit 18: HITMRST.

MISSMRST

Bit 19: MISSMRST.

ICACHE_SR

ICACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													ERRF r	BSYENDF r	BUSYF r

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

ICACHE_CRR1

ICACHE region configuration register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

ICACHE_CRR2

ICACHE region configuration register

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

ICACHE_CRR3

ICACHE region configuration register

Offset: 0x2c, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HBURST rw			MSTSEL rw		REMAPADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REN rw				RSIZE rw				BASEADDR rw

Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

SEC_IWDG

0x50003000: Independent watchdog

5/12 fields covered.

Toggle register map

Offset	Name	15	14	11	3	2	1	0
0x0	KR	KEY
0x4	PR				PR
0x8	RLR			RL
0xc	SR		EWIF		EWU	WVU	RVU	PVU
0x10	WINR			WIN
0x14	EWCR	EWIE	EWIC	EWIT

Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PR rw

Toggle fields

PR

Bits 0-3: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EWIF r											EWU r	WVU r	RVU r	PVU r

Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

EWU

Bit 3: Watchdog interrupt comparator value update.

EWIF

Bit 14: Watchdog Early interrupt flag.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

EWCR

IWDG early wakeup interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EWIE rw	EWIC rw			EWIT rw

Toggle fields

EWIT

Bits 0-11: Watchdog counter window value.

EWIC

Bit 14: Watchdog early interrupt acknowledge.

EWIE

Bit 15: Watchdog early interrupt enable.

SEC_LPDMA1

0x56025000: LPDMA1

36/212 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	25	23	20	19	17	16	15	13	12	11	10	9	8	4	3	2	1	0
0x0	LPDMA_SECCFGR																				SEC3	SEC2	SEC1	SEC0
0x4	LPDMA_PRIVCFGR																				PRIV3	PRIV2	PRIV1	PRIV0
0xc	MISR																				MIS3	MIS2	MIS1	MIS0
0x10	SMISR																				MIS3	MIS2	MIS1	MIS0
0x50	LPDMA_C0LBAR	LBA
0x5c	LPDMA_C0FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x60	LPDMA_C0SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0x64	LPDMA_C0CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x90	LPDMA_C0TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x94	LPDMA_C0TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x98	LPDMA_C0BR1												BNDT
0x9c	LPDMA_C0SAR	SA											SA
0xa0	LPDMA_C0DAR	DA											DA
0xcc	LPDMA_C0LLR	UT1	UT2	UB1	USA	UDA						ULL	LA
0xd0	LPDMA_C1LBAR	LBA
0xdc	LPDMA_C1FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0xe0	LPDMA_C1SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0xe4	LPDMA_C1CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x110	LPDMA_C1TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x114	LPDMA_C1TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x118	LPDMA_C1BR1												BNDT
0x11c	LPDMA_C1SAR	SA											SA
0x120	LPDMA_C1DAR	DA											DA
0x14c	LPDMA_C1LLR	UT1	UT2	UB1	USA	UDA						ULL	LA
0x150	LPDMA_C2LBAR	LBA
0x15c	LPDMA_C2FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x160	LPDMA_C2SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0x164	LPDMA_C2CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x190	LPDMA_C2TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x194	LPDMA_C2TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x198	LPDMA_C2BR1												BNDT
0x19c	LPDMA_C2SAR	SA											SA
0x1a0	LPDMA_C2DAR	DA											DA
0x1cc	LPDMA_C2LLR	UT1	UT2	UB1	USA	UDA						ULL	LA
0x1d0	LPDMA_C3LBAR	LBA
0x1dc	LPDMA_C3FCR													SUSPF	USEF	ULEF	DTEF	HTF	TCF
0x1e0	LPDMA_C3SR													SUSPF	USEF	ULEF	DTEF	HTF	TCF					IDLEF
0x1e4	LPDMA_C3CR							PRIO				LSM		SUSPIE	USEIE	ULEIE	DTEIE	HTIE	TCIE			SUSP	RESET	EN
0x210	LPDMA_C3TR1	DSEC								DINC	DDW_LOG2		SSEC		PAM						SINC		SDW_LOG2
0x214	LPDMA_C3TR2	TCEM					TRIGPOL		TRIGSEL				TRIGM			BREQ		SWREQ		REQSEL
0x218	LPDMA_C3BR1												BNDT
0x21c	LPDMA_C3SAR	SA											SA
0x220	LPDMA_C3DAR	DA											DA
0x24c	LPDMA_C3LLR	UT1	UT2	UB1	USA	UDA						ULL	LA

Toggle registers

LPDMA_SECCFGR

LPDMA secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												SEC3 rw	SEC2 rw	SEC1 rw	SEC0 rw

Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

LPDMA_PRIVCFGR

LPDMA privileged configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRIV3 rw	PRIV2 rw	PRIV1 rw	PRIV0 rw

Toggle fields

PRIV0

Bit 0: PRIV0.

PRIV1

Bit 1: PRIV1.

PRIV2

Bit 2: PRIV2.

PRIV3

Bit 3: PRIV3.

MISR

LPDMA non-secure masked interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

SMISR

LPDMA secure masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												MIS3 r	MIS2 r	MIS1 r	MIS0 r

Toggle fields

MIS0

Bit 0: MIS0.

MIS1

Bit 1: MIS1.

MIS2

Bit 2: MIS2.

MIS3

Bit 3: MIS3.

LPDMA_C0LBAR

channel x linked-list base address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C0FCR

LPDMA channel x flag clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C0SR

channel x status register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C0CR

channel x control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

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EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C0TR1

LPDMA channel x transfer register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

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SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C0TR2

LPDMA channel x transfer register 2

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

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REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if LPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C0BR1

LPDMA channel x block register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

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BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C0SAR

LPDMA channel x source address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

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SA

Bits 0-31: source address.

LPDMA_C0DAR

LPDMA channel x destination address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

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DA

Bits 0-31: destination address.

LPDMA_C0LLR

LPDMA channel x linked-list address register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

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LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPDMA_C1LBAR

channel x linked-list base address register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C1FCR

LPDMA channel x flag clear register

Offset: 0xdc, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

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TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C1SR

channel x status register

Offset: 0xe0, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

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IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C1CR

channel x control register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

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EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C1TR1

LPDMA channel x transfer register 1

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

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SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C1TR2

LPDMA channel x transfer register 2

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C1BR1

LPDMA channel x block register 1

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C1SAR

LPDMA channel x source address register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C1DAR

LPDMA channel x destination address register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C1LLR

LPDMA channel x linked-list address register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPDMA_C2LBAR

channel x linked-list base address register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C2FCR

LPDMA channel x flag clear register

Offset: 0x15c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C2SR

channel x status register

Offset: 0x160, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C2CR

channel x control register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C2TR1

LPDMA channel x transfer register 1

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C2TR2

LPDMA channel x transfer register 2

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C2BR1

LPDMA channel x block register 1

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C2SAR

LPDMA channel x source address register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C2DAR

LPDMA channel x destination address register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C2LLR

LPDMA channel x linked-list address register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

LPDMA_C3LBAR

channel x linked-list base address register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LBA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

LBA

Bits 16-31: linked-list base address of DMA channel x.

LPDMA_C3FCR

LPDMA channel x flag clear register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF w	USEF w	ULEF w	DTEF w	HTF w	TCF w

Toggle fields

TCF

Bit 8: transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag.

HTF

Bit 9: half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag.

DTEF

Bit 10: data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag.

ULEF

Bit 11: update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag.

USEF

Bit 12: user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag.

SUSPF

Bit 13: completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag.

LPDMA_C3SR

channel x status register

Offset: 0x1e0, size: 32, reset: 0x00000001, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPF r	USEF r	ULEF r	DTEF r	HTF r	TCF r								IDLEF r

Toggle fields

IDLEF

Bit 0: idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state)..

TCF

Bit 8: transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]..

HTF

Bit 9: half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination..

DTEF

Bit 10: data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer.

ULEF

Bit 11: update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory.

USEF

Bit 12: user setting error flag - 0: no user setting error event - 1: a user setting error event occurred.

SUSPF

Bit 13: completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred.

LPDMA_C3CR

channel x control register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRIO rw							LSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SUSPIE rw	USEIE rw	ULEIE rw	DTEIE rw	HTIE rw	TCIE rw						SUSP rw	RESET rw	EN rw

Toggle fields

EN

Bit 0: enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored..

RESET

Bit 1: reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence..

SUSP

Bit 2: suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence..

TCIE

Bit 8: transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

HTIE

Bit 9: half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

DTEIE

Bit 10: data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

ULEIE

Bit 11: update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

USEIE

Bit 12: user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

SUSPIE

Bit 13: completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled.

LSM

Bit 16: Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1..

PRIO

Bits 22-23: priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1..

LPDMA_C3TR1

LPDMA channel x transfer register 1

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DSEC rw												DINC rw		DDW_LOG2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSEC rw			PAM rw									SINC rw		SDW_LOG2 rw

Toggle fields

SDW_LOG2

Bits 0-1: binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

SINC

Bit 3: source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

PAM

Bits 11-12: PAM.

SSEC

Bit 15: security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

DDW_LOG2

Bits 16-17: binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued..

DINC

Bit 19: destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer..

DSEC

Bit 31: security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure.

LPDMA_C3TR2

LPDMA channel x transfer register 2

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TCEM rw						TRIGPOL rw					TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGM rw				BREQ rw		SWREQ rw					REQSEL rw

Toggle fields

REQSEL

Bits 0-4: DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting..

SWREQ

Bit 9: Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored..

BREQ

Bit 11: BREQ.

TRIGM

Bits 14-15: Trigger mode.

TRIGSEL

Bits 16-20: Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00..

TRIGPOL

Bits 24-25: Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00.

TCEM

Bits 30-31: Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated..

LPDMA_C3BR1

LPDMA channel x block register 1

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BNDT rw

Toggle fields

BNDT

Bits 0-15: block number of data bytes to transfer from the source.

LPDMA_C3SAR

LPDMA channel x source address register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SA rw

Toggle fields

SA

Bits 0-31: source address.

LPDMA_C3DAR

LPDMA channel x destination address register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DA rw

Toggle fields

DA

Bits 0-31: destination address.

LPDMA_C3LLR

LPDMA channel x linked-list address register

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UT1 rw	UT2 rw	UB1 rw	USA rw	UDA rw											ULL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LA rw

Toggle fields

LA

Bits 2-15: pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored..

ULL

Bit 16: Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update.

UDA

Bit 27: Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update.

USA

Bit 28: Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update.

UB1

Bit 29: Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update.

UT2

Bit 30: Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update.

UT1

Bit 31: Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update.

SEC_LPGPIO1

0x56020000: LPGPIO1

16/96 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	LPGPIO_MODER																	MODE15	MODE14	MODE13	MODE12	MODE11	MODE10	MODE9	MODE8	MODE7	MODE6	MODE5	MODE4	MODE3	MODE2	MODE1	MODE0
0x10	LPGPIO_IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	LPGPIO_ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	LPGPIO_BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x28	LPGPIO_BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

LPGPIO_MODER

LPGPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE15 rw	MODE14 rw	MODE13 rw	MODE12 rw	MODE11 rw	MODE10 rw	MODE9 rw	MODE8 rw	MODE7 rw	MODE6 rw	MODE5 rw	MODE4 rw	MODE3 rw	MODE2 rw	MODE1 rw	MODE0 rw

Toggle fields

MODE0

Bit 0: MODE0.

MODE1

Bit 1: MODE1.

MODE2

Bit 2: MODE2.

MODE3

Bit 3: MODE3.

MODE4

Bit 4: MODE4.

MODE5

Bit 5: MODE5.

MODE6

Bit 6: MODE6.

MODE7

Bit 7: MODE7.

MODE8

Bit 8: MODE8.

MODE9

Bit 9: MODE9.

MODE10

Bit 10: MODE10.

MODE11

Bit 11: MODE11.

MODE12

Bit 12: MODE12.

MODE13

Bit 13: MODE13.

MODE14

Bit 14: MODE14.

MODE15

Bit 15: MODE15.

LPGPIO_IDR

LPGPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: ID0.

ID1

Bit 1: ID1.

ID2

Bit 2: ID2.

ID3

Bit 3: ID3.

ID4

Bit 4: ID4.

ID5

Bit 5: ID5.

ID6

Bit 6: ID6.

ID7

Bit 7: ID7.

ID8

Bit 8: ID8.

ID9

Bit 9: ID9.

ID10

Bit 10: ID10.

ID11

Bit 11: ID11.

ID12

Bit 12: ID12.

ID13

Bit 13: ID13.

ID14

Bit 14: ID14.

ID15

Bit 15: ID15.

LPGPIO_ODR

LPGPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: OD0.

OD1

Bit 1: OD1.

OD2

Bit 2: OD2.

OD3

Bit 3: OD3.

OD4

Bit 4: OD4.

OD5

Bit 5: OD5.

OD6

Bit 6: OD6.

OD7

Bit 7: OD7.

OD8

Bit 8: OD8.

OD9

Bit 9: OD9.

OD10

Bit 10: OD10.

OD11

Bit 11: OD11.

OD12

Bit 12: OD12.

OD13

Bit 13: OD13.

OD14

Bit 14: OD14.

OD15

Bit 15: OD15.

LPGPIO_BSRR

LPGPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LPGPIO_BRR

LPGPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

SEC_LPTIM1

0x56004400: Low power timer

25/110 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR_input			DIEROK										CC2OF	CC1OF		CC2IF	REPOK	UE	DOWN	UP	ARROK		EXTTRIG	ARRM	CC1IF
0x0	ISR_output			DIEROK					CMP2OK								CC2IF	REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR_input			DIEROKCF										CC2OCF	CC1OCF		CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF		EXTTRIGCF	ARRMCF	CC1IF
0x4	ICR_output			DIEROKCF					CMP2OKCF								CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER_input		CC2DE									CC1DE		CC2OIE	CC1OIE		CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE		EXTTRIGIE	ARRMIE	CC1IF
0x8	DIER_output				UEDE				CMP2OKIE								CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL			PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																					RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL										IN2SEL				IN1SEL
0x28	RCR																		REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F			IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR_input

Interrupt and Status Register (intput mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OF r	CC1OF r			CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r		EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Capture 2 interrupt flag.

CC1OF

Bit 12: Capture 1 over-capture flag.

CC2OF

Bit 13: Capture 2 over-capture flag.

DIEROK

Bit 24: Interrupt enable register update OK.

ISR_output

Interrupt and Status Register (output mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r					CMP2OK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Compare 2 interrupt flag.

CMP2OK

Bit 19: Compare register 2 update OK.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR_input

Interrupt Clear Register (intput mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OCF w	CC1OCF w			CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w		EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CC1OCF

Bit 12: Capture/compare 1 over-capture clear flag.

CC2OCF

Bit 13: Capture/compare 2 over-capture clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

ICR_output

Interrupt Clear Register (output mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w					CMP2OKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CMP2OKCF

Bit 19: Compare register 2 update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER_input

LPTIM interrupt Enable Register (intput mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CC2DE rw									CC1DE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OIE rw	CC1OIE rw			CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw		EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CC1OIE

Bit 12: Capture/compare 1 over-capture interrupt enable.

CC2OIE

Bit 13: Capture/compare 2 over-capture interrupt enable.

CC1DE

Bit 16: Capture/compare 1 DMA request enable.

CC2DE

Bit 25: Capture/compare 2 DMA request enable.

DIER_output

LPTIM interrupt Enable Register (output mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UEDE rw				CMP2OKIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CMP2OKIE

Bit 19: Compare register 2 update OK interrupt enable.

UEDE

Bit 23: Update event DMA request enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

SEC_LPTIM2

0x50009400: Low power timer

25/110 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR_input			DIEROK										CC2OF	CC1OF		CC2IF	REPOK	UE	DOWN	UP	ARROK		EXTTRIG	ARRM	CC1IF
0x0	ISR_output			DIEROK					CMP2OK								CC2IF	REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR_input			DIEROKCF										CC2OCF	CC1OCF		CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF		EXTTRIGCF	ARRMCF	CC1IF
0x4	ICR_output			DIEROKCF					CMP2OKCF								CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER_input		CC2DE									CC1DE		CC2OIE	CC1OIE		CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE		EXTTRIGIE	ARRMIE	CC1IF
0x8	DIER_output				UEDE				CMP2OKIE								CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL			PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																					RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL										IN2SEL				IN1SEL
0x28	RCR																		REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F			IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR_input

Interrupt and Status Register (intput mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OF r	CC1OF r			CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r		EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Capture 2 interrupt flag.

CC1OF

Bit 12: Capture 1 over-capture flag.

CC2OF

Bit 13: Capture 2 over-capture flag.

DIEROK

Bit 24: Interrupt enable register update OK.

ISR_output

Interrupt and Status Register (output mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r					CMP2OK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Compare 2 interrupt flag.

CMP2OK

Bit 19: Compare register 2 update OK.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR_input

Interrupt Clear Register (intput mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OCF w	CC1OCF w			CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w		EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CC1OCF

Bit 12: Capture/compare 1 over-capture clear flag.

CC2OCF

Bit 13: Capture/compare 2 over-capture clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

ICR_output

Interrupt Clear Register (output mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w					CMP2OKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CMP2OKCF

Bit 19: Compare register 2 update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER_input

LPTIM interrupt Enable Register (intput mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CC2DE rw									CC1DE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OIE rw	CC1OIE rw			CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw		EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CC1OIE

Bit 12: Capture/compare 1 over-capture interrupt enable.

CC2OIE

Bit 13: Capture/compare 2 over-capture interrupt enable.

CC1DE

Bit 16: Capture/compare 1 DMA request enable.

CC2DE

Bit 25: Capture/compare 2 DMA request enable.

DIER_output

LPTIM interrupt Enable Register (output mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UEDE rw				CMP2OKIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CMP2OKIE

Bit 19: Compare register 2 update OK interrupt enable.

UEDE

Bit 23: Update event DMA request enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

SEC_LPTIM3

0x56004800: Low power timer

25/110 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	12	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR_input			DIEROK										CC2OF	CC1OF		CC2IF	REPOK	UE	DOWN	UP	ARROK		EXTTRIG	ARRM	CC1IF
0x0	ISR_output			DIEROK					CMP2OK								CC2IF	REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR_input			DIEROKCF										CC2OCF	CC1OCF		CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF		EXTTRIGCF	ARRMCF	CC1IF
0x4	ICR_output			DIEROKCF					CMP2OKCF								CC2CF	REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER_input		CC2DE									CC1DE		CC2OIE	CC1OIE		CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE		EXTTRIGIE	ARRMIE	CC1IF
0x8	DIER_output				UEDE				CMP2OKIE								CC2IE	REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL			PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																					RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL										IN2SEL				IN1SEL
0x28	RCR																		REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F			IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR_input

Interrupt and Status Register (intput mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OF r	CC1OF r			CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r		EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Capture 2 interrupt flag.

CC1OF

Bit 12: Capture 1 over-capture flag.

CC2OF

Bit 13: Capture 2 over-capture flag.

DIEROK

Bit 24: Interrupt enable register update OK.

ISR_output

Interrupt and Status Register (output mode)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r					CMP2OK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IF r	REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

CC2IF

Bit 9: Compare 2 interrupt flag.

CMP2OK

Bit 19: Compare register 2 update OK.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR_input

Interrupt Clear Register (intput mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OCF w	CC1OCF w			CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w		EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CC1OCF

Bit 12: Capture/compare 1 over-capture clear flag.

CC2OCF

Bit 13: Capture/compare 2 over-capture clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

ICR_output

Interrupt Clear Register (output mode)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w					CMP2OKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2CF w	REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

CC2CF

Bit 9: Capture/compare 2 clear flag.

CMP2OKCF

Bit 19: Compare register 2 update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER_input

LPTIM interrupt Enable Register (intput mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						CC2DE rw									CC1DE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC2OIE rw	CC1OIE rw			CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw		EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CC1OIE

Bit 12: Capture/compare 1 over-capture interrupt enable.

CC2OIE

Bit 13: Capture/compare 2 over-capture interrupt enable.

CC1DE

Bit 16: Capture/compare 1 DMA request enable.

CC2DE

Bit 25: Capture/compare 2 DMA request enable.

DIER_output

LPTIM interrupt Enable Register (output mode)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UEDE rw				CMP2OKIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC2IE rw	REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CC2IE

Bit 9: Capture/compare 2 interrupt enable.

CMP2OKIE

Bit 19: Compare register 2 update OK interrupt enable.

UEDE

Bit 23: Update event DMA request enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

SEC_LPTIM4

0x56004c00: Low power timer

11/66 fields covered.

Toggle register map

Offset	Name	29	25	24	23	22	21	20	19	18	17	16	15	13	11	9	8	7	6	5	4	3	2	1	0
0x0	ISR			DIEROK													REPOK	UE	DOWN	UP	ARROK	CMP1OK	EXTTRIG	ARRM	CC1IF
0x4	ICR			DIEROKCF													REPOKCF	UECF	DOWNCF	UPCF	ARROKCF	CMP1OKCF	EXTTRIGCF	ARRMCF	CC1IF
0x8	DIER																REPOKIE	UEIE	DOWNIE	UPIE	ARROKIE	CMP1OKIE	EXTTRIGIE	ARRMIE	CC1IF
0xc	CFGR			ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN			TRIGSEL		PRESC			TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR																				RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CCR1												CCR1
0x18	ARR												ARR
0x1c	CNT												CNT
0x24	CFGR2						IC2SEL				IC1SEL									IN2SEL				IN1SEL
0x28	RCR																	REP
0x2c	CCMR1	IC2F	IC2PSC						CC2P		CC2E	CC2SEL		IC1F		IC1PSC						CC1P		CC1E	CC1SEL
0x34	CCR2												CCR2

Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							REPOK r	UE r	DOWN r	UP r	ARROK r	CMP1OK r	EXTTRIG r	ARRM r	CC1IF r

Toggle fields

CC1IF

Bit 0: Compare 1 interrupt flag.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMP1OK

Bit 3: Compare register 1 update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

DIEROK

Bit 24: Interrupt enable register update OK.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DIEROKCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							REPOKCF w	UECF w	DOWNCF w	UPCF w	ARROKCF w	CMP1OKCF w	EXTTRIGCF w	ARRMCF w	CC1IF w

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMP1OKCF

Bit 3: Compare register 1 update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

DIEROKCF

Bit 24: Interrupt enable register update OK clear flag.

DIER

LPTIM interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							REPOKIE rw	UEIE rw	DOWNIE rw	UPIE rw	ARROKIE rw	CMP1OKIE rw	EXTTRIGIE rw	ARRMIE rw	CC1IF rw

Toggle fields

CC1IF

Bit 0: Capture/compare 1 clear flag.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMP1OKIE

Bit 3: Compare register 1 update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CCR1

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/compare 1 value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										IC2SEL rw				IC1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN2SEL rw				IN1SEL rw

Toggle fields

IN1SEL

Bits 0-1: LPTIM input 1 selection.

IN2SEL

Bits 4-5: LPTIM input 2 selection.

IC1SEL

Bits 16-17: LPTIM input capture 1 selection.

IC2SEL

Bits 20-21: LPTIM input capture 2 selection.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition register value.

CCMR1

LPTIM capture/compare mode register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IC2F rw				IC2PSC rw						CC2P rw		CC2E rw	CC2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IC1F rw				IC1PSC rw						CC1P rw		CC1E rw	CC1SEL rw

Toggle fields

CC1SEL

Bit 0: Capture/compare 1 selection.

CC1E

Bit 1: Capture/compare 1 output enable.

CC1P

Bits 2-3: Capture/compare 1 output polarity.

IC1PSC

Bits 8-9: Input capture 1 prescaler.

IC1F

Bits 12-13: Input capture 1 filter.

CC2SEL

Bit 16: Capture/compare 2 selection.

CC2E

Bit 17: Capture/compare 2 output enable.

CC2P

Bits 18-19: Capture/compare 2 output polarity.

IC2PSC

Bits 24-25: Input capture 2 prescaler.

IC2F

Bits 28-29: Input capture 2 filter.

CCR2

LPTIM Compare Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/compare 2 value.

SEC_LPUART1

0x56002400: Universal synchronous asynchronous receiver transmitter

37/120 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1			DEAT					DEDT						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1			DEAT					DEDT						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD												MSBFIRST	DATAINV	TXINV	RXINV	SWAP		STOP									ADDM7
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG				TXFTIE								DEP	DEM	DDRE	OVRDIS		CTSIE	CTSE	RTSE	DMAT	DMAR			HDSEL			EIE
0xc	BRR													BRR				BRR
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ
0x1c	ISR_disabled										REACK	TEACK		RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT		RXFF	TXFF	REACK	TEACK		RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF								CTSCF			TCCF		IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR										TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFNEIE.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFNEIE.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw												MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw		STOP rw									ADDM7 rw

Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

STOP

Bits 12-13: STOP bits.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ADD

Bits 24-31: Address of the LPUART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw				TXFTIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw		CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw			HDSEL rw			EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

TXFTIE

Bit 23: TXFTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BRR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-19: BRR.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w

Toggle fields

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: TXFRQ.

ISR_disabled

Interrupt and status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXE r	TC r	RXNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ISR_enabled

Interrupt and status register

Offset: 0x1c, size: 32, reset: 0x008000C0, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r		RXFF r	TXFF r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFF

Bit 23: TXFF.

RXFF

Bit 24: RXFF.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTSCF w			TCCF w		IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TCCF

Bit 6: Transmission complete clear flag.

CTSCF

Bit 9: CTS clear flag.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Autonomous mode control register

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIGPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

SEC_MDF1

0x50025000: Multi-function digital filter

90/415 fields covered.

Toggle register map

Offset	Name	31	30	27	25	21	19	16	15	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GCR															ILVNB							TRGO
0x4	CKGCR	CKGACTIVE	PROCDIV				CCKDIV		TRGSRC						TRGSENS		CCK1DIR	CCK0DIR	CKGMOD		CCK1EN	CCK0EN	CKGDEN
0x80	MDF_SITF0CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x84	MDF_BSMX0CR	BSMXACTIVE																	BSSEL
0x88	MDF_DFLT0CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x8c	MDF_DFLT0CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x90	MDF_DFLT0RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x94	MDF_DFLT0INTR												INTVAL									INTDIV
0x98	MDF_OLD0CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x9c	MDF_OLD0THLR				OLDTHL				OLDTHL
0xa0	MDF_OLD0THHR				OLDTHH				OLDTHH
0xa4	MDF_DLY0CR	SKPBF															SKPDLY
0xa8	MDF_SCD0CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0xac	MDF_DFLT0IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0xb0	MDF_DFLT0ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0xb4	MDF_OEC0CR				OFFSET				OFFSET
0xec	MDF_SNPS0DR	SDR							EXTSDR						MCICDC
0xf0	MDF_DFLT0DR	DR							DR
0x100	MDF_SITF1CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x104	MDF_BSMX1CR	BSMXACTIVE																	BSSEL
0x108	MDF_DFLT1CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x10c	MDF_DFLT1CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x110	MDF_DFLT1RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x114	MDF_DFLT1INTR												INTVAL									INTDIV
0x118	MDF_OLD1CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x11c	MDF_OLD1THLR				OLDTHL				OLDTHL
0x120	MDF_OLD1THHR				OLDTHH				OLDTHH
0x124	MDF_DLY1CR	SKPBF															SKPDLY
0x128	MDF_SCD1CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x12c	MDF_DFLT1IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x130	MDF_DFLT1ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x134	MDF_OEC1CR				OFFSET				OFFSET
0x16c	MDF_SNPS1DR	SDR							EXTSDR						MCICDC
0x170	MDF_DFLT1DR	DR							DR
0x180	MDF_SITF2CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x184	MDF_BSMX2CR	BSMXACTIVE																	BSSEL
0x188	MDF_DFLT2CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x18c	MDF_DFLT2CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x190	MDF_DFLT2RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x194	MDF_DFLT2INTR												INTVAL									INTDIV
0x198	MDF_OLD2CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x19c	MDF_OLD2THLR				OLDTHL				OLDTHL
0x1a0	MDF_OLD2THHR				OLDTHH				OLDTHH
0x1a4	MDF_DLY2CR	SKPBF															SKPDLY
0x1a8	MDF_SCD2CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x1ac	MDF_DFLT2IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x1b0	MDF_DFLT2ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x1b4	MDF_OEC2CR				OFFSET				OFFSET
0x1ec	MDF_SNPS2DR	SDR							EXTSDR						MCICDC
0x1f0	MDF_DFLT2DR	DR							DR
0x200	MDF_SITF3CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x204	MDF_BSMX3CR	BSMXACTIVE																	BSSEL
0x208	MDF_DFLT3CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x20c	MDF_DFLT3CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x210	MDF_DFLT3RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x214	MDF_DFLT3INTR												INTVAL									INTDIV
0x218	MDF_OLD3CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x21c	MDF_OLD3THLR				OLDTHL				OLDTHL
0x220	MDF_OLD3THHR				OLDTHH				OLDTHH
0x224	MDF_DLY3CR	SKPBF															SKPDLY
0x228	MDF_SCD3CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x22c	MDF_DFLT3IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x230	MDF_DFLT3ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x234	MDF_OEC3CR				OFFSET				OFFSET
0x26c	MDF_SNPS3DR	SDR							EXTSDR						MCICDC
0x270	MDF_DFLT3DR	DR							DR
0x280	MDF_SITF4CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x284	MDF_BSMX4CR	BSMXACTIVE																	BSSEL
0x288	MDF_DFLT4CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x28c	MDF_DFLT4CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x290	MDF_DFLT4RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x294	MDF_DFLT4INTR												INTVAL									INTDIV
0x298	MDF_OLD4CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x29c	MDF_OLD4THLR				OLDTHL				OLDTHL
0x2a0	MDF_OLD4THHR				OLDTHH				OLDTHH
0x2a4	MDF_DLY4CR	SKPBF															SKPDLY
0x2a8	MDF_SCD4CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x2ac	MDF_DFLT4IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x2b0	MDF_DFLT4ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x2b4	MDF_OEC4CR				OFFSET				OFFSET
0x2ec	MDF_SNPS4DR	SDR							EXTSDR						MCICDC
0x2f0	MDF_DFLT4DR	DR							DR
0x300	MDF_SITF5CR	SITFACTIVE									STH							SITFMOD			SCKSRC		SITFEN
0x304	MDF_BSMX5CR	BSMXACTIVE																	BSSEL
0x308	MDF_DFLT5CR	DFLTACTIVE	DFLTRUN	NBDIS				SNPSFMT	TRGSRC						TRGSENS		ACQMOD				FTH	DMAEN	DFLTEN
0x30c	MDF_DFLT5CICR				SCALE			MCICD	MCICD								CICMOD					DATSRC
0x310	MDF_DFLT5RSFR													HPFC		HPFBYP			RSFLTD				RSFLTBYP
0x314	MDF_DFLT5INTR												INTVAL									INTDIV
0x318	MDF_OLD5CR	OLDACTIVE				ACICD				ACICN						BKOLD						THINB	OLDEN
0x31c	MDF_OLD5THLR				OLDTHL				OLDTHL
0x320	MDF_OLD5THHR				OLDTHH				OLDTHH
0x324	MDF_DLY5CR	SKPBF															SKPDLY
0x328	MDF_SCD5CR	SCDACTIVE					SCDT		SCDT							BKSCD							SCDEN
0x32c	MDF_DFLT5IER											RFOVRIE	CKABIE	SATIE	SCDIE	SSOVRIE			OLDIE		SSDRIE	DOVRIE	FTHIE
0x330	MDF_DFLT5ISR											RFOVRF	CKABF	SATF	SCDF	SSOVRF	THHF	THLF	OLDF	RXNEF	SSDRF	DOVRF	FTHF
0x334	MDF_OEC5CR				OFFSET				OFFSET
0x36c	MDF_SNPS5DR	SDR							EXTSDR						MCICDC
0x370	MDF_DFLT5DR	DR							DR

Toggle registers

GCR

MDF global control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ILVNB rw							TRGO rw

Toggle fields

TRGO

Bit 0: TRGO.

ILVNB

Bits 4-7: ILVNB.

CKGCR

MDF clock generator control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKGACTIVE rw	PROCDIV rw											CCKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		CCK1DIR rw	CCK0DIR rw	CKGMOD rw		CCK1EN rw	CCK0EN rw	CKGDEN rw

Toggle fields

CKGDEN

Bit 0: CKGDEN.

CCK0EN

Bit 1: CCK0EN.

CCK1EN

Bit 2: CCK1EN.

CKGMOD

Bit 4: CKGMOD.

CCK0DIR

Bit 5: CCK0DIR.

CCK1DIR

Bit 6: CCK1DIR.

TRGSENS

Bit 8: TRGSENS.

TRGSRC

Bits 12-15: TRGSRC.

CCKDIV

Bits 16-19: CCKDIV.

PROCDIV

Bits 24-30: PROCDIV.

CKGACTIVE

Bit 31: CKGACTIVE.

MDF_SITF0CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x80, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX0CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT0CR

This register is used to control the digital filter x.

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT0CICR

This register is used to control the main CIC filter.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT0RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT0INTR

This register is used to the integrator (INT) settings.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD0CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD0THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD0THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY0CR

This register is used for the adjustment stream delays.

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD0CR

This register is used for the adjustment stream delays.

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT0IER

This register is used for allowing or not the events to generate an interrupt.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

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FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT0ISR

MDF DFLT0 interrupt status register 0

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: FTHF.

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on , writing 0 has no effect. - 1: Reading 1 means that a new data is available on , writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was higher than OLDTHL when the last OLD event occurred. - 1: The signal was lower than OLDTHL when the last OLD event occurred..

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH when the last OLD event occurred. - 1: The signal was higher than OLDTHH when the last OLD event occurred..

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC0CR

This register contains the offset compensation value.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS0DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0xec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT0DR

This register is used to read the data processed by each digital filter.

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF1CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x100, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag.

MDF_BSMX1CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT1CR

This register is used to control the digital filter x.

Offset: 0x108, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT1CICR

This register is used to control the main CIC filter.

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

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DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT1RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT1INTR

This register is used to the integrator (INT) settings.

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

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INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD1CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x118, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD1THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD1THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY1CR

This register is used for the adjustment stream delays.

Offset: 0x124, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD1CR

This register is used for the adjustment stream delays.

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT1IER

MDF DFLTx interrupt enable register x

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT1ISR

This register contains the status flags for each digital filter path.

Offset: 0x130, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC1CR

This register contains the offset compensation value.

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS1DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT1DR

This register is used to read the data processed by each digital filter.

Offset: 0x170, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF2CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x180, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag.

MDF_BSMX2CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x184, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT2CR

This register is used to control the digital filter 2.

Offset: 0x188, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT2CICR

This register is used to control the main CIC filter.

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT2RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT2INTR

This register is used to the integrator (INT) settings.

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD2CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x198, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD2THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD2THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY2CR

This register is used for the adjustment stream delays.

Offset: 0x1a4, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD2CR

This register is used for the adjustment stream delays.

Offset: 0x1a8, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT2IER

MDF DFLTx interrupt enable register x

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT2ISR

This register contains the status flags for each digital filter path.

Offset: 0x1b0, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC2CR

This register contains the offset compensation value.

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS2DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT2DR

This register is used to read the data processed by each digital filter.

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF3CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x200, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX3CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x204, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to a in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT3CR

This register is used to control the digital filter 3.

Offset: 0x208, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT3CICR

This register is used to control the main CIC filter.

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT3RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT3INTR

This register is used to the integrator (INT) settings.

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD3CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x218, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD3THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD3THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY3CR

This register is used for the adjustment stream delays.

Offset: 0x224, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD3CR

This register is used for the adjustment stream delays.

Offset: 0x228, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT3IER

MDF DFLTx interrupt enable register x

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT3ISR

This register contains the status flags for each digital filter path.

Offset: 0x230, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC3CR

This register contains the offset compensation value.

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS3DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT3DR

This register is used to read the data processed by each digital filter.

Offset: 0x270, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF4CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x280, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX4CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x284, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT4CR

This register is used to control the digital filter 4.

Offset: 0x288, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT4CICR

This register is used to control the main CIC filter.

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT4RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT4INTR

This register is used to the integrator (INT) settings.

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD4CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x298, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD4THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD4THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY4CR

This register is used for the adjustment stream delays.

Offset: 0x2a4, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD4CR

This register is used for the adjustment stream delays.

Offset: 0x2a8, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT4IER

MDF DFLTx interrupt enable register x

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT4ISR

This register contains the status flags for each digital filter path.

Offset: 0x2b0, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC4CR

This register contains the offset compensation value.

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS4DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT4DR

This register is used to read the data processed by each digital filter.

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

MDF_SITF5CR

This register is used to control the serial interfaces (SITFx).

Offset: 0x300, size: 32, reset: 0x00001F00, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SITFACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			STH rw							SITFMOD rw			SCKSRC rw		SITFEN rw

Toggle fields

SITFEN

Bit 0: Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled.

SCKSRC

Bits 1-2: Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFMOD

Bits 4-5: Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

STH

Bits 8-12: Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SITFACTIVE

Bit 31: Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured..

MDF_BSMX5CR

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.

Offset: 0x304, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BSMXACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BSSEL rw

Toggle fields

BSSEL

Bits 0-4: Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BSMXACTIVE

Bit 31: BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured..

MDF_DFLT5CR

This register is used to control the digital filter x.

Offset: 0x308, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFLTACTIVE r	DFLTRUN r			NBDIS rw											SNPSFMT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRGSRC rw							TRGSENS rw		ACQMOD rw				FTH rw	DMAEN rw	DFLTEN w

Toggle fields

DFLTEN

Bit 0: Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,.

DMAEN

Bit 1: DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

FTH

Bit 2: RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACQMOD

Bits 4-6: Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSENS

Bit 8: Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

TRGSRC

Bits 12-15: Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SNPSFMT

Bit 16: Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

NBDIS

Bits 20-27: Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

DFLTRUN

Bit 30: Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running.

DFLTACTIVE

Bit 31: Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active.

MDF_DFLT5CICR

This register is used to control the main CIC filter.

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SCALE rw									MCICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCICD rw									CICMOD rw					DATSRC rw

Toggle fields

DATSRC

Bits 0-1: Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

CICMOD

Bits 4-6: Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MCICD

Bits 8-16: CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCALE

Bits 20-25: Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits.

MDF_DFLT5RSFR

This register is used to control the reshape and HPF filters.

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HPFC rw		HPFBYP rw			RSFLTD rw				RSFLTBYP rw

Toggle fields

RSFLTBYP

Bit 0: Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

RSFLTD

Bit 4: Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFBYP

Bit 7: High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

HPFC

Bits 8-9: High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_DFLT5INTR

This register is used to the integrator (INT) settings.

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INTVAL rw									INTDIV rw

Toggle fields

INTDIV

Bits 0-1: Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

INTVAL

Bits 4-10: Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD5CR

This register is used to configure the Out-of Limit Detector function.

Offset: 0x318, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OLDACTIVE r										ACICD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ACICN rw						BKOLD rw						THINB rw	OLDEN rw

Toggle fields

OLDEN

Bit 0: Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode..

THINB

Bit 1: Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

BKOLD

Bits 4-7: Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICN

Bits 12-13: OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

ACICD

Bits 17-21: OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

OLDACTIVE

Bit 31: OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured..

MDF_OLD5THLR

This register is used for the adjustment of the Out-off Limit low threshold.

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHL rw

Toggle fields

OLDTHL

Bits 0-25: OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

MDF_OLD5THHR

This register is used for the adjustment of the Out-off Limit high threshold.

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OLDTHH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OLDTHH rw

Toggle fields

OLDTHH

Bits 0-25: OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.

MDF_DLY5CR

This register is used for the adjustment stream delays.

Offset: 0x324, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SKPBF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SKPDLY rw

Toggle fields

SKPDLY

Bits 0-6: Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,.

SKPBF

Bit 31: Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing..

MDF_SCD5CR

This register is used for the adjustment stream delays.

Offset: 0x328, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCDACTIVE r												SCDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCDT rw								BKSCD rw							SCDEN rw

Toggle fields

SCDEN

Bit 0: Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,.

BKSCD

Bits 4-7: Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDT

Bits 12-19: Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details..

SCDACTIVE

Bit 31: SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured..

MDF_DFLT5IER

MDF DFLTx interrupt enable register x

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRIE rw	CKABIE rw	SATIE rw	SCDIE rw	SSOVRIE rw			OLDIE rw		SSDRIE rw	DOVRIE rw	FTHIE rw

Toggle fields

FTHIE

Bit 0: RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled.

DOVRIE

Bit 1: Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled.

SSDRIE

Bit 2: Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled.

OLDIE

Bit 4: Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled.

SSOVRIE

Bit 7: Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled.

SCDIE

Bit 8: Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled.

SATIE

Bit 9: Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled.

CKABIE

Bit 10: Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled.

RFOVRIE

Bit 11: Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled.

MDF_DFLT5ISR

This register contains the status flags for each digital filter path.

Offset: 0x330, size: 32, reset: 0x00000000, access: Unspecified

4/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RFOVRF rw	CKABF rw	SATF rw	SCDF rw	SSOVRF rw	THHF r	THLF r	OLDF rw	RXNEF r	SSDRF rw	DOVRF rw	FTHF r

Toggle fields

FTHF

Bit 0: RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag..

DOVRF

Bit 1: Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag..

SSDRF

Bit 2: Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag..

RXNEF

Bit 3: RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty..

OLDF

Bit 4: Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags..

THLF

Bit 5: Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred.

THHF

Bit 6: High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred.

SSOVRF

Bit 7: Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag..

SCDF

Bit 8: Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag..

SATF

Bit 9: Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag..

CKABF

Bit 10: Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag..

RFOVRF

Bit 11: Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag..

MDF_OEC5CR

This register contains the offset compensation value.

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET rw

Toggle fields

OFFSET

Bits 0-25: Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE..

MDF_SNPS5DR

This register is used to read the data processed by each digital filter in snapshot mode.

Offset: 0x36c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTSDR r							MCICDC r

Toggle fields

MCICDC

Bits 0-8: Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT).

EXTSDR

Bits 9-15: Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT)..

SDR

Bits 16-31: Contains the 16 MSB of the last valid data processed by the digital filter..

MDF_DFLT5DR

This register is used to read the data processed by each digital filter.

Offset: 0x370, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR r

Toggle fields

DR

Bits 8-31: Data processed by digital filter..

SEC_OCTOSPI1

0x520d1400: OctoSPI

7/95 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	23	22	21	20	19	18	17	16	15	13	12	11	10	7	6	5	4	3	2	1	0
0x0	CR			FMODE				PMM	APMS		TOIE	SMIE	FTIE	TCIE	TEIE			FTHRES			FSEL	DQM			TCEN	DMAEN	ABORT	EN
0x8	DCR1						MTYP				DEVSIZE						CSHT								DLYBYP		FRCK	CKMODE
0xc	DCR2												WRAPSIZE								PRESCALER
0x10	DCR3										CSBOUND										MAXTRAN
0x14	DCR4	REFRESH														REFRESH
0x20	SR																FLEVEL						BUSY	TOF	SMF	FTF	TCF	TEF
0x24	FCR																							CTOF	CSMF		CTCF	CTEF
0x40	DLR	DL														DL
0x48	AR	ADDRESS														ADDRESS
0x50	DR	DATA														DATA
0x80	PSMKR	MASK														MASK
0x88	PSMAR	MATCH														MATCH
0x90	PIR															INTERVAL
0x100	CCR	SIOO		DQSE		DDTR	DMODE			ABSIZE		ABDTR	ABMODE						ADDTR	ADMODE			ISIZE		IDTR	IMODE
0x108	TCR		SSHIFT		DHQC																			DCYC
0x110	IR	INSTRUCTION														INSTRUCTION
0x120	ABR	ALTERNATE														ALTERNATE
0x130	LPTR															TIMEOUT
0x140	WPCCR			DQSE		DDTR	DMODE			ABSIZE		ABDTR	ABMODE						ADDTR	ADMODE			ISIZE		IDTR	IMODE
0x148	WPTCR		SSHIFT		DHQC																			DCYC
0x150	WPIR	INSTRUCTION														INSTRUCTION
0x160	WPABR	ALTERNATE														ALTERNATE
0x180	WCCR			DQSE		DDTR	DMODE			ABSIZE		ABDTR	ABMODE						ADDTR	ADMODE			ISIZE		IDTR	IMODE
0x188	WTCR																							DCYC
0x190	WIR	INSTRUCTION														INSTRUCTION
0x1a0	WABR	ALTERNATE														ALTERNATE
0x200	HLCR							TRWR								TACC											WZL	LM

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FMODE rw						PMM rw	APMS rw		TOIE rw	SMIE rw	FTIE rw	TCIE rw	TEIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTHRES rw					FSEL rw	DQM rw			TCEN rw	DMAEN rw	ABORT rw	EN rw

Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					MTYP rw						DEVSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CSHT rw										DLYBYP rw		FRCK rw	CKMODE rw

Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

DLYBYP

Bit 3: Delay block bypass.

CSHT

Bits 8-13: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-26: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WRAPSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PRESCALER rw

Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											CSBOUND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAXTRAN rw

Toggle fields

MAXTRAN

Bits 0-7: Maximum transfer.

CSBOUND

Bits 16-20: CS boundary.

DCR4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REFRESH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REFRESH rw

Toggle fields

REFRESH

Bits 0-31: Refresh rate.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		FLEVEL r								BUSY r	TOF r	SMF r	FTF r	TCF r	TEF r

Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: status match flag.

TOF

Bit 4: timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CTOF w	CSMF w		CTCF w	CTEF w

Toggle fields

CTEF

Bit 0: Clear Transfer error flag.

CTCF

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SIOO rw		DQSE rw		DDTR rw	DMODE rw					ABSIZE rw		ABDTR rw	ABMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ADDTR rw	ADMODE rw					ISIZE rw		IDTR rw	IMODE rw

Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SSHIFT rw		DHQC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DCYC rw

Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INSTRUCTION rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUT rw

Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WPCCR

wrap communication configuration register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		DQSE rw		DDTR rw	DMODE rw					ABSIZE rw		ABDTR rw	ABMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ADDTR rw	ADMODE rw					ISIZE rw		IDTR rw	IMODE rw

Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPTCR

wrap timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SSHIFT rw		DHQC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DCYC rw

Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPIR

wrap instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INSTRUCTION rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPABR

wrap alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WCCR

write communication configuration register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		DQSE rw		DDTR rw	DMODE rw					ABSIZE rw		ABDTR rw	ABMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ADDTR rw	ADMODE rw					ISIZE rw		IDTR rw	IMODE rw

Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WTCR

write timing configuration register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DCYC rw

Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

WIR

write instruction register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INSTRUCTION rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: ALTERNATE.

HLCR

HyperBus latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TRWR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TACC rw														WZL rw	LM rw

Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

SEC_OPAMP

0x56005000: Operational amplifiers

2/31 fields covered.

Toggle register map

Offset	Name	31	30	15	14	13	12	10	9	5	4	3	1	0
0x0	OPAMP1_CSR	OPA_RANGE	OPAHSM	CALOUT	USERTRIM	CALSEL	CALON	VP_SEL	VM_SEL	PGA_GAIN		OPAMODE	OPALPM	OPAEN
0x4	OPAMP1_OTR						TRIMOFFSETP				TRIMOFFSETN
0x8	OPAMP1_LPOTR						TRIMLPOFFSETP				TRIMLPOFFSETN
0x10	OPAMP2_CRS		OPAHSM	CALOUT	USERTRIM	CALSEL	CALON	VP_SEL	VM_SEL	PGA_GAIN		OPAMODE	OPALPM	OPAEN
0x14	OPAMP2_OTR						TRIMOFFSETP				TRIMOFFSETN
0x18	OPAMP2_LPOTR						TRIMLPOFFSETP				TRIMLPOFFSETN

Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPA_RANGE rw	OPAHSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALOUT r	USERTRIM rw	CALSEL rw	CALON rw		VP_SEL rw	VM_SEL rw				PGA_GAIN rw		OPAMODE rw		OPALPM rw	OPAEN rw

Toggle fields

OPAEN

Bit 0: OPAMP enable.

OPALPM

Bit 1: OPAMP low-power mode The OPAMP must be disabled to change this configuration..

OPAMODE

Bits 2-3: OPAMP PGA mode 00 and 01: internal PGA disabled.

PGA_GAIN

Bits 4-5: OPAMP programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 1x: inverting input not externally connected.

VP_SEL

Bit 10: Non-inverted input selection.

CALON

Bit 12: Calibration mode enable.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-power modes..

CALOUT

Bit 15: OPAMP calibration output During the calibration mode, the offset is trimmed when this signal toggles..

OPAHSM

Bit 30: OPAMP high-speed mode This bit is effective for both normal and low-power modes..

OPA_RANGE

Bit 31: OPAMP range setting This bit must be set before enabling the OPAMP and this bit affects all OPAMP instances..

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMOFFSETP rw								TRIMOFFSETN rw

Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-power mode

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMLPOFFSETP rw								TRIMLPOFFSETN rw

Toggle fields

TRIMLPOFFSETN

Bits 0-4: Low-power mode trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Low-power mode trim for PMOS differential pairs.

OPAMP2_CRS

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	OPAHSM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALOUT r	USERTRIM rw	CALSEL rw	CALON rw		VP_SEL rw	VM_SEL rw				PGA_GAIN rw		OPAMODE rw		OPALPM rw	OPAEN rw

Toggle fields

OPAEN

Bit 0: OPAMP enable.

OPALPM

Bit 1: OPAMP low-power mode The OPAMP must be disabled to change this configuration..

OPAMODE

Bits 2-3: OPAMP PGA mode 00 and 01: internal PGA disabled.

PGA_GAIN

Bits 4-5: OPAMP programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. in PGA mode for filtering) 1x: inverting input not externally connected.

VP_SEL

Bit 10: Non inverted input selection.

CALON

Bit 12: Calibration mode enable.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-power modes..

CALOUT

Bit 15: OPAMP calibration output During calibration mode, the offset is trimmed when this signal toggles..

OPAHSM

Bit 30: OPAMP high-speed mode This bit is effective for both normal and high-speed modes..

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMOFFSETP rw								TRIMOFFSETN rw

Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			TRIMLPOFFSETP rw								TRIMLPOFFSETN rw

Toggle fields

TRIMLPOFFSETN

Bits 0-4: Low-power mode trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Low-power mode trim for PMOS differential pairs.

SEC_PSSI

0x5202c400: PSSI

4/18 fields covered.

Toggle register map

Offset	Name	31	30	23	20	15	14	11	8	7	6	5	3	2	1
0x0	CR	OUTEN	DMAEN		DERDYCFG		ENABLE	EDM	RDYPOL		DEPOL	CKPOL
0x4	SR												RTT1B	RTT4B
0x8	RIS														OVR_RIS
0xc	IER														OVR_IE
0x10	MIS														OVR_MIS
0x14	ICR														OVR_ISC
0x28	DR	BYTE3		BYTE2		BYTE1				BYTE0

Toggle registers

CR

PSSI control register

Offset: 0x0, size: 32, reset: 0x40000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUTEN rw	DMAEN rw										DERDYCFG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	ENABLE rw			EDM rw			RDYPOL rw		DEPOL rw	CKPOL rw

Toggle fields

CKPOL

Bit 5: Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN..

DEPOL

Bit 6: Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface..

RDYPOL

Bit 8: Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface..

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time..

DERDYCFG

Bits 18-20: Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity..

DMAEN

Bit 30: DMA enable bit.

OUTEN

Bit 31: Data direction selection bit.

SR

PSSI status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												RTT1B r	RTT4B r

Toggle fields

RTT4B

Bit 2: RTT4B.

RTT1B

Bit 3: RTT1B.

RIS

PSSI raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_RIS r

Toggle fields

OVR_RIS

Bit 1: OVR_RIS.

IER

PSSI interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_IE rw

Toggle fields

OVR_IE

Bit 1: OVR_IE.

MIS

PSSI masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_MIS r

Toggle fields

OVR_MIS

Bit 1: OVR_MIS.

ICR

PSSI interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OVR_ISC w

Toggle fields

OVR_ISC

Bit 1: OVR_ISC.

DR

PSSI data register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BYTE3 rw								BYTE2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BYTE1 rw								BYTE0 rw

Toggle fields

BYTE0

Bits 0-7: Data byte 0.

BYTE1

Bits 8-15: Data byte 1.

BYTE2

Bits 16-23: Data byte 2.

BYTE3

Bits 24-31: Data byte 3.

SEC_PWR

0x56020800: Power control

24/444 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	PWR_CR1																				SRAM5PD	SRAM4PD		SRAM2PD	SRAM1PD	ULPMEN	RRSB2	RRSB1			LPMS
0x4	PWR_CR2	SRDRUN																	FLASHFWU	SRAM4FWU		PRAMPDS		DC1RAMPDS	ICRAMPDS		SRAM4PDS	SRAM2PDS2	SRAM2PDS1		SRAM1PDS3	SRAM1PDS2	SRAM1PDS1
0x8	PWR_CR3																														FSTEN	REGSEL
0xc	PWR_VOSR												USBBOOSTEN	USBPWREN	BOOSTEN	VOS		VOSRDY	BOOSTRDY	USBBOOSTRDY
0x10	PWR_SVMCR		ASV	IO2SV	USV	AVM2EN	AVM1EN	IO2VMEN	UVMEN																	PVDLS			PVDE
0x14	PWR_WUCR1																									WUPEN8	WUPEN7	WUPEN6	WUPEN5	WUPEN4	WUPEN3	WUPEN2	WUPEN1
0x18	PWR_WUCR2																									WUPP8	WUPP7	WUPP6	WUPP5	WUPP4	WUPP3	WUPP2	WUPP1
0x1c	PWR_WUCR3																	WUSEL8		WUSEL7		WUSEL6		WUSEL5		WUSEL4		WUSEL3		WUSEL2		WUSEL1
0x20	PWR_BDCR1																												MONEN				BREN
0x24	PWR_BDCR2																															VBRS	VBE
0x28	PWR_DBPR																																DBP
0x2c	PWR_UCPDR																															UCPD_STBY	UCPD_DBDIS
0x30	PWR_SECCFGR																	APCSEC	VBSEC	VDMSEC	LPMSEC					WUP8SEC	WUP7SEC	WUP6SEC	WUP5SEC	WUP4SEC	WUP3SEC	WUP2SEC	WUP1SEC
0x34	PWR_PRIVCFGR																															NSPRIV	SPRIV
0x38	PWR_SR																														SBF	STOPF	CSSF
0x3c	PWR_SVMSR					VDDA2RDY	VDDA1RDY	VDDIO2RDY	VDDUSBRDY							ACTVOS		ACTVOSRDY											PVDO			REGS
0x40	PWR_BDSR																													TEMPH	TEMPL	VBATH
0x44	PWR_WUSR																									WUF8	WUF7	WUF6	WUF5	WUF4	WUF3	WUF2	WUF1
0x48	PWR_WUSCR																									CWUF8	CWUF7	CWUF6	CWUF5	CWUF4	CWUF3	CWUF2	CWUF1
0x4c	PWR_APCR																																APC
0x50	PWR_PUCRA																	PU15		PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x54	PWR_PDCRA																		PD14		PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x58	PWR_PUCRB																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x5c	PWR_PDCRB																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5		PD3	PD2	PD1	PD0
0x60	PWR_PUCRC																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x64	PWR_PDCRC																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x68	PWR_PUCRD																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x6c	PWR_PDCRD																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x70	PWR_PUCRE																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x74	PWR_PDCRE																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x78	PWR_PUCRF																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x7c	PWR_PDCRF																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x80	PWR_PUCRG																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x84	PWR_PDCRG																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x88	PWR_PUCRH																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x8c	PWR_PDCRH																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x90	PWR_PUCRI																	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x94	PWR_PDCRI																	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x98	PWR_PUCRJ																					PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x9c	PWR_PDCRJ																					PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0xa8	PWR_CR4				SRAM5PDS13	SRAM5PDS12	SRAM5PDS11	SRAM5PDS10	SRAM5PDS9	SRAM5PDS8	SRAM5PDS7	SRAM5PDS6	SRAM5PDS5	SRAM5PDS4	SRAM5PDS3	SRAM5PDS2	SRAM5PDS1								SRAM1PDS12	SRAM1PDS11	SRAM1PDS10	SRAM1PDS9	SRAM1PDS8	SRAM1PDS7	SRAM1PDS6	SRAM1PDS5	SRAM1PDS4

Toggle registers

PWR_CR1

PWR control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SRAM5PD rw	SRAM4PD rw		SRAM2PD rw	SRAM1PD rw	ULPMEN rw	RRSB2 rw	RRSB1 rw			LPMS rw

Toggle fields

LPMS

Bits 0-2: Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1.

RRSB1

Bit 5: SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode..

RRSB2

Bit 6: SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode..

ULPMEN

Bit 7: BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes..

SRAM1PD

Bit 8: SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1..

SRAM2PD

Bit 9: SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2..

SRAM4PD

Bit 11: SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4..

SRAM5PD

Bit 12: SRAM5 power down This bit is used to reduce the consumption by powering off the SRAM5. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

PWR_CR2

PWR control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRDRUN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FLASHFWU rw	SRAM4FWU rw		PRAMPDS rw		DC1RAMPDS rw	ICRAMPDS rw		SRAM4PDS rw	SRAM2PDS2 rw	SRAM2PDS1 rw		SRAM1PDS3 rw	SRAM1PDS2 rw	SRAM1PDS1 rw

Toggle fields

SRAM1PDS1

Bit 0: SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM1PDS2

Bit 1: SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM1PDS3

Bit 2: SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM2PDS1

Bit 4: SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1..

SRAM2PDS2

Bit 5: SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1..

SRAM4PDS

Bit 6: SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3).

ICRAMPDS

Bit 8: ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3).

DC1RAMPDS

Bit 9: DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3).

PRAMPDS

Bit 11: FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3).

SRAM4FWU

Bit 13: SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes..

FLASHFWU

Bit 14: Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption..

SRDRUN

Bit 31: SmartRun domain in Run mode.

PWR_CR3

PWR control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FSTEN rw	REGSEL rw

Toggle fields

REGSEL

Bit 1: Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS..

FSTEN

Bit 2: Fast soft start.

PWR_VOSR

PWR voltage scaling register

Offset: 0xc, size: 32, reset: 0x00008000, access: read-write

3/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											USBBOOSTEN rw	USBPWREN rw	BOOSTEN rw	VOS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VOSRDY r	BOOSTRDY r	USBBOOSTRDY r

Toggle fields

USBBOOSTRDY

Bit 13: USB EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The USB clock can be provided only after this bit is set. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

BOOSTRDY

Bit 14: EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set..

VOSRDY

Bit 15: Ready bit for VCORE voltage scaling output selection.

VOS

Bits 16-17: Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1..

BOOSTEN

Bit 18: EPOD booster enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. This bit must be set in range 1 and range 2 before increasing the system clock frequency above 50 MHz. This bit is reset when going into Stop modes (0, 1, 2, 3)..

USBPWREN

Bit 19: USB power enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

USBBOOSTEN

Bit 20: USB EPOD booster enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. This bit must be set in range 1 and range 2 before enabling the USB peripheral. This bit is reset when going into Stop modes (0, 1, 2, 3). Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585..

PWR_SVMCR

PWR supply voltage monitoring control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	ASV rw	IO2SV rw	USV rw	AVM2EN rw	AVM1EN rw	IO2VMEN rw	UVMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PVDLS rw			PVDE rw

Toggle fields

PVDE

Bit 4: Power voltage detector enable.

PVDLS

Bits 5-7: Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector:.

UVMEN

Bit 24: VDDUSB independent USB voltage monitor enable.

IO2VMEN

Bit 25: VDDIO2 independent I/Os voltage monitor enable.

AVM1EN

Bit 26: VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold).

AVM2EN

Bit 27: VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold).

USV

Bit 28: VDDUSB independent USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not..

IO2SV

Bit 29: VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not..

ASV

Bit 30: VDDA independent analog supply valid This bit is used to validate the VDDA supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the analog peripherals. If VDDA is not always present in the application, the VDDA voltage monitor can be used to determine whether this supply is ready or not..

PWR_WUCR1

PWR wakeup control register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUPEN8 rw	WUPEN7 rw	WUPEN6 rw	WUPEN5 rw	WUPEN4 rw	WUPEN3 rw	WUPEN2 rw	WUPEN1 rw

Toggle fields

WUPEN1

Bit 0: Wakeup pin WKUP1 enable.

WUPEN2

Bit 1: Wakeup pin WKUP2 enable.

WUPEN3

Bit 2: Wakeup pin WKUP3 enable.

WUPEN4

Bit 3: Wakeup pin WKUP4 enable.

WUPEN5

Bit 4: Wakeup pin WKUP5 enable.

WUPEN6

Bit 5: Wakeup pin WKUP6 enable.

WUPEN7

Bit 6: Wakeup pin WKUP7 enable.

WUPEN8

Bit 7: Wakeup pin WKUP8 enable.

PWR_WUCR2

PWR wakeup control register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUPP8 rw	WUPP7 rw	WUPP6 rw	WUPP5 rw	WUPP4 rw	WUPP3 rw	WUPP2 rw	WUPP1 rw

Toggle fields

WUPP1

Bit 0: Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0..

WUPP2

Bit 1: Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0..

WUPP3

Bit 2: Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0..

WUPP4

Bit 3: Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0..

WUPP5

Bit 4: Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0..

WUPP6

Bit 5: Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0..

WUPP7

Bit 6: Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0..

WUPP8

Bit 7: Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0..

PWR_WUCR3

PWR wakeup control register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUSEL8 rw		WUSEL7 rw		WUSEL6 rw		WUSEL5 rw		WUSEL4 rw		WUSEL3 rw		WUSEL2 rw		WUSEL1 rw

Toggle fields

WUSEL1

Bits 0-1: Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0..

WUSEL2

Bits 2-3: Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0..

WUSEL3

Bits 4-5: Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0..

WUSEL4

Bits 6-7: Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0..

WUSEL5

Bits 8-9: Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0..

WUSEL6

Bits 10-11: Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0..

WUSEL7

Bits 12-13: Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0..

WUSEL8

Bits 14-15: Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0..

PWR_BDCR1

PWR Backup domain control register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MONEN rw				BREN rw

Toggle fields

BREN

Bit 0: Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode..

MONEN

Bit 4: Backup domain voltage and temperature monitoring enable.

PWR_BDCR2

PWR Backup domain control register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														VBRS rw	VBE rw

Toggle fields

VBE

Bit 0: VBAT charging enable.

VBRS

Bit 1: VBAT charging resistor selection.

PWR_DBPR

PWR disable Backup domain register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															DBP rw

Toggle fields

DBP

Bit 0: Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers..

PWR_UCPDR

PWR USB Type-C™ and Power Delivery register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UCPD_STBY rw	UCPD_DBDIS rw

Toggle fields

UCPD_DBDIS

Bit 0: UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)..

UCPD_STBY

Bit 1: UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers..

PWR_SECCFGR

PWR security configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
APCSEC rw	VBSEC rw	VDMSEC rw	LPMSEC rw					WUP8SEC rw	WUP7SEC rw	WUP6SEC rw	WUP5SEC rw	WUP4SEC rw	WUP3SEC rw	WUP2SEC rw	WUP1SEC rw

Toggle fields

WUP1SEC

Bit 0: WUP1 secure protection.

WUP2SEC

Bit 1: WUP2 secure protection.

WUP3SEC

Bit 2: WUP3 secure protection.

WUP4SEC

Bit 3: WUP4 secure protection.

WUP5SEC

Bit 4: WUP5 secure protection.

WUP6SEC

Bit 5: WUP6 secure protection.

WUP7SEC

Bit 6: WUP7 secure protection.

WUP8SEC

Bit 7: WUP8 secure protection.

LPMSEC

Bit 12: Low-power modes secure protection.

VDMSEC

Bit 13: Voltage detection and monitoring secure protection.

VBSEC

Bit 14: Backup domain secure protection.

APCSEC

Bit 15: Pull-up/pull-down secure protection.

PWR_PRIVCFGR

PWR privilege control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														NSPRIV rw	SPRIV rw

Toggle fields

SPRIV

Bit 0: PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access..

NSPRIV

Bit 1: PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure..

PWR_SR

PWR status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													SBF r	STOPF r	CSSF w

Toggle fields

CSSF

Bit 0: Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. Writing 1 to this bit clears the STOPF and SBF flags..

STOPF

Bit 1: Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit..

SBF

Bit 2: Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset..

PWR_SVMSR

PWR supply voltage monitoring status register

Offset: 0x3c, size: 32, reset: 0x00008000, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				VDDA2RDY r	VDDA1RDY r	VDDIO2RDY r	VDDUSBRDY r							ACTVOS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTVOSRDY r											PVDO r			REGS r

Toggle fields

REGS

Bit 1: Regulator selection.

PVDO

Bit 4: VDD voltage detector output.

ACTVOSRDY

Bit 15: Voltage level ready for currently used VOS.

ACTVOS

Bits 16-17: VOS currently applied to VCORE This field provides the last VOS value..

VDDUSBRDY

Bit 24: VDDUSB ready.

VDDIO2RDY

Bit 25: VDDIO2 ready.

VDDA1RDY

Bit 26: VDDA ready versus 1.6V voltage monitor.

VDDA2RDY

Bit 27: VDDA ready versus 1.8 V voltage monitor.

PWR_BDSR

PWR Backup domain status register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TEMPH r	TEMPL r	VBATH r

Toggle fields

VBATH

Bit 1: Backup domain voltage level monitoring versus high threshold.

TEMPL

Bit 2: Temperature level monitoring versus low threshold.

TEMPH

Bit 3: Temperature level monitoring versus high threshold.

PWR_WUSR

PWR wakeup status register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUF8 r	WUF7 r	WUF6 r	WUF5 r	WUF4 r	WUF3 r	WUF2 r	WUF1 r

Toggle fields

WUF1

Bit 0: Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0..

WUF2

Bit 1: Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0..

WUF3

Bit 2: Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0..

WUF4

Bit 3: Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0..

WUF5

Bit 4: Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0..

WUF6

Bit 5: Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared..

WUF7

Bit 6: Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared..

WUF8

Bit 7: Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared..

PWR_WUSCR

PWR wakeup status clear register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CWUF8 w	CWUF7 w	CWUF6 w	CWUF5 w	CWUF4 w	CWUF3 w	CWUF2 w	CWUF1 w

Toggle fields

CWUF1

Bit 0: Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR..

CWUF2

Bit 1: Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR..

CWUF3

Bit 2: Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR..

CWUF4

Bit 3: Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR..

CWUF5

Bit 4: Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR..

CWUF6

Bit 5: Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR..

CWUF7

Bit 6: Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR..

CWUF8

Bit 7: Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR..

PWR_APCR

PWR apply pull configuration register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															APC rw

Toggle fields

APC

Bit 0: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os..

PWR_PUCRA

PWR port A pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw		PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU15

Bit 15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set..

PWR_PDCRA

PWR port A pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PD14 rw		PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD14

Bit 14: Port A pull-down bit 14 When set, this bit activates the pull-down on PA14 when the APC bit is set in PWR_APCR..

PWR_PUCRB

PWR port B pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRB

PWR port B pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw		PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRC

Power port C pull up control register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: PU0.

PU1

Bit 1: PU1.

PU2

Bit 2: PU2.

PU3

Bit 3: PU3.

PU4

Bit 4: PU4.

PU5

Bit 5: PU5.

PU6

Bit 6: PU6.

PU7

Bit 7: PU7.

PU8

Bit 8: PU8.

PU9

Bit 9: PU9.

PU10

Bit 10: PU10.

PU11

Bit 11: PU11.

PU12

Bit 12: PU12.

PU13

Bit 13: PU13.

PU14

Bit 14: PU14.

PU15

Bit 15: PU15.

PWR_PDCRC

PWR port C pull-down control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRD

PWR port D pull-up control register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRD

PWR port D pull-down control register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRE

PWR port E pull-up control register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRE

PWR port E pull-down control register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRF

PWR port F pull-up control register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRF

PWR port F pull-down control register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRG

PWR port G pull-up control register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRG

PWR port G pull-down control register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRH

PWR port H pull-up control register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRH

PWR port H pull-down control register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRI

PWR port I pull-up control register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PU12

Bit 12: .

PU13

Bit 13: .

PU14

Bit 14: .

PU15

Bit 15: .

PWR_PDCRI

PWR port I pull-down control register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PD12

Bit 12: .

PD13

Bit 13: .

PD14

Bit 14: .

PD15

Bit 15: .

PWR_PUCRJ

PWR port J pull-up control register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: .

PU1

Bit 1: .

PU2

Bit 2: .

PU3

Bit 3: .

PU4

Bit 4: .

PU5

Bit 5: .

PU6

Bit 6: .

PU7

Bit 7: .

PU8

Bit 8: .

PU9

Bit 9: .

PU10

Bit 10: .

PU11

Bit 11: .

PWR_PDCRJ

PWR port J pull-down control register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: .

PD1

Bit 1: .

PD2

Bit 2: .

PD3

Bit 3: .

PD4

Bit 4: .

PD5

Bit 5: .

PD6

Bit 6: .

PD7

Bit 7: .

PD8

Bit 8: .

PD9

Bit 9: .

PD10

Bit 10: .

PD11

Bit 11: .

PWR_CR4

PWR control register 4

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SRAM5PDS13 rw	SRAM5PDS12 rw	SRAM5PDS11 rw	SRAM5PDS10 rw	SRAM5PDS9 rw	SRAM5PDS8 rw	SRAM5PDS7 rw	SRAM5PDS6 rw	SRAM5PDS5 rw	SRAM5PDS4 rw	SRAM5PDS3 rw	SRAM5PDS2 rw	SRAM5PDS1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAM1PDS12 rw	SRAM1PDS11 rw	SRAM1PDS10 rw	SRAM1PDS9 rw	SRAM1PDS8 rw	SRAM1PDS7 rw	SRAM1PDS6 rw	SRAM1PDS5 rw	SRAM1PDS4 rw

Toggle fields

SRAM1PDS4

Bit 0: .

SRAM1PDS5

Bit 1: .

SRAM1PDS6

Bit 2: .

SRAM1PDS7

Bit 3: .

SRAM1PDS8

Bit 4: .

SRAM1PDS9

Bit 5: .

SRAM1PDS10

Bit 6: .

SRAM1PDS11

Bit 7: .

SRAM1PDS12

Bit 8: .

SRAM5PDS1

Bit 16: .

SRAM5PDS2

Bit 17: .

SRAM5PDS3

Bit 18: .

SRAM5PDS4

Bit 19: .

SRAM5PDS5

Bit 20: .

SRAM5PDS6

Bit 21: .

SRAM5PDS7

Bit 22: .

SRAM5PDS8

Bit 23: .

SRAM5PDS9

Bit 24: .

SRAM5PDS10

Bit 25: .

SRAM5PDS11

Bit 26: .

SRAM5PDS12

Bit 27: .

SRAM5PDS13

Bit 28: .

SEC_RAMCFG

0x50026000: RAMCFG

24/136 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	M1CR														WSC										SRAMER				ALE				ECCE
0x8	M1ISR																								SRAMBUSY							DED	SEDC
0x28	RAM1ERKEYR																									ERASEKEY
0x40	M2CR														WSC										SRAMER				ALE				ECCE
0x44	M2IER																													ECCNMI		DEIE	SEIE
0x48	M2ISR																								SRAMBUSY							DED	SEDC
0x4c	M2SEAR	ESEA																ESEA
0x50	M2DEAR	EDEA																EDEA
0x54	M2ICR																															CDED	CSEDC
0x58	M2WPR1	P31WP	P30WP	P29WP	P28WP	P27WP	P26WP	P25WP	P24WP	P23WP	P22WP	P21WP	P20WP	P19WP	P18WP	P17WP	P16WP	P15WP	P14WP	P13WP	P12WP	P11WP	P10WP	P9WP	P8WP	P7WP	P6WP	P5WP	P4WP	P3WP	P2WP	P1WP	P0WP
0x5c	M2WPR2	P63WP	P62WP	P61WP	P60WP	P59WP	P58WP	P57WP	P56WP	P55WP	P54WP	P53WP	P52WP	P51WP	P50WP	P49WP	P48WP	P47WP	P46WP	P45WP	P44WP	P43WP	P42WP	P41WP	P40WP	P39WP	P38WP	P37WP	P36WP	P35WP	P34WP	P33WP	P32WP
0x64	M2ECCKEYR																									ECCKEY
0x68	M2ERKEYR																									ERASEKEY
0x80	M3CR														WSC										SRAMER				ALE				ECCE
0x84	M3IER																													ECCNMI		DEIE	SEIE
0x88	M3ISR																								SRAMBUSY							DED	SEDC
0x8c	M3SEAR	ESEA																ESEA
0x90	M3DEAR	EDEA																EDEA
0x94	M3ICR																															CDED	CSEDC
0xa4	M3ECCKEYR																									ECCKEY
0xa8	M3ERKEYR																									ERASEKEY
0xc0	M4CR														WSC										SRAMER				ALE				ECCE
0xc8	M4ISR																								SRAMBUSY							DED	SEDC
0xe8	M4ERKEYR																									ERASEKEY
0x100	M5CR														WSC										SRAMER				ALE				ECCE
0x104	M5IER																													ECCNMI		DEIE	SEIE
0x108	M5ISR																								SRAMBUSY							DED	SEDC
0x10c	M5SEAR	ESEA																ESEA
0x110	M5DEAR	EDEA																EDEA
0x114	M5ICR																															CDED	CSEDC
0x124	M5ECCKEYR																									ECCKEY
0x128	M5ERKEYR																									ERASEKEY
0x140	M6CR														WSC										SRAMER				ALE				ECCE
0x148	M6ISR																								SRAMBUSY							DED	SEDC
0x168	M6ERKEYR																									ERASEKEY

Toggle registers

M1CR

RAMCFG SRAM x control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

Toggle fields

ECCE

Bit 0: ECCE.

ALE

Bit 4: ALE.

SRAMER

Bit 8: SRAMER.

WSC

Bits 16-18: WSC.

M1ISR

RAMCFG RAMx interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMBUSY r							DED r	SEDC r

Toggle fields

SEDC

Bit 0: SEDC.

DED

Bit 1: DED.

SRAMBUSY

Bit 8: SRAMBUSY.

RAM1ERKEYR

RAMCFG SRAM x erase key register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: ERASEKEY.

M2CR

RAMCFG SRAM x control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ESEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ESEA r

Toggle fields

ESEA

Bits 0-31: ESEA.

M2DEAR

RAMCFG RAM x ECC double error address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EDEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EDEA r

Toggle fields

EDEA

Bits 0-31: EDEA.

M2ICR

RAMCFG RAM x interrupt clear register x

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CDED rw	CSEDC rw

Toggle fields

CSEDC

Bit 0: CSEDC.

CDED

Bit 1: CDED.

M2WPR1

RAMCFG SRAM2 write protection register 1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P31WP rw	P30WP rw	P29WP rw	P28WP rw	P27WP rw	P26WP rw	P25WP rw	P24WP rw	P23WP rw	P22WP rw	P21WP rw	P20WP rw	P19WP rw	P18WP rw	P17WP rw	P16WP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P15WP rw	P14WP rw	P13WP rw	P12WP rw	P11WP rw	P10WP rw	P9WP rw	P8WP rw	P7WP rw	P6WP rw	P5WP rw	P4WP rw	P3WP rw	P2WP rw	P1WP rw	P0WP rw

Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: P31WP.

M2WPR2

RAMCFG SRAM2 write protection register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P63WP rw	P62WP rw	P61WP rw	P60WP rw	P59WP rw	P58WP rw	P57WP rw	P56WP rw	P55WP rw	P54WP rw	P53WP rw	P52WP rw	P51WP rw	P50WP rw	P49WP rw	P48WP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P47WP rw	P46WP rw	P45WP rw	P44WP rw	P43WP rw	P42WP rw	P41WP rw	P40WP rw	P39WP rw	P38WP rw	P37WP rw	P36WP rw	P35WP rw	P34WP rw	P33WP rw	P32WP rw

Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: P63WP.

M2ECCKEYR

RAMCFG SRAM x ECC key register

Offset: 0x64, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ECCKEY w

Toggle fields

ECCKEY

Bits 0-7: ECCKEY.

M2ERKEYR

RAMCFG SRAM x erase key register

Offset: 0x68, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: ERASEKEY.

M3CR

RAMCFG SRAM x control register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ESEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ESEA r

Toggle fields

ESEA

Bits 0-31: ESEA.

M3DEAR

RAMCFG RAM x ECC double error address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EDEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EDEA r

Toggle fields

EDEA

Bits 0-31: EDEA.

M3ICR

RAMCFG RAM x interrupt clear register x

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CDED rw	CSEDC rw

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

Toggle fields

ECCE

Bit 0: ECCE.

ALE

Bit 4: ALE.

SRAMER

Bit 8: SRAMER.

WSC

Bits 16-18: WSC.

M4ISR

RAMCFG RAMx interrupt status register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMBUSY r							DED r	SEDC r

Toggle fields

SEDC

Bit 0: SEDC.

DED

Bit 1: DED.

SRAMBUSY

Bit 8: SRAMBUSY.

M4ERKEYR

RAMCFG SRAM x erase key register

Offset: 0xe8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: ERASEKEY.

M5CR

RAMCFG SRAM x control register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ESEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ESEA r

Toggle fields

ESEA

Bits 0-31: ESEA.

M5DEAR

RAMCFG RAM x ECC double error address register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EDEA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EDEA r

Toggle fields

EDEA

Bits 0-31: EDEA.

M5ICR

RAMCFG RAM x interrupt clear register x

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CDED rw	CSEDC rw

Toggle fields

CSEDC

Bit 0: CSEDC.

CDED

Bit 1: CDED.

M5ECCKEYR

RAMCFG RAM x interrupt clear register x

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ECCKEY rw

Toggle fields

ECCKEY

Bits 0-7: ECCKEY.

M5ERKEYR

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection..

M6CR

memory x control register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													WSC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMER rw				ALE rw				ECCE rw

Toggle fields

ECCE

Bit 0: ECCE.

ALE

Bit 4: ALE.

SRAMER

Bit 8: SRAMER.

WSC

Bits 16-18: WSC.

M6ISR

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SRAMBUSY r							DED r	SEDC r

Toggle fields

SEDC

Bit 0: ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers..

DED

Bit 1: ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers..

SRAMBUSY

Bit 8: SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or readout protection regression. Refer to ..

M6ERKEYR

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ERASEKEY w

Toggle fields

ERASEKEY

Bits 0-7: Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection..

SEC_RCC

0x56020c00: Reset and clock control

38/520 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	RCC_CR			PLL3RDY	PLL3ON	PLL2RDY	PLL2ON	PLL1RDY	PLL1ON				HSEEXT	CSSON	HSEBYP	HSERDY	HSEON	SHSIRDY	SHSION	HSI48RDY	HSI48ON		HSIRDY	HSIKERON	HSION	MSIPLLFAST	MSIPLLSEL	MSIKRDY	MSIKON	MSIPLLEN	MSISRDY	MSIKERON	MSISON
0x8	RCC_ICSCR1	MSISRANGE				MSIKRANGE				MSIRGSEL	MSIBIAS			MSICAL0				MSICAL0	MSICAL1					MSICAL2					MSICAL3
0xc	RCC_ICSCR2													MSITRIM0				MSITRIM0	MSITRIM1					MSITRIM2					MSITRIM3
0x10	RCC_ICSCR3												HSITRIM									HSICAL
0x14	RCC_CRRCR																								HSI48CAL
0x1c	RCC_CFGR1		MCOPRE			MCOSEL																						STOPKERWUCK	STOPWUCK	SWS		SW
0x20	RCC_CFGR2												APB2DIS	APB1DIS	AHB2DIS2	AHB2DIS1	AHB1DIS		DPRE				PPRE2				PPRE1			HPRE
0x24	RCC_CFGR3															APB3DIS	AHB3DIS										PPRE3
0x28	RCC_PLL1CFGR														PLL1REN	PLL1QEN	PLL1PEN	PLL1MBOOST				PLL1M							PLL1FRACEN	PLL1RGE		PLL1SRC
0x2c	RCC_PLL2CFGR														PLL2REN	PLL2QEN	PLL2PEN					PLL2M							PLL2FRACEN	PLL2RGE		PLL2SRC
0x30	RCC_PLL3CFGR														PLL3REN	PLL3QEN	PLL3PEN					PLL3M							PLL3FRACEN	PLL3RGE		PLL3SRC
0x34	RCC_PLL1DIVR		PLL1R								PLL1Q							PLL1P							PLL1N
0x38	RCC_PLL1FRACR																	PLL1FRACN
0x3c	RCC_PLL2DIVR		PLL2R								PLL2Q							PLL2P							PLL2N
0x40	RCC_PLL2FRACR																	PLL2FRACN
0x44	RCC_PLL3DIVR		PLL3R								PLL3Q							PLL3P							PLL3N
0x48	RCC_PLL3FRACR																	PLL3FRACN
0x50	RCC_CIER																				SHSIRDYIE	MSIKRDYIE			PLL3RDYIE	PLL2RDYIE	PLL1RDYIE	HSI48RDYIE	HSERDYIE	HSIRDYIE	MSISRDYIE	LSERDYIE	LSIRDYIE
0x54	RCC_CIFR																				SHSIRDYF	MSIKRDYF	CSSF		PLL3RDYF	PLL2RDYF	PLL1RDYF	HSI48RDYF	HSERDYF	HSIRDYF	MSISRDYF	LSERDYF	LSIRDYF
0x58	RCC_CICR																				SHSIRDYC	MSIKRDYC	CSSC		PLL3RDYC	PLL2RDYC	PLL1RDYC	HSI48RDYC	HSERDYC	HSIRDYC	MSISRDYC	LSERDYC	LSIRDYC
0x60	RCC_AHB1RSTR												GPU2DRST	GFXMMURST	DMA2DRST	RAMCFGRST	TSCRST	JPEGRST			CRCRST									MDF1RST	FMACRST	CORDICRST	GPDMA1RST
0x64	RCC_AHB2RSTR1				SDMMC2RST	SDMMC1RST			OTFDEC2RST	OTFDEC1RST		OCTOSPIMRST	SAESRST	PKARST	RNGRST	HASHRST	AESRST		OTGRST		DCMI_PSSIRST		ADC12RST	GPIOJRST	GPIOIRST	GPIOHRST	GPIOGRST	GPIOFRST	GPIOERST	GPIODRST	GPIOCRST	GPIOBRST	GPIOARST
0x68	RCC_AHB2RSTR2																				HSPI1RST				OCTOSPI2RST				OCTOSPI1RST				FSMCRST
0x6c	RCC_AHB3RSTR																						ADF1RST	LPDMA1RST			DAC1RST	ADC4RST					LPGPIO1RST
0x74	RCC_APB1RSTR1							USART6RST	CRSRST		I2C2RST	I2C1RST	UART5RST	UART4RST	USART3RST	USART2RST			SPI2RST									TIM7RST	TIM6RST	TIM5RST	TIM4RST	TIM3RST	TIM2RST
0x78	RCC_APB1RSTR2									UCPD1RST														FDCAN1RST		I2C6RST	I2C5RST	LPTIM2RST				I2C4RST
0x7c	RCC_APB2RSTR					DSIRST	LTDCRST	GFXTIMRST	USBRST		SAI2RST	SAI1RST			TIM17RST	TIM16RST	TIM15RST		USART1RST	TIM8RST	SPI1RST	TIM1RST
0x80	RCC_APB3RSTR												VREFRST					COMPRST	OPAMPRST	LPTIM4RST	LPTIM3RST	LPTIM1RST				I2C3RST	LPUART1RST	SPI3RST				SYSCFGRST
0x88	RCC_AHB1ENR	SRAM1EN	DCACHE1EN		BKPSRAMEN				GTZC1EN			DCACHE2EN	GPU2DEN	GFXMMUEN	DMA2DEN	RAMCFGEN	TSCEN	JPEGEN			CRCEN				FLASHEN					MDF1EN	FMACEN	CORDICEN	GPDMA1EN
0x8c	RCC_AHB2ENR1	SRAM3EN	SRAM2EN		SDMMC2EN	SDMMC1EN			OTFDEC2EN	OTFDEC1EN		OCTOSPIMEN	SAESEN	PKAEN	RNGEN	HASHEN	AESEN	OTGHSPHYEN	OTGEN		DCMI_PSSIEN		ADC12EN	GPIOJEN	GPIOIEN	GPIOHEN	GPIOGEN	GPIOFEN	GPIOEEN	GPIODEN	GPIOCEN	GPIOBEN	GPIOAEN
0x90	RCC_AHB2ENR2	SRAM5EN	SRAM6EN																		HSPI1EN				OCTOSPI2EN				OCTOSPI1EN				FSMCEN
0x94	RCC_AHB3ENR	SRAM4EN																			GTZC2EN		ADF1EN	LPDMA1EN			DAC1EN	ADC4EN			PWREN		LPGPIO1EN
0x9c	RCC_APB1ENR1							USART6EN	CRSEN		I2C2EN	I2C1EN	UART5EN	UART4EN	USART3EN	USART2EN			SPI2EN			WWDGEN						TIM7EN	TIM6EN	TIM5EN	TIM4EN	TIM3EN	TIM2EN
0xa0	RCC_APB1ENR2									UCPD1EN														FDCAN1EN		I2C6EN	I2C5EN	LPTIM2EN				I2C4EN
0xa4	RCC_APB2ENR					DSIEN	LTDCEN	GFXTIMEN	USBEN		SAI2EN	SAI1EN			TIM17EN	TIM16EN	TIM15EN		USART1EN	TIM8EN	SPI1EN	TIM1EN
0xa8	RCC_APB3ENR											RTCAPBEN	VREFEN					COMPEN	OPAMPEN	LPTIM4EN	LPTIM3EN	LPTIM1EN				I2C3EN	LPUART1EN	SPI3EN				SYSCFGEN
0xb0	RCC_AHB1SMENR	SRAM1SMEN	DCACHE1SMEN	ICACHESMEN	BKPSRAMSMEN				GTZC1SMEN			DCACHE2SMEN	GPU2DSMEN	GFXMMUSMEN	DMA2DSMEN	RAMCFGSMEN	TSCSMEN	JPEGSMEN			CRCSMEN				FLASHSMEN					MDF1SMEN	FMACSMEN	CORDICSMEN	GPDMA1SMEN
0xb4	RCC_AHB2SMENR1	SRAM3SMEN	SRAM2SMEN		SDMMC2SMEN	SDMMC1SMEN			OTFDEC2SMEN	OTFDEC1SMEN		OCTOSPIMSMEN	SAESSMEN	PKASMEN	RNGSMEN	HASHSMEN	AESSMEN	OTGHSPHYSMEN	OTGSMEN		DCMI_PSSISMEN		ADC12SMEN	GPIOJSMEN	GPIOISMEN	GPIOHSMEN	GPIOGSMEN	GPIOFSMEN	GPIOESMEN	GPIODSMEN	GPIOCSMEN	GPIOBSMEN	GPIOASMEN
0xb8	RCC_AHB2SMENR2	SRAM5SMEN	SRAM6SMEN																		HSPI1SMEN				OCTOSPI2SMEN				OCTOSPI1SMEN				FSMCSMEN
0xbc	RCC_AHB3SMENR	SRAM4SMEN																			GTZC2SMEN		ADF1SMEN	LPDMA1SMEN			DAC1SMEN	ADC4SMEN			PWRSMEN		LPGPIO1SMEN
0xc4	RCC_APB1SMENR1							USART6SMEN	CRSSMEN		I2C2SMEN	I2C1SMEN	UART5SMEN	UART4SMEN	USART3SMEN	USART2SMEN			SPI2SMEN			WWDGSMEN						TIM7SMEN	TIM6SMEN	TIM5SMEN	TIM4SMEN	TIM3SMEN	TIM2SMEN
0xc8	RCC_APB1SMENR2									UCPD1SMEN														FDCAN1SMEN		I2C6SMEN	I2C5SMEN	LPTIM2SMEN				I2C4SMEN
0xcc	RCC_APB2SMENR					DSISMEN	LTDCSMEN	GFXTIMSMEN	USBSMEN		SAI2SMEN	SAI1SMEN			TIM17SMEN	TIM16SMEN	TIM15SMEN		USART1SMEN	TIM8SMEN	SPI1SMEN	TIM1SMEN
0xd0	RCC_APB3SMENR											RTCAPBSMEN	VREFSMEN					COMPSMEN	OPAMPSMEN	LPTIM4SMEN	LPTIM3SMEN	LPTIM1SMEN				I2C3SMEN	LPUART1SMEN	SPI3SMEN				SYSCFGSMEN
0xd8	RCC_SRDAMR	SRAM4AMEN		ADF1AMEN	LPDMA1AMEN	DAC1AMEN	LPGPIO1AMEN	ADC4AMEN				RTCAPBAMEN	VREFAMEN					COMPAMEN	OPAMPAMEN	LPTIM4AMEN	LPTIM3AMEN	LPTIM1AMEN				I2C3AMEN	LPUART1AMEN	SPI3AMEN
0xe0	RCC_CCIPR1	TIMICSEL				ICLKSEL		FDCAN1SEL		SYSTICKSEL		SPI1SEL		LPTIM2SEL		SPI2SEL		I2C4SEL		I2C2SEL		I2C1SEL		UART5SEL		UART4SEL		USART3SEL		USART2SEL		USART1SEL
0xe4	RCC_CCIPR2	OTGHSSEL				I2C6SEL		I2C5SEL		HSPI1SEL		OCTOSPISEL			LTDCSEL	USART6SEL		DSISEL	SDMMCSEL	RNGSEL		SAESSEL	SAI2SEL			SAI1SEL					MDF1SEL
0xe8	RCC_CCIPR3														ADF1SEL			DAC1SEL	ADCDACSEL			LPTIM1SEL		LPTIM34SEL		I2C3SEL			SPI3SEL		LPUART1SEL
0xf0	RCC_BDCR				LSIPREDIV	LSIRDY	LSION	LSCOSEL	LSCOEN								BDRST	RTCEN			LSEGFON	LSESYSRDY		RTCSEL		LSESYSEN	LSECSSD	LSECSSON	LSEDRV		LSEBYP	LSERDY	LSEON
0xf4	RCC_CSR	LPWRRSTF	WWDGRSTF	IWDGRSTF	SFTRSTF	BORRSTF	PINRSTF	OBLRSTF		RMVF								MSISSRANGE				MSIKSRANGE
0x110	RCC_SECCFGR																				RMVFSEC	HSI48SEC	ICLKSEC	PLL3SEC	PLL2SEC	PLL1SEC	PRESCSEC	SYSCLKSEC	LSESEC	LSISEC	MSISEC	HSESEC	HSISEC
0x114	RCC_PRIVCFGR																															NSPRIV	SPRIV

Toggle registers

RCC_CR

RCC clock control register

Offset: 0x0, size: 32, reset: 0x00000035, access: Unspecified

9/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		PLL3RDY r	PLL3ON rw	PLL2RDY r	PLL2ON rw	PLL1RDY r	PLL1ON rw				HSEEXT rw	CSSON rw	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SHSIRDY r	SHSION rw	HSI48RDY r	HSI48ON rw		HSIRDY r	HSIKERON rw	HSION rw	MSIPLLFAST rw	MSIPLLSEL rw	MSIKRDY r	MSIKON rw	MSIPLLEN rw	MSISRDY r	MSIKERON rw	MSISON rw

Toggle fields

MSISON

Bit 0: MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the�MSIS oscillator on when exiting Standby or Shutdown mode. It is set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes, or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock..

MSIKERON

Bit 1: MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI on in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see Section�11.4.24 for more details). This bit must be configured at 0 before entering Stop 3 mode..

MSISRDY

Bit 2: MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. It is set only when MSIS is enabled by software (by setting MSISON). Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles..

MSIPLLEN

Bit 3: MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)..

MSIKON

Bit 4: MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIK when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. It is set by hardware to force the MSIK oscillator on when STOPWUCK = 0 or STOPKERWUCK�=�0 when exiting Stop modes, or in case of a failure of the HSE oscillator..

MSIKRDY

Bit 5: MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles..

MSIPLLSEL

Bit 6: MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI output clock uses the PLL mode. It�can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to both clock outputs..

MSIPLLFAST

Bit 7: MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The�fast start-up is active when the MSI in PLL mode returns from switch off..

HSION

Bit 8: HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the�HSI16 oscillator on when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock..

HSIKERON

Bit 9: HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON even in Stop modes. Keeping HSI16 on in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to Section�11.4.24 for more details. This bit must be configured at 0 before entering Stop 3 mode..

HSIRDY

Bit 10: HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It is set only when HSI16 is enabled by software (by setting HSION). Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles..

HSI48ON

Bit 12: HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI48 when entering in Stop, Standby, or Shutdown modes..

HSI48RDY

Bit 13: HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Itis set only when HSI48 is enabled by software (by setting HSI48ON)..

SHSION

Bit 14: SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SHSI when entering in Stop, Standby, or Shutdown modes..

SHSIRDY

Bit 15: SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. It is set only when SHSI is enabled by software (by setting SHSION). Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles..

HSEON

Bit 16: HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock..

HSERDY

Bit 17: HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles..

HSEBYP

Bit 18: HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with an external clock. The�external clock must be enabled with the HSEON bit set, to be used by the device. This�bit can be written only if the HSE oscillator is disabled..

CSSON

Bit 19: Clock security system enable This bit is set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset..

HSEEXT

Bit 20: HSE external clock bypass mode This bit is set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled..

PLL1ON

Bit 24: PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock..

PLL1RDY

Bit 25: PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked..

PLL2ON

Bit 26: PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when entering Stop, Standby, or Shutdown mode..

PLL2RDY

Bit 27: PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked..

PLL3ON

Bit 28: PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when entering Stop, Standby, or Shutdown mode..

PLL3RDY

Bit 29: PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked..

RCC_ICSCR1

RCC internal clock sources calibration register 1

Offset: 0x8, size: 32, reset: 0x44000000, access: Unspecified

4/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSISRANGE rw				MSIKRANGE rw				MSIRGSEL rw	MSIBIAS rw			MSICAL0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSICAL0 r	MSICAL1 r					MSICAL2 r					MSICAL3 r

Toggle fields

MSICAL3

Bits 0-4: MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSICAL2

Bits 5-9: MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSICAL1

Bits 10-14: MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSICAL0

Bits 15-19: MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level..

MSIBIAS

Bit 22: MSI bias mode selection This bit is set by software to select the MSI bias mode. By default, the MSI bias is in�continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption when the regulator is in range 4, or when the device is in Stop 1 or Stop�2 mode, but it�decreases the MSI accuracy.

MSIRGSEL

Bit 23: MSI clock range selection This bit is set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR..

MSIKRANGE

Bits 24-27: MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is off (MSISON = 0) or when MSIK is ready (MSIKRDY�=�1). MSIKRANGE must NOT be modified when MSIK is on and NOT ready (MSIKON = 1 and MSIKRDY = 0) Note: MSIKRANGE is kept when the device wakes up from Stop mode, except when the�MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into�range 2 (24 MHz)..

MSISRANGE

Bits 28-31: MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is off (MSISON = 0) or when MSIS is ready (MSISRDY�=�1). MSISRANGE must NOT be modified when MSIS is on and NOT ready (MSISON�=�1 and MSISRDY�=�0) Note: MSISRANGE is kept when the device wakes up from Stop mode, except when the�MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into range 2 (24 MHz)..

RCC_ICSCR2

RCC internal clock sources calibration register 2

Offset: 0xc, size: 32, reset: 0x00084210, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												MSITRIM0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSITRIM0 rw	MSITRIM1 rw					MSITRIM2 rw					MSITRIM3 rw

Toggle fields

MSITRIM3

Bits 0-4: MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

MSITRIM2

Bits 5-9: MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

MSITRIM1

Bits 10-14: MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

MSITRIM0

Bits 15-19: MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI..

RCC_ICSCR3

RCC internal clock sources calibration register 3

Offset: 0x10, size: 32, reset: 0x00100000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											HSITRIM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				HSICAL r

Toggle fields

HSICAL

Bits 0-11: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value..

HSITRIM

Bits 16-20: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI..

RCC_CRRCR

RCC clock recovery RC register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							HSI48CAL r

Toggle fields

HSI48CAL

Bits 0-8: HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value..

RCC_CFGR1

RCC clock configuration register 1

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCOPRE rw			MCOSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										STOPKERWUCK rw	STOPWUCK rw	SWS r		SW rw

Toggle fields

SW

Bits 0-1: system clock switch This bitfield is set and cleared by software to select system clock source (SYSCLK). It is configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. This bitfield is configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK..

SWS

Bits 2-3: system clock switch status This bitfield is set and cleared by hardware to indicate which clock source is used as system clock..

STOPWUCK

Bit 4: wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on�HSE. STOPWUCK must not be modified when the CSS is enabled by HSECSSON in�RCC_CR, and the system clock is HSE (SWS = 10) or a switch on HSE is�requested (SW�=�10)..

STOPKERWUCK

Bit 5: wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals..

MCOSEL

Bits 24-27: microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching..

MCOPRE

Bits 28-30: microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed.

RCC_CFGR2

RCC clock configuration register 2

Offset: 0x20, size: 32, reset: 0x00006000, access: Unspecified

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											APB2DIS rw	APB1DIS rw	AHB2DIS2 rw	AHB2DIS1 rw	AHB1DIS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DPRE rw				PPRE2 rw				PPRE1 rw			HPRE rw

Toggle fields

HPRE

Bits 0-3: AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Table�118). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided.

PPRE1

Bits 4-6: APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1 clock (PCLK1). 0xx: PCLK1 not divided.

PPRE2

Bits 8-10: APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2 clock (PCLK2). 0xx: PCLK2 not divided.

DPRE

Bits 12-14: DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

AHB1DIS

Bit 16: AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1..

AHB2DIS1

Bit 17: AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3..

AHB2DIS2

Bit 18: AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR2 are off..

APB1DIS

Bit 19: APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG..

APB2DIS

Bit 20: APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all APB2 peripherals clocks are off..

RCC_CFGR3

RCC clock configuration register 3

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														APB3DIS rw	AHB3DIS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PPRE3 rw

Toggle fields

PPRE3

Bits 4-6: APB3 prescaler This bitfield is set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided.

AHB3DIS

Bit 16: AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4..

APB3DIS

Bit 17: APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off..

RCC_PLL1CFGR

RCC PLL1 configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PLL1REN rw	PLL1QEN rw	PLL1PEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL1MBOOST rw				PLL1M rw							PLL1FRACEN rw	PLL1RGE rw		PLL1SRC rw

Toggle fields

PLL1SRC

Bits 0-1: PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. It can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, this bitfield value must be zero..

PLL1RGE

Bits 2-3: PLL1 input frequency range This bit is set and reset by software to select the proper reference frequency range used for PLL1. It must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz.

PLL1FRACEN

Bit 4: PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRACN in the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL initialization phase for details)..

PLL1M

Bits 8-11: Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

PLL1MBOOST

Bits 12-15: Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1�input�clock�frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPODboost mode is disabled (see Section�10: Power control (PWR)). others: reserved.

PLL1PEN

Bit 16: PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when pll1_p_ck is not used..

PLL1QEN

Bit 17: PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when pll1_q_ck is not used..

PLL1REN

Bit 18: PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when pll1_r_ck is not used. This bit can be cleared only when the PLL1 is not used as SYSCLK..

RCC_PLL2CFGR

RCC PLL2 configuration register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PLL2REN rw	PLL2QEN rw	PLL2PEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PLL2M rw							PLL2FRACEN rw	PLL2RGE rw		PLL2SRC rw

Toggle fields

PLL2SRC

Bits 0-1: PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. It can be written only when the PLL2 is disabled. To save power, when no PLL2 is used, this bitfield value must be�zero..

PLL2RGE

Bits 2-3: PLL2 input frequency range This bitfield is set and reset by software to select the proper reference frequency range used for�PLL2. It must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz.

PLL2FRACEN

Bit 4: PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRACN in the ΣΔ modulator. In order to latch the PLL2FRACN value into the ΣΔ modulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see PLL initialization phase for details)..

PLL2M

Bits 8-11: Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

PLL2PEN

Bit 16: PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when pll2_p_ck is not used..

PLL2QEN

Bit 17: PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when pll2_q_ck is not used..

PLL2REN

Bit 18: PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when pll2_r_ck is not used..

RCC_PLL3CFGR

RCC PLL3 configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PLL3REN rw	PLL3QEN rw	PLL3PEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PLL3M rw							PLL3FRACEN rw	PLL3RGE rw		PLL3SRC rw

Toggle fields

PLL3SRC

Bits 0-1: PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. It can be written only when the PLL3 is disabled. To save power, when no PLL3 is used, this bitfield value must be�zero..

PLL3RGE

Bits 2-3: PLL3 input frequency range This bit is set and reset by software to select the proper reference frequency range used for�PLL3. It must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz.

PLL3FRACEN

Bit 4: PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRACN in the ΣΔ modulator. In order to latch the PLL3FRACN value into the ΣΔ modulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see PLL initialization phase for details)..

PLL3M

Bits 8-11: Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bitfield can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

PLL3PEN

Bit 16: PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when pll3_p_ck is not used..

PLL3QEN

Bit 17: PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when pll3_q_ck is not used..

PLL3REN

Bit 18: PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when pll3_r_ck is not used..

RCC_PLL1DIVR

RCC PLL1 dividers register

Offset: 0x34, size: 32, reset: 0x01010280, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLL1R rw								PLL1Q rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL1P rw							PLL1N rw

Toggle fields

PLL1N

Bits 0-8: Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded in PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16�MHz.

PLL1P

Bits 9-15: PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll1_p_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

PLL1Q

Bits 16-22: PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll1_q_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

PLL1R

Bits 24-30: PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed. ....

RCC_PLL1FRACR

RCC PLL1 fractional divider register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL1FRACN rw

Toggle fields

PLL1FRACN

Bits 3-15: Fractional part of the multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as�follows: Set PLL1FRACEN = 0. Write the new fractional value into PLL1FRACN. Set PLL1FRACEN = 1..

RCC_PLL2DIVR

RCC PLL2 dividers configuration register

Offset: 0x3c, size: 32, reset: 0x01010280, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLL2R rw								PLL2Q rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL2P rw							PLL2N rw

Toggle fields

PLL2N

Bits 0-8: Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded in PLL2FRACN, with: PLL2N between 4 and 512 input frequency Fref2_ck between 1MHz and 16MHz.

PLL2P

Bits 9-15: PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll2_p_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

PLL2Q

Bits 16-22: PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll2_q_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

PLL2R

Bits 24-30: PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll2_r_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ....

RCC_PLL2FRACR

RCC PLL2 fractional divider register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL2FRACN rw

Toggle fields

PLL2FRACN

Bits 3-15: Fractional part of the multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with PLL2N must be between 4 and 512. PLL2FRACN can be between 0 and 213 - 1. The input frequency Fref2_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into PLL2FRACN. Set the bit PLL2FRACEN to 1..

RCC_PLL3DIVR

RCC PLL3 dividers configuration register

Offset: 0x44, size: 32, reset: 0x01010280, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLL3R rw								PLL3Q rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL3P rw							PLL3N rw

Toggle fields

PLL3N

Bits 0-8: Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). ... ... Others: reserved VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded in PLL3FRACN, with: PLL3N between 4 and 512 input frequency Fref3_ck between 4 and 16MHz.

PLL3P

Bits 9-15: PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll3_p_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

PLL3Q

Bits 16-22: PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll3_q_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

PLL3R

Bits 24-30: PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll3_r_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ....

RCC_PLL3FRACR

RCC PLL3 fractional divider register

Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLL3FRACN rw

Toggle fields

PLL3FRACN

Bits 3-15: Fractional part of the multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with: PLL3N must be between 4 and 512. PLL3FRACN can be between 0 and 213 - 1. The input frequency Fref3_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL3FRACEN to 0. Write the new fractional value into PLL3FRACN. Set the bit PLL3FRACEN to 1..

RCC_CIER

RCC clock interrupt enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SHSIRDYIE rw	MSIKRDYIE rw			PLL3RDYIE rw	PLL2RDYIE rw	PLL1RDYIE rw	HSI48RDYIE rw	HSERDYIE rw	HSIRDYIE rw	MSISRDYIE rw	LSERDYIE rw	LSIRDYIE rw

Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization..

LSERDYIE

Bit 1: LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization..

MSISRDYIE

Bit 2: MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization..

HSIRDYIE

Bit 3: HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization..

HSERDYIE

Bit 4: HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization..

HSI48RDYIE

Bit 5: HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization..

PLL1RDYIE

Bit 6: PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL1 lock..

PLL2RDYIE

Bit 7: PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL2 lock..

PLL3RDYIE

Bit 8: PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL3 lock..

MSIKRDYIE

Bit 11: MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization..

SHSIRDYIE

Bit 12: SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization..

RCC_CIFR

RCC clock interrupt flag register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SHSIRDYF r	MSIKRDYF r	CSSF r		PLL3RDYF r	PLL2RDYF r	PLL1RDYF r	HSI48RDYF r	HSERDYF r	HSIRDYF r	MSISRDYF r	LSERDYF r	LSIRDYF r

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE is set. It is cleared by software by�setting the LSIRDYC bit..

LSERDYF

Bit 1: LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE is set. It is cleared by software by setting the LSERDYC bit..

MSISRDYF

Bit 2: MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. It�is cleared by software by setting the MSISRDYC bit..

HSIRDYF

Bit 3: HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYIE = 1 in�response to setting the HSION (see RCC_CR). When HSION = 0 but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. This bit is cleared by software by setting the HSIRDYC bit..

HSERDYF

Bit 4: HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE is set. It is cleared by software by setting the HSERDYC bit..

HSI48RDYF

Bit 5: HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. it�is cleared by software by setting the HSI48RDYC bit..

PLL1RDYF

Bit 6: PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It is cleared by software by setting the PLL1RDYC bit..

PLL2RDYF

Bit 7: PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It is cleared by software by setting the PLL2RDYC bit..

PLL3RDYF

Bit 8: PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software by setting the PLL3RDYC bit..

CSSF

Bit 10: Clock security system interrupt flag This bit is set by hardware when a failure is detected in the HSE oscillator. It is cleared by software by setting the CSSC bit..

MSIKRDYF

Bit 11: MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. It is cleared by software by setting the MSIKRDYC bit..

SHSIRDYF

Bit 12: SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. It is cleared by software by setting the SHSIRDYC bit..

RCC_CICR

RCC clock interrupt clear register

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			SHSIRDYC w	MSIKRDYC w	CSSC w		PLL3RDYC w	PLL2RDYC w	PLL1RDYC w	HSI48RDYC w	HSERDYC w	HSIRDYC w	MSISRDYC w	LSERDYC w	LSIRDYC w

Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect..

LSERDYC

Bit 1: LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect..

MSISRDYC

Bit 2: MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect..

HSIRDYC

Bit 3: HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect..

HSERDYC

Bit 4: HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect..

HSI48RDYC

Bit 5: HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect..

PLL1RDYC

Bit 6: PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect..

PLL2RDYC

Bit 7: PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect..

PLL3RDYC

Bit 8: PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect..

CSSC

Bit 10: Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect..

MSIKRDYC

Bit 11: MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect..

SHSIRDYC

Bit 12: SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect..

RCC_AHB1RSTR

RCC AHB1 peripheral reset register

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											GPU2DRST rw	GFXMMURST rw	DMA2DRST rw	RAMCFGRST rw	TSCRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JPEGRST rw			CRCRST rw									MDF1RST rw	FMACRST rw	CORDICRST rw	GPDMA1RST rw

Toggle fields

GPDMA1RST

Bit 0: GPDMA1 reset This bit is set and cleared by software..

CORDICRST

Bit 1: CORDIC reset This bit is set and cleared by software..

FMACRST

Bit 2: FMAC reset This bit is set and cleared by software..

MDF1RST

Bit 3: MDF1 reset This bit is set and cleared by software..

CRCRST

Bit 12: CRC reset This bit is set and cleared by software..

JPEGRST

Bit 15: JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

TSCRST

Bit 16: TSC reset This bit is set and cleared by software..

RAMCFGRST

Bit 17: RAMCFG reset This bit is set and cleared by software..

DMA2DRST

Bit 18: DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXMMURST

Bit 19: GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPU2DRST

Bit 20: GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2RSTR1

RCC AHB2 peripheral reset register 1

Offset: 0x64, size: 32, reset: 0x00000000, access: Unspecified

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SDMMC2RST rw	SDMMC1RST rw			OTFDEC2RST rw	OTFDEC1RST rw		OCTOSPIMRST rw	SAESRST rw	PKARST rw	RNGRST rw	HASHRST rw	AESRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OTGRST rw		DCMI_PSSIRST rw		ADC12RST rw	GPIOJRST rw	GPIOIRST rw	GPIOHRST rw	GPIOGRST rw	GPIOFRST rw	GPIOERST rw	GPIODRST rw	GPIOCRST rw	GPIOBRST rw	GPIOARST rw

Toggle fields

GPIOARST

Bit 0: I/O port A reset This bit is set and cleared by software..

GPIOBRST

Bit 1: I/O port B reset This bit is set and cleared by software..

GPIOCRST

Bit 2: I/O port C reset This bit is set and cleared by software..

GPIODRST

Bit 3: I/O port D reset This bit is set and cleared by software..

GPIOERST

Bit 4: I/O port E reset This bit is set and cleared by software..

GPIOFRST

Bit 5: I/O port F reset This bit is set and cleared by software. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value..

GPIOGRST

Bit 6: I/O port G reset This bit is set and cleared by software..

GPIOHRST

Bit 7: I/O port H reset This bit is set and cleared by software..

GPIOIRST

Bit 8: I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOJRST

Bit 9: I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

ADC12RST

Bit 10: ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx..

DCMI_PSSIRST

Bit 12: DCMI and PSSI reset This bit is set and cleared by software..

OTGRST

Bit 14: OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

AESRST

Bit 16: AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HASHRST

Bit 17: HASH reset This bit is set and cleared by software..

RNGRST

Bit 18: RNG reset This bit is set and cleared by software..

PKARST

Bit 19: PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SAESRST

Bit 20: SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPIMRST

Bit 21: OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC1RST

Bit 23: OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC2RST

Bit 24: OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SDMMC1RST

Bit 27: SDMMC1 reset This bit is set and cleared by software..

SDMMC2RST

Bit 28: SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2RSTR2

RCC AHB2 peripheral reset register 2

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSPI1RST rw				OCTOSPI2RST rw				OCTOSPI1RST rw				FSMCRST rw

Toggle fields

FSMCRST

Bit 0: Flexible memory controller reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPI1RST

Bit 4: OCTOSPI1 reset This bit is set and cleared by software..

OCTOSPI2RST

Bit 8: OCTOSPI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HSPI1RST

Bit 12: HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB3RSTR

RCC AHB3 peripheral reset register

Offset: 0x6c, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					ADF1RST rw	LPDMA1RST rw			DAC1RST rw	ADC4RST rw					LPGPIO1RST rw

Toggle fields

LPGPIO1RST

Bit 0: LPGPIO1 reset This bit is set and cleared by software..

ADC4RST

Bit 5: ADC4 reset This bit is set and cleared by software..

DAC1RST

Bit 6: DAC1 reset This bit is set and cleared by software..

LPDMA1RST

Bit 9: LPDMA1 reset This bit is set and cleared by software..

ADF1RST

Bit 10: ADF1 reset This bit is set and cleared by software..

RCC_APB1RSTR1

RCC APB1 peripheral reset register 1

Offset: 0x74, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						USART6RST rw	CRSRST rw		I2C2RST rw	I2C1RST rw	UART5RST rw	UART4RST rw	USART3RST rw	USART2RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2RST rw									TIM7RST rw	TIM6RST rw	TIM5RST rw	TIM4RST rw	TIM3RST rw	TIM2RST rw

Toggle fields

TIM2RST

Bit 0: TIM2 reset This bit is set and cleared by software..

TIM3RST

Bit 1: TIM3 reset This bit is set and cleared by software..

TIM4RST

Bit 2: TIM4 reset This bit is set and cleared by software..

TIM5RST

Bit 3: TIM5 reset This bit is set and cleared by software..

TIM6RST

Bit 4: TIM6 reset This bit is set and cleared by software..

TIM7RST

Bit 5: TIM7 reset This bit is set and cleared by software..

SPI2RST

Bit 14: SPI2 reset This bit is set and cleared by software..

USART2RST

Bit 17: USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USART3RST

Bit 18: USART3 reset This bit is set and cleared by software..

UART4RST

Bit 19: UART4 reset This bit is set and cleared by software..

UART5RST

Bit 20: UART5 reset This bit is set and cleared by software..

I2C1RST

Bit 21: I2C1 reset This bit is set and cleared by software..

I2C2RST

Bit 22: I2C2 reset This bit is set and cleared by software..

CRSRST

Bit 24: CRS reset This bit is set and cleared by software..

USART6RST

Bit 25: USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB1RSTR2

RCC APB1 peripheral reset register 2

Offset: 0x78, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UCPD1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FDCAN1RST rw		I2C6RST rw	I2C5RST rw	LPTIM2RST rw				I2C4RST rw

Toggle fields

I2C4RST

Bit 1: I2C4 reset This bit is set and cleared by software.

LPTIM2RST

Bit 5: LPTIM2 reset This bit is set and cleared by software..

I2C5RST

Bit 6: I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

I2C6RST

Bit 7: I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

FDCAN1RST

Bit 9: FDCAN1 reset This bit is set and cleared by software..

UCPD1RST

Bit 23: UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB2RSTR

RCC APB2 peripheral reset register

Offset: 0x7c, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DSIRST rw	LTDCRST rw	GFXTIMRST rw	USBRST rw		SAI2RST rw	SAI1RST rw			TIM17RST rw	TIM16RST rw	TIM15RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1RST rw	TIM8RST rw	SPI1RST rw	TIM1RST rw

Toggle fields

TIM1RST

Bit 11: TIM1 reset This bit is set and cleared by software..

SPI1RST

Bit 12: SPI1 reset This bit is set and cleared by software..

TIM8RST

Bit 13: TIM8 reset This bit is set and cleared by software..

USART1RST

Bit 14: USART1 reset This bit is set and cleared by software..

TIM15RST

Bit 16: TIM15 reset This bit is set and cleared by software..

TIM16RST

Bit 17: TIM16 reset This bit is set and cleared by software..

TIM17RST

Bit 18: TIM17 reset This bit is set and cleared by software..

SAI1RST

Bit 21: SAI1 reset This bit is set and cleared by software..

SAI2RST

Bit 22: SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USBRST

Bit 24: USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXTIMRST

Bit 25: GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

LTDCRST

Bit 26: LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DSIRST

Bit 27: DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB3RSTR

RCC APB3 peripheral reset register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											VREFRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPRST rw	OPAMPRST rw	LPTIM4RST rw	LPTIM3RST rw	LPTIM1RST rw				I2C3RST rw	LPUART1RST rw	SPI3RST rw				SYSCFGRST rw

Toggle fields

SYSCFGRST

Bit 1: SYSCFG reset This bit is set and cleared by software..

SPI3RST

Bit 5: SPI3 reset This bit is set and cleared by software..

LPUART1RST

Bit 6: LPUART1 reset This bit is set and cleared by software..

I2C3RST

Bit 7: I2C3 reset This bit is set and cleared by software..

LPTIM1RST

Bit 11: LPTIM1 reset This bit is set and cleared by software..

LPTIM3RST

Bit 12: LPTIM3 reset This bit is set and cleared by software..

LPTIM4RST

Bit 13: LPTIM4 reset This bit is set and cleared by software..

OPAMPRST

Bit 14: OPAMP reset This bit is set and cleared by software..

COMPRST

Bit 15: COMP reset This bit is set and cleared by software..

VREFRST

Bit 20: VREFBUF reset This bit is set and cleared by software..

RCC_AHB1ENR

RCC AHB1 peripheral clock enable register

Offset: 0x88, size: 32, reset: 0xD0200100, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM1EN rw	DCACHE1EN rw		BKPSRAMEN rw				GTZC1EN rw			DCACHE2EN rw	GPU2DEN rw	GFXMMUEN rw	DMA2DEN rw	RAMCFGEN rw	TSCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JPEGEN rw			CRCEN rw				FLASHEN rw					MDF1EN rw	FMACEN rw	CORDICEN rw	GPDMA1EN rw

Toggle fields

GPDMA1EN

Bit 0: GPDMA1 clock enable This bit is set and cleared by software..

CORDICEN

Bit 1: CORDIC clock enable This bit is set and cleared by software..

FMACEN

Bit 2: FMAC clock enable This bit is set and reset by software..

MDF1EN

Bit 3: MDF1 clock enable This bit is set and reset by software..

FLASHEN

Bit 8: FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the flash memory is in power-down mode..

CRCEN

Bit 12: CRC clock enable This bit is set and cleared by software..

JPEGEN

Bit 15: JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

TSCEN

Bit 16: Touch sensing controller clock enable This bit is set and cleared by software..

RAMCFGEN

Bit 17: RAMCFG clock enable This bit is set and cleared by software..

DMA2DEN

Bit 18: DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXMMUEN

Bit 19: GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPU2DEN

Bit 20: GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DCACHE2EN

Bit 21: DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GTZC1EN

Bit 24: GTZC1 clock enable This bit is set and reset by software..

BKPSRAMEN

Bit 28: BKPSRAM clock enable This bit is set and reset by software..

DCACHE1EN

Bit 30: DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2, HSPI1 or FSMC, even if the DCACHE1 is bypassed..

SRAM1EN

Bit 31: SRAM1 clock enable This bit is set and reset by software..

RCC_AHB2ENR1

RCC AHB2 peripheral clock enable register 1

Offset: 0x8c, size: 32, reset: 0xC0000000, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM3EN rw	SRAM2EN rw		SDMMC2EN rw	SDMMC1EN rw			OTFDEC2EN rw	OTFDEC1EN rw		OCTOSPIMEN rw	SAESEN rw	PKAEN rw	RNGEN rw	HASHEN rw	AESEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OTGHSPHYEN rw	OTGEN rw		DCMI_PSSIEN rw		ADC12EN rw	GPIOJEN rw	GPIOIEN rw	GPIOHEN rw	GPIOGEN rw	GPIOFEN rw	GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle fields

GPIOAEN

Bit 0: I/O port A clock enable This bit is set and cleared by software..

GPIOBEN

Bit 1: I/O port B clock enable This bit is set and cleared by software..

GPIOCEN

Bit 2: I/O port C clock enable This bit is set and cleared by software..

GPIODEN

Bit 3: I/O port D clock enable This bit is set and cleared by software..

GPIOEEN

Bit 4: I/O port E clock enable This bit is set and cleared by software..

GPIOFEN

Bit 5: I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOGEN

Bit 6: I/O port G clock enable This bit is set and cleared by software..

GPIOHEN

Bit 7: I/O port H clock enable This bit is set and cleared by software..

GPIOIEN

Bit 8: I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOJEN

Bit 9: I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

ADC12EN

Bit 10: ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx..

DCMI_PSSIEN

Bit 12: DCMI and PSSI clock enable This bit is set and cleared by software..

OTGEN

Bit 14: OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTGHSPHYEN

Bit 15: OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

AESEN

Bit 16: AES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HASHEN

Bit 17: HASH clock enable This bit is set and cleared by software.

RNGEN

Bit 18: RNG clock enable This bit is set and cleared by software..

PKAEN

Bit 19: PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SAESEN

Bit 20: SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPIMEN

Bit 21: OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC1EN

Bit 23: OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC2EN

Bit 24: OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SDMMC1EN

Bit 27: SDMMC1 clock enable This bit is set and cleared by software..

SDMMC2EN

Bit 28: SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM2EN

Bit 30: SRAM2 clock enable This bit is set and reset by software..

SRAM3EN

Bit 31: SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2ENR2

RCC AHB2 peripheral clock enable register 2

Offset: 0x90, size: 32, reset: 0x80000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM5EN rw	SRAM6EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSPI1EN rw				OCTOSPI2EN rw				OCTOSPI1EN rw				FSMCEN rw

Toggle fields

FSMCEN

Bit 0: FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPI1EN

Bit 4: OCTOSPI1 clock enable This bit is set and cleared by software..

OCTOSPI2EN

Bit 8: OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HSPI1EN

Bit 12: HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM6EN

Bit 30: SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM5EN

Bit 31: SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB3ENR

RCC AHB3 peripheral clock enable register

Offset: 0x94, size: 32, reset: 0x80000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM4EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			GTZC2EN rw		ADF1EN rw	LPDMA1EN rw			DAC1EN rw	ADC4EN rw			PWREN rw		LPGPIO1EN rw

Toggle fields

LPGPIO1EN

Bit 0: LPGPIO1 enable This bit is set and cleared by software..

PWREN

Bit 2: PWR clock enable This bit is set and cleared by software..

ADC4EN

Bit 5: ADC4 clock enable This bit is set and cleared by software..

DAC1EN

Bit 6: DAC1 clock enable This bit is set and cleared by software..

LPDMA1EN

Bit 9: LPDMA1 clock enable This bit is set and cleared by software..

ADF1EN

Bit 10: ADF1 clock enable This bit is set and cleared by software..

GTZC2EN

Bit 12: GTZC2 clock enable This bit is set and cleared by software..

SRAM4EN

Bit 31: SRAM4 clock enable This bit is set and reset by software..

RCC_APB1ENR1

RCC APB1 peripheral clock enable register 1

Offset: 0x9c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						USART6EN rw	CRSEN rw		I2C2EN rw	I2C1EN rw	UART5EN rw	UART4EN rw	USART3EN rw	USART2EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw			WWDGEN rw						TIM7EN rw	TIM6EN rw	TIM5EN rw	TIM4EN rw	TIM3EN rw	TIM2EN rw

Toggle fields

TIM2EN

Bit 0: TIM2 clock enable This bit is set and cleared by software..

TIM3EN

Bit 1: TIM3 clock enable This bit is set and cleared by software..

TIM4EN

Bit 2: TIM4 clock enable This bit is set and cleared by software..

TIM5EN

Bit 3: TIM5 clock enable This bit is set and cleared by software..

TIM6EN

Bit 4: TIM6 clock enable This bit is set and cleared by software..

TIM7EN

Bit 5: TIM7 clock enable This bit is set and cleared by software..

WWDGEN

Bit 11: WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset..

SPI2EN

Bit 14: SPI2 clock enable This bit is set and cleared by software..

USART2EN

Bit 17: USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USART3EN

Bit 18: USART3 clock enable This bit is set and cleared by software..

UART4EN

Bit 19: UART4 clock enable This bit is set and cleared by software..

UART5EN

Bit 20: UART5 clock enable This bit is set and cleared by software..

I2C1EN

Bit 21: I2C1 clock enable This bit is set and cleared by software..

I2C2EN

Bit 22: I2C2 clock enable This bit is set and cleared by software..

CRSEN

Bit 24: CRS clock enable This bit is set and cleared by software..

USART6EN

Bit 25: USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB1ENR2

RCC APB1 peripheral clock enable register 2

Offset: 0xa0, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UCPD1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FDCAN1EN rw		I2C6EN rw	I2C5EN rw	LPTIM2EN rw				I2C4EN rw

Toggle fields

I2C4EN

Bit 1: I2C4 clock enable This bit is set and cleared by software.

LPTIM2EN

Bit 5: LPTIM2 clock enable This bit is set and cleared by software..

I2C5EN

Bit 6: I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

I2C6EN

Bit 7: I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

FDCAN1EN

Bit 9: FDCAN1 clock enable This bit is set and cleared by software..

UCPD1EN

Bit 23: UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB2ENR

RCC APB2 peripheral clock enable register

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DSIEN rw	LTDCEN rw	GFXTIMEN rw	USBEN rw		SAI2EN rw	SAI1EN rw			TIM17EN rw	TIM16EN rw	TIM15EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw	TIM8EN rw	SPI1EN rw	TIM1EN rw

Toggle fields

TIM1EN

Bit 11: TIM1 clock enable This bit is set and cleared by software..

SPI1EN

Bit 12: SPI1 clock enable This bit is set and cleared by software..

TIM8EN

Bit 13: TIM8 clock enable This bit is set and cleared by software..

USART1EN

Bit 14: USART1clock enable This bit is set and cleared by software..

TIM15EN

Bit 16: TIM15 clock enable This bit is set and cleared by software..

TIM16EN

Bit 17: TIM16 clock enable This bit is set and cleared by software..

TIM17EN

Bit 18: TIM17 clock enable This bit is set and cleared by software..

SAI1EN

Bit 21: SAI1 clock enable This bit is set and cleared by software..

SAI2EN

Bit 22: SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USBEN

Bit 24: USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXTIMEN

Bit 25: GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

LTDCEN

Bit 26: LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DSIEN

Bit 27: DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB3ENR

RCC APB3 peripheral clock enable register

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										RTCAPBEN rw	VREFEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPEN rw	OPAMPEN rw	LPTIM4EN rw	LPTIM3EN rw	LPTIM1EN rw				I2C3EN rw	LPUART1EN rw	SPI3EN rw				SYSCFGEN rw

Toggle fields

SYSCFGEN

Bit 1: SYSCFG clock enable This bit is set and cleared by software..

SPI3EN

Bit 5: SPI3 clock enable This bit is set and cleared by software..

LPUART1EN

Bit 6: LPUART1 clock enable This bit is set and cleared by software..

I2C3EN

Bit 7: I2C3 clock enable This bit is set and cleared by software..

LPTIM1EN

Bit 11: LPTIM1 clock enable This bit is set and cleared by software..

LPTIM3EN

Bit 12: LPTIM3 clock enable This bit is set and cleared by software..

LPTIM4EN

Bit 13: LPTIM4 clock enable This bit is set and cleared by software..

OPAMPEN

Bit 14: OPAMP clock enable This bit is set and cleared by software..

COMPEN

Bit 15: COMP clock enable This bit is set and cleared by software..

VREFEN

Bit 20: VREFBUF clock enable This bit is set and cleared by software..

RTCAPBEN

Bit 21: RTC and TAMP APB clock enable This bit is set and cleared by software..

RCC_AHB1SMENR

RCC AHB1 peripheral clock enable in Sleep and Stop modes register

Offset: 0xb0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM1SMEN rw	DCACHE1SMEN rw	ICACHESMEN rw	BKPSRAMSMEN rw				GTZC1SMEN rw			DCACHE2SMEN rw	GPU2DSMEN rw	GFXMMUSMEN rw	DMA2DSMEN rw	RAMCFGSMEN rw	TSCSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JPEGSMEN rw			CRCSMEN rw				FLASHSMEN rw					MDF1SMEN rw	FMACSMEN rw	CORDICSMEN rw	GPDMA1SMEN rw

Toggle fields

GPDMA1SMEN

Bit 0: GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

CORDICSMEN

Bit 1: CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sleep mode..

FMACSMEN

Bit 2: FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software..

MDF1SMEN

Bit 3: MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

FLASHSMEN

Bit 8: FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software..

CRCSMEN

Bit 12: CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software..

JPEGSMEN

Bit 15: JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

TSCSMEN

Bit 16: TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software..

RAMCFGSMEN

Bit 17: RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software..

DMA2DSMEN

Bit 18: DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXMMUSMEN

Bit 19: GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPU2DSMEN

Bit 20: GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DCACHE2SMEN

Bit 21: DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GTZC1SMEN

Bit 24: GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

BKPSRAMSMEN

Bit 28: BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software.

ICACHESMEN

Bit 29: ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software..

DCACHE1SMEN

Bit 30: DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SRAM1SMEN

Bit 31: SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

RCC_AHB2SMENR1

RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1

Offset: 0xb4, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM3SMEN rw	SRAM2SMEN rw		SDMMC2SMEN rw	SDMMC1SMEN rw			OTFDEC2SMEN rw	OTFDEC1SMEN rw		OCTOSPIMSMEN rw	SAESSMEN rw	PKASMEN rw	RNGSMEN rw	HASHSMEN rw	AESSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OTGHSPHYSMEN rw	OTGSMEN rw		DCMI_PSSISMEN rw		ADC12SMEN rw	GPIOJSMEN rw	GPIOISMEN rw	GPIOHSMEN rw	GPIOGSMEN rw	GPIOFSMEN rw	GPIOESMEN rw	GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle fields

GPIOASMEN

Bit 0: I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOBSMEN

Bit 1: I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOCSMEN

Bit 2: I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIODSMEN

Bit 3: I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOESMEN

Bit 4: I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOFSMEN

Bit 5: I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOGSMEN

Bit 6: I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOHSMEN

Bit 7: I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software..

GPIOISMEN

Bit 8: I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GPIOJSMEN

Bit 9: I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

ADC12SMEN

Bit 10: ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx..

DCMI_PSSISMEN

Bit 12: DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software..

OTGSMEN

Bit 14: OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTGHSPHYSMEN

Bit 15: OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

AESSMEN

Bit 16: AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes This bit is set and cleared by software.

RNGSMEN

Bit 18: RNG clock enable during Sleep and Stop modes This bit is set and cleared by software..

PKASMEN

Bit 19: PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SAESSMEN

Bit 20: SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPIMSMEN

Bit 21: OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC1SMEN

Bit 23: OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OTFDEC2SMEN

Bit 24: OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SDMMC1SMEN

Bit 27: SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SDMMC2SMEN

Bit 28: SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM2SMEN

Bit 30: SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SRAM3SMEN

Bit 31: SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB2SMENR2

RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2

Offset: 0xb8, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM5SMEN rw	SRAM6SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSPI1SMEN rw				OCTOSPI2SMEN rw				OCTOSPI1SMEN rw				FSMCSMEN rw

Toggle fields

FSMCSMEN

Bit 0: FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPI1SMEN

Bit 4: OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

OCTOSPI2SMEN

Bit 8: OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

HSPI1SMEN

Bit 12: HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM6SMEN

Bit 30: SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

SRAM5SMEN

Bit 31: SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_AHB3SMENR

RCC AHB3 peripheral clock enable in Sleep and Stop modes register

Offset: 0xbc, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM4SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			GTZC2SMEN rw		ADF1SMEN rw	LPDMA1SMEN rw			DAC1SMEN rw	ADC4SMEN rw			PWRSMEN rw		LPGPIO1SMEN rw

Toggle fields

LPGPIO1SMEN

Bit 0: LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software..

PWRSMEN

Bit 2: PWR clock enable during Sleep and Stop modes This bit is set and cleared by software..

ADC4SMEN

Bit 5: ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

DAC1SMEN

Bit 6: DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPDMA1SMEN

Bit 9: LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

ADF1SMEN

Bit 10: ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

GTZC2SMEN

Bit 12: GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SRAM4SMEN

Bit 31: SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software..

RCC_APB1SMENR1

RCC APB1 peripheral clock enable in Sleep and Stop modes register 1

Offset: 0xc4, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						USART6SMEN rw	CRSSMEN rw		I2C2SMEN rw	I2C1SMEN rw	UART5SMEN rw	UART4SMEN rw	USART3SMEN rw	USART2SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw			WWDGSMEN rw						TIM7SMEN rw	TIM6SMEN rw	TIM5SMEN rw	TIM4SMEN rw	TIM3SMEN rw	TIM2SMEN rw

Toggle fields

TIM2SMEN

Bit 0: TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM3SMEN

Bit 1: TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM4SMEN

Bit 2: TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM5SMEN

Bit 3: TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM6SMEN

Bit 4: TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM7SMEN

Bit 5: TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software..

WWDGSMEN

Bit 11: Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. It is forced to one by hardware when the hardware WWDG option is activated..

SPI2SMEN

Bit 14: SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

USART2SMEN

Bit 17: USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USART3SMEN

Bit 18: USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

UART4SMEN

Bit 19: UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

UART5SMEN

Bit 20: UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C1SMEN

Bit 21: I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C2SMEN

Bit 22: I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes This bit is set and cleared by software..

USART6SMEN

Bit 25: USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB1SMENR2

RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0xc8, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								UCPD1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FDCAN1SMEN rw		I2C6SMEN rw	I2C5SMEN rw	LPTIM2SMEN rw				I2C4SMEN rw

Toggle fields

I2C4SMEN

Bit 1: I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM2SMEN

Bit 5: LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C5SMEN

Bit 6: I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

I2C6SMEN

Bit 7: I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

FDCAN1SMEN

Bit 9: FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

UCPD1SMEN

Bit 23: UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB2SMENR

RCC APB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0xcc, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DSISMEN rw	LTDCSMEN rw	GFXTIMSMEN rw	USBSMEN rw		SAI2SMEN rw	SAI1SMEN rw			TIM17SMEN rw	TIM16SMEN rw	TIM15SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1SMEN rw	TIM8SMEN rw	SPI1SMEN rw	TIM1SMEN rw

Toggle fields

TIM1SMEN

Bit 11: TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SPI1SMEN

Bit 12: SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

TIM8SMEN

Bit 13: TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software..

USART1SMEN

Bit 14: USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

TIM15SMEN

Bit 16: TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM16SMEN

Bit 17: TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software..

TIM17SMEN

Bit 18: TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SAI1SMEN

Bit 21: SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software..

SAI2SMEN

Bit 22: SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

USBSMEN

Bit 24: USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

GFXTIMSMEN

Bit 25: GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

LTDCSMEN

Bit 26: LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

DSISMEN

Bit 27: DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RCC_APB3SMENR

RCC APB3 peripheral clock enable in Sleep and Stop modes register

Offset: 0xd0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										RTCAPBSMEN rw	VREFSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPSMEN rw	OPAMPSMEN rw	LPTIM4SMEN rw	LPTIM3SMEN rw	LPTIM1SMEN rw				I2C3SMEN rw	LPUART1SMEN rw	SPI3SMEN rw				SYSCFGSMEN rw

Toggle fields

SYSCFGSMEN

Bit 1: SYSCFG clock enable during Sleep and Stop modes This bit is set and cleared by software..

SPI3SMEN

Bit 5: SPI3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPUART1SMEN

Bit 6: LPUART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C3SMEN

Bit 7: I2C3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM1SMEN

Bit 11: LPTIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM3SMEN

Bit 12: LPTIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM4SMEN

Bit 13: LPTIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

OPAMPSMEN

Bit 14: OPAMP clock enable during Sleep and Stop modes This bit is set and cleared by software..

COMPSMEN

Bit 15: COMP clock enable during Sleep and Stop modes This bit is set and cleared by software..

VREFSMEN

Bit 20: VREFBUF clock enable during Sleep and Stop modes This bit is set and cleared by software..

RTCAPBSMEN

Bit 21: RTC and TAMP APB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

RCC_SRDAMR

RCC SmartRun domain peripheral autonomous mode register

Offset: 0xd8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM4AMEN rw		ADF1AMEN rw	LPDMA1AMEN rw	DAC1AMEN rw	LPGPIO1AMEN rw	ADC4AMEN rw				RTCAPBAMEN rw	VREFAMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMPAMEN rw	OPAMPAMEN rw	LPTIM4AMEN rw	LPTIM3AMEN rw	LPTIM1AMEN rw				I2C3AMEN rw	LPUART1AMEN rw	SPI3AMEN rw

Toggle fields

SPI3AMEN

Bit 5: SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPUART1AMEN

Bit 6: LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

I2C3AMEN

Bit 7: I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM1AMEN

Bit 11: LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM3AMEN

Bit 12: LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPTIM4AMEN

Bit 13: LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

OPAMPAMEN

Bit 14: OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

COMPAMEN

Bit 15: COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

VREFAMEN

Bit 20: VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

RTCAPBAMEN

Bit 21: RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

ADC4AMEN

Bit 25: ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPGPIO1AMEN

Bit 26: LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

DAC1AMEN

Bit 27: DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

LPDMA1AMEN

Bit 28: LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

ADF1AMEN

Bit 29: ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes..

SRAM4AMEN

Bit 31: SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software..

RCC_CCIPR1

RCC peripherals independent clock configuration register 1

Offset: 0xe0, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIMICSEL rw				ICLKSEL rw		FDCAN1SEL rw		SYSTICKSEL rw		SPI1SEL rw		LPTIM2SEL rw		SPI2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I2C4SEL rw		I2C2SEL rw		I2C1SEL rw		UART5SEL rw		UART4SEL rw		USART3SEL rw		USART2SEL rw		USART1SEL rw

Toggle fields

USART1SEL

Bits 0-1: USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

USART2SEL

Bits 2-3: USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source. The USART2 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

USART3SEL

Bits 4-5: USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

UART4SEL

Bits 6-7: UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

UART5SEL

Bits 8-9: UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE..

I2C1SEL

Bits 10-11: I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK..

I2C2SEL

Bits 12-13: I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK..

I2C4SEL

Bits 14-15: I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK..

SPI2SEL

Bits 16-17: SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK..

LPTIM2SEL

Bits 18-19: Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1..

SPI1SEL

Bits 20-21: SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK..

SYSTICKSEL

Bits 22-23: SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry..

FDCAN1SEL

Bits 24-25: FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source..

ICLKSEL

Bits 26-27: Intermediate clock source selection These bits are used to select the clock source for the OTG_FS, the USB, and the SDMMC..

TIMICSEL

Bits 29-31: Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16, TIM17, and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4, or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK, and MSIS clock sources cannot be selected as�TIM16, TIM17, or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division..

RCC_CCIPR2

RCC peripherals independent clock configuration register 2

Offset: 0xe4, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OTGHSSEL rw				I2C6SEL rw		I2C5SEL rw		HSPI1SEL rw		OCTOSPISEL rw			LTDCSEL rw	USART6SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DSISEL rw	SDMMCSEL rw	RNGSEL rw		SAESSEL rw	SAI2SEL rw			SAI1SEL rw					MDF1SEL rw

Toggle fields

MDF1SEL

Bits 0-2: MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved.

SAI1SEL

Bits 5-7: SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible..

SAI2SEL

Bits 8-10: SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

SAESSEL

Bit 11: SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

RNGSEL

Bits 12-13: RNG kernel clock source selection These bits are used to select the RNG kernel clock source..

SDMMCSEL

Bit 14: SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change it only after reset and before enabling the SDMMC..

DSISEL

Bit 15: DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value..

USART6SEL

Bits 16-17: USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

LTDCSEL

Bit 18: LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value..

OCTOSPISEL

Bits 20-21: OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source..

HSPI1SEL

Bits 22-23: HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

I2C5SEL

Bits 24-25: I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

I2C6SEL

Bits 26-27: I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

OTGHSSEL

Bits 30-31: OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value..

RCC_CCIPR3

RCC peripherals independent clock configuration register 3

Offset: 0xe8, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													ADF1SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DAC1SEL rw	ADCDACSEL rw			LPTIM1SEL rw		LPTIM34SEL rw		I2C3SEL rw			SPI3SEL rw		LPUART1SEL rw

Toggle fields

LPUART1SEL

Bits 0-2: LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16, LSE, or MSIK..

SPI3SEL

Bits 3-4: SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK..

I2C3SEL

Bits 6-7: I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK..

LPTIM34SEL

Bits 8-9: LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON�=�1..

LPTIM1SEL

Bits 10-11: LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON = 1..

ADCDACSEL

Bits 12-14: ADC1, ADC2, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC2, ADC4, and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC2, ADC4, and DAC1 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in�Stop 2 mode)..

DAC1SEL

Bit 15: DAC1 sample-and-hold clock source selection This bit is used to select the DAC1 sample-and-hold clock source..

ADF1SEL

Bits 16-18: ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK..

RCC_BDCR

RCC backup domain control register

Offset: 0xf0, size: 32, reset: 0x00000000, access: Unspecified

3/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			LSIPREDIV rw	LSIRDY rw	LSION rw	LSCOSEL rw	LSCOEN rw								BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw			LSEGFON rw	LSESYSRDY r		RTCSEL rw		LSESYSEN rw	LSECSSD r	LSECSSON rw	LSEDRV rw		LSEBYP rw	LSERDY r	LSEON rw

Toggle fields

LSEON

Bit 0: LSE oscillator enable This bit is set and cleared by software..

LSERDY

Bit 1: LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After LSEON is cleared, this LSERDY bit goes low after six external low-speed oscillator clock cycles..

LSEBYP

Bit 2: LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. It can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)..

LSEDRV

Bits 3-4: LSE oscillator drive capability This bitfield is set by software to modulate the drive capability of the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode..

LSECSSON

Bit 5: CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable this LSECSSON bit..

LSECSSD

Bit 6: CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by the CCS on the external 32�kHz oscillator (LSE)..

LSESYSEN

Bit 7: LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock generated by RCC, which can be used by any peripheral when its source clock is the LSE, or at system level if one of LSCOSEL, MCO, or MSI PLL mode is needed..

RTCSEL

Bits 8-9: RTC and TAMP clock source selection This bit is set by software to select the clock source for the RTC and TAMP. Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the�backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). BDRST bit can be used to reset them..

LSESYSRDY

Bit 11: LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE system clock is stable.When LSESYSEN is set, this LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles..

LSEGFON

Bit 12: LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch filter. It can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)..

RTCEN

Bit 15: RTC and TAMP clock enable This bit is set and cleared by software..

BDRST

Bit 16: Backup domain software reset This bit is set and cleared by software..

LSCOEN

Bit 24: Low-speed clock output (LSCO) enable This bit is set and cleared by software..

LSCOSEL

Bit 25: Low-speed clock output selection This bit is set and cleared by software..

LSION

Bit 26: LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60��s maximum after the LSION bit is cleared..

LSIRDY

Bit 27: LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After�LSION is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0..

LSIPREDIV

Bit 28: Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI division. It can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC..

RCC_CSR

RCC control/status register

Offset: 0xf4, size: 32, reset: 0x0C004400, access: Unspecified

7/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF r	WWDGRSTF r	IWDGRSTF r	SFTRSTF r	BORRSTF r	PINRSTF r	OBLRSTF r		RMVF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSISSRANGE rw				MSIKSRANGE rw

Toggle fields

MSIKSRANGE

Bits 8-11: MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIK frequency..

MSISSRANGE

Bits 12-15: MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIS frequency..

RMVF

Bit 23: Remove reset flag This bit is set by software to clear the reset flags..

OBLRSTF

Bit 25: Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading occurs. It is cleared by�writing to the RMVF bit..

PINRSTF

Bit 26: NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to�the RMVF bit..

BORRSTF

Bit 27: Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout reset or an exit from Shutdown mode reset occurs. It is cleared by writing to the RMVF bit..

SFTRSTF

Bit 28: Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writing to RMVF..

IWDGRSTF

Bit 29: Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared by writing to the RMVF bit..

WWDGRSTF

Bit 30: Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to�the RMVF bit..

LPWRRSTF

Bit 31: Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shutdown mode entry, whereas the corresponding NRST_STOP, NRST_STBY, or NRST_SHDW option bit is cleared. This bit is cleared by writing to the RMVF bit..

RCC_SECCFGR

RCC secure configuration register

Offset: 0x110, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			RMVFSEC rw	HSI48SEC rw	ICLKSEC rw	PLL3SEC rw	PLL2SEC rw	PLL1SEC rw	PRESCSEC rw	SYSCLKSEC rw	LSESEC rw	LSISEC rw	MSISEC rw	HSESEC rw	HSISEC rw

Toggle fields

HSISEC

Bit 0: HSI clock configuration and status bit security This bit is set and reset by software..

HSESEC

Bit 1: HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software..

MSISEC

Bit 2: MSI clock configuration and status bit security This bit is set and reset by software..

LSISEC

Bit 3: LSI clock configuration and status bit security This bit is set and reset by software..

LSESEC

Bit 4: LSE clock configuration and status bit security This bit is set and reset by software..

SYSCLKSEC

Bit 5: SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set and reset by software..

PRESCSEC

Bit 6: AHBx/APBx prescaler configuration bits security This bit is set and reset by software..

PLL1SEC

Bit 7: PLL1 clock configuration and status bit security This bit is set and reset by software..

PLL2SEC

Bit 8: PLL2 clock configuration and status bit security Set and reset by software..

PLL3SEC

Bit 9: PLL3 clock configuration and status bit security This bit is set and reset by software..

ICLKSEC

Bit 10: Intermediate clock source selection security This bit is set and reset by software..

HSI48SEC

Bit 11: HSI48 clock configuration and status bit security This bit is set and reset by software..

RMVFSEC

Bit 12: Remove reset flag security This bit is set and reset by software..

RCC_PRIVCFGR

RCC privilege configuration register

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														NSPRIV rw	SPRIV rw

Toggle fields

SPRIV

Bit 0: RCC secure function privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access..

NSPRIV

Bit 1: RCC non-secure function privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure..

SEC_RNG

0x520c0800: Random number generator

4/18 fields covered.

Toggle register map

Offset	Name	31	30	25	19	15	12	11	7	6	5	3	2	1	0
0x0	CR	CONFIGLOCK	CONDRST	RNG_CONFIG1	CLKDIV	RNG_CONFIG2	NISTC	RNG_CONFIG3	ARDIS		CED	IE	RNGEN
0x4	SR									SEIS	CEIS		SECS	CECS	DRDY
0x8	DR	RNDATA				RNDATA
0x10	HTCR	HTCFG				HTCFG

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CONFIGLOCK rw	CONDRST rw					RNG_CONFIG1 rw						CLKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNG_CONFIG2 rw			NISTC rw	RNG_CONFIG3 rw				ARDIS rw		CED rw		IE rw	RNGEN rw

Toggle fields

RNGEN

Bit 2: True random number generator enable.

IE

Bit 3: Interrupt Enable.

CED

Bit 5: Clock error detection.

ARDIS

Bit 7: Auto reset disable.

RNG_CONFIG3

Bits 8-11: RNG configuration 3.

NISTC

Bit 12: Non NIST compliant.

RNG_CONFIG2

Bits 13-15: RNG configuration 2.

CLKDIV

Bits 16-19: Clock divider factor.

RNG_CONFIG1

Bits 20-25: RNG configuration 1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: RNG Config Lock.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SEIS rw	CEIS rw			SECS r	CECS r	DRDY r

Toggle fields

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNDATA r

Toggle fields

RNDATA

Bits 0-31: Random data.

HTCR

health test control register

Offset: 0x10, size: 32, reset: 0x00006274, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HTCFG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HTCFG rw

Toggle fields

HTCFG

Bits 0-31: health test configuration.

SEC_RTC

0x56007800: Real-time clock

40/156 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TR										PM	HT		HU					MNT			MNU					ST			SU
0x4	DR									YT				YU				WDU			MT	MU						DT		DU
0x8	SSR	SS																SS
0xc	ICSR																RECALPF				BCDU			BIN		INIT	INITF	RSF	INITS	SHPF	WUTWF
0x10	PRER										PREDIV_A								PREDIV_S
0x14	WUTR	WUTOCLR																WUT
0x18	CR	OUT2EN	TAMPALRM_TYPE	TAMPALRM_PU	ALRBFCLR	ALRAFCLR	TAMPOE	TAMPTS	ITSE	COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE	WUTIE	ALRBIE	ALRAIE	TSE	WUTE	ALRBE	ALRAE	SSRUIE	FMT	BYPSHAD	REFCKON	TSEDGE	WUCKSEL
0x1c	PRIVCR																	PRIV	INITPRIV	CALPRIV										TSPRIV	WUTPRIV	ALRBPRIV	ALRAPRIV
0x20	SECCFGR																	SEC	INITSEC	CALSEC										TSSEC	WUTSEC	ALRBSEC	ALRASEC
0x24	WPR																									KEY
0x28	CALR																	CALP	CALW8	CALW16	LPCAL				CALM
0x2c	SHIFTR	ADD1S																	SUBFS
0x30	TSTR										PM	HT		HU					MNT			MNU					ST			SU
0x34	TSDR																	WDU			MT	MU						DT		DU
0x38	TSSSR	SS																SS
0x40	ALRMAR	MSK4	WDSEL	DT		DU				MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x44	ALRMASSR	SSCLR		MASKSS															SS
0x48	ALRMBR	MSK4	WDSEL	DT		DU				MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x4c	ALRMBSSR	SSCLR		MASKSS															SS
0x50	SR																										SSRUF	ITSF	TSOVF	TSF	WUTF	ALRBF	ALRAF
0x54	MISR																										SSRUMF	ITSMF	TSOVMF	TSMF	WUTMF	ALRBMF	ALRAMF
0x58	SMISR																										SSRUMF	ITSMF	TSOVMF	TSMF	WUTMF	ALRBMF	ALRAMF
0x5c	SCR																										CSSRUF	CITSF	CTSOVF	CTSF	CWUTF	CALRBF	CALRAF
0x70	ALRABINR	SS																SS
0x74	ALRBBINR	SS																SS

Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-31: SS.

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

5/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			BCDU rw			BIN rw		INIT rw	INITF r	RSF rw	INITS r	SHPF r	WUTWF r

Toggle fields

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

BIN

Bits 8-9: BIN.

BCDU

Bits 10-12: BCDU.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WUTOCLR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

WUTOCLR

Bits 16-31: WUTOCLR.

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/29 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUT2EN rw	TAMPALRM_TYPE rw	TAMPALRM_PU rw	ALRBFCLR rw	ALRAFCLR rw	TAMPOE rw	TAMPTS rw	ITSE rw	COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H w	ADD1H w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw	ALRBIE rw	ALRAIE rw	TSE rw	WUTE rw	ALRBE rw	ALRAE rw	SSRUIE rw	FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw	WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

TSEDGE

Bit 3: TSEDGE.

REFCKON

Bit 4: REFCKON.

BYPSHAD

Bit 5: BYPSHAD.

FMT

Bit 6: FMT.

SSRUIE

Bit 7: SSRUIE.

ALRAE

Bit 8: ALRAE.

ALRBE

Bit 9: ALRBE.

WUTE

Bit 10: WUTE.

TSE

Bit 11: TSE.

ALRAIE

Bit 12: ALRAIE.

ALRBIE

Bit 13: ALRBIE.

WUTIE

Bit 14: WUTIE.

TSIE

Bit 15: TSIE.

ADD1H

Bit 16: ADD1H.

SUB1H

Bit 17: SUB1H.

BKP

Bit 18: BKP.

COSEL

Bit 19: COSEL.

POL

Bit 20: POL.

OSEL

Bits 21-22: OSEL.

COE

Bit 23: COE.

ITSE

Bit 24: ITSE.

TAMPTS

Bit 25: TAMPTS.

TAMPOE

Bit 26: TAMPOE.

ALRAFCLR

Bit 27: ALRAFCLR.

ALRBFCLR

Bit 28: ALRBFCLR.

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

OUT2EN

Bit 31: OUT2EN.

PRIVCR

RTC privilege mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV rw	INITPRIV rw	CALPRIV rw										TSPRIV rw	WUTPRIV rw	ALRBPRIV rw	ALRAPRIV rw

Toggle fields

ALRAPRIV

Bit 0: ALRAPRIV.

ALRBPRIV

Bit 1: ALRBPRIV.

WUTPRIV

Bit 2: WUTPRIV.

TSPRIV

Bit 3: TSPRIV.

CALPRIV

Bit 13: CALPRIV.

INITPRIV

Bit 14: INITPRIV.

PRIV

Bit 15: PRIV.

SECCFGR

RTC secure mode control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC rw	INITSEC rw	CALSEC rw										TSSEC rw	WUTSEC rw	ALRBSEC rw	ALRASEC rw

Toggle fields

ALRASEC

Bit 0: ALRASEC.

ALRBSEC

Bit 1: ALRBSEC.

WUTSEC

Bit 2: WUTSEC.

TSSEC

Bit 3: TSSEC.

CALSEC

Bit 13: CALSEC.

INITSEC

Bit 14: INITSEC.

SEC

Bit 15: SEC.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle fields

KEY

Bits 0-7: Write protection key.

CALR

calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw	LPCAL rw				CALM rw

Toggle fields

CALM

Bits 0-8: Calibration minus.

LPCAL

Bit 12: LPCAL.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM r	HT r		HU r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT r			MNU r					ST r			SU r

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU r			MT r	MU r						DT r		DU r

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-31: Sub second value.

ALRMAR

alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMASSR

alarm A sub second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SSCLR rw		MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

SSCLR

Bit 31: SSCLR.

ALRMBR

alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

ALRMBSSR

alarm B sub second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SSCLR rw		MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

SSCLR

Bit 31: SSCLR.

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SSRUF r	ITSF r	TSOVF r	TSF r	WUTF r	ALRBF r	ALRAF r

Toggle fields

ALRAF

Bit 0: ALRAF.

ALRBF

Bit 1: ALRBF.

WUTF

Bit 2: WUTF.

TSF

Bit 3: TSF.

TSOVF

Bit 4: TSOVF.

ITSF

Bit 5: ITSF.

SSRUF

Bit 6: SSRUF.

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SSRUMF r	ITSMF r	TSOVMF r	TSMF r	WUTMF r	ALRBMF r	ALRAMF r

Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SSRUMF

Bit 6: SSRUMF.

SMISR

RTC secure masked interrupt status register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SSRUMF r	ITSMF r	TSOVMF r	TSMF r	WUTMF r	ALRBMF r	ALRAMF r

Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SSRUMF

Bit 6: SSRUMF.

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CSSRUF w	CITSF w	CTSOVF w	CTSF w	CWUTF w	CALRBF w	CALRAF w

Toggle fields

CALRAF

Bit 0: CALRAF.

CALRBF

Bit 1: CALRBF.

CWUTF

Bit 2: CWUTF.

CTSF

Bit 3: CTSF.

CTSOVF

Bit 4: CTSOVF.

CITSF

Bit 5: CITSF.

CSSRUF

Bit 6: CSSRUF.

ALRABINR

RTC alarm A binary mode register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS rw

Toggle fields

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

ALRBBINR

RTC alarm B binary mode register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS rw

Toggle fields

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

SEC_SAI1

0x50015400: Serial audio interface

18/122 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	22	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GCR																					SYNCOUT				SYNCIN
0x4	ACR1			MCKEN	OSR	MCKDIV		NODIV		DMAEN	SAIAEN			OUTDRIV	MONO	SYNCEN		CKSTR	LSBFIRST	DS				PRTCFG		MODE
0x8	ACR2											COMP		CPL	MUTECN						MUTEVAL	MUTE	TRIS	FFLUSH	FTH
0xc	AFRCR								FSOFF	FSPOL	FSDEF		FSALL							FRL
0x10	ASLOTR	SLOTEN														NBSLOT				SLOTSZ			FBOFF
0x14	AIM																				LFSDETIE	AFSDETIE	CNRDYIE	FREQIE	WCKCFGIE	MUTEDETIE	OVRUDRIE
0x18	ASR								FLVL												LFSDET	AFSDET	CNRDY	FREQ	WCKCFG	MUTEDET	OVRUDR
0x1c	ACLRFR																				CLFSDET	CAFSDET	CCNRDY		CWCKCFG	CMUTEDET	COVRUDR
0x20	ADR	DATA										DATA
0x24	BCR1			MCKEN	OSR	MCKDIV		NODIV		DMAEN	SAIAEN			OUTDRIV	MONO	SYNCEN		CKSTR	LSBFIRST	DS				PRTCFG		MODE
0x28	BCR2											COMP		CPL	MUTECN						MUTEVAL	MUTE	TRIS	FFLUSH	FTH
0x2c	BFRCR								FSOFF	FSPOL	FSDEF		FSALL							FRL
0x30	BSLOTR	SLOTEN														NBSLOT				SLOTSZ			FBOFF
0x34	BIM																				LFSDETIE	AFSDETIE	CNRDYIE	FREQIE	WCKCFGIE	MUTEDETIE	OVRUDRIE
0x38	BSR								FLVL												LFSDET	AFSDET	CNRDY	FREQ	WCKCFG	MUTEDET	OVRUDR
0x3c	BCLRFR																				CLFSDET	CAFSDET	CCNRDY		CWCKCFG	CMUTEDET	COVRUDR
0x40	BDR	DATA										DATA
0x44	PDMCR															CKEN4	CKEN3	CKEN2	CKEN1			MICNBR					PDMEN
0x48	PDMDLY		DLYM4R		DLYM4L		DLYM3R		DLYM3L				DLYM2R				DLYM2L				DLYM1R				DLYM1L

Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SYNCOUT rw				SYNCIN rw

Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

ACR1

A Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCKDIV rw						NODIV rw		DMAEN rw	SAIAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OUTDRIV rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle fields

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OUTDRIV

Bit 13: Output drive.

SAIAEN

Bit 16: Audio block A enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCKDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

ACR2

A Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECN rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUSH rw	FTH rw

Toggle fields

FTH

Bits 0-2: FIFO threshold.

FFLUSH

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

AFRCR

A frame configuration register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

ASLOTR

A Slot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

AIM

A Interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFGIE rw	MUTEDETIE rw	OVRUDRIE rw

Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDETIE

Bit 1: Mute detection interrupt enable.

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

ASR

A Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

ACLRFR

A Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CLFSDET w	CAFSDET w	CCNRDY w		CWCKCFG w	CMUTEDET w	COVRUDR w

Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

CMUTEDET

Bit 1: Mute detection flag.

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

CCNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

ADR

A Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

BCR1

B Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCKDIV rw						NODIV rw		DMAEN rw	SAIAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OUTDRIV rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle fields

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OUTDRIV

Bit 13: Output drive.

SAIAEN

Bit 16: Audio block A enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCKDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

BCR2

B Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECN rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUSH rw	FTH rw

Toggle fields

FTH

Bits 0-2: FIFO threshold.

FFLUSH

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

BFRCR

B frame configuration register

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

BSLOTR

B Slot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

BIM

B Interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFGIE rw	MUTEDETIE rw	OVRUDRIE rw

Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDETIE

Bit 1: Mute detection interrupt enable.

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

BSR

B Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

BCLRFR

B Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CLFSDET w	CAFSDET w	CCNRDY w		CWCKCFG w	CMUTEDET w	COVRUDR w

Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

CMUTEDET

Bit 1: Mute detection flag.

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

CCNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

BDR

B Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CKEN4 rw	CKEN3 rw	CKEN2 rw	CKEN1 rw			MICNBR rw					PDMEN rw

Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

CKEN3

Bit 10: CKEN3.

CKEN4

Bit 11: CKEN4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DLYM4R rw				DLYM4L rw				DLYM3R rw				DLYM3L rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DLYM2R rw				DLYM2L rw				DLYM1R rw				DLYM1L rw

Toggle fields

DLYM1L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM1R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM2L

Bits 8-10: Delay line for first microphone of pair 2.

DLYM2R

Bits 12-14: Delay line for second microphone of pair 2.

DLYM3L

Bits 16-18: DLYM3L.

DLYM3R

Bits 20-22: DLYM3R.

DLYM4L

Bits 24-26: DLYM4L.

DLYM4R

Bits 28-30: DLYM4R.

SEC_SDMMC

0x520c8000: Secure digital input/output MultiMediaCard interface

35/140 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	POWER																												DIRPOL	VSWITCHEN	VSWITCH	PWRCTRL
0x4	CLKCR											SELCLKRX		BUSSPEED	DDR	HWFC_EN	NEGEDGE	WIDBUS			PWRSAV			CLKDIV
0x8	ARGR	CMDARG																CMDARG
0xc	CMDR																CMDSUSPEND	BOOTEN	BOOTMODE	DTHOLD	CPSMEN	WAITPEND	WAITINT	WAITRESP		CMDSTOP	CMDTRANS	CMDINDEX
0x10	RESPCMDR																											RESPCMD
0x14	RESP1	CARDSTATUS1																CARDSTATUS1
0x18	RESP2	CARDSTATUS2																CARDSTATUS2
0x1c	RESP3	CARDSTATUS3																CARDSTATUS3
0x20	RESP4	CARDSTATUS4																CARDSTATUS4
0x24	DTIMER	DATATIME																DATATIME
0x28	DLENR								DATALENGTH									DATALENGTH
0x2c	DCTRL																			FIFORST	BOOTACKEN	SDIOEN	RWMOD	RWSTOP	RWSTART	DBLOCKSIZE				DTMODE		DTDIR	DTEN
0x30	DCNTR								DATACOUNT									DATACOUNT
0x34	STAR				IDMABTC	IDMATE	CKSTOP	VSWEND	ACKTIMEOUT	ACKFAIL	SDIOIT	BUSYD0END	BUSYD0	RXFIFOE	TXFIFOE	RXFIFOF	TXFIFOF	RXFIFOHF	TXFIFOHE	CPSMACT	DPSMACT	DABORT	DBCKEND	DHOLD	DATAEND	CMDSENT	CMDREND	RXOVERR	TXUNDERR	DTIMEOUT	CTIMEOUT	DCRCFAIL	CCRCFAIL
0x38	ICR				IDMABTCC	IDMATEC	CKSTOPC	VSWENDC	ACKTIMEOUTC	ACKFAILC	SDIOITC	BUSYD0ENDC										DABORTC	DBCKENDC	DHOLDC	DATAENDC	CMDSENTC	CMDRENDC	RXOVERRC	TXUNDERRC	DTIMEOUTC	CTIMEOUTC	DCRCFAILC	CCRCFAILC
0x3c	MASKR				IDMABTCIE		CKSTOPIE	VSWENDIE	ACKTIMEOUTIE	ACKFAILIE	SDIOITIE	BUSYD0ENDIE			TXFIFOEIE	RXFIFOFIE		RXFIFOHFIE	TXFIFOHEIE			DABORTIE	DBCKENDIE	DHOLDIE	DATAENDIE	CMDSENTIE	CMDRENDIE	RXOVERRIE	TXUNDERRIE	DTIMEOUTIE	CTIMEOUTIE	DCRCFAILIE	CCRCFAILIE
0x40	ACKTIMER								ACKTIME									ACKTIME
0x50	SDMMC_IDMACTRLR																															IDMABMODE	IDMAEN
0x54	SDMMC_IDMABSIZER																IDMABNDT	IDMABNDT
0x58	SDMMC_IDMABASER	IDMABASE																IDMABASE
0x64	SDMMC_IDMALAR	ULA	ULS	ABR														IDMALA
0x68	SDMMC_IDMABAR	IDMABA																IDMABA
0x80	FIFOR0	FIFODATA																FIFODATA
0x84	FIFOR1	FIFODATA																FIFODATA
0x88	FIFOR2	FIFODATA																FIFODATA
0x8c	FIFOR3	FIFODATA																FIFODATA
0x90	FIFOR4	FIFODATA																FIFODATA
0x94	FIFOR5	FIFODATA																FIFODATA
0x98	FIFOR6	FIFODATA																FIFODATA
0x9c	FIFOR7	FIFODATA																FIFODATA
0xa0	FIFOR8	FIFODATA																FIFODATA
0xa4	FIFOR9	FIFODATA																FIFODATA
0xa8	FIFOR10	FIFODATA																FIFODATA
0xac	FIFOR11	FIFODATA																FIFODATA
0xb0	FIFOR12	FIFODATA																FIFODATA
0xb4	FIFOR13	FIFODATA																FIFODATA
0xb8	FIFOR14	FIFODATA																FIFODATA
0xbc	FIFOR15	FIFODATA																FIFODATA

Toggle registers

POWER

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DIRPOL rw	VSWITCHEN rw	VSWITCH rw	PWRCTRL rw

Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits.

VSWITCH

Bit 2: Voltage switch sequence start.

VSWITCHEN

Bit 3: Voltage switch procedure enable.

DIRPOL

Bit 4: Data and command direction signals polarity selection.

CLKCR

clock control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SELCLKRX rw		BUSSPEED rw	DDR rw	HWFC_EN rw	NEGEDGE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WIDBUS rw			PWRSAV rw			CLKDIV rw

Toggle fields

CLKDIV

Bits 0-9: Clock divide factor.

PWRSAV

Bit 12: Power saving configuration bit.

WIDBUS

Bits 14-15: Wide bus mode enable bit.

NEGEDGE

Bit 16: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 17: HW Flow Control enable.

DDR

Bit 18: Data rate signaling selection.

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104.

SELCLKRX

Bits 20-21: Receive clock selection.

ARGR

argument register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDARG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDARG rw

Toggle fields

CMDARG

Bits 0-31: Command argument.

CMDR

command register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															CMDSUSPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BOOTEN rw	BOOTMODE rw	DTHOLD rw	CPSMEN rw	WAITPEND rw	WAITINT rw	WAITRESP rw		CMDSTOP rw	CMDTRANS rw	CMDINDEX rw

Toggle fields

CMDINDEX

Bits 0-5: Command index.

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM.

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM.

WAITRESP

Bits 8-9: Wait for response bits.

WAITINT

Bit 10: CPSM waits for interrupt request.

WAITPEND

Bit 11: CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM.

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit.

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM.

BOOTMODE

Bit 14: Select the boot mode procedure to be used.

BOOTEN

Bit 15: Enable boot mode procedure.

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end.

RESPCMDR

command response register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RESPCMD r

Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS1 r

Toggle fields

CARDSTATUS1

Bits 0-31: CARDSTATUS1.

RESP2

response 2 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS2 r

Toggle fields

CARDSTATUS2

Bits 0-31: CARDSTATUS2.

RESP3

response 3 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS3 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS3 r

Toggle fields

CARDSTATUS3

Bits 0-31: CARDSTATUS3.

RESP4

response 4 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS4 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS4 r

Toggle fields

CARDSTATUS4

Bits 0-31: CARDSTATUS4.

DTIMER

data timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATATIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATATIME rw

Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period.

DLENR

data length register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DATALENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATALENGTH rw

Toggle fields

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		FIFORST rw	BOOTACKEN rw	SDIOEN rw	RWMOD rw	RWSTOP rw	RWSTART rw	DBLOCKSIZE rw				DTMODE rw		DTDIR rw	DTEN rw

Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bits 2-3: Data transfer mode selection.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment.

FIFORST

Bit 13: FIFO reset, will flush any remaining data.

DCNTR

data counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DATACOUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATACOUNT r

Toggle fields

DATACOUNT

Bits 0-24: Data count value.

STAR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			IDMABTC r	IDMATE r	CKSTOP r	VSWEND r	ACKTIMEOUT r	ACKFAIL r	SDIOIT r	BUSYD0END r	BUSYD0 r	RXFIFOE r	TXFIFOE r	RXFIFOF r	TXFIFOF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFIFOHF r	TXFIFOHE r	CPSMACT r	DPSMACT r	DABORT r	DBCKEND r	DHOLD r	DATAEND r	CMDSENT r	CMDREND r	RXOVERR r	TXUNDERR r	DTIMEOUT r	CTIMEOUT r	DCRCFAIL r	CCRCFAIL r

Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error (masked by hardware when IDMA is enabled).

RXOVERR

Bit 5: Received FIFO overrun error (masked by hardware when IDMA is enabled).

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data transfer ended correctly.

DHOLD

Bit 9: Data transfer Hold.

DBCKEND

Bit 10: Data block sent/received.

DABORT

Bit 11: Data transfer aborted by CMD12.

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state.

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state.

TXFIFOHE

Bit 14: Transmit FIFO half empty.

RXFIFOHF

Bit 15: Receive FIFO half full.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response.

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected.

SDIOIT

Bit 22: SDIO interrupt received.

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail).

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout.

VSWEND

Bit 25: Voltage switch critical timing section completion.

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure.

IDMATE

Bit 27: IDMA transfer error.

IDMABTC

Bit 28: IDMA buffer transfer complete.

ICR

interrupt clear register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			IDMABTCC rw	IDMATEC rw	CKSTOPC rw	VSWENDC rw	ACKTIMEOUTC rw	ACKFAILC rw	SDIOITC rw	BUSYD0ENDC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DABORTC rw	DBCKENDC rw	DHOLDC rw	DATAENDC rw	CMDSENTC rw	CMDRENDC rw	RXOVERRC rw	TXUNDERRC rw	DTIMEOUTC rw	CTIMEOUTC rw	DCRCFAILC rw	CCRCFAILC rw

Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

DHOLDC

Bit 9: DHOLD flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

DABORTC

Bit 11: DABORT flag clear bit.

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

ACKFAILC

Bit 23: ACKFAIL flag clear bit.

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit.

VSWENDC

Bit 25: VSWEND flag clear bit.

CKSTOPC

Bit 26: CKSTOP flag clear bit.

IDMATEC

Bit 27: IDMA transfer error clear bit.

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit.

MASKR

mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			IDMABTCIE rw		CKSTOPIE rw	VSWENDIE rw	ACKTIMEOUTIE rw	ACKFAILIE rw	SDIOITIE rw	BUSYD0ENDIE rw			TXFIFOEIE rw	RXFIFOFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFIFOHFIE rw	TXFIFOHEIE rw			DABORTIE rw	DBCKENDIE rw	DHOLDIE rw	DATAENDIE rw	CMDSENTIE rw	CMDRENDIE rw	RXOVERRIE rw	TXUNDERRIE rw	DTIMEOUTIE rw	CTIMEOUTIE rw	DCRCFAILIE rw	CCRCFAILIE rw

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

DHOLDIE

Bit 9: Data hold interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

DABORTIE

Bit 11: Data transfer aborted interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable.

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable.

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable.

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable.

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable.

ACKTIMER

acknowledgment timer register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ACKTIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACKTIME rw

Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period.

SDMMC_IDMACTRLR

DMA control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														IDMABMODE rw	IDMAEN rw

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ULA rw	ULS rw	ABR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDMALA rw

Toggle fields

IDMALA

Bits 2-15: Acknowledge linked list buffer ready.

ABR

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	22	21	20	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1														IOLOCK	TCRCINI	RCRCINI	CRC33_17	SSI	HDDIR	CSUSP	CSTART	MASRX								SPE
0x4	CR2															TSIZE
0x8	CFG1	BPASS	MBR							CRCEN		CRCSIZE				TXDMAEN	RXDMAEN					UDRCFG	FTHVL
0xc	CFG2	AFCNTR	SSOM	SSOE	SSIOP	SSM	CPOL	CPHA	LSBFRST	MASTER	SP			COMM		IOSWP	RDIOP	RDIMM						MIDI				MSSI
0x10	IER																					MODFIE	TIFREIE	CRCEIE	OVRIE	UDRIE	TXTFIE	EOTIE	DPXPIE	TXPIE	RXPIE
0x14	SR	CTSIZE														RXWNE	RXPLVL		TXC	SUSP		MODF	TIFRE	CRCE	OVR	UDR	TXTF	EOT	DXP	TXP	RXP
0x18	IFCR																			SUSPC		MODFC	TIFREC	CRCEC	OVRC	UDRC	TXTFC	EOTC
0x1c	AUTOCR										TRIGEN	TRIGPOL	TRIGSEL
0x20	TXDR	TXDR														TXDR
0x30	RXDR	RXDR														RXDR
0x40	CRCPOLY	CRCPOLY														CRCPOLY
0x44	TXCRC	TXCRC														TXCRC
0x48	RXCRC	RXCRC														RXCRC
0x4c	UDRDR	UDRDR														UDRDR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IOLOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCRCINI rw	RCRCINI rw	CRC33_17 rw	SSI rw	HDDIR rw	CSUSP w	CSTART rw	MASRX rw								SPE rw

Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIZE rw

Toggle fields

TSIZE

Bits 0-15: TSIZE.

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BPASS rw	MBR rw								CRCEN rw		CRCSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDMAEN rw	RXDMAEN rw					UDRCFG rw	FTHVL rw

Toggle fields

FTHVL

Bits 5-8: threshold level.

UDRCFG

Bit 9: Behavior of slave transmitter at underrun condition.

RXDMAEN

Bit 14: Rx DMA stream enable.

TXDMAEN

Bit 15: Tx DMA stream enable.

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

CRCEN

Bit 22: Hardware CRC computation enable.

MBR

Bits 28-30: Master baud rate.

BPASS

Bit 31: BPASS.

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFCNTR rw	SSOM rw	SSOE rw	SSIOP rw		SSM rw	CPOL rw	CPHA rw	LSBFRST rw	MASTER rw	SP rw			COMM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOSWP rw	RDIOP rw	RDIMM rw						MIDI rw				MSSI rw

Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

MIDI

Bits 4-7: Master Inter-Data Idleness.

RDIMM

Bit 13: RDIMM.

RDIOP

Bit 14: RDIOP.

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

COMM

Bits 17-18: SPI Communication Mode.

SP

Bits 19-21: Serial Protocol.

MASTER

Bit 22: SPI Master.

LSBFRST

Bit 23: Data frame format.

CPHA

Bit 24: Clock phase.

CPOL

Bit 25: Clock polarity.

SSM

Bit 26: Software management of SS signal input.

SSIOP

Bit 28: SS input/output polarity.

SSOE

Bit 29: SS output enable.

SSOM

Bit 30: SS output management in master mode.

AFCNTR

Bit 31: Alternate function GPIOs control.

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODFIE rw	TIFREIE rw	CRCEIE rw	OVRIE rw	UDRIE rw	TXTFIE rw	EOTIE rw	DPXPIE rw	TXPIE rw	RXPIE rw

Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

TXPIE

Bit 1: TXP interrupt enable.

DPXPIE

Bit 2: DXP interrupt enabled.

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

TXTFIE

Bit 4: TXTFIE interrupt enable.

UDRIE

Bit 5: UDR interrupt enable.

OVRIE

Bit 6: OVR interrupt enable.

CRCEIE

Bit 7: CRC Interrupt enable.

TIFREIE

Bit 8: TIFRE interrupt enable.

MODFIE

Bit 9: Mode Fault interrupt enable.

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTSIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXWNE r	RXPLVL r		TXC r	SUSP r		MODF r	TIFRE r	CRCE r	OVR r	UDR r	TXTF r	EOT r	DXP r	TXP r	RXP r

Toggle fields

RXP

Bit 0: Rx-Packet available.

TXP

Bit 1: Tx-Packet space available.

DXP

Bit 2: Duplex Packet.

EOT

Bit 3: End Of Transfer.

TXTF

Bit 4: Transmission Transfer Filled.

UDR

Bit 5: Underrun at slave transmission mode.

OVR

Bit 6: Overrun.

CRCE

Bit 7: CRC Error.

TIFRE

Bit 8: TI frame format error.

MODF

Bit 9: Mode Fault.

SUSP

Bit 11: SUSPend.

TXC

Bit 12: TxFIFO transmission complete.

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

RXWNE

Bit 15: RxFIFO Word Not Empty.

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SUSPC w		MODFC w	TIFREC w	CRCEC w	OVRC w	UDRC w	TXTFC w	EOTC w

Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

UDRC

Bit 5: Underrun flag clear.

OVRC

Bit 6: Overrun flag clear.

CRCEC

Bit 7: CRC Error flag clear.

TIFREC

Bit 8: TI frame format error flag clear.

MODFC

Bit 9: Mode Fault flag clear.

SUSPC

Bit 11: SUSPend flag clear.

AUTOCR

SPI autonomous mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TRIGSEL

Bits 16-19: TRIGSEL.

TRIGPOL

Bit 20: TRIGPOL.

TRIGEN

Bit 21: TRIGEN.

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXDR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDR w

Toggle fields

TXDR

Bits 0-31: Transmit data register.

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDR r

Toggle fields

RXDR

Bits 0-31: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRCPOLY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UDRDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UDRDR rw

Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

SEC_SPI2

0x50003800: Serial peripheral interface

18/77 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	22	21	20	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1														IOLOCK	TCRCINI	RCRCINI	CRC33_17	SSI	HDDIR	CSUSP	CSTART	MASRX								SPE
0x4	CR2															TSIZE
0x8	CFG1	BPASS	MBR							CRCEN		CRCSIZE				TXDMAEN	RXDMAEN					UDRCFG	FTHVL
0xc	CFG2	AFCNTR	SSOM	SSOE	SSIOP	SSM	CPOL	CPHA	LSBFRST	MASTER	SP			COMM		IOSWP	RDIOP	RDIMM						MIDI				MSSI
0x10	IER																					MODFIE	TIFREIE	CRCEIE	OVRIE	UDRIE	TXTFIE	EOTIE	DPXPIE	TXPIE	RXPIE
0x14	SR	CTSIZE														RXWNE	RXPLVL		TXC	SUSP		MODF	TIFRE	CRCE	OVR	UDR	TXTF	EOT	DXP	TXP	RXP
0x18	IFCR																			SUSPC		MODFC	TIFREC	CRCEC	OVRC	UDRC	TXTFC	EOTC
0x1c	AUTOCR										TRIGEN	TRIGPOL	TRIGSEL
0x20	TXDR	TXDR														TXDR
0x30	RXDR	RXDR														RXDR
0x40	CRCPOLY	CRCPOLY														CRCPOLY
0x44	TXCRC	TXCRC														TXCRC
0x48	RXCRC	RXCRC														RXCRC
0x4c	UDRDR	UDRDR														UDRDR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IOLOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCRCINI rw	RCRCINI rw	CRC33_17 rw	SSI rw	HDDIR rw	CSUSP w	CSTART rw	MASRX rw								SPE rw

Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIZE rw

Toggle fields

TSIZE

Bits 0-15: TSIZE.

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BPASS rw	MBR rw								CRCEN rw		CRCSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDMAEN rw	RXDMAEN rw					UDRCFG rw	FTHVL rw

Toggle fields

FTHVL

Bits 5-8: threshold level.

UDRCFG

Bit 9: Behavior of slave transmitter at underrun condition.

RXDMAEN

Bit 14: Rx DMA stream enable.

TXDMAEN

Bit 15: Tx DMA stream enable.

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

CRCEN

Bit 22: Hardware CRC computation enable.

MBR

Bits 28-30: Master baud rate.

BPASS

Bit 31: BPASS.

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFCNTR rw	SSOM rw	SSOE rw	SSIOP rw		SSM rw	CPOL rw	CPHA rw	LSBFRST rw	MASTER rw	SP rw			COMM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOSWP rw	RDIOP rw	RDIMM rw						MIDI rw				MSSI rw

Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

MIDI

Bits 4-7: Master Inter-Data Idleness.

RDIMM

Bit 13: RDIMM.

RDIOP

Bit 14: RDIOP.

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

COMM

Bits 17-18: SPI Communication Mode.

SP

Bits 19-21: Serial Protocol.

MASTER

Bit 22: SPI Master.

LSBFRST

Bit 23: Data frame format.

CPHA

Bit 24: Clock phase.

CPOL

Bit 25: Clock polarity.

SSM

Bit 26: Software management of SS signal input.

SSIOP

Bit 28: SS input/output polarity.

SSOE

Bit 29: SS output enable.

SSOM

Bit 30: SS output management in master mode.

AFCNTR

Bit 31: Alternate function GPIOs control.

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODFIE rw	TIFREIE rw	CRCEIE rw	OVRIE rw	UDRIE rw	TXTFIE rw	EOTIE rw	DPXPIE rw	TXPIE rw	RXPIE rw

Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

TXPIE

Bit 1: TXP interrupt enable.

DPXPIE

Bit 2: DXP interrupt enabled.

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

TXTFIE

Bit 4: TXTFIE interrupt enable.

UDRIE

Bit 5: UDR interrupt enable.

OVRIE

Bit 6: OVR interrupt enable.

CRCEIE

Bit 7: CRC Interrupt enable.

TIFREIE

Bit 8: TIFRE interrupt enable.

MODFIE

Bit 9: Mode Fault interrupt enable.

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTSIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXWNE r	RXPLVL r		TXC r	SUSP r		MODF r	TIFRE r	CRCE r	OVR r	UDR r	TXTF r	EOT r	DXP r	TXP r	RXP r

Toggle fields

RXP

Bit 0: Rx-Packet available.

TXP

Bit 1: Tx-Packet space available.

DXP

Bit 2: Duplex Packet.

EOT

Bit 3: End Of Transfer.

TXTF

Bit 4: Transmission Transfer Filled.

UDR

Bit 5: Underrun at slave transmission mode.

OVR

Bit 6: Overrun.

CRCE

Bit 7: CRC Error.

TIFRE

Bit 8: TI frame format error.

MODF

Bit 9: Mode Fault.

SUSP

Bit 11: SUSPend.

TXC

Bit 12: TxFIFO transmission complete.

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

RXWNE

Bit 15: RxFIFO Word Not Empty.

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SUSPC w		MODFC w	TIFREC w	CRCEC w	OVRC w	UDRC w	TXTFC w	EOTC w

Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

UDRC

Bit 5: Underrun flag clear.

OVRC

Bit 6: Overrun flag clear.

CRCEC

Bit 7: CRC Error flag clear.

TIFREC

Bit 8: TI frame format error flag clear.

MODFC

Bit 9: Mode Fault flag clear.

SUSPC

Bit 11: SUSPend flag clear.

AUTOCR

SPI autonomous mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TRIGSEL

Bits 16-19: TRIGSEL.

TRIGPOL

Bit 20: TRIGPOL.

TRIGEN

Bit 21: TRIGEN.

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXDR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDR w

Toggle fields

TXDR

Bits 0-31: Transmit data register.

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDR r

Toggle fields

RXDR

Bits 0-31: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRCPOLY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UDRDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UDRDR rw

Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

SEC_SPI3

0x56002000: Serial peripheral interface

18/77 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	22	21	20	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1														IOLOCK	TCRCINI	RCRCINI	CRC33_17	SSI	HDDIR	CSUSP	CSTART	MASRX								SPE
0x4	CR2															TSIZE
0x8	CFG1	BPASS	MBR							CRCEN		CRCSIZE				TXDMAEN	RXDMAEN					UDRCFG	FTHVL
0xc	CFG2	AFCNTR	SSOM	SSOE	SSIOP	SSM	CPOL	CPHA	LSBFRST	MASTER	SP			COMM		IOSWP	RDIOP	RDIMM						MIDI				MSSI
0x10	IER																					MODFIE	TIFREIE	CRCEIE	OVRIE	UDRIE	TXTFIE	EOTIE	DPXPIE	TXPIE	RXPIE
0x14	SR	CTSIZE														RXWNE	RXPLVL		TXC	SUSP		MODF	TIFRE	CRCE	OVR	UDR	TXTF	EOT	DXP	TXP	RXP
0x18	IFCR																			SUSPC		MODFC	TIFREC	CRCEC	OVRC	UDRC	TXTFC	EOTC
0x1c	AUTOCR										TRIGEN	TRIGPOL	TRIGSEL
0x20	TXDR	TXDR														TXDR
0x30	RXDR	RXDR														RXDR
0x40	CRCPOLY	CRCPOLY														CRCPOLY
0x44	TXCRC	TXCRC														TXCRC
0x48	RXCRC	RXCRC														RXCRC
0x4c	UDRDR	UDRDR														UDRDR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IOLOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCRCINI rw	RCRCINI rw	CRC33_17 rw	SSI rw	HDDIR rw	CSUSP w	CSTART rw	MASRX rw								SPE rw

Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIZE rw

Toggle fields

TSIZE

Bits 0-15: TSIZE.

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BPASS rw	MBR rw								CRCEN rw		CRCSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDMAEN rw	RXDMAEN rw					UDRCFG rw	FTHVL rw

Toggle fields

FTHVL

Bits 5-8: threshold level.

UDRCFG

Bit 9: Behavior of slave transmitter at underrun condition.

RXDMAEN

Bit 14: Rx DMA stream enable.

TXDMAEN

Bit 15: Tx DMA stream enable.

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

CRCEN

Bit 22: Hardware CRC computation enable.

MBR

Bits 28-30: Master baud rate.

BPASS

Bit 31: BPASS.

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFCNTR rw	SSOM rw	SSOE rw	SSIOP rw		SSM rw	CPOL rw	CPHA rw	LSBFRST rw	MASTER rw	SP rw			COMM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOSWP rw	RDIOP rw	RDIMM rw						MIDI rw				MSSI rw

Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

MIDI

Bits 4-7: Master Inter-Data Idleness.

RDIMM

Bit 13: RDIMM.

RDIOP

Bit 14: RDIOP.

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

COMM

Bits 17-18: SPI Communication Mode.

SP

Bits 19-21: Serial Protocol.

MASTER

Bit 22: SPI Master.

LSBFRST

Bit 23: Data frame format.

CPHA

Bit 24: Clock phase.

CPOL

Bit 25: Clock polarity.

SSM

Bit 26: Software management of SS signal input.

SSIOP

Bit 28: SS input/output polarity.

SSOE

Bit 29: SS output enable.

SSOM

Bit 30: SS output management in master mode.

AFCNTR

Bit 31: Alternate function GPIOs control.

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODFIE rw	TIFREIE rw	CRCEIE rw	OVRIE rw	UDRIE rw	TXTFIE rw	EOTIE rw	DPXPIE rw	TXPIE rw	RXPIE rw

Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

TXPIE

Bit 1: TXP interrupt enable.

DPXPIE

Bit 2: DXP interrupt enabled.

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

TXTFIE

Bit 4: TXTFIE interrupt enable.

UDRIE

Bit 5: UDR interrupt enable.

OVRIE

Bit 6: OVR interrupt enable.

CRCEIE

Bit 7: CRC Interrupt enable.

TIFREIE

Bit 8: TIFRE interrupt enable.

MODFIE

Bit 9: Mode Fault interrupt enable.

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTSIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXWNE r	RXPLVL r		TXC r	SUSP r		MODF r	TIFRE r	CRCE r	OVR r	UDR r	TXTF r	EOT r	DXP r	TXP r	RXP r

Toggle fields

RXP

Bit 0: Rx-Packet available.

TXP

Bit 1: Tx-Packet space available.

DXP

Bit 2: Duplex Packet.

EOT

Bit 3: End Of Transfer.

TXTF

Bit 4: Transmission Transfer Filled.

UDR

Bit 5: Underrun at slave transmission mode.

OVR

Bit 6: Overrun.

CRCE

Bit 7: CRC Error.

TIFRE

Bit 8: TI frame format error.

MODF

Bit 9: Mode Fault.

SUSP

Bit 11: SUSPend.

TXC

Bit 12: TxFIFO transmission complete.

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

RXWNE

Bit 15: RxFIFO Word Not Empty.

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SUSPC w		MODFC w	TIFREC w	CRCEC w	OVRC w	UDRC w	TXTFC w	EOTC w

Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

UDRC

Bit 5: Underrun flag clear.

OVRC

Bit 6: Overrun flag clear.

CRCEC

Bit 7: CRC Error flag clear.

TIFREC

Bit 8: TI frame format error flag clear.

MODFC

Bit 9: Mode Fault flag clear.

SUSPC

Bit 11: SUSPend flag clear.

AUTOCR

SPI autonomous mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TRIGSEL

Bits 16-19: TRIGSEL.

TRIGPOL

Bit 20: TRIGPOL.

TRIGEN

Bit 21: TRIGEN.

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXDR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDR w

Toggle fields

TXDR

Bits 0-31: Transmit data register.

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDR r

Toggle fields

RXDR

Bits 0-31: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRCPOLY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UDRDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UDRDR rw

Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

SEC_SYSCFG

0x56000400: System configuration controller

9/44 fields covered.

Toggle register map

Offset	Name	25	23	19	18	17	16	15	11	10	9	8	7	5	4	3	2	1	0
0x0	SECCFGR															FPUSEC		CLASSBSEC	SYSCFGSEC
0x4	CFGR1	ENDCAP		PB9_FMP	PB8_FMP	PB7_FMP	PB6_FMP				ANASWVDD	BOOSTEN
0x8	FPUIMR													FPU_IE
0xc	CNSLCKR																	LOCKNSMPU	LOCKNSVTOR
0x10	CSLOCKR																LOCKSAU	LOCKSMPU	LOCKSVTAIRCR
0x14	CFGR2															ECCL	PVDL	SPL	CLL
0x18	MESR						IPMEE												MCLR
0x1c	CCCSR									RDY3	RDY2	RDY1		CS3	EN3	CS2	EN2	CS1	EN1
0x20	CCVR		PCV3	NCV3				PCV2	NCV2				PCV1			NCV1
0x24	CCCR		PCC3	NCC3				PCC2	NCC2				PCC1			NCC1
0x2c	RSSCMDR							RSSCMD

Toggle registers

SECCFGR

SYSCFG secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												FPUSEC rw		CLASSBSEC rw	SYSCFGSEC rw

Toggle fields

SYSCFGSEC

Bit 0: SYSCFG clock control security.

CLASSBSEC

Bit 1: CLASSBSEC.

FPUSEC

Bit 3: FPUSEC.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						ENDCAP rw						PB9_FMP rw	PB8_FMP rw	PB7_FMP rw	PB6_FMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						ANASWVDD rw	BOOSTEN rw

Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

ANASWVDD

Bit 9: GPIO analog switch control voltage selection.

PB6_FMP

Bit 16: PB6_FMP.

PB7_FMP

Bit 17: PB7_FMP.

PB8_FMP

Bit 18: PB8_FMP.

PB9_FMP

Bit 19: PB9_FMP.

ENDCAP

Bits 24-25: ENDCAP.

FPUIMR

FPU interrupt mask register

Offset: 0x8, size: 32, reset: 0x0000001F, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FPU_IE rw

Toggle fields

FPU_IE

Bits 0-5: Floating point unit interrupts enable bits.

CNSLCKR

SYSCFG CPU non-secure lock register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LOCKNSMPU rw	LOCKNSVTOR rw

Toggle fields

LOCKNSVTOR

Bit 0: VTOR_NS register lock.

LOCKNSMPU

Bit 1: Non-secure MPU registers lock.

CSLOCKR

SYSCFG CPU secure lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													LOCKSAU rw	LOCKSMPU rw	LOCKSVTAIRCR rw

Toggle fields

LOCKSVTAIRCR

Bit 0: LOCKSVTAIRCR.

LOCKSMPU

Bit 1: LOCKSMPU.

LOCKSAU

Bit 2: LOCKSAU.

CFGR2

configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ECCL rw	PVDL rw	SPL rw	CLL rw

Toggle fields

CLL

Bit 0: LOCKUP (hardfault) output enable bit.

SPL

Bit 1: SRAM ECC lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

MESR

memory erase status register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IPMEE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															MCLR rw

Toggle fields

MCLR

Bit 0: MCLR.

IPMEE

Bit 16: IPMEE.

CCCSR

compensation cell control/status register

Offset: 0x1c, size: 32, reset: 0x0000000A, access: Unspecified

3/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					RDY3 r	RDY2 r	RDY1 r			CS3 rw	EN3 rw	CS2 rw	EN2 rw	CS1 rw	EN1 rw

Toggle fields

EN1

Bit 0: EN1.

CS1

Bit 1: CS1.

EN2

Bit 2: EN2.

CS2

Bit 3: CS2.

EN3

Bit 4: EN3.

CS3

Bit 5: CS3.

RDY1

Bit 8: RDY1.

RDY2

Bit 9: RDY2.

RDY3

Bit 10: RDY3.

CCVR

compensation cell value register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PCV3 r				NCV3 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCV2 r				NCV2 r				PCV1 r				NCV1 r

Toggle fields

NCV1

Bits 0-3: NCV1.

PCV1

Bits 4-7: PCV1.

NCV2

Bits 8-11: NCV2.

PCV2

Bits 12-15: PCV2.

NCV3

Bits 16-19: NCV3.

PCV3

Bits 20-23: PCV3.

CCCR

compensation cell code register

Offset: 0x24, size: 32, reset: 0x00007878, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PCC3 rw				NCC3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCC2 rw				NCC2 rw				PCC1 rw				NCC1 rw

Toggle fields

NCC1

Bits 0-3: NCC1.

PCC1

Bits 4-7: PCC1.

NCC2

Bits 8-11: NCC2.

PCC2

Bits 12-15: PCC2.

NCC3

Bits 16-19: NCC3.

PCC3

Bits 20-23: PCC3.

RSSCMDR

RSS command register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSSCMD rw

Toggle fields

RSSCMD

Bits 0-15: RSS commands.

SEC_TAMP

0x56007c00: Tamper and backup registers

61/221 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1				ITAMP13E	ITAMP12E	ITAMP11E		ITAMP9E	ITAMP8E	ITAMP7E	ITAMP6E	ITAMP5E	ITAMP3E	ITAMP2E	ITAMP1E									TAMP8E	TAMP7E	TAMP6E	TAMP5E	TAMP4E	TAMP3E	TAMP2E	TAMP1E
0x4	CR2	TAMP8TRG	TAMP7TRG	TAMP6TRG	TAMP5TRG	TAMP4TRG	TAMP3TRG	TAMP2TRG	TAMP1TRG	BKERASE	BKBLOCK			TAMP3MSK	TAMP2MSK	TAMP1MSK									TAMP8NOER	TAMP7NOER	TAMP6NOER	TAMP5NOER	TAMP4NOER	TAMP3NOER	TAMP2NOER	TAMP1NOER
0x8	CR3																			ITAMP13NOER	ITAMP12NOER	ITAMP11NOER		ITAMP9NOER	TAMP8NOER	TAMP7NOER	TAMP6NOER	TAMP5NOER		ITAMP3NOER	ITAMP2NOER	ITAMP1NOER
0xc	FLTCR																								TAMPPUDIS	TAMPPRCH		TAMPFLT		TAMPFREQ
0x10	ATCR1	FLTEN	ATOSHARE				ATPER							ATCKSEL			ATOSEL4		ATOSEL3		ATOSEL2		ATOSEL1		TAMP8AM	TAMP7AM	TAMP6AM	TAMP5AM	TAMP4AM	TAMP3AM	TAMP2AM	TAMP1AM
0x14	ATSEEDR	SEED															SEED
0x18	ATOR																INITS	SEEDF							PRNG
0x1c	ATCR2	ATOSEL8			ATOSEL7			ATOSEL6			ATOSEL5			ATOSEL4		ATOSEL3	ATOSEL3		ATOSEL2			ATOSEL1
0x20	SECCFGR	TAMPSEC	BHKLOCK							BKPWSEC							CNT1SEC								BKPRWSEC
0x24	PRIVCR	TAMPPRIV	BKPWPRIV	BKPRWPRIV													CNT1PRIV
0x2c	IER				ITAMP13IE	ITAMP12IE	ITAMP11IE		ITAMP9IE	ITAMP8IE	ITAMP7IE	ITAMP6IE	ITAMP5IE	ITAMP3IE	ITAMP2IE	ITAMP1IE									TAMP8IE	TAMP7IE	TAMP6IE	TAMP5IE	TAMP4IE	TAMP3IE	TAMP2IE	TAMP1IE
0x30	SR				ITAMP13IE	ITAMP12F	CITAMP11F		ITAMP9F	ITAMP8F	ITAMP7F	ITAMP6F	ITAMP5F	ITAMP3F	CITAMP2F	CITAMP1F									TAMP8F	TAMP7F	TAMP6F	TAMP5F	TAMP4F	TAMP3F	TAMP2F	TAMP1F
0x34	MISR				ITAMP13MF	ITAMP12MF	ITAMP11MF		ITAMP9MF	ITAMP8MF	ITAMP7MF	ITAMP6MF	ITAMP5MF	ITAMP3MF	ITAMP2MF	ITAMP1MF									TAMP8MF	TAMP7MF	TAMP6MF	TAMP5MF	TAMP4MF	TAMP3MF	TAMP2MF	TAMP1MF
0x38	SMISR				ITAMP13MF	ITAMP12MF	ITAMP11MF		ITAMP9MF	ITAMP8MF	ITAMP7MF	ITAMP6MF	ITAMP5MF	ITAMP3MF	ITAMP2MF	ITAMP1MF									TAMP8MF	TAMP7MF	TAMP6MF	TAMP5MF	TAMP4MF	TAMP3MF	TAMP2MF	TAMP1MF
0x3c	SCR				CITAMP13F	CITAMP12F	CITAMP11F		CITAMP9F	CITAMP8F_bit23	CITAMP7F_bit22	CITAMP6F_bit21	CITAMP5F	CITAMP3F	CITAMP2F	CITAMP1F									CITAMP8F	CITAMP7F	CTAMP6F	CTAMP5F	CTAMP4F	CTAMP3F	CTAMP2F	CTAMP1F
0x40	COUNT1R	COUNT															COUNT
0x54	ERCFGR																															ERCFG0
0x100	BKP0R	BKP															BKP
0x104	BKP1R	BKP															BKP
0x108	BKP2R	BKP															BKP
0x10c	BKP3R	BKP															BKP
0x110	BKP4R	BKP															BKP
0x114	BKP5R	BKP															BKP
0x118	BKP6R	BKP															BKP
0x11c	BKP7R	BKP															BKP
0x120	BKP8R	BKP															BKP
0x124	BKP9R	BKP															BKP
0x128	BKP10R	BKP															BKP
0x12c	BKP11R	BKP															BKP
0x130	BKP12R	BKP															BKP
0x134	BKP13R	BKP															BKP
0x138	BKP14R	BKP															BKP
0x13c	BKP15R	BKP															BKP
0x140	BKP16R	BKP															BKP
0x144	BKP17R	BKP															BKP
0x148	BKP18R	BKP															BKP
0x14c	BKP19R	BKP															BKP
0x150	BKP20R	BKP															BKP
0x154	BKP21R	BKP															BKP
0x158	BKP22R	BKP															BKP
0x15c	BKP23R	BKP															BKP
0x160	BKP24R	BKP															BKP
0x164	BKP25R	BKP															BKP
0x168	BKP26R	BKP															BKP
0x16c	BKP27R	BKP															BKP
0x170	BKP28R	BKP															BKP
0x174	BKP29R	BKP															BKP
0x178	BKP30R	BKP															BKP
0x17c	BKP31R	BKP															BKP

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13E rw	ITAMP12E rw	ITAMP11E rw		ITAMP9E rw	ITAMP8E rw	ITAMP7E rw	ITAMP6E rw	ITAMP5E rw		ITAMP3E rw	ITAMP2E rw	ITAMP1E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8E rw	TAMP7E rw	TAMP6E rw	TAMP5E rw	TAMP4E rw	TAMP3E rw	TAMP2E rw	TAMP1E rw

Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

TAMP4E

Bit 3: TAMP4E.

TAMP5E

Bit 4: TAMP5E.

TAMP6E

Bit 5: TAMP6E.

TAMP7E

Bit 6: TAMP7E.

TAMP8E

Bit 7: TAMP8E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP6E

Bit 21: ITAMP6E.

ITAMP7E

Bit 22: ITAMP7E.

ITAMP8E

Bit 23: ITAMP8E.

ITAMP9E

Bit 24: ITAMP9E.

ITAMP11E

Bit 26: TAMP1E.

ITAMP12E

Bit 27: ITAMP12E.

ITAMP13E

Bit 28: ITAMP13E.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TAMP8TRG rw	TAMP7TRG rw	TAMP6TRG rw	TAMP5TRG rw	TAMP4TRG rw	TAMP3TRG rw	TAMP2TRG rw	TAMP1TRG rw	BKERASE rw	BKBLOCK rw				TAMP3MSK rw	TAMP2MSK rw	TAMP1MSK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8NOER rw	TAMP7NOER rw	TAMP6NOER rw	TAMP5NOER rw	TAMP4NOER rw	TAMP3NOER rw	TAMP2NOER rw	TAMP1NOER rw

Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP4NOER

Bit 3: TAMP4NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKBLOCK

Bit 22: BKBLOCK.

BKERASE

Bit 23: BKERASE.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

TAMP4TRG

Bit 27: TAMP4TRG.

TAMP5TRG

Bit 28: TAMP5TRG.

TAMP6TRG

Bit 29: TAMP6TRG.

TAMP7TRG

Bit 30: TAMP7TRG.

TAMP8TRG

Bit 31: TAMP8TRG.

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ITAMP13NOER rw	ITAMP12NOER rw	ITAMP11NOER rw		ITAMP9NOER rw	TAMP8NOER rw	TAMP7NOER rw	TAMP6NOER rw	TAMP5NOER rw		ITAMP3NOER rw	ITAMP2NOER rw	ITAMP1NOER rw

Toggle fields

ITAMP1NOER

Bit 0: ITAMP1NOER.

ITAMP2NOER

Bit 1: ITAMP2NOER.

ITAMP3NOER

Bit 2: ITAMP3NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

ITAMP9NOER

Bit 8: ITAMP9NOER.

ITAMP11NOER

Bit 10: ITAMP11NOER.

ITAMP12NOER

Bit 11: ITAMP12NOER.

ITAMP13NOER

Bit 12: ITAMP13NOER.

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw

Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

TAMP active tamper control register

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FLTEN rw	ATOSHARE rw				ATPER rw								ATCKSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ATOSEL4 rw		ATOSEL3 rw		ATOSEL2 rw		ATOSEL1 rw		TAMP8AM rw	TAMP7AM rw	TAMP6AM rw	TAMP5AM rw	TAMP4AM rw	TAMP3AM rw	TAMP2AM rw	TAMP1AM rw

Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

TAMP4AM

Bit 3: TAMP4AM.

TAMP5AM

Bit 4: TAMP5AM.

TAMP6AM

Bit 5: TAMP6AM.

TAMP7AM

Bit 6: TAMP7AM.

TAMP8AM

Bit 7: TAMP8AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATOSEL4

Bits 14-15: ATOSEL4.

ATCKSEL

Bits 16-18: ATCKSEL.

ATPER

Bits 24-26: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: ATOSHARE.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEED rw

Toggle fields

SEED

Bits 0-31: SEED.

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INITS r	SEEDF r							PRNG r

Toggle fields

PRNG

Bits 0-7: PRNG.

SEEDF

Bit 14: SEEDF.

INITS

Bit 15: INITS.

ATCR2

TAMP active tamper control register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ATOSEL8 rw			ATOSEL7 rw			ATOSEL6 rw			ATOSEL5 rw				ATOSEL4 rw		ATOSEL3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ATOSEL3 rw		ATOSEL2 rw			ATOSEL1 rw

Toggle fields

ATOSEL1

Bits 8-10: ATOSEL1.

ATOSEL2

Bits 11-13: ATOSEL2.

ATOSEL3

Bits 14-16: ATOSEL3.

ATOSEL4

Bits 17-18: ATOSEL4.

ATOSEL5

Bits 20-22: ATOSEL5.

ATOSEL6

Bits 23-25: ATOSEL6.

ATOSEL7

Bits 26-28: ATOSEL7.

ATOSEL8

Bits 29-31: ATOSEL8.

SECCFGR

TAMP secure mode register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TAMPSEC rw	BHKLOCK rw							BKPWSEC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT1SEC rw								BKPRWSEC rw

Toggle fields

BKPRWSEC

Bits 0-7: BKPRWSEC.

CNT1SEC

Bit 15: CNT1SEC.

BKPWSEC

Bits 16-23: BKPWSEC.

BHKLOCK

Bit 30: BHKLOCK.

TAMPSEC

Bit 31: TAMPSEC.

PRIVCR

TAMP privilege mode control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TAMPPRIV rw	BKPWPRIV rw	BKPRWPRIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT1PRIV rw

Toggle fields

CNT1PRIV

Bit 15: CNT1PRIV.

BKPRWPRIV

Bit 29: BKPRWPRIV.

BKPWPRIV

Bit 30: BKPWPRIV.

TAMPPRIV

Bit 31: TAMPPRIV.

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13IE rw	ITAMP12IE rw	ITAMP11IE rw		ITAMP9IE rw	ITAMP8IE rw	ITAMP7IE rw	ITAMP6IE rw	ITAMP5IE rw		ITAMP3IE rw	ITAMP2IE rw	ITAMP1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8IE rw	TAMP7IE rw	TAMP6IE rw	TAMP5IE rw	TAMP4IE rw	TAMP3IE rw	TAMP2IE rw	TAMP1IE rw

Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

TAMP4IE

Bit 3: TAMP4IE.

TAMP5IE

Bit 4: TAMP5IE.

TAMP6IE

Bit 5: TAMP6IE.

TAMP7IE

Bit 6: TAMP7IE.

TAMP8IE

Bit 7: TAMP8IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP6IE

Bit 21: ITAMP6IE.

ITAMP7IE

Bit 22: ITAMP7IE.

ITAMP8IE

Bit 23: ITAMP8IE.

ITAMP9IE

Bit 24: ITAMP9IE.

ITAMP11IE

Bit 26: ITAMP11IE.

ITAMP12IE

Bit 27: ITAMP12IE.

ITAMP13IE

Bit 28: ITAMP13IE.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13IE r	ITAMP12F r	CITAMP11F r		ITAMP9F r	ITAMP8F r	ITAMP7F r	ITAMP6F r	ITAMP5F r		ITAMP3F r	CITAMP2F r	CITAMP1F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8F r	TAMP7F r	TAMP6F r	TAMP5F r	TAMP4F r	TAMP3F r	TAMP2F r	TAMP1F r

Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

TAMP4F

Bit 3: TAMP4F.

TAMP5F

Bit 4: TAMP5F.

TAMP6F

Bit 5: TAMP6F.

TAMP7F

Bit 6: TAMP7F.

TAMP8F

Bit 7: TAMP8F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP6F

Bit 21: ITAMP6F.

ITAMP7F

Bit 22: ITAMP7F.

ITAMP8F

Bit 23: ITAMP8F.

ITAMP9F

Bit 24: ITAMP9F.

CITAMP11F

Bit 26: CITAMP11F.

ITAMP12F

Bit 27: ITAMP12F.

ITAMP13IE

Bit 28: ITAMP13IE.

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13MF r	ITAMP12MF r	ITAMP11MF r		ITAMP9MF r	ITAMP8MF r	ITAMP7MF r	ITAMP6MF r	ITAMP5MF r		ITAMP3MF r	ITAMP2MF r	ITAMP1MF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8MF r	TAMP7MF r	TAMP6MF r	TAMP5MF r	TAMP4MF r	TAMP3MF r	TAMP2MF r	TAMP1MF r

Toggle fields

TAMP1MF

Bit 0: TAMP1MF.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP6MF

Bit 21: ITAMP6MF.

ITAMP7MF

Bit 22: ITAMP7MF.

ITAMP8MF

Bit 23: ITAMP8MF.

ITAMP9MF

Bit 24: ITAMP9MF.

ITAMP11MF

Bit 26: ITAMP11MF.

ITAMP12MF

Bit 27: ITAMP12MF.

ITAMP13MF

Bit 28: ITAMP13MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13MF r	ITAMP12MF r	ITAMP11MF r		ITAMP9MF r	ITAMP8MF r	ITAMP7MF r	ITAMP6MF r	ITAMP5MF r		ITAMP3MF r	ITAMP2MF r	ITAMP1MF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8MF r	TAMP7MF r	TAMP6MF r	TAMP5MF r	TAMP4MF r	TAMP3MF r	TAMP2MF r	TAMP1MF r

Toggle fields

TAMP1MF

Bit 0: TAMP1MF.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP6MF

Bit 21: ITAMP6MF.

ITAMP7MF

Bit 22: ITAMP7MF.

ITAMP8MF

Bit 23: ITAMP8MF.

ITAMP9MF

Bit 24: ITAMP9MF.

ITAMP11MF

Bit 26: ITAMP11MF.

ITAMP12MF

Bit 27: ITAMP12MF.

ITAMP13MF

Bit 28: ITAMP13MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CITAMP13F rw	CITAMP12F rw	CITAMP11F rw		CITAMP9F rw	CITAMP8F_bit23 rw	CITAMP7F_bit22 rw	CITAMP6F_bit21 rw	CITAMP5F rw		CITAMP3F rw	CITAMP2F rw	CITAMP1F rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CITAMP8F rw	CITAMP7F rw	CTAMP6F rw	CTAMP5F rw	CTAMP4F rw	CTAMP3F rw	CTAMP2F rw	CTAMP1F rw

Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CTAMP4F

Bit 3: CTAMP4F.

CTAMP5F

Bit 4: CTAMP5F.

CTAMP6F

Bit 5: CTAMP6F.

CITAMP7F

Bit 6: CITAMP3F.

CITAMP8F

Bit 7: CITAMP3F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP6F_bit21

Bit 21: CITAMP6F_bit21.

CITAMP7F_bit22

Bit 22: CITAMP7F_bit22.

CITAMP8F_bit23

Bit 23: CITAMP8F_bit23.

CITAMP9F

Bit 24: CITAMP9F.

CITAMP11F

Bit 26: CITAMP11F.

CITAMP12F

Bit 27: CITAMP12F.

CITAMP13F

Bit 28: CITAMP13F.

COUNT1R

TAMP monotonic counter 1register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COUNT r

Toggle fields

COUNT

Bits 0-31: COUNT.

ERCFGR

TAMP erase configuration register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															ERCFG0 rw

Toggle fields

ERCFG0

Bit 0: ERCFG0.

BKP0R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP1R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP2R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP3R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP4R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP5R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP6R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP7R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP8R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP9R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP10R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP11R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP12R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP13R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP14R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP15R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP16R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP17R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP18R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP19R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP20R

TAMP backup register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP21R

TAMP backup register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP22R

TAMP backup register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP23R

TAMP backup register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP24R

TAMP backup register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP25R

TAMP backup register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP26R

TAMP backup register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP27R

TAMP backup register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP28R

TAMP backup register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP29R

TAMP backup register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP30R

TAMP backup register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP31R

TAMP backup register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

SEC_TIM1

0x50012c00: Advanced-timers

1/229 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																				DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2							MMS_3		MMS2					OIS6		OIS5	OIS4N	OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS0_2			CCDS	CCUS		CCPC
0x8	SMCR							SMSPS	SMSPE			TS4_3					SMS3_0	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER									TERRIE	IERRIE	DIRIE	IDXIE						TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR									TERRF	IERRF	DIRF	IDXF			CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input																	IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output								OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input																	IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output								OC4M_bit3								OC3M_3	OC4CE	OC4M_3_0			OC4PE	OC4FE	CC4S_1_0		OC3CE	OC3M_2_0			OC3PE	OC3FE	CC3S_1_0
0x20	CCER											CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY																CNT
0x28	PSC																	PSC
0x2c	ARR													ARR				ARR
0x30	RCR																	REP
0x34	CCR1													CCR1				CCR1
0x38	CCR2													CCR2				CCR2
0x3c	CCR3													CCR3				CCR3
0x40	CCR4													CCR4				CCR4
0x44	BDTR			BK2BID	BKBID	BK2DSRAM	BKDSRM	BK2P	BK2E	BK2F				BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	CCR5	GC5C3	GC5C2	GC5C1										CCR5				CCR5
0x4c	CCR6													CCR6				CCR6
0x50	CCMR3								OC6M								OC5M2	OC6CE	OC6M1			OC6PE	OC6FE			OC5CE	OC5M1			OC5PE	OC5FE
0x54	DTR2															DTPE	DTAE									DTGF
0x58	ECR						PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL					TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1															ETRSEL		ETRSEL		BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP	BKCMP8E	BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2														OCRSEL					BK2CMP4P	BK2CMP3P	BK2CMP2P	BK2CMP1P	BK2INP	BK2CMP8E	BK2CMP7E	BK2CMP6E	BK2CMP5E	BK2CMP4E	BK2CMP3E	BK2CMP2E	BK2CMP1E	BK2INE
0x3dc	DCR													DBSS							DBL								DBA
0x3e0	DMAR	DMAB																DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw		MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OIS4N rw	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS0_2 rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS0_2

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS4N

Bit 15: Output Idle state 4 (OC5 output).

OIS5

Bit 16: Output Idle state 5.

OIS6

Bit 18: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

MMS_3

Bit 25: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS4_3 rw					SMS3_0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS3_0

Bit 16: Slave mode selection.

TS4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw			CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M_3_0 rw			OC4PE rw	OC4FE rw	CC4S_1_0 rw		OC3CE rw	OC3M_2_0 rw			OC3PE rw	OC3FE rw	CC3S_1_0 rw

Toggle fields

CC3S_1_0

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M_2_0

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S_1_0

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M_3_0

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output compare 3 mode.

OC4M_bit3

Bit 24: Output Compare 4 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		BK2BID rw	BKBID rw	BK2DSRAM rw	BKDSRM rw	BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRAM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

CCR5

alternate function register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw										CCR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-19: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

alternate function register 2

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CCR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-19: CCR6.

CCMR3

capture/compare mode register 3

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M rw								OC5M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M1 rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M1 rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M1

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M1

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M2

Bit 16: Output compare 5 mode.

OC6M

Bit 24: Output compare 6 mode.

DTR2

deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Dead-time falling edge generator setup.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

ECR

encoder control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti3[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti3[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw	BKCMP8E rw	BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKCMP8E

Bit 8: tim_brk_cmp8 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

ETRSEL

Bits 14-17: ETR source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BK2CMP4P rw	BK2CMP3P rw	BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2CMP8E rw	BK2CMP7E rw	BK2CMP6E rw	BK2CMP5E rw	BK2CMP4E rw	BK2CMP3E rw	BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2CMP3E

Bit 3: tim_brk2_cmp3 enable.

BK2CMP4E

Bit 4: tim_brk2_cmp4 enable.

BK2CMP5E

Bit 5: tim_brk2_cmp5 enable.

BK2CMP6E

Bit 6: tim_brk2_cmp6 enable.

BK2CMP7E

Bit 7: tim_brk2_cmp7 enable.

BK2CMP8E

Bit 8: tim_brk2_cmp8 enable.

BK2INP

Bit 9: TIMx_BKIN2 input polarity.

BK2CMP1P

Bit 10: tim_brk2_cmp1 input polarity.

BK2CMP2P

Bit 11: tim_brk2_cmp2 input polarity.

BK2CMP3P

Bit 12: tim_brk2_cmp3 input polarity.

BK2CMP4P

Bit 13: tim_brk2_cmp4 input polarity.

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

SEC_TIM15

0x50014000: General purpose timers

1/112 fields covered.

Toggle register map

Offset	Name	31	28	26	24	21	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1													DITHEN	UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2															OIS2	OIS1N	OIS1	TI1S		MMS		CCDS	CCUS		CCPC
0x8	SMCR					TS_4_3				SMS_3							CC1DE		MSM	TS_2_0				SMS
0xc	DIER											TDE	COMDE			CC2DE	CC1DE	UDE	BIE	TIE	COMIE			CC2IE	CC1IE	UIE
0x10	SR															CC2OF	CC1OF		BIF	TIF	COMIF			CC2IF	CC1IF	UIF
0x14	EGR																		BG	TG	COMG			CC2G	CC1G	UG
0x18	CCMR1_Input										IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output				OC2M_bit3					OC1M_bit3		OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																		CC2NP		CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY									CNT
0x28	PSC										PSC
0x2c	ARR						ARR				ARR
0x30	RCR																		REP
0x34	CCR1						CCR1				CCR1
0x38	CCR2						CCR2				CCR2
0x44	BDTR		BKBID	BKDSRM			BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x54	DTR2								DTPE	DTAE									DTGF
0x5c	TISEL														TI2SEL								TI1SEL
0x60	AF1												BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP		BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2							OCRSEL
0x3dc	DCR						DBSS							DBL								DBA
0x3e0	DMAR	DMAB									DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw		MMS rw		CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-5: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output idle state 2 (OC2 output).

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS_4_3 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1DE rw		MSM rw	TS_2_0 rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

SMS_3

Bit 16: Slave mode selection.

TS_4_3

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw			CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw			CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CC2OF rw	CC1OF rw		BIF rw	TIF rw	COMIF rw			CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG rw			CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/Compare 2 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC1M_bit3

Bit 16: Output Compare 1 mode.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CC2NP rw		CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output polarity.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DTR2

timer deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Dead-time falling edge generator setup.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

TISEL

input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects tim_ti1_in[0..15] input.

TI2SEL

Bits 8-11: selects tim_ti2_in[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw		BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: TIMx_BKIN input enable.

BKCMP1E

Bit 1: tim_brk_cmp1 enable.

BKCMP2E

Bit 2: tim_brk_cmp2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: tim_brk_cmp1 input polarity.

BKCMP2P

Bit 11: tim_brk_cmp2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

SEC_TIM16

0x50014400: General purpose timers

1/80 fields covered.

Toggle register map

Offset	Name	31	28	26	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2														OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER										COMDE				CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR														CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR																BG		COMG				CC1G	UG
0x18	CCMR1_Input																IC1F				IC1PSC		CC1S
0x18	CCMR1_Output							OC1M_2									OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																				CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY							CNT
0x28	PSC								PSC
0x2c	ARR				ARR				ARR
0x30	RCR																REP
0x34	CCR1				CCR1				CCR1
0x44	BDTR		BKBID	BKDSRM					MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x50	OR1																							HSE32EN
0x54	DTR2						DTPE	DTAE									DTGF
0x5c	TISEL																				TI1SEL
0x60	AF1										BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP		BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2					OCRSEL
0x3dc	DCR				DBSS							DBL								DBA
0x3e0	DMAR	DMAB							DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		COMDE rw				CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: CC1OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

OR1

option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															HSE32EN rw

Toggle fields

HSE32EN

Bit 0: HSE Divided by 32 enable.

DTR2

timer deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Deadtime asymmetric enable.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

TISEL

TIM17 option register 1

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects tim_ti1_in[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw		BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: TIMx_BKIN input enable.

BKCMP1E

Bit 1: tim_brk_cmp1 enable.

BKCMP2E

Bit 2: tim_brk_cmp2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: tim_brk_cmp1 input polarity.

BKCMP2P

Bit 11: tim_brk_cmp2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: tim_ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

TIM17 option register 1

Offset: 0x3e0, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

SEC_TIM17

0x50014800: General purpose timers

1/80 fields covered.

Toggle register map

Offset	Name	31	28	26	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2														OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER										COMDE				CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR														CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR																BG		COMG				CC1G	UG
0x18	CCMR1_Input																IC1F				IC1PSC		CC1S
0x18	CCMR1_Output							OC1M_2									OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																				CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY							CNT
0x28	PSC								PSC
0x2c	ARR				ARR				ARR
0x30	RCR																REP
0x34	CCR1				CCR1				CCR1
0x44	BDTR		BKBID	BKDSRM					MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x50	OR1																							HSE32EN
0x54	DTR2						DTPE	DTAE									DTGF
0x5c	TISEL																				TI1SEL
0x60	AF1										BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP		BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2					OCRSEL
0x3dc	DCR				DBSS							DBL								DBA
0x3e0	DMAR	DMAB							DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		COMDE rw				CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: CC1OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

OR1

option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															HSE32EN rw

Toggle fields

HSE32EN

Bit 0: HSE Divided by 32 enable.

DTR2

timer deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Deadtime asymmetric enable.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

TISEL

TIM17 option register 1

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects tim_ti1_in[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw		BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: TIMx_BKIN input enable.

BKCMP1E

Bit 1: tim_brk_cmp1 enable.

BKCMP2E

Bit 2: tim_brk_cmp2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: tim_brk_cmp1 input polarity.

BKCMP2P

Bit 11: tim_brk_cmp2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: tim_ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

TIM17 option register 1

Offset: 0x3e0, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

SEC_TIM2

0x50000000: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

SEC_TIM3

0x50000400: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

SEC_TIM4

0x50000800: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

SEC_TIM5

0x50000c00: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

SEC_TIM6

0x50001000: General-purpose-timers

0/16 fields covered.

Toggle register map

Offset	Name	31	19	15	12	11	8	7	6	3	2	1	0
0x0	CR1				DITHEN	UIFREMAP		ARPE		OPM	URS	UDIS	CEN
0x4	CR2								MMS
0xc	DIER						UDE						UIE
0x10	SR												UIF
0x14	EGR												UG
0x24	CNT	UIFCPY		CNT
0x28	PSC			PSC
0x2c	ARR		ARR	ARR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw				ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle register map

Offset	Name	31	19	15	12	11	8	7	6	3	2	1	0
0x0	CR1				DITHEN	UIFREMAP		ARPE		OPM	URS	UDIS	CEN
0x4	CR2								MMS
0xc	DIER						UDE						UIE
0x10	SR												UIF
0x14	EGR												UG
0x24	CNT	UIFCPY		CNT
0x28	PSC			PSC
0x2c	ARR		ARR	ARR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw				ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																				DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2							MMS_3		MMS2					OIS6		OIS5	OIS4N	OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS0_2			CCDS	CCUS		CCPC
0x8	SMCR							SMSPS	SMSPE			TS4_3					SMS3_0	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER									TERRIE	IERRIE	DIRIE	IDXIE						TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR									TERRF	IERRF	DIRF	IDXF			CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input																	IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output								OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input																	IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output								OC4M_bit3								OC3M_3	OC4CE	OC4M_3_0			OC4PE	OC4FE	CC4S_1_0		OC3CE	OC3M_2_0			OC3PE	OC3FE	CC3S_1_0
0x20	CCER											CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY																CNT
0x28	PSC																	PSC
0x2c	ARR													ARR				ARR
0x30	RCR																	REP
0x34	CCR1													CCR1				CCR1
0x38	CCR2													CCR2				CCR2
0x3c	CCR3													CCR3				CCR3
0x40	CCR4													CCR4				CCR4
0x44	BDTR			BK2BID	BKBID	BK2DSRAM	BKDSRM	BK2P	BK2E	BK2F				BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	CCR5	GC5C3	GC5C2	GC5C1										CCR5				CCR5
0x4c	CCR6													CCR6				CCR6
0x50	CCMR3								OC6M								OC5M2	OC6CE	OC6M1			OC6PE	OC6FE			OC5CE	OC5M1			OC5PE	OC5FE
0x54	DTR2															DTPE	DTAE									DTGF
0x58	ECR						PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL					TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1															ETRSEL		ETRSEL		BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP	BKCMP8E	BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2														OCRSEL					BK2CMP4P	BK2CMP3P	BK2CMP2P	BK2CMP1P	BK2INP	BK2CMP8E	BK2CMP7E	BK2CMP6E	BK2CMP5E	BK2CMP4E	BK2CMP3E	BK2CMP2E	BK2CMP1E	BK2INE
0x3dc	DCR													DBSS							DBL								DBA
0x3e0	DMAR	DMAB																DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw		MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OIS4N rw	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS0_2 rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS0_2

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS4N

Bit 15: Output Idle state 4 (OC5 output).

OIS5

Bit 16: Output Idle state 5.

OIS6

Bit 18: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

MMS_3

Bit 25: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS4_3 rw					SMS3_0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS3_0

Bit 16: Slave mode selection.

TS4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw			CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M_3_0 rw			OC4PE rw	OC4FE rw	CC4S_1_0 rw		OC3CE rw	OC3M_2_0 rw			OC3PE rw	OC3FE rw	CC3S_1_0 rw

Toggle fields

CC3S_1_0

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M_2_0

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S_1_0

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M_3_0

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output compare 3 mode.

OC4M_bit3

Bit 24: Output Compare 4 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		BK2BID rw	BKBID rw	BK2DSRAM rw	BKDSRM rw	BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRAM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

CCR5

alternate function register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw										CCR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-19: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

alternate function register 2

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CCR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-19: CCR6.

CCMR3

capture/compare mode register 3

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M rw								OC5M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M1 rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M1 rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M1

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M1

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M2

Bit 16: Output compare 5 mode.

OC6M

Bit 24: Output compare 6 mode.

DTR2

deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Dead-time falling edge generator setup.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

ECR

encoder control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti3[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti3[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw	BKCMP8E rw	BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKCMP8E

Bit 8: tim_brk_cmp8 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

ETRSEL

Bits 14-17: ETR source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BK2CMP4P rw	BK2CMP3P rw	BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2CMP8E rw	BK2CMP7E rw	BK2CMP6E rw	BK2CMP5E rw	BK2CMP4E rw	BK2CMP3E rw	BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2CMP3E

Bit 3: tim_brk2_cmp3 enable.

BK2CMP4E

Bit 4: tim_brk2_cmp4 enable.

BK2CMP5E

Bit 5: tim_brk2_cmp5 enable.

BK2CMP6E

Bit 6: tim_brk2_cmp6 enable.

BK2CMP7E

Bit 7: tim_brk2_cmp7 enable.

BK2CMP8E

Bit 8: tim_brk2_cmp8 enable.

BK2INP

Bit 9: TIMx_BKIN2 input polarity.

BK2CMP1P

Bit 10: tim_brk2_cmp1 input polarity.

BK2CMP2P

Bit 11: tim_brk2_cmp2 input polarity.

BK2CMP3P

Bit 12: tim_brk2_cmp3 input polarity.

BK2CMP4P

Bit 13: tim_brk2_cmp4 input polarity.

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

SEC_TSC

0x50024000: Touch sensing controller

18/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR	CTPH				CTPL				SSD							SSE	SSPSC	PGPSC							MCV			IODEF	SYNCPOL	AM	START	TSCE
0x4	IER																															MCEIE	EOAIE
0x8	ICR																															MCEIC	EOAIC
0xc	ISR																															MCEF	EOAF
0x10	IOHCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x18	IOASCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x20	IOSCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x28	IOCCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x30	IOGCSR									G8S	G7S	G6S	G5S	G4S	G3S	G2S	G1S									G8E	G7E	G6E	G5E	G4E	G3E	G2E	G1E
0x34	IOG1CR																			CNT
0x38	IOG2CR																			CNT
0x3c	IOG3CR																			CNT
0x40	IOG4CR																			CNT
0x44	IOG5CR																			CNT
0x48	IOG6CR																			CNT
0x4c	IOG7CR																			CNT
0x50	IOG8CR																			CNT

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTPH rw				CTPL rw				SSD rw							SSE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSPSC rw	PGPSC rw							MCV rw			IODEF rw	SYNCPOL rw	AM rw	START rw	TSCE rw

Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIE rw	EOAIE rw

Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIC rw	EOAIC rw

Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEF r	EOAF r

Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								G8S r	G7S r	G6S r	G5S r	G4S r	G3S r	G2S r	G1S r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								G8E rw	G7E rw	G6E rw	G5E rw	G4E rw	G3E rw	G2E rw	G1E rw

Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

SEC_UART5

0x50005000: Universal synchronous asynchronous receiver transmitter

50/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

SEC_USART1

0x50013800: Universal synchronous asynchronous receiver transmitter

50/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

SEC_USART3

0x50004800: Universal synchronous asynchronous receiver transmitter

50/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

SEC_VREFBUF

0x56007400: Voltage reference buffer

1/5 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	VREFBUF_CSR																										VRS			VRR		HIZ	ENVR
0x4	VREFBUF_CCR																											TRIM

Toggle registers

VREFBUF_CSR

VREFBUF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VRS rw			VRR r		HIZ rw	ENVR rw

Toggle fields

ENVR

Bit 0: ENVR.

HIZ

Bit 1: HIZ.

VRR

Bit 3: VRR.

VRS

Bits 4-6: VRS.

VREFBUF_CCR

VREFBUF calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRIM rw

Toggle fields

TRIM

Bits 0-5: TRIM.

SEC_WWDG

0x50002c00: System window watchdog

0/6 fields covered.

Toggle register map

Offset	Name	13	9	7	6	0
0x0	CR			WDGA	T
0x4	CFR	WDGTB	EWI		W
0x8	SR					EWIF

Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		WDGTB rw				EWI rw			W rw

Toggle fields

W

Bits 0-6: 7-bit window value.

EWI

Bit 9: Early wakeup interrupt.

WDGTB

Bits 11-13: Timer base.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

SPI1

0x40013000: Serial peripheral interface

18/77 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	22	21	20	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1														IOLOCK	TCRCINI	RCRCINI	CRC33_17	SSI	HDDIR	CSUSP	CSTART	MASRX								SPE
0x4	CR2															TSIZE
0x8	CFG1	BPASS	MBR							CRCEN		CRCSIZE				TXDMAEN	RXDMAEN					UDRCFG	FTHVL
0xc	CFG2	AFCNTR	SSOM	SSOE	SSIOP	SSM	CPOL	CPHA	LSBFRST	MASTER	SP			COMM		IOSWP	RDIOP	RDIMM						MIDI				MSSI
0x10	IER																					MODFIE	TIFREIE	CRCEIE	OVRIE	UDRIE	TXTFIE	EOTIE	DPXPIE	TXPIE	RXPIE
0x14	SR	CTSIZE														RXWNE	RXPLVL		TXC	SUSP		MODF	TIFRE	CRCE	OVR	UDR	TXTF	EOT	DXP	TXP	RXP
0x18	IFCR																			SUSPC		MODFC	TIFREC	CRCEC	OVRC	UDRC	TXTFC	EOTC
0x1c	AUTOCR										TRIGEN	TRIGPOL	TRIGSEL
0x20	TXDR	TXDR														TXDR
0x30	RXDR	RXDR														RXDR
0x40	CRCPOLY	CRCPOLY														CRCPOLY
0x44	TXCRC	TXCRC														TXCRC
0x48	RXCRC	RXCRC														RXCRC
0x4c	UDRDR	UDRDR														UDRDR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IOLOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCRCINI rw	RCRCINI rw	CRC33_17 rw	SSI rw	HDDIR rw	CSUSP w	CSTART rw	MASRX rw								SPE rw

Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIZE rw

Toggle fields

TSIZE

Bits 0-15: TSIZE.

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BPASS rw	MBR rw								CRCEN rw		CRCSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDMAEN rw	RXDMAEN rw					UDRCFG rw	FTHVL rw

Toggle fields

FTHVL

Bits 5-8: threshold level.

UDRCFG

Bit 9: Behavior of slave transmitter at underrun condition.

RXDMAEN

Bit 14: Rx DMA stream enable.

TXDMAEN

Bit 15: Tx DMA stream enable.

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

CRCEN

Bit 22: Hardware CRC computation enable.

MBR

Bits 28-30: Master baud rate.

BPASS

Bit 31: BPASS.

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFCNTR rw	SSOM rw	SSOE rw	SSIOP rw		SSM rw	CPOL rw	CPHA rw	LSBFRST rw	MASTER rw	SP rw			COMM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOSWP rw	RDIOP rw	RDIMM rw						MIDI rw				MSSI rw

Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

MIDI

Bits 4-7: Master Inter-Data Idleness.

RDIMM

Bit 13: RDIMM.

RDIOP

Bit 14: RDIOP.

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

COMM

Bits 17-18: SPI Communication Mode.

SP

Bits 19-21: Serial Protocol.

MASTER

Bit 22: SPI Master.

LSBFRST

Bit 23: Data frame format.

CPHA

Bit 24: Clock phase.

CPOL

Bit 25: Clock polarity.

SSM

Bit 26: Software management of SS signal input.

SSIOP

Bit 28: SS input/output polarity.

SSOE

Bit 29: SS output enable.

SSOM

Bit 30: SS output management in master mode.

AFCNTR

Bit 31: Alternate function GPIOs control.

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODFIE rw	TIFREIE rw	CRCEIE rw	OVRIE rw	UDRIE rw	TXTFIE rw	EOTIE rw	DPXPIE rw	TXPIE rw	RXPIE rw

Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

TXPIE

Bit 1: TXP interrupt enable.

DPXPIE

Bit 2: DXP interrupt enabled.

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

TXTFIE

Bit 4: TXTFIE interrupt enable.

UDRIE

Bit 5: UDR interrupt enable.

OVRIE

Bit 6: OVR interrupt enable.

CRCEIE

Bit 7: CRC Interrupt enable.

TIFREIE

Bit 8: TIFRE interrupt enable.

MODFIE

Bit 9: Mode Fault interrupt enable.

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTSIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXWNE r	RXPLVL r		TXC r	SUSP r		MODF r	TIFRE r	CRCE r	OVR r	UDR r	TXTF r	EOT r	DXP r	TXP r	RXP r

Toggle fields

RXP

Bit 0: Rx-Packet available.

TXP

Bit 1: Tx-Packet space available.

DXP

Bit 2: Duplex Packet.

EOT

Bit 3: End Of Transfer.

TXTF

Bit 4: Transmission Transfer Filled.

UDR

Bit 5: Underrun at slave transmission mode.

OVR

Bit 6: Overrun.

CRCE

Bit 7: CRC Error.

TIFRE

Bit 8: TI frame format error.

MODF

Bit 9: Mode Fault.

SUSP

Bit 11: SUSPend.

TXC

Bit 12: TxFIFO transmission complete.

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

RXWNE

Bit 15: RxFIFO Word Not Empty.

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SUSPC w		MODFC w	TIFREC w	CRCEC w	OVRC w	UDRC w	TXTFC w	EOTC w

Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

UDRC

Bit 5: Underrun flag clear.

OVRC

Bit 6: Overrun flag clear.

CRCEC

Bit 7: CRC Error flag clear.

TIFREC

Bit 8: TI frame format error flag clear.

MODFC

Bit 9: Mode Fault flag clear.

SUSPC

Bit 11: SUSPend flag clear.

AUTOCR

SPI autonomous mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TRIGSEL

Bits 16-19: TRIGSEL.

TRIGPOL

Bit 20: TRIGPOL.

TRIGEN

Bit 21: TRIGEN.

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXDR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDR w

Toggle fields

TXDR

Bits 0-31: Transmit data register.

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDR r

Toggle fields

RXDR

Bits 0-31: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRCPOLY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UDRDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UDRDR rw

Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

SPI2

0x40003800: Serial peripheral interface

18/77 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	22	21	20	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1														IOLOCK	TCRCINI	RCRCINI	CRC33_17	SSI	HDDIR	CSUSP	CSTART	MASRX								SPE
0x4	CR2															TSIZE
0x8	CFG1	BPASS	MBR							CRCEN		CRCSIZE				TXDMAEN	RXDMAEN					UDRCFG	FTHVL
0xc	CFG2	AFCNTR	SSOM	SSOE	SSIOP	SSM	CPOL	CPHA	LSBFRST	MASTER	SP			COMM		IOSWP	RDIOP	RDIMM						MIDI				MSSI
0x10	IER																					MODFIE	TIFREIE	CRCEIE	OVRIE	UDRIE	TXTFIE	EOTIE	DPXPIE	TXPIE	RXPIE
0x14	SR	CTSIZE														RXWNE	RXPLVL		TXC	SUSP		MODF	TIFRE	CRCE	OVR	UDR	TXTF	EOT	DXP	TXP	RXP
0x18	IFCR																			SUSPC		MODFC	TIFREC	CRCEC	OVRC	UDRC	TXTFC	EOTC
0x1c	AUTOCR										TRIGEN	TRIGPOL	TRIGSEL
0x20	TXDR	TXDR														TXDR
0x30	RXDR	RXDR														RXDR
0x40	CRCPOLY	CRCPOLY														CRCPOLY
0x44	TXCRC	TXCRC														TXCRC
0x48	RXCRC	RXCRC														RXCRC
0x4c	UDRDR	UDRDR														UDRDR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IOLOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCRCINI rw	RCRCINI rw	CRC33_17 rw	SSI rw	HDDIR rw	CSUSP w	CSTART rw	MASRX rw								SPE rw

Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIZE rw

Toggle fields

TSIZE

Bits 0-15: TSIZE.

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BPASS rw	MBR rw								CRCEN rw		CRCSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDMAEN rw	RXDMAEN rw					UDRCFG rw	FTHVL rw

Toggle fields

FTHVL

Bits 5-8: threshold level.

UDRCFG

Bit 9: Behavior of slave transmitter at underrun condition.

RXDMAEN

Bit 14: Rx DMA stream enable.

TXDMAEN

Bit 15: Tx DMA stream enable.

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

CRCEN

Bit 22: Hardware CRC computation enable.

MBR

Bits 28-30: Master baud rate.

BPASS

Bit 31: BPASS.

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFCNTR rw	SSOM rw	SSOE rw	SSIOP rw		SSM rw	CPOL rw	CPHA rw	LSBFRST rw	MASTER rw	SP rw			COMM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOSWP rw	RDIOP rw	RDIMM rw						MIDI rw				MSSI rw

Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

MIDI

Bits 4-7: Master Inter-Data Idleness.

RDIMM

Bit 13: RDIMM.

RDIOP

Bit 14: RDIOP.

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

COMM

Bits 17-18: SPI Communication Mode.

SP

Bits 19-21: Serial Protocol.

MASTER

Bit 22: SPI Master.

LSBFRST

Bit 23: Data frame format.

CPHA

Bit 24: Clock phase.

CPOL

Bit 25: Clock polarity.

SSM

Bit 26: Software management of SS signal input.

SSIOP

Bit 28: SS input/output polarity.

SSOE

Bit 29: SS output enable.

SSOM

Bit 30: SS output management in master mode.

AFCNTR

Bit 31: Alternate function GPIOs control.

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODFIE rw	TIFREIE rw	CRCEIE rw	OVRIE rw	UDRIE rw	TXTFIE rw	EOTIE rw	DPXPIE rw	TXPIE rw	RXPIE rw

Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

TXPIE

Bit 1: TXP interrupt enable.

DPXPIE

Bit 2: DXP interrupt enabled.

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

TXTFIE

Bit 4: TXTFIE interrupt enable.

UDRIE

Bit 5: UDR interrupt enable.

OVRIE

Bit 6: OVR interrupt enable.

CRCEIE

Bit 7: CRC Interrupt enable.

TIFREIE

Bit 8: TIFRE interrupt enable.

MODFIE

Bit 9: Mode Fault interrupt enable.

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTSIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXWNE r	RXPLVL r		TXC r	SUSP r		MODF r	TIFRE r	CRCE r	OVR r	UDR r	TXTF r	EOT r	DXP r	TXP r	RXP r

Toggle fields

RXP

Bit 0: Rx-Packet available.

TXP

Bit 1: Tx-Packet space available.

DXP

Bit 2: Duplex Packet.

EOT

Bit 3: End Of Transfer.

TXTF

Bit 4: Transmission Transfer Filled.

UDR

Bit 5: Underrun at slave transmission mode.

OVR

Bit 6: Overrun.

CRCE

Bit 7: CRC Error.

TIFRE

Bit 8: TI frame format error.

MODF

Bit 9: Mode Fault.

SUSP

Bit 11: SUSPend.

TXC

Bit 12: TxFIFO transmission complete.

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

RXWNE

Bit 15: RxFIFO Word Not Empty.

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SUSPC w		MODFC w	TIFREC w	CRCEC w	OVRC w	UDRC w	TXTFC w	EOTC w

Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

UDRC

Bit 5: Underrun flag clear.

OVRC

Bit 6: Overrun flag clear.

CRCEC

Bit 7: CRC Error flag clear.

TIFREC

Bit 8: TI frame format error flag clear.

MODFC

Bit 9: Mode Fault flag clear.

SUSPC

Bit 11: SUSPend flag clear.

AUTOCR

SPI autonomous mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TRIGSEL

Bits 16-19: TRIGSEL.

TRIGPOL

Bit 20: TRIGPOL.

TRIGEN

Bit 21: TRIGEN.

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXDR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDR w

Toggle fields

TXDR

Bits 0-31: Transmit data register.

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDR r

Toggle fields

RXDR

Bits 0-31: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRCPOLY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UDRDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UDRDR rw

Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

SPI3

0x46002000: Serial peripheral interface

18/77 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	22	21	20	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1														IOLOCK	TCRCINI	RCRCINI	CRC33_17	SSI	HDDIR	CSUSP	CSTART	MASRX								SPE
0x4	CR2															TSIZE
0x8	CFG1	BPASS	MBR							CRCEN		CRCSIZE				TXDMAEN	RXDMAEN					UDRCFG	FTHVL
0xc	CFG2	AFCNTR	SSOM	SSOE	SSIOP	SSM	CPOL	CPHA	LSBFRST	MASTER	SP			COMM		IOSWP	RDIOP	RDIMM						MIDI				MSSI
0x10	IER																					MODFIE	TIFREIE	CRCEIE	OVRIE	UDRIE	TXTFIE	EOTIE	DPXPIE	TXPIE	RXPIE
0x14	SR	CTSIZE														RXWNE	RXPLVL		TXC	SUSP		MODF	TIFRE	CRCE	OVR	UDR	TXTF	EOT	DXP	TXP	RXP
0x18	IFCR																			SUSPC		MODFC	TIFREC	CRCEC	OVRC	UDRC	TXTFC	EOTC
0x1c	AUTOCR										TRIGEN	TRIGPOL	TRIGSEL
0x20	TXDR	TXDR														TXDR
0x30	RXDR	RXDR														RXDR
0x40	CRCPOLY	CRCPOLY														CRCPOLY
0x44	TXCRC	TXCRC														TXCRC
0x48	RXCRC	RXCRC														RXCRC
0x4c	UDRDR	UDRDR														UDRDR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IOLOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCRCINI rw	RCRCINI rw	CRC33_17 rw	SSI rw	HDDIR rw	CSUSP w	CSTART rw	MASRX rw								SPE rw

Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIZE rw

Toggle fields

TSIZE

Bits 0-15: TSIZE.

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BPASS rw	MBR rw								CRCEN rw		CRCSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDMAEN rw	RXDMAEN rw					UDRCFG rw	FTHVL rw

Toggle fields

FTHVL

Bits 5-8: threshold level.

UDRCFG

Bit 9: Behavior of slave transmitter at underrun condition.

RXDMAEN

Bit 14: Rx DMA stream enable.

TXDMAEN

Bit 15: Tx DMA stream enable.

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

CRCEN

Bit 22: Hardware CRC computation enable.

MBR

Bits 28-30: Master baud rate.

BPASS

Bit 31: BPASS.

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFCNTR rw	SSOM rw	SSOE rw	SSIOP rw		SSM rw	CPOL rw	CPHA rw	LSBFRST rw	MASTER rw	SP rw			COMM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOSWP rw	RDIOP rw	RDIMM rw						MIDI rw				MSSI rw

Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

MIDI

Bits 4-7: Master Inter-Data Idleness.

RDIMM

Bit 13: RDIMM.

RDIOP

Bit 14: RDIOP.

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

COMM

Bits 17-18: SPI Communication Mode.

SP

Bits 19-21: Serial Protocol.

MASTER

Bit 22: SPI Master.

LSBFRST

Bit 23: Data frame format.

CPHA

Bit 24: Clock phase.

CPOL

Bit 25: Clock polarity.

SSM

Bit 26: Software management of SS signal input.

SSIOP

Bit 28: SS input/output polarity.

SSOE

Bit 29: SS output enable.

SSOM

Bit 30: SS output management in master mode.

AFCNTR

Bit 31: Alternate function GPIOs control.

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODFIE rw	TIFREIE rw	CRCEIE rw	OVRIE rw	UDRIE rw	TXTFIE rw	EOTIE rw	DPXPIE rw	TXPIE rw	RXPIE rw

Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

TXPIE

Bit 1: TXP interrupt enable.

DPXPIE

Bit 2: DXP interrupt enabled.

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

TXTFIE

Bit 4: TXTFIE interrupt enable.

UDRIE

Bit 5: UDR interrupt enable.

OVRIE

Bit 6: OVR interrupt enable.

CRCEIE

Bit 7: CRC Interrupt enable.

TIFREIE

Bit 8: TIFRE interrupt enable.

MODFIE

Bit 9: Mode Fault interrupt enable.

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTSIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXWNE r	RXPLVL r		TXC r	SUSP r		MODF r	TIFRE r	CRCE r	OVR r	UDR r	TXTF r	EOT r	DXP r	TXP r	RXP r

Toggle fields

RXP

Bit 0: Rx-Packet available.

TXP

Bit 1: Tx-Packet space available.

DXP

Bit 2: Duplex Packet.

EOT

Bit 3: End Of Transfer.

TXTF

Bit 4: Transmission Transfer Filled.

UDR

Bit 5: Underrun at slave transmission mode.

OVR

Bit 6: Overrun.

CRCE

Bit 7: CRC Error.

TIFRE

Bit 8: TI frame format error.

MODF

Bit 9: Mode Fault.

SUSP

Bit 11: SUSPend.

TXC

Bit 12: TxFIFO transmission complete.

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

RXWNE

Bit 15: RxFIFO Word Not Empty.

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SUSPC w		MODFC w	TIFREC w	CRCEC w	OVRC w	UDRC w	TXTFC w	EOTC w

Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

UDRC

Bit 5: Underrun flag clear.

OVRC

Bit 6: Overrun flag clear.

CRCEC

Bit 7: CRC Error flag clear.

TIFREC

Bit 8: TI frame format error flag clear.

MODFC

Bit 9: Mode Fault flag clear.

SUSPC

Bit 11: SUSPend flag clear.

AUTOCR

SPI autonomous mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TRIGEN rw	TRIGPOL rw	TRIGSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TRIGSEL

Bits 16-19: TRIGSEL.

TRIGPOL

Bit 20: TRIGPOL.

TRIGEN

Bit 21: TRIGEN.

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXDR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDR w

Toggle fields

TXDR

Bits 0-31: Transmit data register.

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXDR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDR r

Toggle fields

RXDR

Bits 0-31: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRCPOLY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXCRC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UDRDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UDRDR rw

Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

SYSCFG

0x46000400: System configuration controller

9/44 fields covered.

Toggle register map

Offset	Name	25	23	19	18	17	16	15	11	10	9	8	7	5	4	3	2	1	0
0x0	SECCFGR															FPUSEC		CLASSBSEC	SYSCFGSEC
0x4	CFGR1	ENDCAP		PB9_FMP	PB8_FMP	PB7_FMP	PB6_FMP				ANASWVDD	BOOSTEN
0x8	FPUIMR													FPU_IE
0xc	CNSLCKR																	LOCKNSMPU	LOCKNSVTOR
0x10	CSLOCKR																LOCKSAU	LOCKSMPU	LOCKSVTAIRCR
0x14	CFGR2															ECCL	PVDL	SPL	CLL
0x18	MESR						IPMEE												MCLR
0x1c	CCCSR									RDY3	RDY2	RDY1		CS3	EN3	CS2	EN2	CS1	EN1
0x20	CCVR		PCV3	NCV3				PCV2	NCV2				PCV1			NCV1
0x24	CCCR		PCC3	NCC3				PCC2	NCC2				PCC1			NCC1
0x2c	RSSCMDR							RSSCMD

Toggle registers

SECCFGR

SYSCFG secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												FPUSEC rw		CLASSBSEC rw	SYSCFGSEC rw

Toggle fields

SYSCFGSEC

Bit 0: SYSCFG clock control security.

CLASSBSEC

Bit 1: CLASSBSEC.

FPUSEC

Bit 3: FPUSEC.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						ENDCAP rw						PB9_FMP rw	PB8_FMP rw	PB7_FMP rw	PB6_FMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						ANASWVDD rw	BOOSTEN rw

Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

ANASWVDD

Bit 9: GPIO analog switch control voltage selection.

PB6_FMP

Bit 16: PB6_FMP.

PB7_FMP

Bit 17: PB7_FMP.

PB8_FMP

Bit 18: PB8_FMP.

PB9_FMP

Bit 19: PB9_FMP.

ENDCAP

Bits 24-25: ENDCAP.

FPUIMR

FPU interrupt mask register

Offset: 0x8, size: 32, reset: 0x0000001F, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FPU_IE rw

Toggle fields

FPU_IE

Bits 0-5: Floating point unit interrupts enable bits.

CNSLCKR

SYSCFG CPU non-secure lock register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LOCKNSMPU rw	LOCKNSVTOR rw

Toggle fields

LOCKNSVTOR

Bit 0: VTOR_NS register lock.

LOCKNSMPU

Bit 1: Non-secure MPU registers lock.

CSLOCKR

SYSCFG CPU secure lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													LOCKSAU rw	LOCKSMPU rw	LOCKSVTAIRCR rw

Toggle fields

LOCKSVTAIRCR

Bit 0: LOCKSVTAIRCR.

LOCKSMPU

Bit 1: LOCKSMPU.

LOCKSAU

Bit 2: LOCKSAU.

CFGR2

configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ECCL rw	PVDL rw	SPL rw	CLL rw

Toggle fields

CLL

Bit 0: LOCKUP (hardfault) output enable bit.

SPL

Bit 1: SRAM ECC lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

MESR

memory erase status register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IPMEE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															MCLR rw

Toggle fields

MCLR

Bit 0: MCLR.

IPMEE

Bit 16: IPMEE.

CCCSR

compensation cell control/status register

Offset: 0x1c, size: 32, reset: 0x0000000A, access: Unspecified

3/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					RDY3 r	RDY2 r	RDY1 r			CS3 rw	EN3 rw	CS2 rw	EN2 rw	CS1 rw	EN1 rw

Toggle fields

EN1

Bit 0: EN1.

CS1

Bit 1: CS1.

EN2

Bit 2: EN2.

CS2

Bit 3: CS2.

EN3

Bit 4: EN3.

CS3

Bit 5: CS3.

RDY1

Bit 8: RDY1.

RDY2

Bit 9: RDY2.

RDY3

Bit 10: RDY3.

CCVR

compensation cell value register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PCV3 r				NCV3 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCV2 r				NCV2 r				PCV1 r				NCV1 r

Toggle fields

NCV1

Bits 0-3: NCV1.

PCV1

Bits 4-7: PCV1.

NCV2

Bits 8-11: NCV2.

PCV2

Bits 12-15: PCV2.

NCV3

Bits 16-19: NCV3.

PCV3

Bits 20-23: PCV3.

CCCR

compensation cell code register

Offset: 0x24, size: 32, reset: 0x00007878, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PCC3 rw				NCC3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCC2 rw				NCC2 rw				PCC1 rw				NCC1 rw

Toggle fields

NCC1

Bits 0-3: NCC1.

PCC1

Bits 4-7: PCC1.

NCC2

Bits 8-11: NCC2.

PCC2

Bits 12-15: PCC2.

NCC3

Bits 16-19: NCC3.

PCC3

Bits 20-23: PCC3.

RSSCMDR

RSS command register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSSCMD rw

Toggle fields

RSSCMD

Bits 0-15: RSS commands.

TAMP

0x46007c00: Tamper and backup registers

61/221 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1				ITAMP13E	ITAMP12E	ITAMP11E		ITAMP9E	ITAMP8E	ITAMP7E	ITAMP6E	ITAMP5E	ITAMP3E	ITAMP2E	ITAMP1E									TAMP8E	TAMP7E	TAMP6E	TAMP5E	TAMP4E	TAMP3E	TAMP2E	TAMP1E
0x4	CR2	TAMP8TRG	TAMP7TRG	TAMP6TRG	TAMP5TRG	TAMP4TRG	TAMP3TRG	TAMP2TRG	TAMP1TRG	BKERASE	BKBLOCK			TAMP3MSK	TAMP2MSK	TAMP1MSK									TAMP8NOER	TAMP7NOER	TAMP6NOER	TAMP5NOER	TAMP4NOER	TAMP3NOER	TAMP2NOER	TAMP1NOER
0x8	CR3																			ITAMP13NOER	ITAMP12NOER	ITAMP11NOER		ITAMP9NOER	TAMP8NOER	TAMP7NOER	TAMP6NOER	TAMP5NOER		ITAMP3NOER	ITAMP2NOER	ITAMP1NOER
0xc	FLTCR																								TAMPPUDIS	TAMPPRCH		TAMPFLT		TAMPFREQ
0x10	ATCR1	FLTEN	ATOSHARE				ATPER							ATCKSEL			ATOSEL4		ATOSEL3		ATOSEL2		ATOSEL1		TAMP8AM	TAMP7AM	TAMP6AM	TAMP5AM	TAMP4AM	TAMP3AM	TAMP2AM	TAMP1AM
0x14	ATSEEDR	SEED															SEED
0x18	ATOR																INITS	SEEDF							PRNG
0x1c	ATCR2	ATOSEL8			ATOSEL7			ATOSEL6			ATOSEL5			ATOSEL4		ATOSEL3	ATOSEL3		ATOSEL2			ATOSEL1
0x20	SECCFGR	TAMPSEC	BHKLOCK							BKPWSEC							CNT1SEC								BKPRWSEC
0x24	PRIVCR	TAMPPRIV	BKPWPRIV	BKPRWPRIV													CNT1PRIV
0x2c	IER				ITAMP13IE	ITAMP12IE	ITAMP11IE		ITAMP9IE	ITAMP8IE	ITAMP7IE	ITAMP6IE	ITAMP5IE	ITAMP3IE	ITAMP2IE	ITAMP1IE									TAMP8IE	TAMP7IE	TAMP6IE	TAMP5IE	TAMP4IE	TAMP3IE	TAMP2IE	TAMP1IE
0x30	SR				ITAMP13IE	ITAMP12F	CITAMP11F		ITAMP9F	ITAMP8F	ITAMP7F	ITAMP6F	ITAMP5F	ITAMP3F	CITAMP2F	CITAMP1F									TAMP8F	TAMP7F	TAMP6F	TAMP5F	TAMP4F	TAMP3F	TAMP2F	TAMP1F
0x34	MISR				ITAMP13MF	ITAMP12MF	ITAMP11MF		ITAMP9MF	ITAMP8MF	ITAMP7MF	ITAMP6MF	ITAMP5MF	ITAMP3MF	ITAMP2MF	ITAMP1MF									TAMP8MF	TAMP7MF	TAMP6MF	TAMP5MF	TAMP4MF	TAMP3MF	TAMP2MF	TAMP1MF
0x38	SMISR				ITAMP13MF	ITAMP12MF	ITAMP11MF		ITAMP9MF	ITAMP8MF	ITAMP7MF	ITAMP6MF	ITAMP5MF	ITAMP3MF	ITAMP2MF	ITAMP1MF									TAMP8MF	TAMP7MF	TAMP6MF	TAMP5MF	TAMP4MF	TAMP3MF	TAMP2MF	TAMP1MF
0x3c	SCR				CITAMP13F	CITAMP12F	CITAMP11F		CITAMP9F	CITAMP8F_bit23	CITAMP7F_bit22	CITAMP6F_bit21	CITAMP5F	CITAMP3F	CITAMP2F	CITAMP1F									CITAMP8F	CITAMP7F	CTAMP6F	CTAMP5F	CTAMP4F	CTAMP3F	CTAMP2F	CTAMP1F
0x40	COUNT1R	COUNT															COUNT
0x54	ERCFGR																															ERCFG0
0x100	BKP0R	BKP															BKP
0x104	BKP1R	BKP															BKP
0x108	BKP2R	BKP															BKP
0x10c	BKP3R	BKP															BKP
0x110	BKP4R	BKP															BKP
0x114	BKP5R	BKP															BKP
0x118	BKP6R	BKP															BKP
0x11c	BKP7R	BKP															BKP
0x120	BKP8R	BKP															BKP
0x124	BKP9R	BKP															BKP
0x128	BKP10R	BKP															BKP
0x12c	BKP11R	BKP															BKP
0x130	BKP12R	BKP															BKP
0x134	BKP13R	BKP															BKP
0x138	BKP14R	BKP															BKP
0x13c	BKP15R	BKP															BKP
0x140	BKP16R	BKP															BKP
0x144	BKP17R	BKP															BKP
0x148	BKP18R	BKP															BKP
0x14c	BKP19R	BKP															BKP
0x150	BKP20R	BKP															BKP
0x154	BKP21R	BKP															BKP
0x158	BKP22R	BKP															BKP
0x15c	BKP23R	BKP															BKP
0x160	BKP24R	BKP															BKP
0x164	BKP25R	BKP															BKP
0x168	BKP26R	BKP															BKP
0x16c	BKP27R	BKP															BKP
0x170	BKP28R	BKP															BKP
0x174	BKP29R	BKP															BKP
0x178	BKP30R	BKP															BKP
0x17c	BKP31R	BKP															BKP

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13E rw	ITAMP12E rw	ITAMP11E rw		ITAMP9E rw	ITAMP8E rw	ITAMP7E rw	ITAMP6E rw	ITAMP5E rw		ITAMP3E rw	ITAMP2E rw	ITAMP1E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8E rw	TAMP7E rw	TAMP6E rw	TAMP5E rw	TAMP4E rw	TAMP3E rw	TAMP2E rw	TAMP1E rw

Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

TAMP4E

Bit 3: TAMP4E.

TAMP5E

Bit 4: TAMP5E.

TAMP6E

Bit 5: TAMP6E.

TAMP7E

Bit 6: TAMP7E.

TAMP8E

Bit 7: TAMP8E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP6E

Bit 21: ITAMP6E.

ITAMP7E

Bit 22: ITAMP7E.

ITAMP8E

Bit 23: ITAMP8E.

ITAMP9E

Bit 24: ITAMP9E.

ITAMP11E

Bit 26: TAMP1E.

ITAMP12E

Bit 27: ITAMP12E.

ITAMP13E

Bit 28: ITAMP13E.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TAMP8TRG rw	TAMP7TRG rw	TAMP6TRG rw	TAMP5TRG rw	TAMP4TRG rw	TAMP3TRG rw	TAMP2TRG rw	TAMP1TRG rw	BKERASE rw	BKBLOCK rw				TAMP3MSK rw	TAMP2MSK rw	TAMP1MSK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8NOER rw	TAMP7NOER rw	TAMP6NOER rw	TAMP5NOER rw	TAMP4NOER rw	TAMP3NOER rw	TAMP2NOER rw	TAMP1NOER rw

Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP4NOER

Bit 3: TAMP4NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKBLOCK

Bit 22: BKBLOCK.

BKERASE

Bit 23: BKERASE.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

TAMP4TRG

Bit 27: TAMP4TRG.

TAMP5TRG

Bit 28: TAMP5TRG.

TAMP6TRG

Bit 29: TAMP6TRG.

TAMP7TRG

Bit 30: TAMP7TRG.

TAMP8TRG

Bit 31: TAMP8TRG.

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ITAMP13NOER rw	ITAMP12NOER rw	ITAMP11NOER rw		ITAMP9NOER rw	TAMP8NOER rw	TAMP7NOER rw	TAMP6NOER rw	TAMP5NOER rw		ITAMP3NOER rw	ITAMP2NOER rw	ITAMP1NOER rw

Toggle fields

ITAMP1NOER

Bit 0: ITAMP1NOER.

ITAMP2NOER

Bit 1: ITAMP2NOER.

ITAMP3NOER

Bit 2: ITAMP3NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

ITAMP9NOER

Bit 8: ITAMP9NOER.

ITAMP11NOER

Bit 10: ITAMP11NOER.

ITAMP12NOER

Bit 11: ITAMP12NOER.

ITAMP13NOER

Bit 12: ITAMP13NOER.

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw

Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

TAMP active tamper control register

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FLTEN rw	ATOSHARE rw				ATPER rw								ATCKSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ATOSEL4 rw		ATOSEL3 rw		ATOSEL2 rw		ATOSEL1 rw		TAMP8AM rw	TAMP7AM rw	TAMP6AM rw	TAMP5AM rw	TAMP4AM rw	TAMP3AM rw	TAMP2AM rw	TAMP1AM rw

Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

TAMP4AM

Bit 3: TAMP4AM.

TAMP5AM

Bit 4: TAMP5AM.

TAMP6AM

Bit 5: TAMP6AM.

TAMP7AM

Bit 6: TAMP7AM.

TAMP8AM

Bit 7: TAMP8AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATOSEL4

Bits 14-15: ATOSEL4.

ATCKSEL

Bits 16-18: ATCKSEL.

ATPER

Bits 24-26: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: ATOSHARE.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEED rw

Toggle fields

SEED

Bits 0-31: SEED.

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INITS r	SEEDF r							PRNG r

Toggle fields

PRNG

Bits 0-7: PRNG.

SEEDF

Bit 14: SEEDF.

INITS

Bit 15: INITS.

ATCR2

TAMP active tamper control register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ATOSEL8 rw			ATOSEL7 rw			ATOSEL6 rw			ATOSEL5 rw				ATOSEL4 rw		ATOSEL3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ATOSEL3 rw		ATOSEL2 rw			ATOSEL1 rw

Toggle fields

ATOSEL1

Bits 8-10: ATOSEL1.

ATOSEL2

Bits 11-13: ATOSEL2.

ATOSEL3

Bits 14-16: ATOSEL3.

ATOSEL4

Bits 17-18: ATOSEL4.

ATOSEL5

Bits 20-22: ATOSEL5.

ATOSEL6

Bits 23-25: ATOSEL6.

ATOSEL7

Bits 26-28: ATOSEL7.

ATOSEL8

Bits 29-31: ATOSEL8.

SECCFGR

TAMP secure mode register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TAMPSEC rw	BHKLOCK rw							BKPWSEC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT1SEC rw								BKPRWSEC rw

Toggle fields

BKPRWSEC

Bits 0-7: BKPRWSEC.

CNT1SEC

Bit 15: CNT1SEC.

BKPWSEC

Bits 16-23: BKPWSEC.

BHKLOCK

Bit 30: BHKLOCK.

TAMPSEC

Bit 31: TAMPSEC.

PRIVCR

TAMP privilege mode control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TAMPPRIV rw	BKPWPRIV rw	BKPRWPRIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT1PRIV rw

Toggle fields

CNT1PRIV

Bit 15: CNT1PRIV.

BKPRWPRIV

Bit 29: BKPRWPRIV.

BKPWPRIV

Bit 30: BKPWPRIV.

TAMPPRIV

Bit 31: TAMPPRIV.

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13IE rw	ITAMP12IE rw	ITAMP11IE rw		ITAMP9IE rw	ITAMP8IE rw	ITAMP7IE rw	ITAMP6IE rw	ITAMP5IE rw		ITAMP3IE rw	ITAMP2IE rw	ITAMP1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8IE rw	TAMP7IE rw	TAMP6IE rw	TAMP5IE rw	TAMP4IE rw	TAMP3IE rw	TAMP2IE rw	TAMP1IE rw

Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

TAMP4IE

Bit 3: TAMP4IE.

TAMP5IE

Bit 4: TAMP5IE.

TAMP6IE

Bit 5: TAMP6IE.

TAMP7IE

Bit 6: TAMP7IE.

TAMP8IE

Bit 7: TAMP8IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP6IE

Bit 21: ITAMP6IE.

ITAMP7IE

Bit 22: ITAMP7IE.

ITAMP8IE

Bit 23: ITAMP8IE.

ITAMP9IE

Bit 24: ITAMP9IE.

ITAMP11IE

Bit 26: ITAMP11IE.

ITAMP12IE

Bit 27: ITAMP12IE.

ITAMP13IE

Bit 28: ITAMP13IE.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13IE r	ITAMP12F r	CITAMP11F r		ITAMP9F r	ITAMP8F r	ITAMP7F r	ITAMP6F r	ITAMP5F r		ITAMP3F r	CITAMP2F r	CITAMP1F r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8F r	TAMP7F r	TAMP6F r	TAMP5F r	TAMP4F r	TAMP3F r	TAMP2F r	TAMP1F r

Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

TAMP4F

Bit 3: TAMP4F.

TAMP5F

Bit 4: TAMP5F.

TAMP6F

Bit 5: TAMP6F.

TAMP7F

Bit 6: TAMP7F.

TAMP8F

Bit 7: TAMP8F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP6F

Bit 21: ITAMP6F.

ITAMP7F

Bit 22: ITAMP7F.

ITAMP8F

Bit 23: ITAMP8F.

ITAMP9F

Bit 24: ITAMP9F.

CITAMP11F

Bit 26: CITAMP11F.

ITAMP12F

Bit 27: ITAMP12F.

ITAMP13IE

Bit 28: ITAMP13IE.

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13MF r	ITAMP12MF r	ITAMP11MF r		ITAMP9MF r	ITAMP8MF r	ITAMP7MF r	ITAMP6MF r	ITAMP5MF r		ITAMP3MF r	ITAMP2MF r	ITAMP1MF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8MF r	TAMP7MF r	TAMP6MF r	TAMP5MF r	TAMP4MF r	TAMP3MF r	TAMP2MF r	TAMP1MF r

Toggle fields

TAMP1MF

Bit 0: TAMP1MF.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP6MF

Bit 21: ITAMP6MF.

ITAMP7MF

Bit 22: ITAMP7MF.

ITAMP8MF

Bit 23: ITAMP8MF.

ITAMP9MF

Bit 24: ITAMP9MF.

ITAMP11MF

Bit 26: ITAMP11MF.

ITAMP12MF

Bit 27: ITAMP12MF.

ITAMP13MF

Bit 28: ITAMP13MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			ITAMP13MF r	ITAMP12MF r	ITAMP11MF r		ITAMP9MF r	ITAMP8MF r	ITAMP7MF r	ITAMP6MF r	ITAMP5MF r		ITAMP3MF r	ITAMP2MF r	ITAMP1MF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TAMP8MF r	TAMP7MF r	TAMP6MF r	TAMP5MF r	TAMP4MF r	TAMP3MF r	TAMP2MF r	TAMP1MF r

Toggle fields

TAMP1MF

Bit 0: TAMP1MF.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP6MF

Bit 21: ITAMP6MF.

ITAMP7MF

Bit 22: ITAMP7MF.

ITAMP8MF

Bit 23: ITAMP8MF.

ITAMP9MF

Bit 24: ITAMP9MF.

ITAMP11MF

Bit 26: ITAMP11MF.

ITAMP12MF

Bit 27: ITAMP12MF.

ITAMP13MF

Bit 28: ITAMP13MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			CITAMP13F rw	CITAMP12F rw	CITAMP11F rw		CITAMP9F rw	CITAMP8F_bit23 rw	CITAMP7F_bit22 rw	CITAMP6F_bit21 rw	CITAMP5F rw		CITAMP3F rw	CITAMP2F rw	CITAMP1F rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CITAMP8F rw	CITAMP7F rw	CTAMP6F rw	CTAMP5F rw	CTAMP4F rw	CTAMP3F rw	CTAMP2F rw	CTAMP1F rw

Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CTAMP4F

Bit 3: CTAMP4F.

CTAMP5F

Bit 4: CTAMP5F.

CTAMP6F

Bit 5: CTAMP6F.

CITAMP7F

Bit 6: CITAMP3F.

CITAMP8F

Bit 7: CITAMP3F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP6F_bit21

Bit 21: CITAMP6F_bit21.

CITAMP7F_bit22

Bit 22: CITAMP7F_bit22.

CITAMP8F_bit23

Bit 23: CITAMP8F_bit23.

CITAMP9F

Bit 24: CITAMP9F.

CITAMP11F

Bit 26: CITAMP11F.

CITAMP12F

Bit 27: CITAMP12F.

CITAMP13F

Bit 28: CITAMP13F.

COUNT1R

TAMP monotonic counter 1register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COUNT r

Toggle fields

COUNT

Bits 0-31: COUNT.

ERCFGR

TAMP erase configuration register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															ERCFG0 rw

Toggle fields

ERCFG0

Bit 0: ERCFG0.

BKP0R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP1R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP2R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP3R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP4R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP5R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP6R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP7R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP8R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP9R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP10R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP11R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP12R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP13R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP14R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP15R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP16R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP17R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP18R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP19R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP20R

TAMP backup register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP21R

TAMP backup register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP22R

TAMP backup register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP23R

TAMP backup register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP24R

TAMP backup register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP25R

TAMP backup register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP26R

TAMP backup register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP27R

TAMP backup register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP28R

TAMP backup register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP29R

TAMP backup register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP30R

TAMP backup register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP31R

TAMP backup register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

TIM1

0x40012c00: Advanced-timers

1/229 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																				DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2							MMS_3		MMS2					OIS6		OIS5	OIS4N	OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS0_2			CCDS	CCUS		CCPC
0x8	SMCR							SMSPS	SMSPE			TS4_3					SMS3_0	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER									TERRIE	IERRIE	DIRIE	IDXIE						TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR									TERRF	IERRF	DIRF	IDXF			CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input																	IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output								OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input																	IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output								OC4M_bit3								OC3M_3	OC4CE	OC4M_3_0			OC4PE	OC4FE	CC4S_1_0		OC3CE	OC3M_2_0			OC3PE	OC3FE	CC3S_1_0
0x20	CCER											CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY																CNT
0x28	PSC																	PSC
0x2c	ARR													ARR				ARR
0x30	RCR																	REP
0x34	CCR1													CCR1				CCR1
0x38	CCR2													CCR2				CCR2
0x3c	CCR3													CCR3				CCR3
0x40	CCR4													CCR4				CCR4
0x44	BDTR			BK2BID	BKBID	BK2DSRAM	BKDSRM	BK2P	BK2E	BK2F				BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	CCR5	GC5C3	GC5C2	GC5C1										CCR5				CCR5
0x4c	CCR6													CCR6				CCR6
0x50	CCMR3								OC6M								OC5M2	OC6CE	OC6M1			OC6PE	OC6FE			OC5CE	OC5M1			OC5PE	OC5FE
0x54	DTR2															DTPE	DTAE									DTGF
0x58	ECR						PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL					TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1															ETRSEL		ETRSEL		BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP	BKCMP8E	BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2														OCRSEL					BK2CMP4P	BK2CMP3P	BK2CMP2P	BK2CMP1P	BK2INP	BK2CMP8E	BK2CMP7E	BK2CMP6E	BK2CMP5E	BK2CMP4E	BK2CMP3E	BK2CMP2E	BK2CMP1E	BK2INE
0x3dc	DCR													DBSS							DBL								DBA
0x3e0	DMAR	DMAB																DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw		MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OIS4N rw	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS0_2 rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS0_2

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS4N

Bit 15: Output Idle state 4 (OC5 output).

OIS5

Bit 16: Output Idle state 5.

OIS6

Bit 18: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

MMS_3

Bit 25: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS4_3 rw					SMS3_0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS3_0

Bit 16: Slave mode selection.

TS4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw			CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M_3_0 rw			OC4PE rw	OC4FE rw	CC4S_1_0 rw		OC3CE rw	OC3M_2_0 rw			OC3PE rw	OC3FE rw	CC3S_1_0 rw

Toggle fields

CC3S_1_0

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M_2_0

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S_1_0

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M_3_0

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output compare 3 mode.

OC4M_bit3

Bit 24: Output Compare 4 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		BK2BID rw	BKBID rw	BK2DSRAM rw	BKDSRM rw	BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRAM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

CCR5

alternate function register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw										CCR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-19: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

alternate function register 2

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CCR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-19: CCR6.

CCMR3

capture/compare mode register 3

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M rw								OC5M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M1 rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M1 rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M1

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M1

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M2

Bit 16: Output compare 5 mode.

OC6M

Bit 24: Output compare 6 mode.

DTR2

deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Dead-time falling edge generator setup.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

ECR

encoder control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti3[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti3[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw	BKCMP8E rw	BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKCMP8E

Bit 8: tim_brk_cmp8 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

ETRSEL

Bits 14-17: ETR source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BK2CMP4P rw	BK2CMP3P rw	BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2CMP8E rw	BK2CMP7E rw	BK2CMP6E rw	BK2CMP5E rw	BK2CMP4E rw	BK2CMP3E rw	BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2CMP3E

Bit 3: tim_brk2_cmp3 enable.

BK2CMP4E

Bit 4: tim_brk2_cmp4 enable.

BK2CMP5E

Bit 5: tim_brk2_cmp5 enable.

BK2CMP6E

Bit 6: tim_brk2_cmp6 enable.

BK2CMP7E

Bit 7: tim_brk2_cmp7 enable.

BK2CMP8E

Bit 8: tim_brk2_cmp8 enable.

BK2INP

Bit 9: TIMx_BKIN2 input polarity.

BK2CMP1P

Bit 10: tim_brk2_cmp1 input polarity.

BK2CMP2P

Bit 11: tim_brk2_cmp2 input polarity.

BK2CMP3P

Bit 12: tim_brk2_cmp3 input polarity.

BK2CMP4P

Bit 13: tim_brk2_cmp4 input polarity.

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

TIM15

0x40014000: General purpose timers

1/112 fields covered.

Toggle register map

Offset	Name	31	28	26	24	21	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1													DITHEN	UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2															OIS2	OIS1N	OIS1	TI1S		MMS		CCDS	CCUS		CCPC
0x8	SMCR					TS_4_3				SMS_3							CC1DE		MSM	TS_2_0				SMS
0xc	DIER											TDE	COMDE			CC2DE	CC1DE	UDE	BIE	TIE	COMIE			CC2IE	CC1IE	UIE
0x10	SR															CC2OF	CC1OF		BIF	TIF	COMIF			CC2IF	CC1IF	UIF
0x14	EGR																		BG	TG	COMG			CC2G	CC1G	UG
0x18	CCMR1_Input										IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output				OC2M_bit3					OC1M_bit3		OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																		CC2NP		CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY									CNT
0x28	PSC										PSC
0x2c	ARR						ARR				ARR
0x30	RCR																		REP
0x34	CCR1						CCR1				CCR1
0x38	CCR2						CCR2				CCR2
0x44	BDTR		BKBID	BKDSRM			BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x54	DTR2								DTPE	DTAE									DTGF
0x5c	TISEL														TI2SEL								TI1SEL
0x60	AF1												BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP		BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2							OCRSEL
0x3dc	DCR						DBSS							DBL								DBA
0x3e0	DMAR	DMAB									DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw		MMS rw		CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-5: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output idle state 2 (OC2 output).

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS_4_3 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1DE rw		MSM rw	TS_2_0 rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

SMS_3

Bit 16: Slave mode selection.

TS_4_3

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw			CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw			CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CC2OF rw	CC1OF rw		BIF rw	TIF rw	COMIF rw			CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG rw			CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/Compare 2 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC1M_bit3

Bit 16: Output Compare 1 mode.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CC2NP rw		CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output polarity.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DTR2

timer deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Dead-time falling edge generator setup.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

TISEL

input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects tim_ti1_in[0..15] input.

TI2SEL

Bits 8-11: selects tim_ti2_in[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw		BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: TIMx_BKIN input enable.

BKCMP1E

Bit 1: tim_brk_cmp1 enable.

BKCMP2E

Bit 2: tim_brk_cmp2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: tim_brk_cmp1 input polarity.

BKCMP2P

Bit 11: tim_brk_cmp2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

TIM16

0x40014400: General purpose timers

1/80 fields covered.

Toggle register map

Offset	Name	31	28	26	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2														OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER										COMDE				CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR														CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR																BG		COMG				CC1G	UG
0x18	CCMR1_Input																IC1F				IC1PSC		CC1S
0x18	CCMR1_Output							OC1M_2									OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																				CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY							CNT
0x28	PSC								PSC
0x2c	ARR				ARR				ARR
0x30	RCR																REP
0x34	CCR1				CCR1				CCR1
0x44	BDTR		BKBID	BKDSRM					MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x50	OR1																							HSE32EN
0x54	DTR2						DTPE	DTAE									DTGF
0x5c	TISEL																				TI1SEL
0x60	AF1										BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP		BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2					OCRSEL
0x3dc	DCR				DBSS							DBL								DBA
0x3e0	DMAR	DMAB							DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		COMDE rw				CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: CC1OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

OR1

option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															HSE32EN rw

Toggle fields

HSE32EN

Bit 0: HSE Divided by 32 enable.

DTR2

timer deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Deadtime asymmetric enable.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

TISEL

TIM17 option register 1

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects tim_ti1_in[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw		BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: TIMx_BKIN input enable.

BKCMP1E

Bit 1: tim_brk_cmp1 enable.

BKCMP2E

Bit 2: tim_brk_cmp2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: tim_brk_cmp1 input polarity.

BKCMP2P

Bit 11: tim_brk_cmp2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: tim_ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

TIM17 option register 1

Offset: 0x3e0, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

TIM17

0x40014800: General purpose timers

1/80 fields covered.

Toggle register map

Offset	Name	31	28	26	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2														OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER										COMDE				CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR														CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR																BG		COMG				CC1G	UG
0x18	CCMR1_Input																IC1F				IC1PSC		CC1S
0x18	CCMR1_Output							OC1M_2									OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																				CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY							CNT
0x28	PSC								PSC
0x2c	ARR				ARR				ARR
0x30	RCR																REP
0x34	CCR1				CCR1				CCR1
0x44	BDTR		BKBID	BKDSRM					MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x50	OR1																							HSE32EN
0x54	DTR2						DTPE	DTAE									DTGF
0x5c	TISEL																				TI1SEL
0x60	AF1										BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP		BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2					OCRSEL
0x3dc	DCR				DBSS							DBL								DBA
0x3e0	DMAR	DMAB							DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		COMDE rw				CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/Compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: CC1OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

OR1

option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															HSE32EN rw

Toggle fields

HSE32EN

Bit 0: HSE Divided by 32 enable.

DTR2

timer deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Deadtime asymmetric enable.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

TISEL

TIM17 option register 1

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects tim_ti1_in[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw		BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: TIMx_BKIN input enable.

BKCMP1E

Bit 1: tim_brk_cmp1 enable.

BKCMP2E

Bit 2: tim_brk_cmp2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: tim_brk_cmp1 input polarity.

BKCMP2P

Bit 11: tim_brk_cmp2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: tim_ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

TIM17 option register 1

Offset: 0x3e0, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

TIM2

0x40000000: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

TIM3

0x40000400: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

TIM4

0x40000800: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

TIM5

0x40000c00: General-purpose-timers

0/140 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																		DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2					MMS_3																		TI1S	MMS			CCDS
0x8	SMCR					SMSPS	SMSPE			TS_4_3					SMS_bit3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS
0xc	DIER							TERRIE	IERRIE	DIRIE	IDXIE						TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR							TERRF	IERRF	DIRF	IDXF								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input															IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output						OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input															IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output						OC4M_bit3								OC3M_bit3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER															CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT_bit31	CNT_H													CNT_L
0x28	PSC															PSC
0x2c	ARR	ARR_H														ARR_L
0x34	CCR1	CCR1_H														CCR1_L
0x38	CCR2	CCR2_H														CCR2_L
0x3c	CCR3	CCR3_H														CCR3_L
0x40	CCR4	CCR4_H														CCR4_L
0x58	ECR				PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL			TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1													ETRSEL		ETRSEL
0x64	AF2												OCRSEL
0x3dc	DCR											DBSS							DBL								DBA
0x3e0	DMAR	ETRSEL														ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

MMS_3

Bit 25: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS_4_3 rw					SMS_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS_2_0

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC4M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT_bit31 rw	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

ECR

DMA address for full transfer

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti1[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti2[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-17: etr_in source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 0-31: DMA register for burst accesses.

TIM6

0x40001000: General-purpose-timers

0/16 fields covered.

Toggle register map

Offset	Name	31	19	15	12	11	8	7	6	3	2	1	0
0x0	CR1				DITHEN	UIFREMAP		ARPE		OPM	URS	UDIS	CEN
0x4	CR2								MMS
0xc	DIER						UDE						UIE
0x10	SR												UIF
0x14	EGR												UG
0x24	CNT	UIFCPY		CNT
0x28	PSC			PSC
0x2c	ARR		ARR	ARR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw				ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle register map

Offset	Name	31	19	15	12	11	8	7	6	3	2	1	0
0x0	CR1				DITHEN	UIFREMAP		ARPE		OPM	URS	UDIS	CEN
0x4	CR2								MMS
0xc	DIER						UDE						UIE
0x10	SR												UIF
0x14	EGR												UG
0x24	CNT	UIFCPY		CNT
0x28	PSC			PSC
0x2c	ARR		ARR	ARR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw				ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering Enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																				DITHEN	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2							MMS_3		MMS2					OIS6		OIS5	OIS4N	OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS0_2			CCDS	CCUS		CCPC
0x8	SMCR							SMSPS	SMSPE			TS4_3					SMS3_0	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER									TERRIE	IERRIE	DIRIE	IDXIE						TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR									TERRF	IERRF	DIRF	IDXF			CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																								B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input																	IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output								OC2M_bit3								OC1M_bit3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input																	IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output								OC4M_bit3								OC3M_3	OC4CE	OC4M_3_0			OC4PE	OC4FE	CC4S_1_0		OC3CE	OC3M_2_0			OC3PE	OC3FE	CC3S_1_0
0x20	CCER											CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY																CNT
0x28	PSC																	PSC
0x2c	ARR													ARR				ARR
0x30	RCR																	REP
0x34	CCR1													CCR1				CCR1
0x38	CCR2													CCR2				CCR2
0x3c	CCR3													CCR3				CCR3
0x40	CCR4													CCR4				CCR4
0x44	BDTR			BK2BID	BKBID	BK2DSRAM	BKDSRM	BK2P	BK2E	BK2F				BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	CCR5	GC5C3	GC5C2	GC5C1										CCR5				CCR5
0x4c	CCR6													CCR6				CCR6
0x50	CCMR3								OC6M								OC5M2	OC6CE	OC6M1			OC6PE	OC6FE			OC5CE	OC5M1			OC5PE	OC5FE
0x54	DTR2															DTPE	DTAE									DTGF
0x58	ECR						PWPRSC			PW																IPOS		FIDX			IDIR		IE
0x5c	TISEL					TI4SEL								TI3SEL								TI2SEL								TI1SEL
0x60	AF1															ETRSEL		ETRSEL		BKCMP4P	BKCMP3P	BKCMP2P	BKCMP1P	BKINP	BKCMP8E	BKCMP7E	BKCMP6E	BKCMP5E	BKCMP4E	BKCMP3E	BKCMP2E	BKCMP1E	BKINE
0x64	AF2														OCRSEL					BK2CMP4P	BK2CMP3P	BK2CMP2P	BK2CMP1P	BK2INP	BK2CMP8E	BK2CMP7E	BK2CMP6E	BK2CMP5E	BK2CMP4E	BK2CMP3E	BK2CMP2E	BK2CMP1E	BK2INE
0x3dc	DCR													DBSS							DBL								DBA
0x3e0	DMAR	DMAB																DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DITHEN rw	UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

DITHEN

Bit 12: Dithering enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						MMS_3 rw		MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OIS4N rw	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS0_2 rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS0_2

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS4N

Bit 15: Output Idle state 4 (OC5 output).

OIS5

Bit 16: Output Idle state 5.

OIS6

Bit 18: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

MMS_3

Bit 25: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SMSPS rw	SMSPE rw			TS4_3 rw					SMS3_0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS3_0

Bit 16: Slave mode selection.

TS4_3

Bits 20-21: Trigger selection.

SMSPE

Bit 24: SMS preload enable.

SMSPS

Bit 25: SMS preload source.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRIE rw	IERRIE rw	DIRIE rw	IDXIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

IDXIE

Bit 20: Index interrupt enable.

DIRIE

Bit 21: Direction change interrupt enable.

IERRIE

Bit 22: Index error interrupt enable.

TERRIE

Bit 23: Transition error interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TERRF rw	IERRF rw	DIRF rw	IDXF rw			CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

IDXF

Bit 20: Index interrupt flag.

DIRF

Bit 21: Direction change interrupt flag.

IERRF

Bit 22: Index error interrupt flag.

TERRF

Bit 23: Transition error interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_bit3 rw								OC1M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_bit3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_bit3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M_3_0 rw			OC4PE rw	OC4FE rw	CC4S_1_0 rw		OC3CE rw	OC3M_2_0 rw			OC3PE rw	OC3FE rw	CC3S_1_0 rw

Toggle fields

CC3S_1_0

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M_2_0

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S_1_0

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M_3_0

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output compare 3 mode.

OC4M_bit3

Bit 24: Output Compare 4 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		BK2BID rw	BKBID rw	BK2DSRAM rw	BKDSRM rw	BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRAM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

CCR5

alternate function register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw										CCR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-19: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

alternate function register 2

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CCR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-19: CCR6.

CCMR3

capture/compare mode register 3

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M rw								OC5M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M1 rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M1 rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M1

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M1

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M2

Bit 16: Output compare 5 mode.

OC6M

Bit 24: Output compare 6 mode.

DTR2

deadtime register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DTPE rw	DTAE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DTGF rw

Toggle fields

DTGF

Bits 0-7: Dead-time falling edge generator setup.

DTAE

Bit 16: Deadtime asymmetric enable.

DTPE

Bit 17: Deadtime preload enable.

ECR

encoder control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PWPRSC rw			PW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IPOS rw		FIDX rw			IDIR rw		IE rw

Toggle fields

IE

Bit 0: Index enable.

IDIR

Bits 1-2: Index direction.

FIDX

Bit 5: First index.

IPOS

Bits 6-7: Index positioning.

PW

Bits 16-23: Pulse width.

PWPRSC

Bits 24-26: Pulse width prescaler.

TISEL

timer input selection register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: Selects tim_ti3[0..15] input.

TI2SEL

Bits 8-11: Selects tim_ti3[0..15] input.

TI3SEL

Bits 16-19: Selects tim_ti3[0..15] input.

TI4SEL

Bits 24-27: Selects tim_ti4[0..15] input.

AF1

alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw		BKCMP4P rw	BKCMP3P rw	BKCMP2P rw	BKCMP1P rw	BKINP rw	BKCMP8E rw	BKCMP7E rw	BKCMP6E rw	BKCMP5E rw	BKCMP4E rw	BKCMP3E rw	BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKCMP3E

Bit 3: tim_brk_cmp3 enable.

BKCMP4E

Bit 4: tim_brk_cmp4 enable.

BKCMP5E

Bit 5: tim_brk_cmp5 enable.

BKCMP6E

Bit 6: tim_brk_cmp6 enable.

BKCMP7E

Bit 7: tim_brk_cmp7 enable.

BKCMP8E

Bit 8: tim_brk_cmp8 enable.

BKINP

Bit 9: TIMx_BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

BKCMP3P

Bit 12: tim_brk_cmp3 input polarity.

BKCMP4P

Bit 13: tim_brk_cmp4 input polarity.

ETRSEL

Bits 14-17: ETR source selection.

AF2

alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OCRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BK2CMP4P rw	BK2CMP3P rw	BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2CMP8E rw	BK2CMP7E rw	BK2CMP6E rw	BK2CMP5E rw	BK2CMP4E rw	BK2CMP3E rw	BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2CMP3E

Bit 3: tim_brk2_cmp3 enable.

BK2CMP4E

Bit 4: tim_brk2_cmp4 enable.

BK2CMP5E

Bit 5: tim_brk2_cmp5 enable.

BK2CMP6E

Bit 6: tim_brk2_cmp6 enable.

BK2CMP7E

Bit 7: tim_brk2_cmp7 enable.

BK2CMP8E

Bit 8: tim_brk2_cmp8 enable.

BK2INP

Bit 9: TIMx_BKIN2 input polarity.

BK2CMP1P

Bit 10: tim_brk2_cmp1 input polarity.

BK2CMP2P

Bit 11: tim_brk2_cmp2 input polarity.

BK2CMP3P

Bit 12: tim_brk2_cmp3 input polarity.

BK2CMP4P

Bit 13: tim_brk2_cmp4 input polarity.

OCRSEL

Bits 16-18: ocref_clr source selection.

DCR

DMA control register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DBSS

Bits 16-19: DMA burst source selection.

DMAR

DMA address for full transfer

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

TSC

0x40024000: Touch sensing controller

18/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR	CTPH				CTPL				SSD							SSE	SSPSC	PGPSC							MCV			IODEF	SYNCPOL	AM	START	TSCE
0x4	IER																															MCEIE	EOAIE
0x8	ICR																															MCEIC	EOAIC
0xc	ISR																															MCEF	EOAF
0x10	IOHCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x18	IOASCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x20	IOSCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x28	IOCCR	G8_IO4	G8_IO3	G8_IO2	G8_IO1	G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x30	IOGCSR									G8S	G7S	G6S	G5S	G4S	G3S	G2S	G1S									G8E	G7E	G6E	G5E	G4E	G3E	G2E	G1E
0x34	IOG1CR																			CNT
0x38	IOG2CR																			CNT
0x3c	IOG3CR																			CNT
0x40	IOG4CR																			CNT
0x44	IOG5CR																			CNT
0x48	IOG6CR																			CNT
0x4c	IOG7CR																			CNT
0x50	IOG8CR																			CNT

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTPH rw				CTPL rw				SSD rw							SSE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSPSC rw	PGPSC rw							MCV rw			IODEF rw	SYNCPOL rw	AM rw	START rw	TSCE rw

Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIE rw	EOAIE rw

Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIC rw	EOAIC rw

Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEF r	EOAF r

Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
G8_IO4 rw	G8_IO3 rw	G8_IO2 rw	G8_IO1 rw	G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								G8S r	G7S r	G6S r	G5S r	G4S r	G3S r	G2S r	G1S r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								G8E rw	G7E rw	G6E rw	G5E rw	G4E rw	G3E rw	G2E rw	G1E rw

Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

50/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

50/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

50/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE		EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER
0x30	AUTOCR	TECLREN									TRIGSEL				IDLEDIS	TRIGEN	TRIGPOL	TDN

Toggle registers

CR1_disabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

CR1_enabled

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXFNFIE

Bit 7: TXFIFO not full interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt.

EOBIE

Bit 27: End of Block interruptenable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD

Bits 24-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR_disabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: UDR.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: TCBGT.

ISR_enabled

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x028000C0, access: read-only

26/26 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r		EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXFNE

Bit 5: RXFNE.

TC

Bit 6: TC.

TXFNF

Bit 7: TXFNF.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NECF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

AUTOCR

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TECLREN rw									TRIGSEL rw				IDLEDIS rw	TRIGEN rw	TRIGPOL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDN rw

Toggle fields

TDN

Bits 0-15: TDN.

TRIGPOL

Bit 16: TRIPOL.

TRIGEN

Bit 17: TRIGEN.

IDLEDIS

Bit 18: IDLEDIS.

TRIGSEL

Bits 19-22: TRIGSEL.

TECLREN

Bit 31: TECLREN.

VREFBUF

0x46007400: Voltage reference buffer

1/5 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	VREFBUF_CSR																										VRS			VRR		HIZ	ENVR
0x4	VREFBUF_CCR																											TRIM

Toggle registers

VREFBUF_CSR

VREFBUF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VRS rw			VRR r		HIZ rw	ENVR rw

Toggle fields

ENVR

Bit 0: ENVR.

HIZ

Bit 1: HIZ.

VRR

Bit 3: VRR.

VRS

Bits 4-6: VRS.

VREFBUF_CCR

VREFBUF calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRIM rw

Toggle fields

TRIM

Bits 0-5: TRIM.

WWDG

0x40002c00: System window watchdog

0/6 fields covered.

Toggle register map

Offset	Name	13	9	7	6	0
0x0	CR			WDGA	T
0x4	CFR	WDGTB	EWI		W
0x8	SR					EWIF

Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		WDGTB rw				EWI rw			W rw

Toggle fields

W

Bits 0-6: 7-bit window value.

EWI

Bit 9: Early wakeup interrupt.

WDGTB

Bits 11-13: Timer base.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.