ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

Allowed values:
0: NotReady: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase..

Allowed values:
0: NotAtEnd: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
1: AtEnd: End of sampling phase reached

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

Allowed values:
0: NotComplete: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
1: Complete: Regular channel conversion complete

EOS

Bit 3: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
1: Complete: Regular conversions sequence complete

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it..

Allowed values:
0: NoOverrun: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun: Overrun has occurred

JEOC

Bit 5: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register.

Allowed values:
0: NotComplete: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
1: Complete: Injected channel conversion complete

JEOS

Bit 6: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
1: Complete: Injected conversions sequence complete

AWD1

Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_LTR1, & ADC_HTR1 register. It is cleared by software. writing 1 to it..

Allowed values:
0: NoEvent: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
1: Event: Analog watchdog x event occurred

AWD2

Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_LTR2 & ADC_HTR2 register. It is cleared by software writing 1 to it..

Allowed values:
0: NoEvent: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
1: Event: Analog watchdog x event occurred

AWD3

Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_LTR3 & ADC_HTR3 register. It is cleared by software writing 1 to it..

Allowed values:
0: NoEvent: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
1: Event: Analog watchdog x event occurred

LDORDY

Bit 12: ADC voltage regulator ready This bit is set by hardware. It indicates that the ADC internal supply is ready. The ADC is available after tADCVREG_SETUP time..

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: ADRDY interrupt disabled
1: Enabled: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: EOSMP interrupt disabled
1: Enabled: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: EOS interrupt disabled
1: Enabled: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

JEOCIE

Bit 5: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: Software is allowed to write this bit only when JADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: JEOC interrupt disable
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

JEOSIE

Bit 6: End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: Software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: JEOS interrupt disabled
1: Enabled: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.

AWD1IE

Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog x interrupt disabled
1: Enabled: Analog watchdog x interrupt enabled

AWD2IE

Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog x interrupt disabled
1: Enabled: Analog watchdog x interrupt enabled

AWD3IE

Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog x interrupt disabled
1: Enabled: Analog watchdog x interrupt enabled

ADEN

Bit 0: ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator).

Allowed values:
0: Disabled: ADC is disabled
1: Enabled: ADC is enabled

ADDIS

Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: NotOngoing: No ADDIS command ongoing
1: InProgress: An ADDIS command is in progress

ADSTART

Bit 2: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion starts immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode (CONT = 0, DISCEN = 0) when software trigger is selected (EXTEN[1:0] = 0x0): at the assertion of the end of regular conversion sequence (EOS) flag. In Discontinuous conversion mode (CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN[1:0] = 0x0): at the end of conversion (EOC) flag. in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).

Allowed values:
0: NotActive: No ADC regular conversion is ongoing
1: Active: ADC is operating and eventually converting a regular channel

JADSTART

Bit 3: ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion starts immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the end of injected conversion sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time as JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In Auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).

Allowed values:
0: NotActive: No ADC injected conversion is ongoing
1: Active: ADC is operating and eventually converting an injected channel

ADSTP

Bit 4: ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)..

Allowed values:
0: NotStopping: No ADC stop regular conversion command ongoing
1: Stopping: ADSTP command is in progress

JADSTP

Bit 5: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).

Allowed values:
0: NotStopped: No ADC stop injected conversion command ongoing
1: Stopped: ADSTP command is in progress

ADCALLIN

Bit 16: Linearity calibration This bit is set and cleared by software to enable the linearity calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: Writing ADCAL launches a calibration without the linearity calibration
1: Enabled: Writing ADCAL launches a calibration with he linearity calibration

CALINDEX

Bits 24-27: Calibration factor This bitfield controls the calibration factor to be read or written. Calibration index 0 is dedicated to single-ended and differential offsets, calibration index 1 to 7 to the linearity calibration factors, and index 8 to the internal offset: Others: Reserved, must not be used Note: ADC_CALFACT2[31:0] correspond to the location of CALINDEX[3:0] calibration factor data (see for details)..

Allowed values:
0: OffsetCalFactor: Offset calibration factor
1: CalFactor1: Calibration factor 1
2: CalFactor2: Calibration factor 2
3: CalFactor3: Calibration factor 3
4: CalFactor4: Calibration factor 4
5: CalFactor5: Calibration factor 5
6: CalFactor6: Calibration factor 6
7: CalFactor7: Calibration factor 7 and (write access only) internal offset
8: InternalOffset: Internal offset (read access only)
9: CalibrationMode: Calibration mode selection

ADVREGEN

Bit 28: ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

DEEPPWD

Bit 29: Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: ADC not in deep-power down
1: Enabled: ADC in deep-power down

ADCAL

Bit 31: ADC calibration This bit is set by software to start the ADC calibration. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0..

Allowed values:
0: NotCalibrating: Calibration complete
1: Calibrating: Calibration in progress

DMNGT

Bits 0-1: Data management configuration This bit is set and cleared by software to select how the ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: DR: Store output data in DR only
1: DMA_OneShot: DMA One Shot Mode selected
2: DFSDM: DFSDM mode selected
3: DMA_Circular: DMA Circular Mode selected

RES

Bits 2-3: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: FourteenBit: 14 bits
1: TwelveBit: 12 bits
2: TenBit: 10 bits
3: EightBit: 8 bits

EXTSEL

Bits 5-9: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Refer to the ADC external trigger for regular channels in signals for details on trigger mapping. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: TIM1_OC1: tim1_oc1
1: TIM1_OC2: tim1_oc2
2: TIM1_OC3: tim1_oc3
3: TIM2_OC2: tim2_oc2
4: TIM3_TRGO: tim3_trgo
5: TIM4_OC4: tim4_oc4
6: EXTI11: exti11
7: TIM8_TRGO: tim8_trgo
8: TIM8_TRGO2: tim8_trgo2
9: TIM1_TRGO: tim1_trgo
10: TIM1_TRGO2: tim1_trgo2
11: TIM2_TRGO: tim2_trgo
12: TIM4_TRGO: tim4_trgo
13: TIM6_TRGO: tim6_trgo
14: TIM15_TRGO: tim15_trgo
15: TIM3_OC4: tim3_oc4
16: EXTI15: exti15
18: LPTIM1_CH1: lptim1_ch1
19: LPTIM2_CH1: lptim2_ch1
20: LPTIM3_CH1: lptim3_ch1
21: LPTIM4_OUT: lptim4_out

EXTEN

Bits 10-11: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Hardware trigger detection disabled (conversions can be launched by software)
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Preserve: ADC_DR register is preserved with the old data when an overrun is detected
1: Overwrite: ADC_DR register is overwritten with the last conversion result when an overrun is detected

CONT

Bit 13: Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Auto-delayed conversion mode off
1: Enabled: Auto-delayed conversion mode on

DISCEN

Bit 16: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Discontinuous mode for regular channels disabled
1: Enabled: Discontinuous mode for regular channels enabled

DISCNUM

Bits 17-19: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: n1: 1 channel
1: n2: 2 channels
2: n3: 3 channels
3: n4: 4 channels
4: n5: 5 channels
5: n6: 6 channels
6: n7: 7 channels
7: n8: 8 channels

JDISCEN

Bit 20: Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set..

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

AWD1SGL

Bit 22: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: AllChannels: Analog watchdog 1 enabled on all channels
1: SingleChannel: Analog watchdog 1 enabled on a single channel

AWD1EN

Bit 23: Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing)..

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0x13

ROVSE

Bit 0: Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: Disabled: Regular oversampling disabled
1: Enabled: Regular oversampling enabled

JOVSE

Bit 1: Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: Disabled: Injected oversampling disabled
1: Enabled: Injected oversampling enabled

OVSS

Bits 5-8: Oversampling right shift This bit field is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xb

TROVS

Bit 9: Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Automatic: All oversampled conversions for a channel are done consecutively following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Continued: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: Resumed: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

BULB

Bit 13: Bulb sampling mode This bit is set and cleared by software to select the bulb sampling mode. SMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Bulb sampling mode disabled
1: Enabled: Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion.

SWTRIG

Bit 14: Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Software trigger starts the conversion for sampling time control trigger mode
1: Enabled: Software trigger starts the sampling for sampling time control trigger mode

SMPTRIG

Bit 15: Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN[1:0] bits must be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN[1:0] bits is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Sampling time control trigger mode disabled
1: Enabled: Sampling time control trigger mode enabled

OSR

Bits 16-25: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x ... 1023: 1024x Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0x3ff

LFTRIG

Bit 27: Low-frequency trigger This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Low-frequency trigger mode disabled
1: Enabled: Low-frequency trigger mode enabled

LSHIFT

Bits 28-31: Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xf

SMP0

Bits 0-2: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP1

Bits 3-5: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP2

Bits 6-8: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP3

Bits 9-11: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP4

Bits 12-14: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP5

Bits 15-17: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP6

Bits 18-20: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP7

Bits 21-23: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP8

Bits 24-26: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP9

Bits 27-29: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP10

Bits 0-2: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP11

Bits 3-5: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP12

Bits 6-8: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP13

Bits 9-11: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP14

Bits 12-14: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP15

Bits 15-17: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP16

Bits 18-20: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP17

Bits 21-23: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP18

Bits 24-26: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

SMP19

Bits 27-29: Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Cycles5: 5 ADC clock cycles
1: Cycles6: 6 ADC clock cycles
2: Cycles12: 12 ADC clock cycles
3: Cycles20: 20 ADC clock cycles
4: Cycles36: 36 ADC clock cycles
5: Cycles68: 68 ADC clock cycles
6: Cycles391: 391 ADC clock cycles
7: Cycles814: 814 ADC clock cycles

PCSEL0

Bit 0: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL1

Bit 1: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL2

Bit 2: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL3

Bit 3: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL4

Bit 4: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL5

Bit 5: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL6

Bit 6: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL7

Bit 7: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL8

Bit 8: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL9

Bit 9: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL10

Bit 10: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL11

Bit 11: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL12

Bit 12: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL13

Bit 13: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL14

Bit 14: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL15

Bit 15: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL16

Bit 16: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL17

Bit 17: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL18

Bit 18: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

PCSEL19

Bit 19: Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel I/O instance to be converted. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotPreselected: Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
1: Preselected: Input channel x is preselected for conversion

L

Bits 0-3: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0xf

SQ1

Bits 6-10: 1st conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ2

Bits 12-16: 2nd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ3

Bits 18-22: 3rd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ4

Bits 24-28: 4th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the regular conversion sequence..

Allowed values: 0x0-0x1f

SQ5

Bits 0-4: 5th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ6

Bits 6-10: 6th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ7

Bits 12-16: 7th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ8

Bits 18-22: 8th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ9

Bits 24-28: 9th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ10

Bits 0-4: 10th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ11

Bits 6-10: 11th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ12

Bits 12-16: 12th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ13

Bits 18-22: 13th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ14

Bits 24-28: 14th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ15

Bits 0-4: 15th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

SQ16

Bits 6-10: 16th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0x1f

RDATA

Bits 0-31: Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in ..

JL

Bits 0-1: Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-6: External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Refer to the ADC external trigger for injected channels in internal signals for details on trigger mapping. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values:
0: TIM1_TRGO: tim1_trgo
1: TIM1_OC4: tim1_oc4
2: TIM2_TRGO: tim2_trgo
3: TIM2_OC1: tim2_oc1
4: TIM3_OC4: tim3_oc4
5: TIM4_TRGO: tim4_trgo
6: EXTI15: exti15
7: TIM8_OC4: tim8_oc4
8: TIM1_TRGO2: tim1_trgo2
9: TIM8_TRGO: tim8_trgo
10: TIM8_TRGO2: tim8_trgo2
11: TIM3_OC3: tim3_oc3
12: TIM3_TRGO: tim3_trgo
13: TIM3_OC1: tim3_oc1
14: TIM6_TRGO: tim6_trgo
15: TIM15_TRGO: tim15_trgo
16: LPTIM1_CH2: lptim1_ch2
17: LPTIM2_CH2: lptim2_ch2
18: LPTIM3_CH1: lptim3_ch1
19: LPTIM4_OUT1: lptim4_out1

JEXTEN

Bits 7-8: External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values:
0: Disabled: Hardware trigger detection disabled (conversions can be launched by software)
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges

JSQ1

Bits 9-13: 1st conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values: 0x0-0x1f

JSQ2

Bits 15-19: 2nd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values: 0x0-0x1f

JSQ3

Bits 21-25: 3rd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values: 0x0-0x1f

JSQ4

Bits 27-31: 4th conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing..

Allowed values: 0x0-0x1f

OFFSET

Bits 0-23: Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (regular or injected). The channel to which the data offset y applies must be programmed to the OFFSETy_CH[4:0] bits. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[21:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offsets (OFFSETy) point to the same channel, only the offset with the lowest y value is considered for the subtraction. For example, if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[25:0] that is subtracted when converting channel 4..

Allowed values: 0x0-0xffffff

POSOFF

Bit 24: offset sign This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Negative: Negative offset
1: Positive: Positive offset

USAT

Bit 25: Unsigned saturation enable This bit is written by software to enable or disable the unsigned saturation feature. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and keeping converted data size
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

SSAT

Bit 26: Signed saturation enable This bit is written by software to enable or disable the Signed saturation feature. (see OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT) for details). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

OFFSET_CH

Bits 27-31: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into OFFSETy[25:0] bits applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If OFFSETy_EN bit is set, it is not allowed to select the same channel in different ADC_OFRy registers..

Allowed values: 0x0-0x1f

OFFSET

Bits 0-23: Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (regular or injected). The channel to which the data offset y applies must be programmed to the OFFSETy_CH[4:0] bits. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[21:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offsets (OFFSETy) point to the same channel, only the offset with the lowest y value is considered for the subtraction. For example, if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[25:0] that is subtracted when converting channel 4..

Allowed values: 0x0-0xffffff

POSOFF

Bit 24: offset sign This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Negative: Negative offset
1: Positive: Positive offset

USAT

Bit 25: Unsigned saturation enable This bit is written by software to enable or disable the unsigned saturation feature. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and keeping converted data size
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

SSAT

Bit 26: Signed saturation enable This bit is written by software to enable or disable the Signed saturation feature. (see OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT) for details). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

OFFSET_CH

Bits 27-31: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into OFFSETy[25:0] bits applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If OFFSETy_EN bit is set, it is not allowed to select the same channel in different ADC_OFRy registers..

Allowed values: 0x0-0x1f

OFFSET

Bits 0-23: Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (regular or injected). The channel to which the data offset y applies must be programmed to the OFFSETy_CH[4:0] bits. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[21:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offsets (OFFSETy) point to the same channel, only the offset with the lowest y value is considered for the subtraction. For example, if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[25:0] that is subtracted when converting channel 4..

Allowed values: 0x0-0xffffff

POSOFF

Bit 24: offset sign This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Negative: Negative offset
1: Positive: Positive offset

USAT

Bit 25: Unsigned saturation enable This bit is written by software to enable or disable the unsigned saturation feature. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and keeping converted data size
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

SSAT

Bit 26: Signed saturation enable This bit is written by software to enable or disable the Signed saturation feature. (see OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT) for details). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

OFFSET_CH

Bits 27-31: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into OFFSETy[25:0] bits applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If OFFSETy_EN bit is set, it is not allowed to select the same channel in different ADC_OFRy registers..

Allowed values: 0x0-0x1f

OFFSET

Bits 0-23: Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (regular or injected). The channel to which the data offset y applies must be programmed to the OFFSETy_CH[4:0] bits. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[21:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offsets (OFFSETy) point to the same channel, only the offset with the lowest y value is considered for the subtraction. For example, if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[25:0] that is subtracted when converting channel 4..

Allowed values: 0x0-0xffffff

POSOFF

Bit 24: offset sign This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Negative: Negative offset
1: Positive: Positive offset

USAT

Bit 25: Unsigned saturation enable This bit is written by software to enable or disable the unsigned saturation feature. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and keeping converted data size
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

SSAT

Bit 26: Signed saturation enable This bit is written by software to enable or disable the Signed saturation feature. (see OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT) for details). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain converted data size

OFFSET_CH

Bits 27-31: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into OFFSETy[25:0] bits applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If OFFSETy_EN bit is set, it is not allowed to select the same channel in different ADC_OFRy registers..

Allowed values: 0x0-0x1f

GCOMPCOEFF

Bits 0-13: Gain compensation coefficient These bits are set and cleared by software to program the gain compensation coefficient. ... ... The coefficient is divided by 4096 to get the gain factor ranging from 0 to 3.999756. Note: This gain compensation is only applied when GCOMP bit of ADCx_CFGR2 register is 1..

Allowed values: 0x0-0x3fff

GCOMP

Bit 31: Gain compensation mode This bit is set and cleared by software to enable the gain compensation mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Regular ADC operating mode
1: Enabled: Gain compensation enabled and applied to all channels

JDATA

Bits 0-31: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ..

Allowed values: 0x0-0xffffffff

JDATA

Bits 0-31: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ..

Allowed values: 0x0-0xffffffff

JDATA

Bits 0-31: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ..

Allowed values: 0x0-0xffffffff

JDATA

Bits 0-31: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ..

Allowed values: 0x0-0xffffffff

AWD2CH

Bits 0-19: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: ADC analog input channel x is not monitored by AWDy
1: Enabled: ADC analog input channel x is monitored by AWDy

AWD3CH

Bits 0-19: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: ADC analog input channel x is not monitored by AWDy
1: Enabled: ADC analog input channel x is monitored by AWDy

LTR1

Bits 0-24: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)..

Allowed values: 0x0-0x1ffffff

HTR1

Bits 0-24: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)..

Allowed values: 0x0-0x1ffffff

AWDFILT1

Bits 29-31: Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NoFiltering: No filtering
1: Detections2: Two consecutive detections generates an AWDx flag or an interrupt
2: Detections3: Three consecutive detections generates an AWDx flag or an interrupt
3: Detections4: Four consecutive detections generates an AWDx flag or an interrupt
4: Detections5: Five consecutive detections generates an AWDx flag or an interrupt
5: Detections6: Six consecutive detections generates an AWDx flag or an interrupt
6: Detections7: Seven consecutive detections generates an AWDx flag or an interrupt
7: Detections8: Eight consecutive detections generates an AWDx flag or an interrupt

LTR2

Bits 0-24: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)..

Allowed values: 0x0-0x1ffffff

HTR2

Bits 0-24: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)..

Allowed values: 0x0-0x1ffffff

LTR3

Bits 0-24: Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)..

Allowed values: 0x0-0x1ffffff

HTR3

Bits 0-24: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)..

Allowed values: 0x0-0x1ffffff

DIFSEL

Bits 0-19: Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow selecting if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: SingleEnded: ADC analog input channel x is configured in single-ended mode
1: Differential: ADC analog input channel x is configured in differential mode

I_APB_ADDR

Bits 0-7: Delayed write access address This bitfield contains the address that is being written during delayed write accesses..

Allowed values: 0x0-0xff

I_APB_DATA

Bits 8-15: Delayed write access data This bitfield contains the data that are being written during delayed write accesses..

Allowed values: 0x0-0xff

VALIDITY

Bit 16: Delayed write access status bit This bit indicates the communication status between the ADC digital and analog blocks..

Allowed values:
0: InProgress: Operation still in progress
1: Complete: Operation complete

LATCH_COEF

Bit 24: Calibration factor latch enable bit This bit latches the calibration factor in the CALFACT[31:0] bits..

Allowed values:
0: NoEffect: No effect
1: Latch: Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT[31:0] bits must be programmed with the content of CALINDEX[3:0] bits.

CAPTURE_COEF

Bit 25: Calibration factor capture enable bit This bit enables the internal calibration factor capture..

Allowed values:
0: Disabled: Calibration factor not captured
1: Enabled: Calibration factor available in CALFACT[31:0] bits, the calibration factor index being defined by CALINDEX[3:0] bits

CALFACT

Bits 0-31: Linearity or offset calibration factor These bits can be written either by hardware or by software. They contain the 32-bit offset or linearity calibration factor. When CAPTURE_COEF is set to 1, the calibration factor of the analog block is read back and stored in CALFACT[31:0], indexed by CALINDEX[3:0] bits. When LATCH_COEF is set to 1, the calibration factor of the analog block is updated with the value programmed in CALFACT[31:0], indexed by CALINDEX[3:0] bits. To read all calibration factors, perform nine accesses to the ADC_CALFACT2 register. To write all calibration factors, perform eight accesses to the ADC_CALFACT2 register. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)..

Allowed values: 0x0-0xffffffff

PRESC

Bits 18-21: ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

VREFEN

Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: VREFINT channel disabled
1: Enabled: VREFINT channel enabled

VSENSESEL

Bit 23: Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: Temperature sensor channel disabled
1: Enabled: Temperature sensor channel enabled

VBATEN

Bit 24: VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: VBAT channel disabled
1: Enabled: VBAT channel enabled

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotAtEnd: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
1: AtEnd: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
1: Complete: Regular channel conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
1: Complete: Regular conversions sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun: Overrun has occurred

AWD1

Bit 7: AWD1.

Allowed values:
0: NoEvent: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
1: Event: Analog watchdog x event occurred

AWD2

Bit 8: AWD2.

Allowed values:
0: NoEvent: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
1: Event: Analog watchdog x event occurred

AWD3

Bit 9: AWD3.

Allowed values:
0: NoEvent: No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
1: Event: Analog watchdog x event occurred

EOCAL

Bit 11: EOCAL.

Allowed values:
0: NotComplete: Calibration is not complete
1: Complete: Calibration is complete

LDORDY

Bit 12: LDORDY.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADRDY interrupt disabled
1: Enabled: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: EOSMP interrupt disabled
1: Enabled: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: EOS interrupt disabled
1: Enabled: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

AWD1IE

Bit 7: AWD1IE.

Allowed values:
0: Disabled: Analog watchdog x interrupt disabled
1: Enabled: Analog watchdog x interrupt enabled

AWD2IE

Bit 8: AWD2IE.

Allowed values:
0: Disabled: Analog watchdog x interrupt disabled
1: Enabled: Analog watchdog x interrupt enabled

AWD3IE

Bit 9: AWD3IE.

Allowed values:
0: Disabled: Analog watchdog x interrupt disabled
1: Enabled: Analog watchdog x interrupt enabled

EOCALIE

Bit 11: EOCALIE.

Allowed values:
0: Disabled: End of calibration interrupt disabled
1: Enabled: End of calibration interrupt enabled

LDORDYIE

Bit 12: LDORDYIE.

Allowed values:
0: Disabled: LDO ready interrupt disabled
1: Enabled: LDO ready interrupt enabled. An interrupt is generated when the LDO output is ready.

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC is disabled
1: Enabled: ADC is enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotOngoing: No ADDIS command ongoing
1: InProgress: An ADDIS command is in progress

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No ADC regular conversion is ongoing
1: Active: ADC is operating and eventually converting a regular channel

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No ADC stop regular conversion command ongoing
1: Stopping: ADSTP command is in progress

ADVREGEN

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

ADCAL

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: Calibration complete
1: Calibrating: Calibration in progress

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: One-shot mode selected
1: Circular: Circular mode selected

RES

Bits 2-3: RES.

Allowed values:
0: TwelveBit: 12 bits
1: TenBit: 10 bits
2: EightBit: 8 bits
3: SixBit: 6 bits

SCANDIR

Bit 4: SCANDIR.

Allowed values:
0: Upward: Upward scan sequence (from CHSEL0 to CHSEL23)
1: Downward: Downward scan sequence (from CHSEL23 to CHSEL0)

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-8: EXTSEL.

Allowed values:
0: TIM1_TRGO2: tim1_trgo2
1: TIM1_OC4: tim1_oc4
2: TIM2_TRGO: tim2_trgo
3: TIM15_TRGO: tim15_trgo
4: TIM6_TRGO: tim6_trgo
5: LPTIM1_CH1: lptim1_ch1
6: LPTIM3_CH2: lptim3_ch2
7: EXTI15: exti15

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Hardware trigger detection disabled (conversions can be launched by software)
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: ADC_DR register is preserved with the old data when an overrun is detected
1: Overwrite: ADC_DR register is overwritten with the last conversion result when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

WAIT

Bit 14: WAIT.

Allowed values:
0: Disabled: Wait conversion mode off
1: Enabled: Wait conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode for regular channels disabled
1: Enabled: Discontinuous mode for regular channels enabled

CHSELRMOD

Bit 21: CHSELRMOD.

Allowed values:
0: BitPerInput: Each bit of the ADC_CHSELR register enables an input
1: Sequence: ADC_CHSELR register is able to sequence up to 8 channels

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: AllChannels: Analog watchdog 1 enabled on all channels
1: SingleChannel: Analog watchdog 1 enabled on a single channel

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

AWD1CH

Bits 26-30: AWD1CH.

Allowed values: 0x0-0x13

OVSE

Bit 0: OVSE.

Allowed values:
0: Disabled: Oversampler disabled
1: Enabled: Oversampler enabled

OVSR

Bits 2-4: OVSR.

Allowed values: 0x0-0x7

OVSS

Bits 5-8: OVSS.

Allowed values: 0x0-0x8

TOVS

Bit 9: TOVS.

Allowed values:
0: Automatic: All oversampled conversions for a channel are done consecutively following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

LFTRIG

Bit 29: LFTRIG.

Allowed values:
0: Disabled: Low-frequency trigger mode disabled
1: Enabled: Low-frequency trigger mode enabled

SMP1

Bits 0-2: SMP1.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles814_5: 814.5 ADC clock cycles

SMP2

Bits 4-6: SMP2.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles814_5: 814.5 ADC clock cycles

SMPSEL0

Bit 8: SMPSEL0.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL1

Bit 9: SMPSEL1.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL2

Bit 10: SMPSEL2.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL3

Bit 11: SMPSEL3.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL4

Bit 12: SMPSEL4.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL5

Bit 13: SMPSEL5.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL6

Bit 14: SMPSEL6.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL7

Bit 15: SMPSEL7.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL8

Bit 16: SMPSEL8.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL9

Bit 17: SMPSEL9.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL10

Bit 18: SMPSEL10.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL11

Bit 19: SMPSEL11.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL12

Bit 20: SMPSEL12.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL13

Bit 21: SMPSEL13.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL14

Bit 22: SMPSEL14.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL15

Bit 23: SMPSEL15.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL16

Bit 24: SMPSEL16.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL17

Bit 25: SMPSEL17.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL18

Bit 26: SMPSEL18.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL19

Bit 27: SMPSEL19.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL20

Bit 28: SMPSEL20.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL21

Bit 29: SMPSEL21.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL22

Bit 30: SMPSEL22.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

SMPSEL23

Bit 31: SMPSEL23.

Allowed values:
0: SMP1: Sampling time of channel x uses the setting of SMP1 register.
1: SMP2: Sampling time of channel x uses the setting of SMP2 register.

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

LT2

Bits 0-11: LT2.

Allowed values: 0x0-0xfff

HT2

Bits 16-27: HT2.

Allowed values: 0x0-0xfff

CHSEL0

Bit 0: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL1

Bit 1: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL2

Bit 2: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL3

Bit 3: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL4

Bit 4: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL5

Bit 5: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL6

Bit 6: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL7

Bit 7: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL8

Bit 8: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL9

Bit 9: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL10

Bit 10: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL11

Bit 11: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL12

Bit 12: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL13

Bit 13: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL14

Bit 14: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL15

Bit 15: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL16

Bit 16: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL17

Bit 17: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion

CHSEL18

Bit 18: CHSEL.

Allowed values:
0: Disabled: Input channel x is not selected for conversion
1: Enabled: Input channel x is selected for conversion