STM32WB07 Peripheral Coverage

ADC

0x41006000: ADC address block description

3/101 fields covered.

Toggle register map

Offset	Name	31	27	23	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	VERSION_ID																	VERSION_ID
0x4	CONF				VBIAS_PRECH_FORCE	ADC_CONT_1V2	BIT_INVERT_DIFF	BIT_INVERT_SN	OVR_DF_CFG	OVR_DS_CFG	DMA_DF_ENA	DMA_DS_ENA	SAMPLE_RATE				OP_MODE		SMPS_SYNCHRO_ENA	SEQ_LEN				SEQUENCE	CONT
0x8	CTRL																			ADC_LDO_ENA	TEST_MODE	DIG_AUD_MODE	STOP_OP_MOD	START_CON	ADC_ON_OFF
0xc	OCM_CTRL																							OCM_ENA	OCM_SRC
0x10	PGA_CONF																		PGA_BIAS			PGA_GAIN
0x14	SWITCH									SE_VIN_7		SE_VIN_6		SE_VIN_5		SE_VIN_4		SE_VIN_3		SE_VIN_2		SE_VIN_1		SE_VIN_0
0x18	DF_CONF							DF_HALF_D_EN	DF_HPF_EN	DF_MICROL_RN	PDM_RATE				DF_O_S2U	DF_I_U2S	DF_ITP1P2	DF_CIC_DHF	DF_CIC_DEC_FACTOR
0x1c	DS_CONF																			DS_WIDTH			DS_RATIO
0x20	SEQ_1	SEQ7	SEQ6	SEQ5		SEQ4				SEQ3				SEQ2				SEQ1				SEQ0
0x24	SEQ_2	SEQ15	SEQ14	SEQ13		SEQ12				SEQ11				SEQ10				SEQ9				SEQ8
0x28	COMP_1						OFFSET1			OFFSET1				GAIN1
0x2c	COMP_2						OFFSET2			OFFSET2				GAIN2
0x30	COMP_3						OFFSET3			OFFSET3				GAIN3
0x34	COMP_4						OFFSET4			OFFSET4				GAIN4
0x38	COMP_SEL							GAIN_OFFSET8		GAIN_OFFSET7		GAIN_OFFSET6		GAIN_OFFSET5		GAIN_OFFSET4		GAIN_OFFSET3		GAIN_OFFSET2		GAIN_OFFSET1		GAIN_OFFSET0
0x3c	WD_TH		WD_HT											WD_LT
0x40	WD_CONF									AWD_CHX
0x44	DS_DATAOUT									DS_DATA
0x48	DF_DATAOUT									DF_DATA
0x4c	IRQ_STATUS																	DF_OVRFL_IRQ	OVR_DF_IRQ	OVR_DS_IRQ	AWD_IRQ	EOS_IRQ	EODF_IRQ	EODS_IRQ	EOC_IRQ
0x50	IRQ_ENABLE																	DF_OVRFL_IRQ_ENA	OVR_DF_IRQ_ENA	OVR_DS_IRQ_ENA	AWD_IRQ_ENA	EOS_IRQ_ENA	EODF_IRQ_ENA	EODS_IRQ_ENA	EOC_IRQ_ENA
0x54	TIMER_CONF								PRECH_DELAY_SEL	VBIAS_PRECH_DELAY								ADC_LDO_DELAY

Toggle registers

VERSION_ID

VERSION_ID register

Offset: 0x0, size: 32, reset: 0x00000020, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								VERSION_ID r

Toggle fields

VERSION_ID

Bits 0-7: version of the embedded IP..

CONF

ADC configuration register

Offset: 0x4, size: 32, reset: 0x00020002, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											VBIAS_PRECH_FORCE rw	ADC_CONT_1V2 rw	BIT_INVERT_DIFF rw	BIT_INVERT_SN rw	OVR_DF_CFG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVR_DS_CFG rw	DMA_DF_ENA rw	DMA_DS_ENA rw	SAMPLE_RATE rw				OP_MODE rw		SMPS_SYNCHRO_ENA rw	SEQ_LEN rw				SEQUENCE rw	CONT rw

Toggle fields

CONT

Bit 0: regular sequence runs continuously when ADC mode is enabled.

SEQUENCE

Bit 1: enable the sequence mode (active by default).

SEQ_LEN

Bits 2-5: number of conversions in a regular sequence.

SMPS_SYNCHRO_ENA

Bit 6: synchronize the ADC start conversion with a pulse generated by the.

OP_MODE

Bits 7-8: ADC mode selection (= data path selection).

SAMPLE_RATE

Bits 11-12: conversion rate of ADC.

DMA_DS_ENA

Bit 13: enable DMA mode for Down Sampler data path.

DMA_DF_ENA

Bit 14: enable DMA mode for Decimation Filter data path.

OVR_DS_CFG

Bit 15: Down Sampler overrun configuration.

OVR_DF_CFG

Bit 16: decimation overrun configuration.

BIT_INVERT_SN

Bit 17: invert bit to bit the ADC data output when a single.

BIT_INVERT_DIFF

Bit 18: invert bit to bit the ADC data output when a differential.

ADC_CONT_1V2

Bit 19: select the input sampling method.

VBIAS_PRECH_FORCE

Bit 20: possibility to keep the VBIAS_PRECH enabled to deactivate the filter.

CTRL

ADC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ADC_LDO_ENA rw	TEST_MODE rw	DIG_AUD_MODE rw	STOP_OP_MOD rw	START_CON rw	ADC_ON_OFF rw

Toggle fields

ADC_ON_OFF

Bit 0: ADC_ON_OFF: – 0: power off the ADC – 1: power on the ADC.

START_CON

Bit 1: generate a start pulse to initiate an ADC conversion.

STOP_OP_MOD

Bit 2: stop the on-going OP_MODE (ADC mode, Analog audio mode, Full.

DIG_AUD_MODE

Bit 3: enable the digital audio mode (the data path uses the decimation filter).

TEST_MODE

Bit 4: select the functional or the test mode of the ADC.

ADC_LDO_ENA

Bit 5: enable the LDO associated to the ADC block.

OCM_CTRL

Occasionnal mode control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OCM_ENA rw	OCM_SRC rw

Toggle fields

OCM_SRC

Bit 0: select the occasional conversion source.

OCM_ENA

Bit 1: start occasional conversion in analog audio and full modes.

PGA_CONF

PGA configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									PGA_BIAS rw			PGA_GAIN rw

Toggle fields

PGA_GAIN

Bits 0-3: from 6 to 30 dB.

PGA_BIAS

Bits 4-6: set the microphone bias voltage.

SWITCH

ADC switch control for Input Selection

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SE_VIN_7 rw		SE_VIN_6 rw		SE_VIN_5 rw		SE_VIN_4 rw		SE_VIN_3 rw		SE_VIN_2 rw		SE_VIN_1 rw		SE_VIN_0 rw

Toggle fields

SE_VIN_0

Bits 0-1: input voltage for VINM[0] / VINP[0]-VINM[0].

SE_VIN_1

Bits 2-3: input voltage for VINM[1] / VINP[1]-VINM[1].

SE_VIN_2

Bits 4-5: input voltage for VINM[2] / VINP[2]-VINM[2].

SE_VIN_3

Bits 6-7: input voltage for VINM[3] / VINP[3]-VINM[3].

SE_VIN_4

Bits 8-9: input voltage for VINP[0].

SE_VIN_5

Bits 10-11: input voltage for VINP[1].

SE_VIN_6

Bits 12-13: input voltage for VINP[2].

SE_VIN_7

Bits 14-15: input voltage for VINP[3].

DF_CONF

Decimation filter configuration register

Offset: 0x18, size: 32, reset: 0x00003015, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														DF_HALF_D_EN rw	DF_HPF_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DF_MICROL_RN rw	PDM_RATE rw				DF_O_S2U rw	DF_I_U2S rw	DF_ITP1P2 rw	DF_CIC_DHF rw	DF_CIC_DEC_FACTOR rw

Toggle fields

DF_CIC_DEC_FACTOR

Bits 0-6: .

DF_CIC_DHF

Bit 7: CIC filter decimator half factor.

DF_ITP1P2

Bit 8: 1.2 fractional interpolator enable.

DF_I_U2S

Bit 9: select signed/unsigned format for input.

DF_O_S2U

Bit 10: select signed/unsigned format for data output.

PDM_RATE

Bits 11-14: select the PDM clock rate..

DF_MICROL_RN

Bit 15: left/right channel selection on digital microphone.

DF_HPF_EN

Bit 16: high pass filter enable..

DF_HALF_D_EN

Bit 17: half dynamic enable..

DS_CONF

Downsampler configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DS_WIDTH rw			DS_RATIO rw

Toggle fields

DS_RATIO

Bits 0-2: program the Down Sampler ratio (N factor).

DS_WIDTH

Bits 3-5: program the Down Sampler width of data output (DSDTATA).

SEQ_1

ADC regular sequence configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ7 rw				SEQ6 rw				SEQ5 rw				SEQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ3 rw				SEQ2 rw				SEQ1 rw				SEQ0 rw

Toggle fields

SEQ0

Bits 0-3: channel number code for first conversion of the sequence.

SEQ1

Bits 4-7: channel number code for second conversion of the sequence..

SEQ2

Bits 8-11: channel number code for 3rd conversion of the sequence..

SEQ3

Bits 12-15: channel number code for 4th conversion of the sequence..

SEQ4

Bits 16-19: channel number code for 5th conversion of the sequence..

SEQ5

Bits 20-23: channel number code for 6th conversion of the sequence..

SEQ6

Bits 24-27: channel number code for 7th conversion of the sequence..

SEQ7

Bits 28-31: channel number code for 8th conversion of the sequence..

SEQ_2

ADC regular sequence configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ15 rw				SEQ14 rw				SEQ13 rw				SEQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ11 rw				SEQ10 rw				SEQ9 rw				SEQ8 rw

Toggle fields

SEQ8

Bits 0-3: channel number code for 9th conversion of the sequence.

SEQ9

Bits 4-7: channel number code for 10th conversion of the sequence..

SEQ10

Bits 8-11: channel number code for 11th conversion of the sequence..

SEQ11

Bits 12-15: channel number code for 12th conversion of the sequence..

SEQ12

Bits 16-19: channel number code for 13th conversion of the sequence..

SEQ13

Bits 20-23: channel number code for 14th conversion of the sequence..

SEQ14

Bits 24-27: channel number code for 15th conversion of the sequence..

SEQ15

Bits 28-31: channel number code for 16th conversion of the sequence..

COMP_1

ADC Gain and offset correction values register 1

Offset: 0x28, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OFFSET1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET1 rw				GAIN1 rw

Toggle fields

GAIN1

Bits 0-11: first calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET1

Bits 12-18: first calibration point: signed offset compensation[6:0].

COMP_2

ADC Gain and offset correction values register 2

Offset: 0x2c, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OFFSET2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET2 rw				GAIN2 rw

Toggle fields

GAIN2

Bits 0-11: second calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET2

Bits 12-18: second calibration point: signed offset compensation[6:0].

COMP_3

ADC Gain and offset correction values register 3

Offset: 0x30, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OFFSET3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET3 rw				GAIN3 rw

Toggle fields

GAIN3

Bits 0-11: third calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET3

Bits 12-18: third calibration point: signed offset compensation[6:0].

COMP_4

ADC Gain and offset correction values register 4

Offset: 0x34, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OFFSET4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET4 rw				GAIN4 rw

Toggle fields

GAIN4

Bits 0-11: fourth calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET4

Bits 12-18: fourth calibration point: signed offset compensation[6:0].

COMP_SEL

ADC Gain and Offset selection values register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														GAIN_OFFSET8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GAIN_OFFSET7 rw		GAIN_OFFSET6 rw		GAIN_OFFSET5 rw		GAIN_OFFSET4 rw		GAIN_OFFSET3 rw		GAIN_OFFSET2 rw		GAIN_OFFSET1 rw		GAIN_OFFSET0 rw

Toggle fields

GAIN_OFFSET0

Bits 0-1: gain / offset used in ADC single negative mode with Vinput range = 1.2V.

GAIN_OFFSET1

Bits 2-3: gain / offset used in ADC single positive mode with Vinput range = 1.2V.

GAIN_OFFSET2

Bits 4-5: gain / offset used in ADC differential mode with Vinput range = 1.2V.

GAIN_OFFSET3

Bits 6-7: gain / offset used in ADC single negative mode with Vinput range = 2.4V.

GAIN_OFFSET4

Bits 8-9: gain / offset used in ADC single positive mode with Vinput range = 2.4V.

GAIN_OFFSET5

Bits 10-11: gain / offset used in ADC differential mode with Vinput range = 2.4V.

GAIN_OFFSET6

Bits 12-13: gain / offset used in ADC single negative mode with Vinput range = 3.6V.

GAIN_OFFSET7

Bits 14-15: gain / offset used in ADC single positive mode with Vinput range = 3.6V.

GAIN_OFFSET8

Bits 16-17: gain / offset used in ADC differential mode with Vinput range = 3.6V.

WD_TH

High/low limits for event monitoring a channel register

Offset: 0x3c, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				WD_HT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WD_LT rw

Toggle fields

WD_LT

Bits 0-11: analog watchdog low level threshold..

WD_HT

Bits 16-27: analog watchdog high level threshold..

WD_CONF

Channel selection for event monitoring register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD_CHX rw

Toggle fields

AWD_CHX

Bits 0-15: analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog..

DS_DATAOUT

Downsampler Data output register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DS_DATA r

Toggle fields

DS_DATA

Bits 0-15: contain the converted data at the output of the Down Sampler.

DF_DATAOUT

Decimation filter Data output register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DF_DATA r

Toggle fields

DF_DATA

Bits 0-15: contain the converted data at the output of the decimation filter..

IRQ_STATUS

Interrupt Status register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DF_OVRFL_IRQ rw	OVR_DF_IRQ rw	OVR_DS_IRQ rw	AWD_IRQ rw	EOS_IRQ rw	EODF_IRQ rw	EODS_IRQ rw	EOC_IRQ rw

Toggle fields

EOC_IRQ

Bit 0: (Used in test mode only): set when the ADC conversion is completed..

EODS_IRQ

Bit 1: set when the Down Sampler conversion is completed..

EODF_IRQ

Bit 2: set when the decimation filter conversion is completed.

EOS_IRQ

Bit 3: set when a sequence of conversion is completed.

AWD_IRQ

Bit 4: set when an analog watchdog event occurs.

OVR_DS_IRQ

Bit 5: set to indicate a Down Sampler overrun (at least one data is lost).

OVR_DF_IRQ

Bit 6: set to indicate a decimation filter overrun (a data is lost).

DF_OVRFL_IRQ

Bit 7: set to indicate the decimation filter is saturated..

IRQ_ENABLE

Enable/disable Interrupts

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DF_OVRFL_IRQ_ENA rw	OVR_DF_IRQ_ENA rw	OVR_DS_IRQ_ENA rw	AWD_IRQ_ENA rw	EOS_IRQ_ENA rw	EODF_IRQ_ENA rw	EODS_IRQ_ENA rw	EOC_IRQ_ENA rw

Toggle fields

EOC_IRQ_ENA

Bit 0: (Used in test mode only): End of ADC conversion interrupt enable.

EODS_IRQ_ENA

Bit 1: End of conversion interrupt enable for the Down Sampler output.

EODF_IRQ_ENA

Bit 2: End of conversion interrupt enable for the decimation filter output.

EOS_IRQ_ENA

Bit 3: End of regular sequence interrupt enable.

AWD_IRQ_ENA

Bit 4: analog watchdog interrupt enable.

OVR_DS_IRQ_ENA

Bit 5: Down Sampler overrun interrupt enable.

OVR_DF_IRQ_ENA

Bit 6: decimation filter overrun interrupt enable.

DF_OVRFL_IRQ_ENA

Bit 7: decimation filter saturation interrupt enable.

TIMER_CONF

Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it

Offset: 0x54, size: 32, reset: 0x00009628, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															PRECH_DELAY_SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VBIAS_PRECH_DELAY rw								ADC_LDO_DELAY rw

Toggle fields

ADC_LDO_DELAY

Bits 0-7: define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion..

VBIAS_PRECH_DELAY

Bits 8-15: define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration.

PRECH_DELAY_SEL

Bit 16: Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer.

BLUE

0x60000000:

68/119 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	1	0
0x4	INTERRUPT1REG	RCVOK	RCVCRCERR	TIMECAPTURETRIG	RCVCMD	RCVNOMD	RCVTIMEOUT	DONE	TXOK	CONFIGERROR	ACTIVE2ERROR	TXRXSKIP	SEMATIMEOUTERROR	RCVLENGTHERROR		NOACTIVELERROR	TXDATAREADYERROR	ALLTABLEREADYERROR	ENCERROR	TXERROR_4	TXERROR_3	TXERROR_2	TXERROR_1	TXERROR_0	SEQDONE		RXOVERFLOWERROR	ADDPOINTERROR
0x8	INTERRUPT2REG																													AESLEPRIVINT	AESMANENCINT
0xc	TIMEOUTDESTREG																													DESTINATION
0x10	TIMEOUTREG	TIMEOUT															TIMEOUT
0x14	TIMERCAPTUREREG	TIMERCAPTURE															TIMERCAPTURE
0x18	CMDREG																												CLEARSEMAREQ		TXRXSKIP
0x1c	STATUSREG	RCVOK	RCVCRCERR	TIMECAPTURETRIG	RCVCMD	RCVNOMD	RCVTIMEOUT	DONE	TXOK	CONFIGERROR	ACTIVE2ERROR	TXRXSKIP	SEMATIMEOUTERROR	RCVLENGTHERROR		NOACTIVELERROR	TXDATAREADYERROR	ALLTABLEREADYERROR	ENCERROR	TXERROR_4	TXERROR_3	TXERROR_2	TXERROR_1	TXERROR_0	SEQDONE	PREVTRANSMIT	RXOVERFLOWERROR	ADDPOINTERROR	NOTSUPPORTED_FUNCTION		AESONFLYBUSY
0x20	INTERRUPT1ENABLEREG	RCVOK	RCVCRCERR	TIMECAPTURETRIG	RCVCMD	RCVNOMD	RCVTIMEOUT	DONE	TXOK	CONFIGERROR	ACTIVE2ERROR	TXRXSKIP	SEMATIMEOUTERROR	RCVLENGTHERROR		NOACTIVELERROR	TXDATAREADYERROR	ALLTABLEREADYERROR	ENCERROR	TXERROR_4	TXERROR_3	TXERROR_2	TXERROR_1	TXERROR_0	SEQDONE		RXOVERFLOWERROR	ADDPOINTERROR
0x24	INTERRUPT1LATENCYREG																								INTERRUPT1LATENCY
0x28	MANAESKEY0REG	MANAESKEY_31_0															MANAESKEY_31_0
0x2c	MANAESKEY1REG	MANAESKEY_63_32															MANAESKEY_63_32
0x30	MANAESKEY2REG	MANAESKEY_95_64															MANAESKEY_95_64
0x34	MANAESKEY3REG	MANAESKEY_127_96															MANAESKEY_127_96
0x38	MANAESCLEARTEXT0REG	AES															AES
0x3c	MANAESCLEARTEXT1REG	AES															AES
0x40	MANAESCLEARTEXT2REG	AES															AES
0x44	MANAESCLEARTEXT3REG	AES															AES
0x48	MANAESCIPHERTEXT0REG	AES															AES
0x4c	MANAESCIPHERTEXT1REG	AES															AES
0x50	MANAESCIPHERTEXT2REG	AES															AES
0x54	MANAESCIPHERTEXT3REG	AES															AES
0x58	MANAESCMDREG																													INTENA	START
0x5c	MANAESSTATREG																														BUSY
0x60	AESLEPRIVPOINTERREG									POINTER							POINTER
0x64	AESLEPRIVHASHREG									HASH							HASH
0x68	AESLEPRIVPRANDREG									PRAND							PRAND
0x6c	AESLEPRIVCMDREG																						NBKEYS							INTENA	START
0x70	AESLEPRIVSTATREG																						KEYFNDINDEX							KEYFND	BUSY
0x74	DEBUGCMDREG												AESDEBUGMODE														SEQDEBUGBUSSEL			SEQDEBUGMODE	CLEARDEBUGINT
0x78	DEBUGSTATUSREG												AESDBG_3	AESDBG_2	AESDBG_1	AESDBG_0										DEBUGSTATUSREG

Toggle registers

INTERRUPT1REG

INTERRUPT1REG register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RCVOK rw	RCVCRCERR rw	TIMECAPTURETRIG rw	RCVCMD rw	RCVNOMD rw	RCVTIMEOUT rw	DONE rw	TXOK rw	CONFIGERROR rw	ACTIVE2ERROR rw	TXRXSKIP rw		SEMATIMEOUTERROR rw	RCVLENGTHERROR rw		NOACTIVELERROR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDATAREADYERROR rw	ALLTABLEREADYERROR rw	ENCERROR rw	TXERROR_4 rw	TXERROR_3 rw	TXERROR_2 rw	TXERROR_1 rw	TXERROR_0 rw	SEQDONE rw		RXOVERFLOWERROR rw	ADDPOINTERROR rw

Toggle fields

ADDPOINTERROR

Bit 4: Address Pointer Error..

RXOVERFLOWERROR

Bit 5: Receive Overflow error..

SEQDONE

Bit 7: Sequencer end of task..

TXERROR_0

Bit 8: Transmission error 0: transmit block missing data error..

TXERROR_1

Bit 9: Transmission error 1: a TX skip happened during an on-going transmission..

TXERROR_2

Bit 10: Transmission error 2: channel index is greater than 39..

TXERROR_3

Bit 11: Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state..

TXERROR_4

Bit 12: Transmission error 4: a CTE issue occurred..

ENCERROR

Bit 13: Encryption error on reception..

ALLTABLEREADYERROR

Bit 14: All RAM Table not ready on time..

TXDATAREADYERROR

Bit 15: Transmit data pack not ready error.

NOACTIVELERROR

Bit 16: GlobalStatMach..

RCVLENGTHERROR

Bit 18: Receive length error..

SEMATIMEOUTERROR

Bit 19: Semaphore timeout error.

TXRXSKIP

Bit 21: Transmission/Reception skip..

ACTIVE2ERROR

Bit 22: Active2 Radio state error..

CONFIGERROR

Bit 23: Data pointer configuration error..

TXOK

Bit 24: Previous transmitted packet received OK by the peer device..

DONE

Bit 25: Receive/Transmit done..

RCVTIMEOUT

Bit 26: Receive timeout (no preamble found)..

RCVNOMD

Bit 27: Received low MD bit..

RCVCMD

Bit 28: Received command.

TIMECAPTURETRIG

Bit 29: A time has been captured in TIMERCAPTUREREG..

RCVCRCERR

Bit 30: Receive data fail.

RCVOK

Bit 31: Receive data OK..

INTERRUPT2REG

INTERRUPT2REG register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														AESLEPRIVINT rw	AESMANENCINT rw

Toggle fields

AESMANENCINT

Bit 0: AES manual encryption..

AESLEPRIVINT

Bit 1: AES LE privacy engine..

TIMEOUTDESTREG

TIMEOUTDESTREG register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DESTINATION rw

Toggle fields

DESTINATION

Bits 0-1: Timeout timer Destination.

TIMEOUTREG

TIMEOUTREG register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIMEOUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUT rw

Toggle fields

TIMEOUT

Bits 0-31: Timer1 or Timer2 Timeout value (depending on Destination register).

TIMERCAPTUREREG

TIMERCAPTUREREG register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIMERCAPTURE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMERCAPTURE r

Toggle fields

TIMERCAPTURE

Bits 0-31: Interpolated absolute time capture register.

CMDREG

CMDREG register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CLEARSEMAREQ w			TXRXSKIP w

Toggle fields

TXRXSKIP

Bit 0: Transmission/Reception skip command..

CLEARSEMAREQ

Bit 3: Semaphore Clear command..

STATUSREG

STATUSREG register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RCVOK r	RCVCRCERR r	TIMECAPTURETRIG r	RCVCMD r	RCVNOMD r	RCVTIMEOUT r	DONE r	TXOK r	CONFIGERROR r	ACTIVE2ERROR r	TXRXSKIP r		SEMATIMEOUTERROR r	RCVLENGTHERROR r		NOACTIVELERROR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDATAREADYERROR r	ALLTABLEREADYERROR r	ENCERROR r	TXERROR_4 r	TXERROR_3 r	TXERROR_2 r	TXERROR_1 r	TXERROR_0 r	SEQDONE r	PREVTRANSMIT r	RXOVERFLOWERROR r	ADDPOINTERROR r	NOTSUPPORTED_FUNCTION r			AESONFLYBUSY r

Toggle fields

AESONFLYBUSY

Bit 0: AES on the fligh encryption busy status.

NOTSUPPORTED_FUNCTION

Bit 3: indicates the SW requests an unsupported feature..

ADDPOINTERROR

Bit 4: Address Pointer Error status.

RXOVERFLOWERROR

Bit 5: AHB arbiter is full and there is no more storage capability available in RX datapath.

PREVTRANSMIT

Bit 6: Previous event was a Transmission (1) or Reception (0) status.

SEQDONE

Bit 7: Sequencer end of task status..

TXERROR_0

Bit 8: Transmission error 0 status: Transmit block missing data error..

TXERROR_1

Bit 9: Transmission error 1 status.

TXERROR_2

Bit 10: Transmission error 2 status..

TXERROR_3

Bit 11: Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach..

TXERROR_4

Bit 12: Transmission error 4 status.

ENCERROR

Bit 13: Encryption error on receive status.

ALLTABLEREADYERROR

Bit 14: All RAM Table not ready status.

TXDATAREADYERROR

Bit 15: Transmit data pack not ready status..

NOACTIVELERROR

Bit 16: GlobalStatMach..

RCVLENGTHERROR

Bit 18: Receive length error status.

SEMATIMEOUTERROR

Bit 19: Semaphore timeout error status.

TXRXSKIP

Bit 21: Transmission/Reception skip status..

ACTIVE2ERROR

Bit 22: Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step..

CONFIGERROR

Bit 23: Data pointer configuration error status.

TXOK

Bit 24: Previous transmitted packet received OK by the peer device status..

DONE

Bit 25: Receive/Transmit done status..

RCVTIMEOUT

Bit 26: Receive timeout status (no access address found).

RCVNOMD

Bit 27: Received MD bit status (valid only on Data Physical Channel PDU reception).

RCVCMD

Bit 28: Received command status (valid only on Data Physical Channel PDU reception)..

TIMECAPTURETRIG

Bit 29: indicates a time has been captured in TIMERCAPTUREREG when set..

RCVCRCERR

Bit 30: Receive data fail (CRC error or invalid CI field) status..

RCVOK

Bit 31: Receive data OK status.

INTERRUPT1ENABLEREG

INTERRUPT1ENABLEREG register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

25/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RCVOK r	RCVCRCERR r	TIMECAPTURETRIG r	RCVCMD r	RCVNOMD r	RCVTIMEOUT r	DONE r	TXOK r	CONFIGERROR r	ACTIVE2ERROR r	TXRXSKIP r		SEMATIMEOUTERROR r	RCVLENGTHERROR r		NOACTIVELERROR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDATAREADYERROR r	ALLTABLEREADYERROR r	ENCERROR r	TXERROR_4 r	TXERROR_3 r	TXERROR_2 r	TXERROR_1 r	TXERROR_0 r	SEQDONE r		RXOVERFLOWERROR r	ADDPOINTERROR r

Toggle fields

ADDPOINTERROR

Bit 4: Address Pointer Error enable interruption.

RXOVERFLOWERROR

Bit 5: Rx Overflow Error enable interruption.

SEQDONE

Bit 7: Sequencer end of task enable interruption.

TXERROR_0

Bit 8: Transmission error 0 enable interruption.

TXERROR_1

Bit 9: Transmission error 1 enable interruption.

TXERROR_2

Bit 10: Transmission error 2 enable interruption.

TXERROR_3

Bit 11: Transmission error 3 enable interruption.

TXERROR_4

Bit 12: Transmission error 4 enable interruption.

ENCERROR

Bit 13: Encryption error on receive enable interruption.

ALLTABLEREADYERROR

Bit 14: All RAM Table not ready enable interruption.

TXDATAREADYERROR

Bit 15: Transmit data pack not ready enable interruption.

NOACTIVELERROR

Bit 16: active bit error enable interruption.

RCVLENGTHERROR

Bit 18: Receive length error enable interruption.

SEMATIMEOUTERROR

Bit 19: Semaphore timeout error enable interruption.

TXRXSKIP

Bit 21: Transmission/Reception skip enable interruption.

ACTIVE2ERROR

Bit 22: Active2 Radio state error enable interruption.

CONFIGERROR

Bit 23: Data pointer configuration error enable interruption.

TXOK

Bit 24: Previous transmitted packet received OK enable interruption.

DONE

Bit 25: Receive/Transmit done interruption.

RCVTIMEOUT

Bit 26: Receive timeout enable interruption (no preamble found).

RCVNOMD

Bit 27: Received MD bit embedded in the PDU data packet header was zero enable interruption.

RCVCMD

Bit 28: Received command enable interruption.

TIMECAPTURETRIG

Bit 29: TimerCaptureReg time capture enable interruption.

RCVCRCERR

Bit 30: Receive data fail enable interruption.

RCVOK

Bit 31: Receive data OK enable interruption.

INTERRUPT1LATENCYREG

INTERRUPT1LATENCYREG register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								INTERRUPT1LATENCY r

Toggle fields

INTERRUPT1LATENCY

Bits 0-7: relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence..

MANAESKEY0REG

MANAESKEY0REG register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_31_0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_31_0 rw

Toggle fields

MANAESKEY_31_0

Bits 0-31: Manual mode AES key.

MANAESKEY1REG

MANAESKEY1REG register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_63_32 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_63_32 rw

Toggle fields

MANAESKEY_63_32

Bits 0-31: Manual mode AES key.

MANAESKEY2REG

MANAESKEY2REG register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_95_64 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_95_64 rw

Toggle fields

MANAESKEY_95_64

Bits 0-31: Manual mode AES key.

MANAESKEY3REG

MANAESKEY3REG register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_127_96 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_127_96 rw

Toggle fields

MANAESKEY_127_96

Bits 0-31: Manual mode AES key.

MANAESCLEARTEXT0REG

MANAESCLEARTEXT0REG register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCLEARTEXT1REG

MANAESCLEARTEXT1REG register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCLEARTEXT2REG

MANAESCLEARTEXT2REG register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCLEARTEXT3REG

MANAESCLEARTEXT3REG register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCIPHERTEXT0REG

MANAESCIPHERTEXT0REG register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCIPHERTEXT1REG

MANAESCIPHERTEXT1REG register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCIPHERTEXT2REG

MANAESCIPHERTEXT2REG register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCIPHERTEXT3REG

MANAESCIPHERTEXT3REG register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCMDREG

MANAESCMDREG register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														INTENA rw	START w

Toggle fields

START

Bit 0: AES Manual encryption Start command..

INTENA

Bit 1: AES Manual encryption interrupt enable on Interrupt2Reg.

MANAESSTATREG

MANAESSTATREG register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															BUSY r

Toggle fields

BUSY

Bit 0: AES manual encryption busy status.

AESLEPRIVPOINTERREG

AESLEPRIVPOINTERREG register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								POINTER rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POINTER rw

Toggle fields

POINTER

Bits 0-23: AES Le privacy pointer.

AESLEPRIVHASHREG

AESLEPRIVHASHREG register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HASH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HASH rw

Toggle fields

HASH

Bits 0-23: AES Le privacy Reference Hash.

AESLEPRIVPRANDREG

AESLEPRIVPRANDREG register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRAND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRAND rw

Toggle fields

PRAND

Bits 0-23: AES Le privacy Prand.

AESLEPRIVCMDREG

AESLEPRIVCMDREG register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						NBKEYS rw								INTENA rw	START w

Toggle fields

START

Bit 0: AES Le privacy Start command..

INTENA

Bit 1: AES Le privacy interrupt enable on Interrupt2Reg.

NBKEYS

Bits 2-9: AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list..

AESLEPRIVSTATREG

AESLEPRIVSTATREG register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						KEYFNDINDEX r								KEYFND r	BUSY r

Toggle fields

BUSY

Bit 0: AES Le privacy busy status.

KEYFND

Bit 1: AES Le privacy key finding status.

KEYFNDINDEX

Bits 2-9: AES Le privacy index of the key found in the resolution key list..

DEBUGCMDREG

DebugCmd register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AESDEBUGMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SEQDEBUGBUSSEL rw				SEQDEBUGMODE rw	CLEARDEBUGINT rw

Toggle fields

CLEARDEBUGINT

Bit 0: CLEARDEBUGINT.

SEQDEBUGMODE

Bit 1: SEQDEBUGMODE.

SEQDEBUGBUSSEL

Bits 2-5: SEQDEBUGBUSSEL.

AESDEBUGMODE

Bits 16-19: AESDEBUGMODE.

DEBUGSTATUSREG

DebugStatus register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AESDBG_3 r	AESDBG_2 r	AESDBG_1 r	AESDBG_0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DEBUGSTATUSREG r

Toggle fields

DEBUGSTATUSREG

Bits 0-6: DEBUGSTATUSREG.

AESDBG_0

Bit 16: AESDBG_0.

AESDBG_1

Bit 17: AESDBG_1.

AESDBG_2

Bit 18: AESDBG_2.

AESDBG_3

Bit 19: AESDBG_3.

CRC

0x48200000: CRC address block description

10/10 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x0 (16-bit)	DR16		DR16
0x0 (8-bit)	DR8			DR8
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	INIT	INIT
0x14	POL	POL	POL

Toggle registers

DR

CRC data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

Allowed values: 0x0-0xffffffff

DR16

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR16 rw

Toggle fields

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR8 rw

Toggle fields

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

CRC independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle fields

IDR

Bits 0-31: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

Allowed values: 0x0-0xffffffff

CR

CRC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle fields

RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data This bitfield controls the reversal of the bit order of the input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

CRC initial value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INIT rw

Toggle fields

INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

Allowed values: 0x0-0xffffffff

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle fields

POL

Bits 0-31: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

Allowed values: 0x0-0xffffffff

DMA

0x48700000:

32/184 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR	TE1F8	HTIF8	TCIF8	GIF8	TE1F7	HTIF7	TCIF7	GIF7	TE1F6	HTIF6	TCIF6	GIF6	TEIF5	HTIF5	TCIF5	GIF5	TEIF4	HTIF4	TCIF4	GIF4	TEIF3	HTIF3	TCIF3	GIF3	TEIF2	HTIF2	TCIF2	GIF2	TEIF1	HTIF1	TCIF1	GIF1
0x4	IFCR	CTEIF8	CHTIF8	CTCIF8	CGIF8	CTEIF7	CHTIF7	CTCIF7	CGIF7	CTEIF6	CHTIF6	CTCIF6	CGIF6	CTEIF5	CHTIF5	CTCIF5	CGIF5	CTEIF4	CHTIF4	CTCIF4	CGIF4	CTEIF3	CHTIF3	CTCIF3	CGIF3	CTEIF2	CHTIF2	CTCIF2	CGIF2	CTEIF1	CHTIF1	CTCIF1	CGIF1
0x8	CCR1																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	CNDTR1																	NDT
0x10	CPAR1	PA																PA
0x14	CMAR1	MA																MA
0x1c	CCR2																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	CNDTR2																	NDT
0x24	CPAR2	PA																PA
0x28	CMAR2	MA																MA
0x30	CCR3																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	CNDTR3																	NDT
0x38	CPAR3	PA																PA
0x3c	CMAR3	MA																MA
0x44	CCR4																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	CNDTR4																	NDT
0x4c	CPAR4	PA																PA
0x50	CMAR4	MA																MA
0x58	CCR5																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	CNDTR5																	NDT
0x60	CPAR5	PA																PA
0x64	CMAR5	MA																MA
0x6c	CCR6																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	CNDTR6																	NDT
0x74	CPAR6	PA																PA
0x78	CMAR6	MA																MA
0x80	CCR7																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	CNDTR7																	NDT
0x88	CPAR7	PA																PA
0x8c	CMAR7	MA																MA
0x94	CCR8																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x98	CNDTR8																	NDT
0x9c	CPAR8	PA																PA
0xa0	CMAR8	MA																MA

Toggle registers

ISR

DMA_ISR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TE1F8 r	HTIF8 r	TCIF8 r	GIF8 r	TE1F7 r	HTIF7 r	TCIF7 r	GIF7 r	TE1F6 r	HTIF6 r	TCIF6 r	GIF6 r	TEIF5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF4 r	HTIF4 r	TCIF4 r	GIF4 r	TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle fields

GIF1

Bit 0: GIF1: Channel 1 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 1 1: A TE, HT or TC event occurred on channel 1.

TCIF1

Bit 1: TCIF1: Channel 1 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 1 1: A transfer complete (TC) event occurred on channel 1.

HTIF1

Bit 2: HTIF1: Channel 1 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 1 1: A half transfer (HT) event occurred on channel 1.

TEIF1

Bit 3: TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 1 1: A transfer error (TE) occurred on channel 1.

GIF2

Bit 4: GIF2: Channel 2 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 2 1: A TE, HT or TC event occurred on channel 2.

TCIF2

Bit 5: TCIF2: Channel 2 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 2 1: A transfer complete (TC) event occurred on channel 2.

HTIF2

Bit 6: HTIF2: Channel 2 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 2 1: A half transfer (HT) event occurred on channel 2.

TEIF2

Bit 7: TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 2 1: A transfer error (TE) occurred on channel 2.

GIF3

Bit 8: GIF3: Channel 3 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 3 1: A TE, HT or TC event occurred on channel 3.

TCIF3

Bit 9: TCIF3: Channel 3 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 3 1: A transfer complete (TC) event occurred on channel 3.

HTIF3

Bit 10: HTIF3: Channel 3 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 3 1: A half transfer (HT) event occurred on channel 3.

TEIF3

Bit 11: TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 3 1: A transfer error (TE) occurred on channel 3.

GIF4

Bit 12: GIF4: Channel 4 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 4 1: A TE, HT or TC event occurred on channel 4.

TCIF4

Bit 13: TCIF4: Channel 4 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 4 1: A transfer complete (TC) event occurred on channel 4.

HTIF4

Bit 14: HTIF4: Channel 4 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 4 1: A half transfer (HT) event occurred on channel 4.

TEIF4

Bit 15: TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 4 1: A transfer error (TE) occurred on channel 4.

GIF5

Bit 16: GIF5: Channel 5 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 5 1: A TE, HT or TC event occurred on channel 5.

TCIF5

Bit 17: TCIF5: Channel 5 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 5 1: A transfer complete (TC) event occurred on channel 5.

HTIF5

Bit 18: HTIF5: Channel 5 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 5 1: A half transfer (HT) event occurred on channel 5.

TEIF5

Bit 19: TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 5 1: A transfer error (TE) occurred on channel 5.

GIF6

Bit 20: GIF6: Channel 6 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 6 1: A TE, HT or TC event occurred on channel 6.

TCIF6

Bit 21: TCIF6: Channel 6 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 6 1: A transfer complete (TC) event occurred on channel 6.

HTIF6

Bit 22: HTIF6: Channel 6 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 6 1: A half transfer (HT) event occurred on channel 6.

TE1F6

Bit 23: TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 6 1: A transfer error (TE) occurred on channel 6.

GIF7

Bit 24: GIF7: Channel 7 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 7 1: A TE, HT or TC event occurred on channel 7.

TCIF7

Bit 25: TCIF7: Channel 7 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 7 1: A transfer complete (TC) event occurred on channel 7.

HTIF7

Bit 26: HTIF7: Channel 7 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 7 1: A half transfer (HT) event occurred on channel 7.

TE1F7

Bit 27: TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 7 1: A transfer error (TE) occurred on channel 7.

GIF8

Bit 28: GIF8: Channel 8 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 8 1: A TE, HT or TC event occurred on channel 8.

TCIF8

Bit 29: TCIF8: Channel 8 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 8 1: A transfer complete (TC) event occurred on channel 8.

HTIF8

Bit 30: HTIF8: Channel 8 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 8 1: A half transfer (HT) event occurred on channel 8.

TE1F8

Bit 31: TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 8 1: A transfer error (TE) occurred on channel 8.

IFCR

DMA_IFCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTEIF8 w	CHTIF8 w	CTCIF8 w	CGIF8 w	CTEIF7 w	CHTIF7 w	CTCIF7 w	CGIF7 w	CTEIF6 w	CHTIF6 w	CTCIF6 w	CGIF6 w	CTEIF5 w	CHTIF5 w	CTCIF5 w	CGIF5 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF4 w	CTCIF4 w	CGIF4 w	CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle fields

CGIF1

Bit 0: CGIF1: Channel 1 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF1

Bit 1: CTCIF1: Channel 1 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF1

Bit 2: CHTIF1: Channel 1 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF1

Bit 3: CTEIF1: Channel 1 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF2

Bit 4: CGIF2: Channel 2 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF2

Bit 5: CTCIF2: Channel 2 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF2

Bit 6: CHTIF2: Channel 2 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF2

Bit 7: CTEIF2: Channel 2 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF3

Bit 8: CGIF3: Channel 3 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF3

Bit 9: CTCIF3: Channel 3 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF3

Bit 10: CHTIF3: Channel 3 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF3

Bit 11: CTEIF3: Channel 3 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF4

Bit 12: CGIF4: Channel 4 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF4

Bit 13: CTCIF4: Channel 4 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF4

Bit 14: CHTIF4: Channel 4 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF4

Bit 15: CTEIF4: Channel 4 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF5

Bit 16: CGIF5: Channel 5 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF5

Bit 17: CTCIF5: Channel 5 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF5

Bit 18: CHTIF5: Channel 5 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF5

Bit 19: CTEIF5: Channel 5 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF6

Bit 20: CGIF6: Channel 6 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF6

Bit 21: CTCIF6: Channel 6 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF6

Bit 22: CHTIF6: Channel 6 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF6

Bit 23: CTEIF6: Channel 6 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF7

Bit 24: CGIF7: Channel 7 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF7

Bit 25: CTCIF7: Channel 7 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF7

Bit 26: CHTIF7: Channel 7 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF7

Bit 27: CTEIF7: Channel 7 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF8

Bit 28: CGIF8: Channel 8 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF8

Bit 29: CTCIF8: Channel 8 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF8

Bit 30: CHTIF8: Channel 8 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF8

Bit 31: CTEIF8: Channel 8 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CCR1

DMA_CCRx register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR1

DMA_CNDTRx register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR1

DMA_CPARx register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR1

DMA_CMARx register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR2

DMA_CCRx register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR2

DMA_CNDTRx register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR2

DMA_CPARx register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR2

DMA_CMARx register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR3

DMA_CCRx register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR3

DMA_CNDTRx register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR3

DMA_CPARx register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR3

DMA_CMARx register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR4

DMA_CCRx register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR4

DMA_CNDTRx register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR4

DMA_CPARx register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR4

DMA_CMARx register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR5

DMA_CCRx register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR5

DMA_CNDTRx register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR5

DMA_CPARx register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR5

DMA_CMARx register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR6

DMA_CCRx register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR6

DMA_CNDTRx register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR6

DMA_CPARx register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR6

DMA_CMARx register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR7

DMA_CCRx register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR7

DMA_CNDTRx register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR7

DMA_CPARx register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR7

DMA_CMARx register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR8

DMA_CCRx register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR8

DMA_CNDTRx register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR8

DMA_CPARx register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR8

DMA_CMARx register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMAMUX

0x48800000:

0/8 fields covered.

Toggle register map

Offset	Name	4
0x0	C0CR	DMAREQ_ID
0x4	C1CR	DMAREQ_ID
0x8	C2CR	DMAREQ_ID
0xc	C3CR	DMAREQ_ID
0x10	C4CR	DMAREQ_ID
0x14	C5CR	DMAREQ_ID
0x18	C6CR	DMAREQ_ID
0x1c	C7CR	DMAREQ_ID

Toggle registers

C0CR

CxCR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C1CR

CxCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C2CR

CxCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C3CR

CxCR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C4CR

CxCR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C5CR

CxCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C6CR

CxCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C7CR

CxCR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

FLASH_CTRL

0x40001000: 4kb addressable space

5/34 fields covered.

Toggle register map

Offset	Name	31	20	19	18	15	7	5	4	3	2	1	0
0x0	COMMAND						COMMAND
0x4	CONFIG							WAIT_STATES			DIS_GROUP_WRITE	REMAP
0x8	IRQSTAT								READOK_MIS	ILLCMD_MIS	CMDERR_MIS	CMDSTART_MIS	CMDDONE_MIS
0xc	IRQMASK								READOKM	ILLCMDM	CMDERRM	CMDSTARTM	CMDDONEM
0x10	IRQRAW								READOK_RIS	ILLCMD_RIS	CMDERR_RIS	CMDSTART_RIS	CMDDONE_RIS
0x14	SIZE		SWD_DISABLE	FLASH_SECURE	RAM_SIZE	FLASH_SIZE
0x18	ADDRESS					XADDR		YADDR
0x24	LFSRVAL	LFSRVAL				LFSRVAL
0x34	PAGEPROT0	SEG1				SEG0
0x38	PAGEPROT1	SEG3				SEG2
0x40	DATA0	DATA0				DATA0
0x44	DATA1	DATA1				DATA1
0x48	DATA2	DATA2				DATA2
0x4c	DATA3	DATA3				DATA3

Toggle registers

COMMAND

COMMAND register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								COMMAND rw

Toggle fields

COMMAND

Bits 0-7: Macro commands for flash operations (may require DATA0...DATA3 to be set): - 0x11 : ERASE - 0x22 : MASSERASE - 0x33 : WRITE - 0x55 : MASSREAD - 0xAA : SLEEP - 0xBB : WAKEUP - 0xCC : BURSTWRITE - 0xEE : OTPWRITE - 0xFF : KEYWRITE.

CONFIG

CONFIG register

Offset: 0x4, size: 32, reset: 0x00000010, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WAIT_STATES rw			DIS_GROUP_WRITE rw	REMAP rw

Toggle fields

REMAP

Bit 1: Bit to redirect boot area on SRAM0..

DIS_GROUP_WRITE

Bit 2: Burst write Control: - 0 : burst write allowed - 1 : burst write forbidden.

WAIT_STATES

Bits 4-5: Number of wait states to be inserted on Flash read (AHB accesses).

IRQSTAT

IRQSTAT register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											READOK_MIS rw	ILLCMD_MIS rw	CMDERR_MIS rw	CMDSTART_MIS rw	CMDDONE_MIS rw

Toggle fields

CMDDONE_MIS

Bit 0: Command done masked interrupt status..

CMDSTART_MIS

Bit 1: Command started masked interrupt status..

CMDERR_MIS

Bit 2: Command error masked interrupt status..

ILLCMD_MIS

Bit 3: Illegal command masked interrupt status.

READOK_MIS

Bit 4: Mass read OK masked interrupt status..

IRQMASK

IRQMASK register

Offset: 0xc, size: 32, reset: 0x0000003F, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											READOKM rw	ILLCMDM rw	CMDERRM rw	CMDSTARTM rw	CMDDONEM rw

Toggle fields

CMDDONEM

Bit 0: Command done mask.

CMDSTARTM

Bit 1: Command started mask..

CMDERRM

Bit 2: Command error mask..

ILLCMDM

Bit 3: Illegal command mask..

READOKM

Bit 4: Mass read OK mask..

IRQRAW

IRQRAW register

Offset: 0x10, size: 32, reset: 0x00000001, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											READOK_RIS rw	ILLCMD_RIS rw	CMDERR_RIS rw	CMDSTART_RIS rw	CMDDONE_RIS rw

Toggle fields

CMDDONE_RIS

Bit 0: Command done raw/unmasked interrupt status. This it is set once the requested command execution is completed. Cleared by writing 1..

CMDSTART_RIS

Bit 1: Command started raw/unmasked interrupt status. This bit is set once the requested command execution has started..

CMDERR_RIS

Bit 2: Command error raw/unmasked interrupt status.

ILLCMD_RIS

Bit 3: Illegal command raw/unmasked interrupt status..

READOK_RIS

Bit 4: Mass read OK raw/unmasked interrupt status.

SIZE

SIZE register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											SWD_DISABLE r	FLASH_SECURE r	RAM_SIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLASH_SIZE r

Toggle fields

FLASH_SIZE

Bits 0-15: Maximum valid address for flash memory: - 00 : 0x0BFFF (192kb) - 01 : 0x0FFFF (256kb) - 10 : 0x17FFF (384kb) - 11 : 0x1FFFF (512kb).

RAM_SIZE

Bits 17-18: RAM memory size selection: - 00 : 32kb - 01 : 32kb - 10 : 48kb - 11 : 64kb.

FLASH_SECURE

Bit 19: Flash memory protection (0: no key present, 1: key present).

SWD_DISABLE

Bit 20: Flash+SWD protection: 0: No SWD protection (refer to FLASH_SECURE) 1: Flash and SWD protected.

ADDRESS

ADDRESS register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XADDR rw										YADDR rw

Toggle fields

YADDR

Bits 0-5: Flash column address offset to be used with some COMMAND.

XADDR

Bits 6-15: Flash row address offset to be used with some COMMAND.

LFSRVAL

LFSRVAL register

Offset: 0x24, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LFSRVAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LFSRVAL r

Toggle fields

LFSRVAL

Bits 0-31: Flash read data CRC signature.

PAGEPROT0

PAGEPROT0 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEG1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEG0 rw

Toggle fields

SEG0

Bits 0-15: First segment definition..

SEG1

Bits 16-31: Second segment definition. See SEG0 description for details on SEG1[31:16] content.

PAGEPROT1

PAGEPROT1 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEG3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEG2 rw

Toggle fields

SEG2

Bits 0-15: Third segment definition. See PAGEPROT0 SEG0 description for details on SEG2[15:0] content.

SEG3

Bits 16-31: Fourth segment definition. See PAGEPROT0 SEG0 description for details on SEG3[15:0] content..

DATA0

DATA0 register

Offset: 0x40, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA0 rw

Toggle fields

DATA0

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD.

DATA1

DATA1 register

Offset: 0x44, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA1 rw

Toggle fields

DATA1

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

DATA2

DATA2 register

Offset: 0x48, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA2 rw

Toggle fields

DATA2

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

DATA3

DATA3 register

Offset: 0x4c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA3 rw

Toggle fields

DATA3

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

GLOBALSTATMACH

0x200000c0:

0/31 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	22	21	20	15	7	6	2	0
0x0	WORD0	RadioConfigPtr											RadioConfigPtr
0x4	WORD1	Timer2InitDelayNoCal							Timer12InitDelayCal				WakeupInitDelay	Active	CurStMachNum
0x8	WORD2	ReceiveNoCalDelayChk							ReceiveCalDelayChk				TransmitNoCalDelayChk	TransmitCalDelayChk
0xc	WORD3	TimeCapture	TimeCaptureSel	TxdelayEnd					TxdelayStart				TxdataReadyCheck	ConfigEndDuration
0x10	WORD4					RcvTimeout							RcvTimeout	TxReadyTimeout
0x14	WORD5	IntConfigError	IntActive2Err	intTxRxSkip	IntSeqDone		IntSemaTimeoutError	IntRcvLengthError	IntNoActiveLError	IntTxDataReadyError	IntAllTableReadyError	IntAddPointError				ChkFlagAutoClearEna	AutoTxRxskipEn
0x18	WORD6														DefaultAntennaID

Toggle registers

WORD0

WORD0 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RadioConfigPtr rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RadioConfigPtr rw

Toggle fields

RadioConfigPtr

Bits 0-31: Radio Configuration address Pointer..

WORD1

WORD1 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Timer2InitDelayNoCal rw								Timer12InitDelayCal rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WakeupInitDelay rw								Active rw	CurStMachNum rw

Toggle fields

CurStMachNum

Bits 0-6: current connection machine number..

Active

Bit 7: Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence..

WakeupInitDelay

Bits 8-15: Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM..

Timer12InitDelayCal

Bits 16-23: Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM..

Timer2InitDelayNoCal

Bits 24-31: Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM..

WORD2

WORD2 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ReceiveNoCalDelayChk rw								ReceiveCalDelayChk rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TransmitNoCalDelayChk rw								TransmitCalDelayChk rw

Toggle fields

TransmitCalDelayChk

Bits 0-7: Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block..

TransmitNoCalDelayChk

Bits 8-15: Delay between TX request sent to the Radio FSM and the start pulse to the transmit block..

ReceiveCalDelayChk

Bits 16-23: Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block..

ReceiveNoCalDelayChk

Bits 24-31: Delay between RX request sent to the Radio FSM and the start pulse to the receive block..

WORD3

WORD3 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TimeCapture rw	TimeCaptureSel rw	TxdelayEnd rw						TxdelayStart rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxdataReadyCheck rw								ConfigEndDuration rw

Toggle fields

ConfigEndDuration

Bits 0-7: Duration for the Sequencer to execute the final configuration..

TxdataReadyCheck

Bits 8-15: Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table..

TxdelayStart

Bits 16-23: Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator..

TxdelayEnd

Bits 24-29: Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer..

TimeCaptureSel

Bit 30: - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event)..

TimeCapture

Bit 31: - 0: No capture is requested to monitor the Bluetooth LE sequence..

WORD4

WORD4 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				RcvTimeout rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RcvTimeout rw								TxReadyTimeout rw

Toggle fields

TxReadyTimeout

Bits 0-7: Transmission ready timeout..

RcvTimeout

Bits 8-27: Receive window timeout..

WORD5

WORD5 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IntConfigError rw	IntActive2Err rw	intTxRxSkip rw	IntSeqDone rw		IntSemaTimeoutError rw	IntRcvLengthError rw		IntNoActiveLError rw	IntTxDataReadyError rw	IntAllTableReadyError rw	IntAddPointError rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													ChkFlagAutoClearEna rw		AutoTxRxskipEn rw

Toggle fields

AutoTxRxskipEn

Bit 0: Automatic transfer (TX or RX) skip enable..

ChkFlagAutoClearEna

Bit 2: Active bit Auto Clear Enable..

IntAddPointError

Bit 20: Address pointer error interrupt enable..

IntAllTableReadyError

Bit 21: All table ready error interrupt enable..

IntTxDataReadyError

Bit 22: Transmission data payload ready error interrupt enable..

IntNoActiveLError

Bit 23: Active bit low value reading interrupt enable..

IntRcvLengthError

Bit 25: Too long received payload length interrupt enable..

IntSemaTimeoutError

Bit 26: Semaphore timeout error interrupt enable..

IntSeqDone

Bit 28: Sequencer end of task interrupt enable..

intTxRxSkip

Bit 29: Transmission or reception skip interrupt enable..

IntActive2Err

Bit 30: not in ACTIVE2 information from Radio FSM received on time interrupt enable..

IntConfigError

Bit 31: Configuration error interrupt enable..

WORD6

WORD6 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DefaultAntennaID rw

Toggle fields

DefaultAntennaID

Bits 0-6: Default Antenna ID corresponding to the number of the antenna used to receive/transmit:.

GPIOA

0x48000000: GPIOA address block description

177/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE[15]		MODE[14]		MODE[13]		MODE[12]		MODE[11]		MODE[10]		MODE[9]		MODE[8]		MODE[7]		MODE[6]		MODE[5]		MODE[4]		MODE[3]		MODE[2]		MODE[1]		MODE[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEED[15]		OSPEED[14]		OSPEED[13]		OSPEED[12]		OSPEED[11]		OSPEED[10]		OSPEED[9]		OSPEED[8]		OSPEED[7]		OSPEED[6]		OSPEED[5]		OSPEED[4]		OSPEED[3]		OSPEED[2]		OSPEED[1]		OSPEED[0]
0xc	PUPDR	PUPD[15]		PUPD[14]		PUPD[13]		PUPD[12]		PUPD[11]		PUPD[10]		PUPD[9]		PUPD[8]		PUPD[7]		PUPD[6]		PUPD[5]		PUPD[4]		PUPD[3]		PUPD[2]		PUPD[1]		PUPD[0]
0x10	IDR																	ID[15]	ID[14]	ID[13]	ID[12]	ID[11]	ID[10]	ID[9]	ID[8]	ID[7]	ID[6]	ID[5]	ID[4]	ID[3]	ID[2]	ID[1]	ID[0]
0x14	ODR																	OD[15]	OD[14]	OD[13]	OD[12]	OD[11]	OD[10]	OD[9]	OD[8]	OD[7]	OD[6]	OD[5]	OD[4]	OD[3]	OD[2]	OD[1]	OD[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFSEL[7]				AFSEL[6]				AFSEL[5]				AFSEL[4]				AFSEL[3]				AFSEL[2]				AFSEL[1]				AFSEL[0]
0x24	AFRH	AFSEL[15]				AFSEL[14]				AFSEL[13]				AFSEL[12]				AFSEL[11]				AFSEL[10]				AFSEL[9]				AFSEL[8]
0x28	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE[15] rw		MODE[14] rw		MODE[13] rw		MODE[12] rw		MODE[11] rw		MODE[10] rw		MODE[9] rw		MODE[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE[7] rw		MODE[6] rw		MODE[5] rw		MODE[4] rw		MODE[3] rw		MODE[2] rw		MODE[1] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED[15] rw		OSPEED[14] rw		OSPEED[13] rw		OSPEED[12] rw		OSPEED[11] rw		OSPEED[10] rw		OSPEED[9] rw		OSPEED[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED[7] rw		OSPEED[6] rw		OSPEED[5] rw		OSPEED[4] rw		OSPEED[3] rw		OSPEED[2] rw		OSPEED[1] rw		OSPEED[0] rw

Toggle fields

OSPEED[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD[15] rw		PUPD[14] rw		PUPD[13] rw		PUPD[12] rw		PUPD[11] rw		PUPD[10] rw		PUPD[9] rw		PUPD[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD[7] rw		PUPD[6] rw		PUPD[5] rw		PUPD[4] rw		PUPD[3] rw		PUPD[2] rw		PUPD[1] rw		PUPD[0] rw

Toggle fields

PUPD[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID[15] r	ID[14] r	ID[13] r	ID[12] r	ID[11] r	ID[10] r	ID[9] r	ID[8] r	ID[7] r	ID[6] r	ID[5] r	ID[4] r	ID[3] r	ID[2] r	ID[1] r	ID[0] r

Toggle fields

ID[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD[15] rw	OD[14] rw	OD[13] rw	OD[12] rw	OD[11] rw	OD[10] rw	OD[9] rw	OD[8] rw	OD[7] rw	OD[6] rw	OD[5] rw	OD[4] rw	OD[3] rw	OD[2] rw	OD[1] rw	OD[0] rw

Toggle fields

OD[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = '1' + LCKR[15:0] WR LCKR[16] = '0' + LCKR[15:0] WR LCKR[16] = '1' + LCKR[15:0] RD LCKR RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the lock. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns '1' until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL[7] rw				AFSEL[6] rw				AFSEL[5] rw				AFSEL[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[3] rw				AFSEL[2] rw				AFSEL[1] rw				AFSEL[0] rw

Toggle fields

AFSEL[0]

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[1]

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[2]

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[3]

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[4]

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[5]

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[6]

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[7]

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL[15] rw				AFSEL[14] rw				AFSEL[13] rw				AFSEL[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[11] rw				AFSEL[10] rw				AFSEL[9] rw				AFSEL[8] rw

Toggle fields

AFSEL[8]

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[9]

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[10]

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[11]

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[12]

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[13]

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[14]

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[15]

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOB

0x48100000:

177/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE[15]		MODE[14]		MODE[13]		MODE[12]		MODE[11]		MODE[10]		MODE[9]		MODE[8]		MODE[7]		MODE[6]		MODE[5]		MODE[4]		MODE[3]		MODE[2]		MODE[1]		MODE[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEED[15]		OSPEED[14]		OSPEED[13]		OSPEED[12]		OSPEED[11]		OSPEED[10]		OSPEED[9]		OSPEED[8]		OSPEED[7]		OSPEED[6]		OSPEED[5]		OSPEED[4]		OSPEED[3]		OSPEED[2]		OSPEED[1]		OSPEED[0]
0xc	PUPDR	PUPD[15]		PUPD[14]		PUPD[13]		PUPD[12]		PUPD[11]		PUPD[10]		PUPD[9]		PUPD[8]		PUPD[7]		PUPD[6]		PUPD[5]		PUPD[4]		PUPD[3]		PUPD[2]		PUPD[1]		PUPD[0]
0x10	IDR																	ID[15]	ID[14]	ID[13]	ID[12]	ID[11]	ID[10]	ID[9]	ID[8]	ID[7]	ID[6]	ID[5]	ID[4]	ID[3]	ID[2]	ID[1]	ID[0]
0x14	ODR																	OD[15]	OD[14]	OD[13]	OD[12]	OD[11]	OD[10]	OD[9]	OD[8]	OD[7]	OD[6]	OD[5]	OD[4]	OD[3]	OD[2]	OD[1]	OD[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFSEL[7]				AFSEL[6]				AFSEL[5]				AFSEL[4]				AFSEL[3]				AFSEL[2]				AFSEL[1]				AFSEL[0]
0x24	AFRH	AFSEL[15]				AFSEL[14]				AFSEL[13]				AFSEL[12]				AFSEL[11]				AFSEL[10]				AFSEL[9]				AFSEL[8]
0x28	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]

Toggle registers

MODER

MODER register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE[15] rw		MODE[14] rw		MODE[13] rw		MODE[12] rw		MODE[11] rw		MODE[10] rw		MODE[9] rw		MODE[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE[7] rw		MODE[6] rw		MODE[5] rw		MODE[4] rw		MODE[3] rw		MODE[2] rw		MODE[1] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

OTYPER register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

OSPEEDR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED[15] rw		OSPEED[14] rw		OSPEED[13] rw		OSPEED[12] rw		OSPEED[11] rw		OSPEED[10] rw		OSPEED[9] rw		OSPEED[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED[7] rw		OSPEED[6] rw		OSPEED[5] rw		OSPEED[4] rw		OSPEED[3] rw		OSPEED[2] rw		OSPEED[1] rw		OSPEED[0] rw

Toggle fields

OSPEED[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

PUPDR register

Offset: 0xc, size: 32, reset: 0x55005555, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD[15] rw		PUPD[14] rw		PUPD[13] rw		PUPD[12] rw		PUPD[11] rw		PUPD[10] rw		PUPD[9] rw		PUPD[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD[7] rw		PUPD[6] rw		PUPD[5] rw		PUPD[4] rw		PUPD[3] rw		PUPD[2] rw		PUPD[1] rw		PUPD[0] rw

Toggle fields

PUPD[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

IDR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID[15] r	ID[14] r	ID[13] r	ID[12] r	ID[11] r	ID[10] r	ID[9] r	ID[8] r	ID[7] r	ID[6] r	ID[5] r	ID[4] r	ID[3] r	ID[2] r	ID[1] r	ID[0] r

Toggle fields

ID[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

ODR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD[15] rw	OD[14] rw	OD[13] rw	OD[12] rw	OD[11] rw	OD[10] rw	OD[9] rw	OD[8] rw	OD[7] rw	OD[6] rw	OD[5] rw	OD[4] rw	OD[3] rw	OD[2] rw	OD[1] rw	OD[0] rw

Toggle fields

OD[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

BSRR register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

LCKR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = '1' + LCKR[15:0] WR LCKR[16] = '0' + LCKR[15:0] WR LCKR[16] = '1' + LCKR[15:0] RD LCKR RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the lock. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns '1' until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL[7] rw				AFSEL[6] rw				AFSEL[5] rw				AFSEL[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[3] rw				AFSEL[2] rw				AFSEL[1] rw				AFSEL[0] rw

Toggle fields

AFSEL[0]

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[1]

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[2]

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[3]

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[4]

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[5]

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[6]

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[7]

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

AFRH register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL[15] rw				AFSEL[14] rw				AFSEL[13] rw				AFSEL[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[11] rw				AFSEL[10] rw				AFSEL[9] rw				AFSEL[8] rw

Toggle fields

AFSEL[8]

Bits 0-3: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[9]

Bits 4-7: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[10]

Bits 8-11: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[11]

Bits 12-15: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[12]

Bits 16-19: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[13]

Bits 20-23: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[14]

Bits 24-27: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[15]

Bits 28-31: Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os..

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

BRR register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

I2C1

0x41000000: I2C address block description

17/76 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1
0xc	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

Toggle registers

CR1

I2C control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

STOPIE

Bit 5: Stop detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Note: Transfer Complete (TC) Note: Transfer Complete Reload (TCR).

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Note: Arbitration Loss (ARLO) Note: Bus Error detection (BERR) Note: Overrun/Underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT).

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. Note: This filter can only be programmed when the I2C is disabled (PE = 0)..

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. Note: WUPEN can be set only when DNF = '0000'.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

SMBDEN

Bit 21: SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

CR2

I2C control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set..

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master mode: Note: Writing '0' to this bit has no effect..

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit has no effect when RELOAD is set. Note: This bit has no effect is slave mode when SBC=0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

OAR1

I2C own address 1 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

OA1MODE

Bit 10: Own address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

OA1EN

Bit 15: Own address 1 enable.

OAR2

I2C own address 2 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own address 2 masks Note: These bits can be written only when OA2EN=0. Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

OA2EN

Bit 15: Own address 2 enable.

TIMINGR

I2C timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

PRESC

Bits 28-31: Timing prescaler This field is used to prescale i2c_ker_ck in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page2521) and for SCL high and low level counters (refer to I2C master initialization on page2536). tPRESC = (PRESC+1) x tI2CCLK.

TIMEOUTR

I2C timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

I2C interrupt and status register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0..

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0..

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0..

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0..

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0..

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0..

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0..

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set..

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE = 0..

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0..

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0..

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0..

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR = 1)..

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

ICR

I2C interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register..

STOPCF

Bit 5: STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

ARLOCF

Bit 9: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

PECR

I2C PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0..

RXDR

I2C receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus.

TXDR

I2C transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE = 1..

I2C2

0x41001000:

18/75 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES							NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1													OA1EN					OA1MODE	OA1
0xc	OAR2													OA2EN					OA2MSK			OA2
0x10	TIMING	PRESC					SCLDEL				SDADEL			SCLH								SCLL
0x14	TIMEOUT	TEXTEN	TIMEOUTB											TIMEOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE						DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR															ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																					PEC
0x24	RXDR																					RXDATA
0x28	TXDR																					TXDATA

Toggle registers

CR1

I2C2_CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw		NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN r	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable - 0: Peripheral disable - 1: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable - 0: Transmit (TXIS) interrupt disabled - 1: Transmit (TXIS) interrupt enabled.

RXIE

Bit 2: RX Interrupt enable - 0: Receive (RXNE) interrupt disabled - 1: Receive (RXNE) interrupt enabled.

ADDRIE

Bit 3: Address match Interrupt enable (slave only) - 0: Address match (ADDR) interrupts disabled - 1: Address match (ADDR) interrupts enabled.

NACKIE

Bit 4: Not acknowledge received Interrupt enable - 0: Not acknowledge (NACKF) received interrupts disabled - 1: Not acknowledge (NACKF) received interrupts enabled.

STOPIE

Bit 5: STOP detection Interrupt enable - 0: Stop detection (STOPF) interrupt disabled - 1: Stop detection (STOPF) interrupt enabled.

TCIE

Bit 6: Transfer Complete interrupt enable - 0: Transfer Complete interrupt disabled - 1: Transfer Complete interrupt enabled.

ERRIE

Bit 7: Error interrupts enable - 0: Error detection interrupts disabled - 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK - 0000: Digital filter disabled - 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK - 1111: digital filter enabled and filtering capability up to15 tI2CCLK.

ANFOFF

Bit 12: Analog noise filter OFF - 0: Analog noise filter enabled - 1: Analog noise filter disabled.

TXDMAEN

Bit 14: DMA transmission requests enable - 0: DMA mode disabled for transmission - 1: DMA mode enabled for transmission.

RXDMAEN

Bit 15: DMA reception requests enable - 0: DMA mode disabled for reception - 1: DMA mode enabled for reception.

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode. - 0: Slave byte control disabled - 1: Slave byte control enabled.

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. - 0: Clock stretching enabled - 1: Clock stretching disabled Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

GCEN

Bit 19: General call enable - 0: General call disabled. Address 0b00000000 is NACKed. - 1: General call enabled. Address 0b00000000 is ACKed..

SMBHEN

Bit 20: SMBus Host address enable - 0: Host address disabled. Address 0b0001000x is NACKed. - 1: Host address enabled. Address 0b0001000x is ACKed..

SMBDEN

Bit 21: SMBus Device Default address enable - 0: Device default address disabled. Address 0b1100001x is NACKed. - 1: Device default address enabled. Address 0b1100001x is ACKed..

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): - 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. - 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. Host mode (SMBHEN=1): - 0: SMBus Alert pin (SMBA) not supported. - 1: SMBus Alert pin (SMBA) supported..

PECEN

Bit 23: PEC enable - 0: PEC calculation disabled - 1: PEC calculation enabled.

CR2

I2C2_CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address.

RD_WRN

Bit 10: Transfer direction (master mode) - 0: Master requests a write transfer. - 1: Master requests a read transfer..

ADD10

Bit 11: Ten-bit addressing mode (master mode) - 0: The master operates in 7-bit addressing mode, - 1: The master operates in 10-bit addressing mode.

HEAD10R

Bit 12: Ten bit (10-bit) address header only read direction (master receiver mode) - 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. - 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction..

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. - 0: No Start generation. - 1: Restart/Start generation: If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free..

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: - 0: No Stop generation. - 1: Stop generation after current byte transfer..

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. - 0: an ACK is sent after current received byte. - 1: a NACK is sent after current received byte..

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software. - 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). - 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low..

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. - 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. - 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred..

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. - 0: No PEC transfer. - 1: PEC transmission/reception is requested.

OAR1

I2C2_OAR1 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode - 0: Own address 1 is a 7-bit address. - 1: Own address 1 is a 10-bit address..

OA1EN

Bit 15: Own Address 1 enable - 0: Own address 1 disabled. The received slave address OA1 is NACKed. - 1: Own address 1 enabled. The received slave address OA1 is ACKed..

OAR2

I2C2_OAR2 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own Address 2 masks - 000: No mask - 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. - 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. - 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. - 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. - 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. - 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. - 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged..

OA2EN

Bit 15: Own Address 2 enable - 0: Own address 2 disabled. The received slave address OA2 is NACKed. - 1: Own address 2 enabled. The received slave address OA2 is ACKed..

TIMING

I2C2_TIMING register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in transmission mode. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in transmission mode. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters and for SCL high and low level counters tPRESC = (PRESC+1) x tI2CCLK.

TIMEOUT

I2C2_TIMEOUT register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection - 0: TIMEOUTA is used to detect SCL low timeout - 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) Note: This bit can be written only when TIMOUTEN=0..

TIMEOUTEN

Bit 15: Clock timeout enable - 0: SCL timeout detection is disabled - 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1)..

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable - 0: Extended clock timeout detection is disabled - 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1)..

ISR

I2C2_ISR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). - 0: Write transfer, slave enters receiver mode. - 1: Read transfer, slave enters transmitter mode..

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

ICR

I2C2_ICR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

PECR

I2C2_PECR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

RXDR

I2C2_RXDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: Eight bit (8-bit) receive data Data byte received from the I2C bus..

TXDR

I2C2_TXDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: Eight bits (8-bit) transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

IWDG

0x40003000:

3/7 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0	KR	KEY
0x4	PR			PR
0x8	RLR		RL
0xc	SR			WVU	RVU	PVU
0x10	WINR		WIN

Toggle registers

KR

IWDG_KR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value. Software can only write these bits. Reading returns the reset value. These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. Writing the key value CCCCh starts the watchdog.

PR

IWDG_PR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle fields

PR

Bits 0-2: Prescaler divider. Set and reset by software. These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider/4 001: divider/8 010: divider/16 011: divider/32 100: divider/64 101: divider/128 110: divider/256 111: divider/256.

RLR

IWDG_RLR register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value. Set and reset by software. These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value..

SR

IWDG_SR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

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PVU

Bit 0: Watchdog prescaler value update. Read only bit. This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset.

RVU

Bit 1: Watchdog counter reload value update. Read only bit. This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset.

WVU

Bit 2: Watchdog counter window value update. Read only bit. This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic window = 1.

WINR

IWDG_WINR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle fields

WIN

Bits 0-11: Watchdog counter window value. Set and reset by software. These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value..

LPUART

0x41005000:

21/80 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1			DEAT					DEDT						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE_TXFNFIE	TCIE	RXNEIE_RXFNEIE	IDLEIE	TE	RE		UE
0x4	CR2	ADD												MSBFIRST	DATAINV	TXINV	RXINV	SWAP		STOP									ADDM7
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG				TXFTIE								DEP	DEM	DDRE	OVRDIS		CTSIE	CTSE	RTSE	DMAT	DMAR			HDSEL			EIE
0xc	BRR													BRR				BRR
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ
0x1c	ISR					TXFT	RXFT		RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXE_TXFNF	TC	RXNE_RXFNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF								CTSCF			TCCF		IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE_TXFNFIE rw	TCIE rw	RXNEIE_RXFNEIE rw	IDLEIE rw	TE rw	RE rw		UE rw

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UE

Bit 0: UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled.

RE

Bit 2: RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit.

TE

Bit 3: TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled.

IDLEIE

Bit 4: IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register.

RXNEIE_RXFNEIE

Bit 5: RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register.

TCIE

Bit 6: TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register.

TXEIE_TXFNFIE

Bit 7: TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register.

PEIE

Bit 8: PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register.

PS

Bit 9: PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0)..

PCE

Bit 10: PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0)..

WAKE

Bit 11: WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0)..

M0

Bit 12: M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0)..

MME

Bit 13: MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode.

CMIE

Bit 14: CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register..

DEDT

Bits 16-20: DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0)..

DEAT

Bits 21-25: DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0)..

M1

Bit 28: Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s.

FIFOEN

Bit 29: FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled..

TXFEIE

Bit 30: TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register.

RXFFIE

Bit 31: RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register.

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw												MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw		STOP rw									ADDM7 rw

Toggle fields

ADDM7

Bit 4: ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0).

STOP

Bits 12-13: STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0)..

SWAP

Bit 15: SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0)..

RXINV

Bit 16: RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0)..

TXINV

Bit 17: TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0)..

DATAINV

Bit 18: DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0)..

MSBFIRST

Bit 19: MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0)..

ADD

Bits 24-31: ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw				TXFTIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw		CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw			HDSEL rw			EIE rw

Toggle fields

EIE

Bit 0: EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register..

HDSEL

Bit 3: HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0)..

DMAR

Bit 6: DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception.

DMAT

Bit 7: DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission.

RTSE

Bit 8: RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0)..

CTSE

Bit 9: CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0).

CTSIE

Bit 10: CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register.

OVRDIS

Bit 12: OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0)..

DDRE

Bit 13: DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0)..

DEM

Bit 14: DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0)..

DEP

Bit 15: DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0)..

TXFTIE

Bit 23: TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG..

RXFTCFG

Bits 25-27: RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved..

RXFTIE

Bit 28: RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG..

TXFTCFG

Bits 29-31: TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved..

BRR

BRR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BRR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-19: BRR[19:0].

RQR

RQR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w

Toggle fields

SBKRQ

Bit 1: SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available..

MMRQ

Bit 2: MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag..

RXFRQ

Bit 3: RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0 When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes..

ISR

ISR register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r		RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXE_TXFNF r	TC r	RXNE_RXFNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error.

FE

Bit 1: FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected.

NF

Bit 2: NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected.

ORE

Bit 3: ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected.

IDLE

Bit 4: IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected.

RXNE_RXFNE

Bit 5: RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read..

TC

Bit 6: TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete.

TXE_TXFNF

Bit 7: TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full.

CTSIF

Bit 9: CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line.

CTS

Bit 10: CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset.

BUSY

Bit 16: BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going.

CMF

Bit 17: CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected.

SBKF

Bit 18: SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted.

RWU

Bit 19: RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode.

TEACK

Bit 21: TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode..

TXFE

Bit 23: TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty..

RXFF

Bit 24: RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full..

RXFT

Bit 26: RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesnt reach the programmed threshold. -1: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesnt reach the programmed threshold. -1: TXFIFO reached the programmed threshold.

ICR

ICR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTSCF w			TCCF w		IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.

NECF

Bit 2: NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register..

ORECF

Bit 3: ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TCCF

Bit 6: TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.

CTSCF

Bit 9: CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

CMCF

Bit 17: CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.

WUCF

Bit 20: WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register.

RDR

RDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

TDR

TDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1..

PRESC

PRESC register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be 1011 i.e. input clock divided by 256.

PKA

0x48300000:

1/9 fields covered.

Toggle register map

Offset	Name	7	3	2	1	0
0x0	CSR	SFT_RST			READY	GO
0x4	ISR		ADD_ERR	RAM_ERR		PROC_END
0x8	IEN		ADDERR_EN	RAMERR_EN		READY_EN

Toggle registers

CSR

PKA_CSR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SFT_RST rw						READY r	GO rw

Toggle fields

GO

Bit 0: PKA start processing command. Writing 0 has no effect Writing 1 starts the encryption engine.

READY

Bit 1: PKA readiness status. 0: The PKA is still computing 1: The PKA is ready to start a new calculation.

SFT_RST

Bit 7: PKA software reset. Writing 0 clears the bit and releases the PKA block reset. Writing 1 resets the PKA block. The PKA RAM content is not changed..

ISR

PKA_ISR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ADD_ERR rw	RAM_ERR rw		PROC_END rw

Toggle fields

PROC_END

Bit 0: PKA process ending interrupt. When read: 0: No new event detected 1: The PKA process is ended (This bit is set to 1 when the PKA_CSR.READY bit rises.) When written: To clear the pending interrupt, the user must write this bit to 1 and clear it just after by writing 0. If the write 0 does not occur, the interrupt is generated on next event towards the CPU if enabled in PKA_IER but the flag is seen at 0 when the interrupt handler reads it in this register (as clear action is still active)..

RAM_ERR

Bit 2: RAM read / write access error interrupt..

ADD_ERR

Bit 3: AHB Address error interrupt..

IEN

PKA_IEN register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ADDERR_EN rw	RAMERR_EN rw		READY_EN rw

Toggle fields

READY_EN

Bit 0: READY interrupt enable..

RAMERR_EN

Bit 2: RAM access error interrupt enable..

ADDERR_EN

Bit 3: AHB Address error interrupt enable..

PWRC

0x48500000:

8/129 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												APC			ENSDNBOR	LPMS
0x4	CR2						LSILPMUFEN	ENTS		RAMRET3	RAMRET2	RAMRET1		PVDLS			PVDE
0x8	CR3	EIWL		EWBLEHCPU	EWBLE	EWU11	EWU10	EWU9	EWU8	EWU7	EWU6	EWU5	EWU4	EWU3	EWU2	EWU1	EWU0
0xc	CR4					WUP11	WUP10	WUP9	WUP8	WUP7	WUP6	WUP5	WUP4	WUP3	WUP2	WUP1	WUP0
0x10	SR1	IWUF		WBLEHCPUF	WBLEF	WUF11	WUF10	WUF9	WUF8	WUF7	WUF6	WUF5	WUF4	WUF3	WUF2	WUF1	WUF0
0x14	SR2	IOBOOTVAL				PVDO		REGMS	REGLPS						SMPSRDY	SMPSENR	SMPSBYPR
0x1c	CR5				CLKDETR_DISABLE	SMPS_ENA_DCM	NOSMPS	SMPSFBYP	SMPSLPOPEN			SMPSBOMSEL		SMPSLVL
0x20	PUCRA	PUA
0x24	PDCRA	PDA
0x28	PUCRB	PUB
0x2c	PDCRB	PDB
0x30	CR6	EWU27	EWU26	EWU25	EWU24	EWU23	EWU22	EWU21	EWU20	EWU19	EWU18	EWU17	EWU16	EWU15	EWU14	EWU13	EWU12
0x34	CR7	WUP27	WUP26	WUP25	WUP24	WUP23	WUP22	WUP21	WUP20	WUP19	WUP18	WUP17	WUP16	WUP15	WUP14	WUP13	WUP12
0x38	SR3	WUF27	WUF26	WUF25	WUF24	WUF23	WUF22	WUF21	WUF20	WUF19	WUF18	WUF17	WUF16	WUF15	WUF14	WUF13	WUF12
0x40	IOxCFG	IOCFG7		IOCFG6		IOCFG5		IOCFG4		IOCFG3		IOCFG2		IOCFG1		IOCFG0
0x84	DBGR																DEEPSTOP2
0x88	EXTSRR						RFPHASEF	DEEPSTOPF

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000114, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											APC rw			ENSDNBOR rw	LPMS rw

Toggle fields

LPMS

Bit 0: LPMS Low Power Mode Selection Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep..

ENSDNBOR

Bit 1: Enable BOR reset supervising during SHUTDOWN mode..

APC

Bit 4: APC Apply Pull-up and pull-down configuration from CPU.

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					LSILPMUFEN rw	ENTS rw		RAMRET3 rw	RAMRET2 rw	RAMRET1 rw		PVDLS rw			PVDE rw

Toggle fields

PVDE

Bit 0: PVDE Programmable Voltage Detector Enable When this bit is set the Power Voltage Detector is enabled.

PVDLS

Bits 1-3: PVDLS[2:0] Programmable Voltage Detector Level selection then PVDO=1).

RAMRET1

Bit 5: RAMRET1: RAM1 retention during low power mode.

RAMRET2

Bit 6: Enables the RAM2 bank retention in DEEPSTOP mode..

RAMRET3

Bit 7: Enables the RAM3 bank retention in DEEPSTOP mode..

ENTS

Bit 9: Enable the temperature sensor..

LSILPMUFEN

Bit 10: LSI LPMU force enable..

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWL rw		EWBLEHCPU rw	EWBLE rw	EWU11 rw	EWU10 rw	EWU9 rw	EWU8 rw	EWU7 rw	EWU6 rw	EWU5 rw	EWU4 rw	EWU3 rw	EWU2 rw	EWU1 rw	EWU0 rw

Toggle fields

EWU0

Bit 0: EWU0 Enable WakeUp line 0 (PB0) When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit..

EWU1

Bit 1: EWU1 Enable WakeUp line 1 (PB1) When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit..

EWU2

Bit 2: EWU2 Enable WakeUp line 2 (PB2) When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit..

EWU3

Bit 3: EWU3 Enable WakeUp line 3 (PB3) When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit..

EWU4

Bit 4: EWU4 Enable WakeUp line 4 (PB4) When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit..

EWU5

Bit 5: EWU5 Enable WakeUp line 5 (PB5) When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit..

EWU6

Bit 6: EWU6 Enable WakeUp line 6 (PB6) When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit..

EWU7

Bit 7: EWU7 Enable WakeUp line 7 (PB7) When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit..

EWU8

Bit 8: EWU8 Enable WakeUp line 8 (PA8) When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit..

EWU9

Bit 9: EWU9 Enable WakeUp line 9 (PA9) When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit..

EWU10

Bit 10: EWU10 Enable WakeUp line 10 (PA10) When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit..

EWU11

Bit 11: EWU11 Enable WakeUp line 11 (PA11) When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit..

EWBLE

Bit 12: EWBLE: Enable wakeup on BLE event. 0: Wakeup on BLE line is disabled (default). 1: Wakeup on BLE line is enabled..

EWBLEHCPU

Bit 13: EWBLEHCPU: Enable wakeup on BLE Host CPU event. 0: Wakeup on BLE Host CPU line is disabled (default). 1: Wakeup on BLE Host CPU line is enabled..

EIWL

Bit 15: EIWL: Enable wakeup on Internal event (RTC). 0: Wakeup on internal line is disabled (default). 1: Wakeup on internal line is enabled..

CR4

CR4 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WUP11 rw	WUP10 rw	WUP9 rw	WUP8 rw	WUP7 rw	WUP6 rw	WUP5 rw	WUP4 rw	WUP3 rw	WUP2 rw	WUP1 rw	WUP0 rw

Toggle fields

WUP0

Bit 0: WUP0 Wake-up Line Polarity 0 (PB0) This bit defines the polarity used for event detection on external wake-up line 0.

WUP1

Bit 1: WUP1 Wake-up Line Polarity 1 (PB1) This bit defines the polarity used for event detection on external wake-up line 1.

WUP2

Bit 2: WUP2 Wake-up Line Polarity 2 (PB2) This bit defines the polarity used for event detection on external wake-up line 2.

WUP3

Bit 3: WUP3 Wake-up Line Polarity 3 (PB3) This bit defines the polarity used for event detection on external wake-up line 3.

WUP4

Bit 4: WUP4 Wake-up Line Polarity 4 (PB4) This bit defines the polarity used for event detection on external wake-up line 4.

WUP5

Bit 5: WUP5 Wake-up Line Polarity 5 (PB5) This bit defines the polarity used for event detection on external wake-up line 5.

WUP6

Bit 6: WUP6 Wake-up Line Polarity 6 (PB6) This bit defines the polarity used for event detection on external wake-up line 6.

WUP7

Bit 7: WUP7 Wake-up Line Polarity 7 (PB7) This bit defines the polarity used for event detection on external wake-up line 7.

WUP8

Bit 8: WUP8 Wake-up Line Polarity 8 (PA8) This bit defines the polarity used for event detection on external wake-up line 8.

WUP9

Bit 9: WUP9 Wake-up Line Polarity 9 (PA9) This bit defines the polarity used for event detection on external wake-up line 9.

WUP10

Bit 10: WUP10 Wake-up Line Polarity 10 (PA10) This bit defines the polarity used for event detection on external wake-up line 10.

WUP11

Bit 11: WUP11 Wake-up Line Polarity 11 (PA11) This bit defines the polarity used for event detection on external wake-up line 11.

SR1

SR1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IWUF r		WBLEHCPUF rw	WBLEF rw	WUF11 rw	WUF10 rw	WUF9 rw	WUF8 rw	WUF7 rw	WUF6 rw	WUF5 rw	WUF4 rw	WUF3 rw	WUF2 rw	WUF1 rw	WUF0 rw

Toggle fields

WUF0

Bit 0: WUF0 WakeUp Flag 0 (PB0) This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF1

Bit 1: WUF1 WakeUp Flag 1 (PB1) This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF2

Bit 2: WUF2 WakeUp Flag 2 (PB2) This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF3

Bit 3: WUF3 WakeUp Flag 3 (PB3) This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF4

Bit 4: WUF4 WakeUp Flag 4 (PB4) This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF5

Bit 5: WUF5 WakeUp Flag 5 (PB5) This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF6

Bit 6: WUF6 WakeUp Flag 6 (PB6) This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF7

Bit 7: WUF7 WakeUp Flag 7 (PB7) This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF8

Bit 8: WUF8 WakeUp Flag 8 (PA8) This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF9

Bit 9: WUF9 WakeUp Flag 9 (PA9) This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF10

Bit 10: WUF10 WakeUp Flag 10 (PA10) This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF11

Bit 11: WUF11 WakeUp Flag 11 (PA11) This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WBLEF

Bit 12: WBLEF: BLE wakeup flag. 0: no wakeup from BLE occurred since last clear. 1: a wakeup from BLE occurred since last clear. Cleared by writing 1 in this bit..

WBLEHCPUF

Bit 13: WBLEHCPUF: BLE Host CPU wakeup flag. 0: no wakeup from BLE Host CPU occurred since last clear. 1: a wakeup from BLE Host CPU occurred since last clear. Cleared by writing 1 in this bit..

IWUF

Bit 15: IWUF: Internal wakeup flag (RTC). 0: no wakeup from RTC occurred since last clear. 1: a wakeup from RTC occurred since last clear. Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of the RTC wakeup line on the PWRC block)..

SR2

SR2 register

Offset: 0x14, size: 32, reset: 0x00000306, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOBOOTVAL r				PVDO r		REGMS r	REGLPS r						SMPSRDY r	SMPSENR r	SMPSBYPR r

Toggle fields

SMPSBYPR

Bit 0: SMPSBYPR: SMPS Force Bypass Control Replica This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state..

SMPSENR

Bit 1: SMPSENR: SMPS Enable Control Replica This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state..

SMPSRDY

Bit 2: SMPSRDY: SMPS Ready Status This bit provides the information whether SMPS is ready..

REGLPS

Bit 8: REGLPS: Regulator Low Power Started This bit provides the information whether low power regulator is ready..

REGMS

Bit 9: REGMS: Regulator Main LDO Started This bit provides the information whether main regulator is ready..

PVDO

Bit 11: PVDO: Power Voltage Detector Output When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is lower than the selected PVD threshold (CR2.PVDLS).

IOBOOTVAL

Bits 12-15: Bit3: PA11 input value on VDD33 latched at POR Bit2: PA10 input value on VDD33 latched at POR Bit1: PA9 input value on VDD33 latched at POR Bit0: PA8 input value on VDD33 latched at POR.

CR5

CR5 register

Offset: 0x1c, size: 32, reset: 0x00006014, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CLKDETR_DISABLE rw	SMPS_ENA_DCM rw	NOSMPS rw	SMPSFBYP rw	SMPSLPOPEN rw			SMPSBOMSEL rw		SMPSLVL rw

Toggle fields

SMPSLVL

Bits 0-3: SMPSLVL[3:0] SMPS Output Level Voltage Selection Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) Vout = 1.2 + 0.05*SMPSOUT (V).

SMPSBOMSEL

Bits 4-5: SMPSBOMSEL: SMPS BOM Selection:.

SMPSLPOPEN

Bit 8: SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed..

SMPSFBYP

Bit 9: SMPSFB Force SMPS Regulator in bypass mode When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR..

NOSMPS

Bit 10: NOSMPS: No SMPS Mode When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM..

SMPS_ENA_DCM

Bit 11: SMPS_ENA_DCM: enable discontinuous conduction mode.

CLKDETR_DISABLE

Bit 12: CLKDETR_DISABLE: disable SMPS clock detection The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock..

PUCRA

PUCRA register

Offset: 0x20, size: 32, reset: 0x00000F07, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUA rw

Toggle fields

PUA

Bits 0-15: PUA[x] : Pull Up Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set.

PDCRA

PDCRA register

Offset: 0x24, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PDA rw

Toggle fields

PDA

Bits 0-15: PDA[x]: Pull Down Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set.

PUCRB

PUCRB register

Offset: 0x28, size: 32, reset: 0x0000F0FF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUB rw

Toggle fields

PUB

Bits 0-15: PUB[x] : Pull Up Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set.

PDCRB

PDCRB register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PDB rw

Toggle fields

PDB

Bits 0-15: PDB[x]: Pull Down Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set.

CR6

CR6 register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EWU27 rw	EWU26 rw	EWU25 rw	EWU24 rw	EWU23 rw	EWU22 rw	EWU21 rw	EWU20 rw	EWU19 rw	EWU18 rw	EWU17 rw	EWU16 rw	EWU15 rw	EWU14 rw	EWU13 rw	EWU12 rw

Toggle fields

EWU12

Bit 0: EWU12 Enable WakeUp line 12 (PA0) When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit..

EWU13

Bit 1: EWU13 Enable WakeUp line 13 (PA1) When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit..

EWU14

Bit 2: EWU14 Enable WakeUp line 14 (PA2) When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit..

EWU15

Bit 3: EWU15 Enable WakeUp line 15 (PA3) When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit..

EWU16

Bit 4: EWU16 Enable WakeUp line 16 (PB12) When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit..

EWU17

Bit 5: EWU17 Enable WakeUp line 17 (PB13) When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit..

EWU18

Bit 6: EWU18 Enable WakeUp line 18 (PB14) When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit..

EWU19

Bit 7: EWU19 Enable WakeUp line 19 (PB15) When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit..

EWU20

Bit 8: Enable wakeup on PB8 I/O event..

EWU21

Bit 9: Enable wakeup on PB9 I/O event..

EWU22

Bit 10: Enable wakeup on PB10 I/O event..

EWU23

Bit 11: Enable wakeup on PB11 I/O event..

EWU24

Bit 12: Enable wakeup on PA12 I/O event..

EWU25

Bit 13: Enable wakeup on PA13 I/O event..

EWU26

Bit 14: Enable wakeup on PA14 I/O event..

EWU27

Bit 15: Enable wakeup on PA15 I/O event..

CR7

CR7 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUP27 rw	WUP26 rw	WUP25 rw	WUP24 rw	WUP23 rw	WUP22 rw	WUP21 rw	WUP20 rw	WUP19 rw	WUP18 rw	WUP17 rw	WUP16 rw	WUP15 rw	WUP14 rw	WUP13 rw	WUP12 rw

Toggle fields

WUP12

Bit 0: WUP12 Wake-up Line Polarity 12 (PA0) This bit defines the polarity used for event detection on external wake-up line 12.

WUP13

Bit 1: WUP13 Wake-up Line Polarity 13 (PA1) This bit defines the polarity used for event detection on external wake-up line 13.

WUP14

Bit 2: WUP14 Wake-up Line Polarity 14 (PA2) This bit defines the polarity used for event detection on external wake-up line 14.

WUP15

Bit 3: WUP15 Wake-up Line Polarity 15 (PA3) This bit defines the polarity used for event detection on external wake-up line 15.

WUP16

Bit 4: WUP16 Wake-up Line Polarity 16 (PB12) This bit defines the polarity used for event detection on external wake-up line 16.

WUP17

Bit 5: WUP17 Wake-up Line Polarity 17 (PB13) This bit defines the polarity used for event detection on external wake-up line 17.

WUP18

Bit 6: WUP18 Wake-up Line Polarity 18 (PB14) This bit defines the polarity used for event detection on external wake-up line 18.

WUP19

Bit 7: WUP19 Wake-up Line Polarity 19 (PB15) This bit defines the polarity used for event detection on external wake-up line 19.

WUP20

Bit 8: Wake-up polarity for PB8 IO event..

WUP21

Bit 9: Wake-up polarity for PB9 IO event..

WUP22

Bit 10: Wake-up polarity for PB10 IO event..

WUP23

Bit 11: Wake-up polarity for PB11 IO event..

WUP24

Bit 12: Wake-up polarity for PB12 IO event..

WUP25

Bit 13: Wake-up polarity for PB13 IO event..

WUP26

Bit 14: Wake-up polarity for PB14 IO event..

WUP27

Bit 15: Wake-up polarity for PB15 IO event..

SR3

SR3 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUF27 rw	WUF26 rw	WUF25 rw	WUF24 rw	WUF23 rw	WUF22 rw	WUF21 rw	WUF20 rw	WUF19 rw	WUF18 rw	WUF17 rw	WUF16 rw	WUF15 rw	WUF14 rw	WUF13 rw	WUF12 rw

Toggle fields

WUF12

Bit 0: WUF12 WakeUp Flag 12 PA0 This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF13

Bit 1: WUF13 WakeUp Flag 13 PA1 This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF14

Bit 2: WUF14 WakeUp Flag 14 PA2 This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF15

Bit 3: WUF15 WakeUp Flag 15 PA3 This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF16

Bit 4: WUF16 WakeUp Flag 16 PB12 This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF17

Bit 5: WUF17 WakeUp Flag 17 PB13 This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF18

Bit 6: WUF18 WakeUp Flag 18 PB14 This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF19

Bit 7: PA7 I/O wake-up flag..

WUF20

Bit 8: PB8 I/O wake-up flag..

WUF21

Bit 9: PB9 I/O wake-up flag..

WUF22

Bit 10: PB10 I/O wake-up flag..

WUF23

Bit 11: PB11 I/O wake-up flag..

WUF24

Bit 12: PB12 I/O wake-up flag..

WUF25

Bit 13: PB13 I/O wake-up flag..

WUF26

Bit 14: PB14 I/O wake-up flag..

WUF27

Bit 15: PB15 I/O wake-up flag..

IOxCFG

IOxCFG register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOCFG7 rw		IOCFG6 rw		IOCFG5 rw		IOCFG4 rw		IOCFG3 rw		IOCFG2 rw		IOCFG1 rw		IOCFG0 rw

Toggle fields

IOCFG0

Bits 0-1: Drive configuration for PA8..

IOCFG1

Bits 2-3: Drive configuration for PA9..

IOCFG2

Bits 4-5: Drive configuration for PA10..

IOCFG3

Bits 6-7: Drive configuration for PA11..

IOCFG4

Bits 8-9: Drive configuration for PA4..

IOCFG5

Bits 10-11: Drive configuration for PA5..

IOCFG6

Bits 12-13: Drive configuration for PA6..

IOCFG7

Bits 14-15: Drive configuration for PA7..

DBGR

DBGR register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															DEEPSTOP2 rw

Toggle fields

DEEPSTOP2

Bit 0: DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. 0: normal DEEPSTOP will be applied 1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP..

EXTSRR

EXTSRR register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					RFPHASEF rw	DEEPSTOPF rw

Toggle fields

DEEPSTOPF

Bit 9: DEEPSTOPF System DeepStop Flag This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field.

RFPHASEF

Bit 10: RFPHASEF RFPHASE Flag This bit is set by hardware after a Radio wake-up event (BLE activation); it is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP..

RADIO

0x60001500:

20/99 fields covered.

Toggle register map

Offset	Name	7	6	5	4	3	2	1	0
0x0	AA0_DIG_USR	AA_7_0
0x4	AA1_DIG_USR	AA_15_8
0x8	AA2_DIG_USR	AA_23_16
0xc	AA3_DIG_USR	AA_31_24
0x10	DEM_MOD_DIG_USR	CHANNEL_NUM
0x14	FSM_USR	PA_POWER					EN_CALIB_SYNTH	EN_CALIB_CBP
0x18	PHYCTRL_DIG_USR						RXTXPHY
0x48	AFC1_DIG_ENG	AFC_DELAY_BEFORE				AFC_DELAY_AFTER
0x54	CR0_DIG_ENG	CR_GAIN_BEFORE				CR_GAIN_AFTER
0x68	CR0_LR	CR_LR_GAIN_BEFORE				CR_LR_GAIN_AFTER
0x6c	VIT_CONF_DIG_ENG	SPARE							VIT_EN
0x84	LR_PD_THR_DIG_ENG	LR_PD_THR
0x88	LR_RSSI_THR_DIG_ENG	LR_RSSI_THR
0x8c	LR_AAC_THR_DIG_ENG	LR_AAC_THR
0xa8	SYNTHCAL0_DIG_ENG	SYNTH_IF_FREQ_CAL				SYNTHCAL_DEBUG_BUS_SEL
0xf0	DTB5_DIG_ENG			PORT_SELECTED_0	PORT_SELECTED_EN	INITIALIZE	RX_ACTIVE	TX_ACTIVE	RXTX_START_SEL
0x148	RXADC_ANA_USR	RXADC_DELAYTRIM_Q_TST_SEL	RXADC_DELAYTRIM_I_TST_SEL	RFD_RXADC_DELAYTRIM_Q			RFD_RXADC_DELAYTRIM_I
0x154	LDO_ANA_ENG								RFD_RF_REG_BYPASS
0x174	CBIAS0_ANA_ENG	RFD_CBIAS_IPTAT_TRIM				RFD_CBIAS_IBIAS_TRIM
0x178	CBIAS1_ANA_ENG	CBIAS0_TRIM_TST_SEL
0x180	SYNTHCAL0_DIG_OUT		VCO_CALAMP_OUT_6_0
0x184	SYNTHCAL1_DIG_OUT					VCO_CALAMP_OUT_10_7
0x188	SYNTHCAL2_DIG_OUT		VCO_CALFREQ_OUT
0x18c	SYNTHCAL3_DIG_OUT	SYNTHCAL_DEBUG_BUS
0x190	SYNTHCAL4_DIG_OUT			MOD_REF_DAC_WORD_OUT
0x194	SYNTHCAL5_DIG_OUT					CBP_CALIB_WORD
0x198	FSM_STATUS_DIG_OUT	SYNTH_CAL_ERROR			STATUS
0x1a4	RSSI0_DIG_OUT	RSSI_MEAS_OUT_7_0
0x1a8	RSSI1_DIG_OUT	RSSI_MEAS_OUT_15_8
0x1ac	AGC_DIG_OUT					AGC_ATT_OUT
0x1b0	DEMOD_DIG_OUT				RX_END	PD_FOUND	AAC_FOUND	CI_FIELD
0x1bc	AGC2_ANA_TST					AGC_ANTENNAE_USR_TRIM			AGC2_ANA_TST_SEL
0x1c0	AGC0_DIG_ENG		AGC_ENABLE	AGC_THR_HIGH
0x1c4	AGC1_DIG_ENG	AGC_LOCK_SYNC	AGC_AUTOLOCK	AGC_THR_LOW_6
0x1e8	AGC10_DIG_ENG			ATT_ANT_0		ATT_LNA_0	ATT_IF_0
0x1ec	AGC11_DIG_ENG			ATT_ANT_1		ATT_LNA_1	ATT_IF_1
0x1f0	AGC12_DIG_ENG			ATT_ANT_2		ATT_LNA_2	ATT_IF_2
0x1f4	AGC13_DIG_ENG			ATT_ANT_3		ATT_LNA_3	ATT_IF_3
0x1f8	AGC14_DIG_ENG			ATT_ANT_4		ATT_LNA_4	ATT_IF_4
0x1fc	AGC15_DIG_ENG			ATT_ANT_5		ATT_LNA_5	ATT_IF_5
0x200	AGC16_DIG_ENG			ATT_ANT_6		ATT_LNA_6	ATT_IF_6
0x204	AGC17_DIG_ENG			ATT_ANT_7		ATT_LNA_7	ATT_IF_7
0x208	AGC18_DIG_ENG			ATT_ANT_8		ATT_LNA_8	ATT_IF_8
0x20c	AGC19_DIG_ENG			ATT_ANT_9		ATT_LNA_9	ATT_IF_9
0x224	RXADC_HW_TRIM_OUT			HW_RXADC_DELAYTRIM_Q			HW_RXADC_DELAYTRIM_I
0x228	CBIAS0_HW_TRIM_OUT	HW_CBIAS_IPTAT_TRIM				HW_CBIAS_IBIAS_TRIM
0x230	AGC_HW_TRIM_OUT					HW_AGC_ANTENNAE_TRIM
0x23c	DEMOD_IQ2_DIG_TST					EXTCFG_TRIG_SELECTION		EXTCFG_SAMPLING_TIME
0x240	ANTSW0_DIG_USR		RX_TIME_TO_SAMPLE
0x244	ANTSW1_DIG_USR			RX_TIME_TO_SWITCH
0x248	ANTSW2_DIG_USR		TX_TIME_TO_SWITCH
0x24c	ANTSW3_DIG_USR		TX_TIME_TO_SWITCH_2M

Toggle registers

AA0_DIG_USR

AA0_DIG_USR register

Offset: 0x0, size: 32, reset: 0x000000D6, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_7_0 rw

Toggle fields

AA_7_0

Bits 0-7: Least significant byte of the Bluetooth LE Access Address code.

AA1_DIG_USR

AA1_DIG_USR register

Offset: 0x4, size: 32, reset: 0x000000BE, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_15_8 rw

Toggle fields

AA_15_8

Bits 0-7: Next byte of the Bluetooth LE Access Address code..

AA2_DIG_USR

AA2_DIG_USR register

Offset: 0x8, size: 32, reset: 0x00000089, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_23_16 rw

Toggle fields

AA_23_16

Bits 0-7: Next byte of the Bluetooth LE Access Address code.

AA3_DIG_USR

AA3_DIG_USR register

Offset: 0xc, size: 32, reset: 0x0000008E, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_31_24 rw

Toggle fields

AA_31_24

Bits 0-7: Most significant byte of the Bluetooth LE Access Address code..

DEM_MOD_DIG_USR

DEM_MOD_DIG_USR register

Offset: 0x10, size: 32, reset: 0x00000026, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CHANNEL_NUM rw

Toggle fields

CHANNEL_NUM

Bits 1-7: Index for internal lock up table in which the synthesizer setup is contained..

FSM_USR

RADIO_FSM_USR register

Offset: 0x14, size: 32, reset: 0x00000004, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PA_POWER rw					EN_CALIB_SYNTH rw	EN_CALIB_CBP rw

Toggle fields

EN_CALIB_CBP

Bit 1: CBP calibration enable bit..

EN_CALIB_SYNTH

Bit 2: SYNTH calibration enable bit..

PA_POWER

Bits 3-7: PA Power coefficient..

PHYCTRL_DIG_USR

PHYCTRL_DIG_USR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													RXTXPHY rw

Toggle fields

RXTXPHY

Bits 0-2: RXTXPHY selection..

AFC1_DIG_ENG

AFC1_DIG_ENG register

Offset: 0x48, size: 32, reset: 0x00000044, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AFC_DELAY_BEFORE rw				AFC_DELAY_AFTER rw

Toggle fields

AFC_DELAY_AFTER

Bits 0-3: Set the decay factor of the AFC loop after Access Address detection.

AFC_DELAY_BEFORE

Bits 4-7: Set the decay factor of the AFC loop before Access Address detection.

CR0_DIG_ENG

CR0_DIG_ENG register

Offset: 0x54, size: 32, reset: 0x00000044, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CR_GAIN_BEFORE rw				CR_GAIN_AFTER rw

Toggle fields

CR_GAIN_AFTER

Bits 0-3: Set the gain of the clock recovery loop before Access Address detection to the value.

CR_GAIN_BEFORE

Bits 4-7: Set the gain of the clock recovery loop before Access Address detection to the value.

CR0_LR

CR0_LR register

Offset: 0x68, size: 32, reset: 0x00000066, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CR_LR_GAIN_BEFORE rw				CR_LR_GAIN_AFTER rw

Toggle fields

CR_LR_GAIN_AFTER

Bits 0-3: Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use.

CR_LR_GAIN_BEFORE

Bits 4-7: Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use.

VIT_CONF_DIG_ENG

VIT_CONF_DIG_ENG register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SPARE rw							VIT_EN rw

Toggle fields

VIT_EN

Bit 0: Viterbi enable.

SPARE

Bits 2-7: spare.

LR_PD_THR_DIG_ENG

LR_PD_THR_DIG_ENG register

Offset: 0x84, size: 32, reset: 0x00000050, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LR_PD_THR rw

Toggle fields

LR_PD_THR

Bits 0-7: preamble detect threshold value.

LR_RSSI_THR_DIG_ENG

LR_RSSI_THR_DIG_ENG register

Offset: 0x88, size: 32, reset: 0x0000001B, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LR_RSSI_THR rw

Toggle fields

LR_RSSI_THR

Bits 0-7: RSSI or peak threshold value.

LR_AAC_THR_DIG_ENG

LR_AAC_THR_DIG_ENG register

Offset: 0x8c, size: 32, reset: 0x00000038, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LR_AAC_THR rw

Toggle fields

LR_AAC_THR

Bits 0-7: address coded correlation threshold.

SYNTHCAL0_DIG_ENG

SYNTHCAL0_DIG_ENG register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTH_IF_FREQ_CAL rw				SYNTHCAL_DEBUG_BUS_SEL rw

Toggle fields

SYNTHCAL_DEBUG_BUS_SEL

Bits 0-3: for Debug purpose.

SYNTH_IF_FREQ_CAL

Bits 6-7: Define the frequency applied on the PLL during calibration phase.

DTB5_DIG_ENG

DTB5_DIG_ENG register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										PORT_SELECTED_0 rw	PORT_SELECTED_EN rw	INITIALIZE rw	RX_ACTIVE rw	TX_ACTIVE rw	RXTX_START_SEL rw

Toggle fields

RXTX_START_SEL

Bit 0: enable the possibility to control some signals by the other register bits instead of system design:.

TX_ACTIVE

Bit 1: Force TX_ACTIVE signal.

RX_ACTIVE

Bit 2: Force RX_ACTIVE signal.

INITIALIZE

Bit 3: Force INITIALIZE signal (emulate a token request of the IP_BLE).

PORT_SELECTED_EN

Bit 4: enable port selection.

PORT_SELECTED_0

Bit 5: force port_selected[0] signal.

RXADC_ANA_USR

RXADC_ANA_USR register

Offset: 0x148, size: 32, reset: 0x0000001B, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXADC_DELAYTRIM_Q_TST_SEL rw	RXADC_DELAYTRIM_I_TST_SEL rw	RFD_RXADC_DELAYTRIM_Q rw			RFD_RXADC_DELAYTRIM_I rw

Toggle fields

RFD_RXADC_DELAYTRIM_I

Bits 0-2: ADC loop delay control bits for I channel to apply when SW overload is enabled.

RFD_RXADC_DELAYTRIM_Q

Bits 3-5: ADC loop delay control bits for Q channel to apply when SW overload is enabled.

RXADC_DELAYTRIM_I_TST_SEL

Bit 6: Enable the SW overload on RXADX delay trimming.

RXADC_DELAYTRIM_Q_TST_SEL

Bit 7: Enable the SW overload on RXADX delay trimming.

LDO_ANA_ENG

LDO_ANA_ENG register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RFD_RF_REG_BYPASS rw

Toggle fields

RFD_RF_REG_BYPASS

Bit 0: RF_REG Bypass mode:.

CBIAS0_ANA_ENG

CBIAS0_ANA_ENG register

Offset: 0x174, size: 32, reset: 0x00000088, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RFD_CBIAS_IPTAT_TRIM rw				RFD_CBIAS_IBIAS_TRIM rw

Toggle fields

RFD_CBIAS_IBIAS_TRIM

Bits 0-3: overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1).

RFD_CBIAS_IPTAT_TRIM

Bits 4-7: overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1).

CBIAS1_ANA_ENG

CBIAS1_ANA_ENG register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CBIAS0_TRIM_TST_SEL rw

Toggle fields

CBIAS0_TRIM_TST_SEL

Bit 7: When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings.

SYNTHCAL0_DIG_OUT

SYNTHCAL0_DIG_OUT register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VCO_CALAMP_OUT_6_0 r

Toggle fields

VCO_CALAMP_OUT_6_0

Bits 0-6: VCO CALAMP value.

SYNTHCAL1_DIG_OUT

SYNTHCAL1_DIG_OUT register

Offset: 0x184, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VCO_CALAMP_OUT_10_7 r

Toggle fields

VCO_CALAMP_OUT_10_7

Bits 0-3: VCO CALAMP value.

SYNTHCAL2_DIG_OUT

SYNTHCAL2_DIG_OUT register

Offset: 0x188, size: 32, reset: 0x00000040, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VCO_CALFREQ_OUT r

Toggle fields

VCO_CALFREQ_OUT

Bits 0-6: VCO CALFREQ value.

SYNTHCAL3_DIG_OUT

SYNTHCAL3_DIG_OUT register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTHCAL_DEBUG_BUS r

Toggle fields

SYNTHCAL_DEBUG_BUS

Bits 0-7: Calibration debug bus..

SYNTHCAL4_DIG_OUT

SYNTHCAL4_DIG_OUT register

Offset: 0x190, size: 32, reset: 0x00000018, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										MOD_REF_DAC_WORD_OUT r

Toggle fields

MOD_REF_DAC_WORD_OUT

Bits 0-5: Calibration word.

SYNTHCAL5_DIG_OUT

SYNTHCAL5_DIG_OUT register

Offset: 0x194, size: 32, reset: 0x00000007, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CBP_CALIB_WORD r

Toggle fields

CBP_CALIB_WORD

Bits 0-3: CBP Calibration word.

FSM_STATUS_DIG_OUT

FSM_STATUS_DIG_OUT register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTH_CAL_ERROR r			STATUS r

Toggle fields

STATUS

Bits 0-4: RF FSM state:.

SYNTH_CAL_ERROR

Bit 7: PLL calibration error.

RSSI0_DIG_OUT

RSSI0_DIG_OUT register

Offset: 0x1a4, size: 32, reset: 0x00000008, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RSSI_MEAS_OUT_7_0 r

Toggle fields

RSSI_MEAS_OUT_7_0

Bits 0-7: Measure of the received signal strength..

RSSI1_DIG_OUT

RSSI1_DIG_OUT register

Offset: 0x1a8, size: 32, reset: 0x00000008, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RSSI_MEAS_OUT_15_8 r

Toggle fields

RSSI_MEAS_OUT_15_8

Bits 0-7: Measure of the received signal strength.

AGC_DIG_OUT

AGC_DIG_OUT register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_ATT_OUT r

Toggle fields

AGC_ATT_OUT

Bits 0-3: AGC attenuation value.

DEMOD_DIG_OUT

DEMOD_DIG_OUT register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RX_END r	PD_FOUND r	AAC_FOUND r	CI_FIELD r

Toggle fields

CI_FIELD

Bits 0-1: CI field.

AAC_FOUND

Bit 2: aac_found.

PD_FOUND

Bit 3: pd_found.

RX_END

Bit 4: rx_end.

AGC2_ANA_TST

AGC2_ANA_TST register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_ANTENNAE_USR_TRIM rw			AGC2_ANA_TST_SEL rw

Toggle fields

AGC2_ANA_TST_SEL

Bit 0: Selection:.

AGC_ANTENNAE_USR_TRIM

Bits 1-3: the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1).

AGC0_DIG_ENG

AGC0_DIG_ENG register

Offset: 0x1c0, size: 32, reset: 0x0000004A, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									AGC_ENABLE rw	AGC_THR_HIGH rw

Toggle fields

AGC_THR_HIGH

Bits 0-5: High AGC threshold.

AGC_ENABLE

Bit 6: Enable AGC.

AGC1_DIG_ENG

AGC1_DIG_ENG register

Offset: 0x1c4, size: 32, reset: 0x00000084, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AGC_LOCK_SYNC rw	AGC_AUTOLOCK rw	AGC_THR_LOW_6 rw

Toggle fields

AGC_THR_LOW_6

Bits 0-5: Low threshold for 6dB steps.

AGC_AUTOLOCK

Bit 6: AGC locks when level is steady between high threshold and lock threshold.

AGC_LOCK_SYNC

Bit 7: AGC locks when Access Address is detected (recommended).

AGC10_DIG_ENG

AGC10_DIG_ENG register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_0 rw		ATT_LNA_0 rw	ATT_IF_0 rw

Toggle fields

ATT_IF_0

Bits 0-2: Attenuation at IF Level for the AGC step 0:.

ATT_LNA_0

Bit 3: Attenuation at LNA Level for the AGC step 0:.

ATT_ANT_0

Bits 4-5: Attenuation at Antenna Level for the AGC step 0:.

AGC11_DIG_ENG

AGC11_DIG_ENG register

Offset: 0x1ec, size: 32, reset: 0x00000010, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_1 rw		ATT_LNA_1 rw	ATT_IF_1 rw

Toggle fields

ATT_IF_1

Bits 0-2: Attenuation at IF Level for the AGC step 1.

ATT_LNA_1

Bit 3: Attenuation at LNA Level for the AGC step 1.

ATT_ANT_1

Bits 4-5: Attenuation at Antenna Level for the AGC step 1.

AGC12_DIG_ENG

AGC12_DIG_ENG register

Offset: 0x1f0, size: 32, reset: 0x00000020, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_2 rw		ATT_LNA_2 rw	ATT_IF_2 rw

Toggle fields

ATT_IF_2

Bits 0-2: Attenuation at IF Level for the AGC step 2.

ATT_LNA_2

Bit 3: Attenuation at LNA Level for the AGC step 2.

ATT_ANT_2

Bits 4-5: Attenuation at Antenna Level for the AGC step 2.

AGC13_DIG_ENG

AGC13_DIG_ENG register

Offset: 0x1f4, size: 32, reset: 0x00000030, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_3 rw		ATT_LNA_3 rw	ATT_IF_3 rw

Toggle fields

ATT_IF_3

Bits 0-2: Attenuation at IF Level for the AGC step 3.

ATT_LNA_3

Bit 3: Attenuation at LNA Level for the AGC step 3.

ATT_ANT_3

Bits 4-5: Attenuation at Antenna Level for the AGC step 3.

AGC14_DIG_ENG

AGC14_DIG_ENG register

Offset: 0x1f8, size: 32, reset: 0x00000038, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_4 rw		ATT_LNA_4 rw	ATT_IF_4 rw

Toggle fields

ATT_IF_4

Bits 0-2: Attenuation at IF Level for the AGC step 4.

ATT_LNA_4

Bit 3: Attenuation at LNA Level for the AGC step 4.

ATT_ANT_4

Bits 4-5: Attenuation at Antenna Level for the AGC step 4.

AGC15_DIG_ENG

AGC15_DIG_ENG register

Offset: 0x1fc, size: 32, reset: 0x00000039, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_5 rw		ATT_LNA_5 rw	ATT_IF_5 rw

Toggle fields

ATT_IF_5

Bits 0-2: Attenuation at IF Level for the AGC step 5.

ATT_LNA_5

Bit 3: Attenuation at LNA Level for the AGC step 5.

ATT_ANT_5

Bits 4-5: Attenuation at Antenna Level for the AGC step 5.

AGC16_DIG_ENG

AGC16_DIG_ENG register

Offset: 0x200, size: 32, reset: 0x0000003A, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_6 rw		ATT_LNA_6 rw	ATT_IF_6 rw

Toggle fields

ATT_IF_6

Bits 0-2: Attenuation at IF Level for the AGC step 6.

ATT_LNA_6

Bit 3: Attenuation at LNA Level for the AGC step 6.

ATT_ANT_6

Bits 4-5: Attenuation at Antenna Level for the AGC step 6.

AGC17_DIG_ENG

AGC17_DIG_ENG register

Offset: 0x204, size: 32, reset: 0x0000003B, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_7 rw		ATT_LNA_7 rw	ATT_IF_7 rw

Toggle fields

ATT_IF_7

Bits 0-2: Attenuation at IF Level for the AGC step 7.

ATT_LNA_7

Bit 3: Attenuation at LNA Level for the AGC step 7.

ATT_ANT_7

Bits 4-5: Attenuation at Antenna Level for the AGC step 7.

AGC18_DIG_ENG

AGC18_DIG_ENG register

Offset: 0x208, size: 32, reset: 0x0000003C, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_8 rw		ATT_LNA_8 rw	ATT_IF_8 rw

Toggle fields

ATT_IF_8

Bits 0-2: Attenuation at IF Level for the AGC step 8.

ATT_LNA_8

Bit 3: Attenuation at LNA Level for the AGC step 8.

ATT_ANT_8

Bits 4-5: Attenuation at Antenna Level for the AGC step 8.

AGC19_DIG_ENG

AGC19_DIG_ENG register

Offset: 0x20c, size: 32, reset: 0x0000003D, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_9 rw		ATT_LNA_9 rw	ATT_IF_9 rw

Toggle fields

ATT_IF_9

Bits 0-2: Attenuation at IF Level for the AGC step 9.

ATT_LNA_9

Bit 3: Attenuation at LNA Level for the AGC step 9.

ATT_ANT_9

Bits 4-5: Attenuation at Antenna Level for the AGC step 9.

RXADC_HW_TRIM_OUT

RXADC_HW_TRIM_OUT register

Offset: 0x224, size: 32, reset: 0x0000001B, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										HW_RXADC_DELAYTRIM_Q r			HW_RXADC_DELAYTRIM_I r

Toggle fields

HW_RXADC_DELAYTRIM_I

Bits 0-2: control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR)..

HW_RXADC_DELAYTRIM_Q

Bits 3-5: control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR)..

CBIAS0_HW_TRIM_OUT

CBIAS0_HW_TRIM_OUT register

Offset: 0x228, size: 32, reset: 0x00000088, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								HW_CBIAS_IPTAT_TRIM r				HW_CBIAS_IBIAS_TRIM r

Toggle fields

HW_CBIAS_IBIAS_TRIM

Bits 0-3: CBIAS current (provided by the HW trimming, automatically loaded on POR)..

HW_CBIAS_IPTAT_TRIM

Bits 4-7: CBIAS current (provided by the HW trimming, automatically loaded on POR)..

AGC_HW_TRIM_OUT

AGC_HW_TRIM_OUT register

Offset: 0x230, size: 32, reset: 0x00000006, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												HW_AGC_ANTENNAE_TRIM r

Toggle fields

HW_AGC_ANTENNAE_TRIM

Bits 1-3: AGC trim value (provided by the HW trimming, automatically loaded on POR)..

DEMOD_IQ2_DIG_TST

DEMOD_IQ2_DIG_TST register

Offset: 0x23c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EXTCFG_TRIG_SELECTION rw		EXTCFG_SAMPLING_TIME rw

Toggle fields

EXTCFG_SAMPLING_TIME

Bits 0-1: Defines the sampling time, when extended configuration is enabled:.

EXTCFG_TRIG_SELECTION

Bits 2-3: Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled:.

ANTSW0_DIG_USR

ANTSW0_DIG_USR register

Offset: 0x240, size: 32, reset: 0x0000001C, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									RX_TIME_TO_SAMPLE rw

Toggle fields

RX_TIME_TO_SAMPLE

Bits 0-6: specifies the exact timing of the first I/Q sampling in the reference period..

ANTSW1_DIG_USR

ANTSW1_DIG_USR register

Offset: 0x244, size: 32, reset: 0x0000000B, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RX_TIME_TO_SWITCH rw

Toggle fields

RX_TIME_TO_SWITCH

Bits 0-5: specifies the exact timing of the antenna switching at receiver level (in AoA)..

ANTSW2_DIG_USR

ANTSW2_DIG_USR register

Offset: 0x248, size: 32, reset: 0x00000029, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TX_TIME_TO_SWITCH rw

Toggle fields

TX_TIME_TO_SWITCH

Bits 0-6: specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD)..

ANTSW3_DIG_USR

ANTSW3_DIG_USR register

Offset: 0x24c, size: 32, reset: 0x00000023, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TX_TIME_TO_SWITCH_2M rw

Toggle fields

TX_TIME_TO_SWITCH_2M

Bits 0-6: specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD)..

RADIO_CONTROL

0x60001000:

5/10 fields covered.

Toggle register map

Offset	Name	26	18	15	13	11	8	7	0
0x0	ID			PRODUCT		VERSION		REVISION
0x4	CLK32COUNT_REG						SLOW_COUNT
0x8	CLK32PERIOD_REG		SLOW_PERIOD	SLOW_PERIOD
0xc	CLK32FREQUENCY_REG	SLOW_FREQUENCY		SLOW_FREQUENCY
0x10	IRQ_STATUS				RADIO_FSM_IRQ				SLOW_CLK_IRQ
0x14	IRQ_ENABLE				RADIO_FSM_IRQ_MASK				SLOW_CLK_IRQ_MASK

Toggle registers

ID

RADIO_CONTROL_ID register

Offset: 0x0, size: 32, reset: 0x00003000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRODUCT r				VERSION r				REVISION r

Toggle fields

REVISION

Bits 4-7: Incremented for metal fix version.

VERSION

Bits 8-11: Cut Number.

PRODUCT

Bits 12-15: incremented on major features add-on like new Bluetooth LE SIG version support.

CLK32COUNT_REG

CLK32COUNT_REG register

Offset: 0x4, size: 32, reset: 0x00000017, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SLOW_COUNT rw

Toggle fields

SLOW_COUNT

Bits 0-8: program the window length (in slow clock period) for slow clock measurement..

CLK32PERIOD_REG

CLK32PERIOD_REG register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SLOW_PERIOD r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SLOW_PERIOD r

Toggle fields

SLOW_PERIOD

Bits 0-18: indicates slow clock period information..

CLK32FREQUENCY_REG

CLK32FREQUENCY_REG register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SLOW_FREQUENCY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SLOW_FREQUENCY r

Toggle fields

SLOW_FREQUENCY

Bits 0-26: value equal to (2^39/ SLOW_PERIOD)..

IRQ_STATUS

RADIO_CONTROL_IRQ_STATUS register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RADIO_FSM_IRQ rw													SLOW_CLK_IRQ rw

Toggle fields

SLOW_CLK_IRQ

Bit 0: slow clock measurement end of calculation interrupt status.

RADIO_FSM_IRQ

Bits 8-13: Radio FSM interrupt status (aka RfFsm_event_irq)..

IRQ_ENABLE

RADIO_CONTROL_IRQ_ENABLE register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RADIO_FSM_IRQ_MASK rw													SLOW_CLK_IRQ_MASK rw

Toggle fields

SLOW_CLK_IRQ_MASK

Bit 0: mask slow clock measurement interrupt.

RADIO_FSM_IRQ_MASK

Bits 8-13: mask for each RfFsm_event (Radio FSM) interrupt..

RCC

0x48400000:

12/96 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	22	21	18	17	16	15	14	13	12	10	9	8	7	6	5	4	3	2	1	0
0x0	CR												HSERDY	HSEON		HSIPLLRDY	HSIPLLON	HSEPLLBUFON	HSIRDY	LOCKDET_NSTOP			LSEBYP	LSERDY	LSEON	LSIRDY	LSION
0x8	CFGR	CCOPRE			MCOSEL			LCOSEL	SPI2I2SCLKSEL	SPI3I2SCLKSEL			IOBOOSTEN	CLKSLOWSEL	CLKSLOWSEL			SMPSDIV				CLKSYSDIV					STOPHSI	HSESEL	SMPSINV
0x18	CIER																				WDGRSTIE	RTCRSTIE	HSIPLLUNLOCKDETIE	HSIPLLRDYIE	HSERDYIE	HSIRDYIE		LSERDYIE	LSIRDYIE
0x1c	CIFR																				WDGRSTIF	RTCRSTIF	HSIPLLUNLOCKDETIF	HSIPLLRDYIF	HSERDYIF	HSIRDYIF		LSERDYIF	LSIRDYIF
0x20	CSCMDR																					EOFSEQ_IRQ	EOFSEQ_IE	STATUS		CLKSYSDIV_REQ			REQUEST
0x30	AHBRSTR											RNGRST		PKARST				CRCRST								GPIOBRST	GPIOARST		DMARST
0x34	APB0RSTR															WDGRST		RTCRST			SYSCFGRST								TIM1RST
0x38	APB1RSTR								I2C2RST		I2C1RST					SPI3RST		SPI2RST	USARTRST		LPUARTRST				ADCRST				SPI1RST
0x40	APB2RSTR																												MRBLERST
0x50	AHBENR											RNGEN		PKAEN				CRCEN								GPIOBEN	GPIOAEN		DMAEN
0x54	APB0ENR															WDGEN		RTCEN			SYSCFGEN								TIM1EN
0x58	APB1ENR								I2C2EN		I2C1EN					SPI3EN		SPI2EN	USART1EN		LPUARTEN			ADCANAEN	ADCDIGEN				SPI1EN
0x60	APB2ENR																										CLKBLEDIV		MRBLEEN
0x94	CSR		LOCKUPRSTF	WDGRSTF	SFTRSTF	PORRSTF	PADRSTF		RMVF
0x98	RFSWHSECR																SWXOTUNE					SWXOTUNEEN	GMC			SATRG
0x9c	RFHSECR																							XOTUNE

Toggle registers

CR

CR register

Offset: 0x0, size: 32, reset: 0x00001400, access: read-write

5/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	HSIPLLRDY r	HSIPLLON rw	HSEPLLBUFON rw		HSIRDY r	LOCKDET_NSTOP rw			LSEBYP rw	LSERDY r	LSEON rw	LSIRDY r	LSION rw

Toggle fields

LSION

Bit 2: Internal Low Speed oscillator enable Set and reset by software. Reset source only for this field: PORESETn.

LSIRDY

Bit 3: Internal Low Speed oscillator Ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. Reset source only for this field: PORESETn.

LSEON

Bit 4: External Low Speed Clock enable. Set and reset by software. Reset source only for this field: PORESETn.

LSERDY

Bit 5: External Low Speed Clock ready flag. Set by hardware to indicate that LSE oscillator is stable..

LSEBYP

Bit 6: External Low Speed Clock bypass. Set and reset by software. Reset source only for this field: PORESETn.

LOCKDET_NSTOP

Bits 7-9: Lock detector Nstop value When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0..

HSIRDY

Bit 10: Internal High Speed clock ready flag. Set by hardware to indicate that internal RC 64MHz oscillator is stable. This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request)..

HSEPLLBUFON

Bit 12: External High Speed Clock Buffer for PLL RF2G4 enable. Set and reset by software..

HSIPLLON

Bit 13: Internal High Speed Clock PLL enable.

HSIPLLRDY

Bit 14: Internal High Speed Clock PLL ready flag..

HSEON

Bit 16: External High Speed Clock enable. Set and reset by software. in low power mode, HSE is turned off..

HSERDY

Bit 17: External High Speed Clock ready flag. Set by hardware to indicate that HSE oscillator is stable..

CFGR

CFGR register

Offset: 0x8, size: 32, reset: 0x00000240, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCOPRE rw			MCOSEL rw			LCOSEL rw		SPI2I2SCLKSEL rw	SPI3I2SCLKSEL rw					IOBOOSTEN rw	CLKSLOWSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKSLOWSEL rw			SMPSDIV rw					CLKSYSDIV rw					STOPHSI rw	HSESEL rw	SMPSINV rw

Toggle fields

SMPSINV

Bit 0: bit to control inversion of the SMPS clock.

HSESEL

Bit 1: Clock source selection request:.

STOPHSI

Bit 2: Stop HSI clock source request.

CLKSYSDIV

Bits 5-7: CLKSYSDIV: system clock divided factor from HSI_64M..

SMPSDIV

Bit 12: SMPS clock prescaling factor to generate 4MHz or 8MHz.

CLKSLOWSEL

Bits 15-16: slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn.

IOBOOSTEN

Bit 17: IO BOOSTER enable Set and reset by software..

SPI3I2SCLKSEL

Bit 22: Selection of I2S1 clock: 1x:64MHz peripheral clock.

SPI2I2SCLKSEL

Bit 23: Selection of I2S clock: 1x:64MHz peripheral clock.

LCOSEL

Bits 24-25: Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn.

MCOSEL

Bits 26-28: Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible..

CCOPRE

Bits 29-31: Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used.

CIER

CIER register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							WDGRSTIE rw	RTCRSTIE rw	HSIPLLUNLOCKDETIE rw	HSIPLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw		LSERDYIE rw	LSIRDYIE rw

Toggle fields

LSIRDYIE

Bit 0: LSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization..

LSERDYIE

Bit 1: LSE Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization..

HSIRDYIE

Bit 3: HSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization..

HSERDYIE

Bit 4: HSE Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization..

HSIPLLRDYIE

Bit 5: HSI PLL Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE..

HSIPLLUNLOCKDETIE

Bit 6: HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock..

RTCRSTIE

Bit 7: RTCRSTIE: RTC reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the RTC reset end..

WDGRSTIE

Bit 8: WDGRSTIE: Watchdog reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the watchdog reset end..

CIFR

CIFR register

Offset: 0x1c, size: 32, reset: 0x00000008, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							WDGRSTIF rw	RTCRSTIF rw	HSIPLLUNLOCKDETIF rw	HSIPLLRDYIF rw	HSERDYIF rw	HSIRDYIF rw		LSERDYIF rw	LSIRDYIF rw

Toggle fields

LSIRDYIF

Bit 0: LSI Ready Interrupt flag Set by hardware when LSI clock becomes stable..

LSERDYIF

Bit 1: LSE Ready Interrupt Flag. Set by hardware when LSE clock becomes stable..

HSIRDYIF

Bit 3: HSI Ready Interrupt Flag. Set by hardware when HSI becomes stable..

HSERDYIF

Bit 4: HSE Ready Interrupt Flag. Set by hardware when HSE becomes stable..

HSIPLLRDYIF

Bit 5: HSI PLL Ready Interrupt Flag. Set by hardware when HSI PLL 64MHz becomes stable..

HSIPLLUNLOCKDETIF

Bit 6: HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag..

RTCRSTIF

Bit 7: RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

WDGRSTIF

Bit 8: WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

CSCMDR

CSCMDR register

Offset: 0x20, size: 32, reset: 0x00000080, access: read-write

1/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EOFSEQ_IRQ rw	EOFSEQ_IE rw	STATUS r		CLKSYSDIV_REQ rw			REQUEST rw

Toggle fields

REQUEST

Bit 0: Request for system clock switching Cleared by hardware when system clock frequency switch is done.

CLKSYSDIV_REQ

Bits 1-3: system clock dividing factor from HSI_64M requested Note: behavior depends on BLEEN in APB2ENR register.

STATUS

Bits 4-5: Status of clock switch sequence.

EOFSEQ_IE

Bit 6: End of sequence Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the clock system switch..

EOFSEQ_IRQ

Bit 7: End of Sequence flag Set by hardware when clock system swtich is ended.

AHBRSTR

AHBRSTR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													RNGRST rw		PKARST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw									GPIOBRST rw	GPIOARST rw		DMARST rw

Toggle fields

DMARST

Bit 0: DMA and DMAMUX reset Set and reset by software..

GPIOARST

Bit 2: GPIOA reset Set and reset by software..

GPIOBRST

Bit 3: GPIOB reset Set and reset by software..

CRCRST

Bit 12: CRC reset Set and reset by software..

PKARST

Bit 16: PKA reset Set and reset by software..

RNGRST

Bit 18: RNG reset Set and reset by software..

APB0RSTR

APB0RSTR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WDGRST rw		RTCRST rw				SYSCFGRST rw								TIM1RST rw

Toggle fields

TIM1RST

Bit 0: TIM1: Advanced Timer reset Set and reset by software..

SYSCFGRST

Bit 8: SYSTEM CONFIG reset Set and reset by software..

RTCRST

Bit 12: RTC reset Set and reset by software..

WDGRST

Bit 14: WATCHDOG reset Set and reset by software..

APB1RSTR

APB1RSTR register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								I2C2RST rw		I2C1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3RST rw		SPI2RST rw		USARTRST rw		LPUARTRST rw				ADCRST rw				SPI1RST rw

Toggle fields

SPI1RST

Bit 0: SPI1 reset.

ADCRST

Bit 4: ADC reset..

LPUARTRST

Bit 8: LPUART reset Set and reset by software..

USARTRST

Bit 10: USART reset Set and reset by software..

SPI2RST

Bit 12: SPI2 reset..

SPI3RST

Bit 14: SPI3 reset Set and reset by software..

I2C1RST

Bit 21: I2C1 reset Set and reset by software..

I2C2RST

Bit 23: 2C2 reset..

APB2RSTR

APB2RSTR register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															MRBLERST rw

Toggle fields

MRBLERST

Bit 0: MR_BLE (Bluetooth radio) reset..

AHBENR

AHBENR register

Offset: 0x50, size: 32, reset: 0x0000000C, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													RNGEN rw		PKAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw									GPIOBEN rw	GPIOAEN rw		DMAEN rw

Toggle fields

DMAEN

Bit 0: DMA and DMAMUX enable Set and enable by software..

GPIOAEN

Bit 2: GPIOA enable. It must be enabled by default.

GPIOBEN

Bit 3: GPIOB enable. It must be enabled by default.

CRCEN

Bit 12: CRC enable Set and enable by software..

PKAEN

Bit 16: PKA clock enable Set and enable by software..

RNGEN

Bit 18: RNG clock enable Set and enable by software..

APB0ENR

APB0ENR register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WDGEN rw		RTCEN rw				SYSCFGEN rw								TIM1EN rw

Toggle fields

TIM1EN

Bit 0: TIM1 enable.

SYSCFGEN

Bit 8: SYSTEM CONFIG enable Set and enable by software..

RTCEN

Bit 12: RTC clock enable Set and enable by software. Reset source only for this field: PORESETn.

WDGEN

Bit 14: Watchdog clock enable. Set and enable by software..

APB1ENR

APB1ENR register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								I2C2EN rw		I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3EN rw		SPI2EN rw		USART1EN rw		LPUARTEN rw			ADCANAEN rw	ADCDIGEN rw				SPI1EN rw

Toggle fields

SPI1EN

Bit 0: SPI1 enable..

ADCDIGEN

Bit 4: ADC clock enable for digital part of the ADC block..

ADCANAEN

Bit 5: ADC clock enable for the analog part of the ADC block..

LPUARTEN

Bit 8: LPUART clock enable Set and enable by software..

USART1EN

Bit 10: USART clock enable Set and enable by software..

SPI2EN

Bit 12: SPI2 enable.

SPI3EN

Bit 14: SPI3 clock enable Set and enable by software..

I2C1EN

Bit 21: I2C1 clock enable Set and enable by software..

I2C2EN

Bit 23: I2C2 enable..

APB2ENR

APB2ENR register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKBLEDIV rw		MRBLEEN rw

Toggle fields

MRBLEEN

Bit 0: MR_BLE enable.

CLKBLEDIV

Bit 2: MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1.

CSR

CSR register

Offset: 0x94, size: 32, reset: 0x0C000000, access: read-write

5/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	LOCKUPRSTF r	WDGRSTF r	SFTRSTF r	PORRSTF r	PADRSTF r			RMVF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

RMVF

Bit 23: Remove reset flag Set by software to clear the value of the reset flags. It auto clears by HW after clearing reason flags.

PADRSTF

Bit 26: SYSTEM reset flag Reset by software by writing the RMVF bit. Set by hardware when a reset from pad occurs..

PORRSTF

Bit 27: POWER reset flag Reset by software by writing the RMVF bit. Set by hardware when a power reset occurs from LPMURESET block..

SFTRSTF

Bit 28: Software reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs..

WDGRSTF

Bit 29: Watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a watchdog reset from V33 domain occurs..

LOCKUPRSTF

Bit 30: LOCK UP reset flag from CM0 Reset by software by writing the RMVF bit. Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals..

RFSWHSECR

RFSWHSECR register

Offset: 0x98, size: 32, reset: 0x00000030, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SWXOTUNE rw						SWXOTUNEEN rw	GMC rw			SATRG rw

Toggle fields

SATRG

Bit 3: Sense Amplifier threshold Set by software..

GMC

Bits 4-6: High Speed External XO current control Set by software..

SWXOTUNEEN

Bit 7: RF-HSE capacitor bank tuning by SW enable Set by software.

SWXOTUNE

Bits 8-13: RF-HSE capacitor bank tuning value by SW Set by software.

RFHSECR

RFHSECR register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										XOTUNE r

Toggle fields

XOTUNE

Bits 0-5: RF-HSE capacitor bank tuning Set by option byte loading soon after Power On Reset..

RNG

0x48600000:

4/6 fields covered.

Toggle register map

Offset	Name	15	3	2	1	0
0x0	CR		TST_CLK		RNG_DIS
0x4	SR			FAULT	REVCLK	RNGRDY
0x8	VAL	RND_VAL

Toggle registers

CR

RNG_CR register

Offset: 0x0, size: 32, reset: 0x0000FF00, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TST_CLK rw		RNG_DIS rw

Toggle fields

RNG_DIS

Bit 1: This bit enables or disables the random number generator. 0: RNG is enabled (default) 1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block..

TST_CLK

Bit 3: Reset reveal clock error flags when writing a '1' without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset..

SR

RNG_SR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FAULT r	REVCLK r	RNGRDY r

Toggle fields

RNGRDY

Bit 0: New random value ready.

REVCLK

Bit 1: RNGCLK clock reveal bit..

FAULT

Bit 2: Fault reveal bit..

VAL

RNG_VAL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RND_VAL r

Toggle fields

RND_VAL

Bits 0-15: Random value.

RRM

0x60001400:

1/33 fields covered.

Toggle register map

Offset	Name	31	15	4	3	2	1	0
0x10	UDRA_CTRL0							RELOAD_RDCFGPTR
0x14	UDRA_IRQ_ENABLE					CMD_END	CMD_START	RADIO_CFG_PTR_RELOADED
0x18	UDRA_IRQ_STATUS					CMD_END	CMD_STARD	RADIO_CFG_PTR_RELOADED
0x1c	UDRA_RADIO_CFG_PTR	RADIO_CONFIG_ADDRESS	RADIO_CONFIG_ADDRESS
0x20	SEMA_IRQ_ENABLE						UNLOCK	LOCK
0x24	SEMA_IRQ_STATUS						UNLOCK	LOCK
0x28	BLE_IRQ_ENABLE			PORT_CMD_END	PORT_CMD_START		PORT_RELEASE	PORT_GRANT
0x2c	BLE_IRQ_STATUS			CMD_END	CMD_START		PORT_RELEASE	PORT_GRANT
0x60	VP_CPU_CMD_BUS				COMMAND_REQ	COMMAND
0x64	VP_CPU_SEMA_BUS				TAKE_REQ	TAKE_PRIO
0x68	VP_CPU_IRQ_ENABLE			PORT_CMD_END	PORT_CMD_START		PORT_RELEASE	PORT_GRANT
0x6c	VP_CPU_IRQ_STATUS			CMD_END	CMD_START	PORT_PREEMPT	PORT_RELEASE	PORT_GRANT

Toggle registers

UDRA_CTRL0

UDRA_CTRL0 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RELOAD_RDCFGPTR rw

Toggle fields

RELOAD_RDCFGPTR

Bit 0: reload the radio configuration pointer from RAM..

UDRA_IRQ_ENABLE

UDRA_IRQ_ENABLE register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CMD_END rw	CMD_START rw	RADIO_CFG_PTR_RELOADED rw

Toggle fields

RADIO_CFG_PTR_RELOADED

Bit 0: UDRA interrupt enable (reload radio config pointer).

CMD_START

Bit 1: UDRA interrupt enable (command start).

CMD_END

Bit 2: UDRA interrupt enable (command end).

UDRA_IRQ_STATUS

UDRA_IRQ_STATUS register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CMD_END rw	CMD_STARD rw	RADIO_CFG_PTR_RELOADED rw

Toggle fields

RADIO_CFG_PTR_RELOADED

Bit 0: On read, returns the UDRA reload radio configuration pointer interrupt status..

CMD_STARD

Bit 1: On read, returns the UDRA command start interrupt status..

CMD_END

Bit 2: On read, returns the UDRA command end interrupt status.

UDRA_RADIO_CFG_PTR

UDRA_RADIO_CFG_PTR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RADIO_CONFIG_ADDRESS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RADIO_CONFIG_ADDRESS r

Toggle fields

RADIO_CONFIG_ADDRESS

Bits 0-31: UDRA radio configuration address..

SEMA_IRQ_ENABLE

SEMA_IRQ_ENABLE register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UNLOCK rw	LOCK rw

Toggle fields

LOCK

Bit 0: semaphore locked (= one port granted) interrupt enable.

UNLOCK

Bit 1: semaphore unlocked (=no port selected) interrupt enable.

SEMA_IRQ_STATUS

SEMA_IRQ_STATUS register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UNLOCK rw	LOCK rw

Toggle fields

LOCK

Bit 0: On read, returns the semaphore locked interrupt status..

UNLOCK

Bit 1: On read, returns the semaphore unlocked interrupt status..

BLE_IRQ_ENABLE

BLE_IRQ_ENABLE register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PORT_CMD_END rw	PORT_CMD_START rw		PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: IP_BLE Port grant interrupt enable.

PORT_RELEASE

Bit 1: IP_BLE Port release interrupt enable.

PORT_CMD_START

Bit 3: IP_BLE Port command start interrup enable.

PORT_CMD_END

Bit 4: IP_BLE Port command end interrup enable.

BLE_IRQ_STATUS

BLE_IRQ_STATUS register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMD_END rw	CMD_START rw		PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: IP_BLE hardware port granted interrupt status:.

PORT_RELEASE

Bit 1: IP_BLE hardware port released interrupt status..

CMD_START

Bit 3: IP_BLE hardware port command start interrupt status..

CMD_END

Bit 4: IP_BLE hardware port command end interrupt status..

VP_CPU_CMD_BUS

VP_CPU_CMD_BUS register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												COMMAND_REQ rw	COMMAND rw

Toggle fields

COMMAND

Bits 0-2: command number.

COMMAND_REQ

Bit 3: CPU Virtual port command request:.

VP_CPU_SEMA_BUS

VP_CPU_SEMA_BUS register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TAKE_REQ rw	TAKE_PRIO rw

Toggle fields

TAKE_PRIO

Bits 0-2: semaphore priority: priority value (between 0 and 7) of the take request..

TAKE_REQ

Bit 3: semaphore token request:.

VP_CPU_IRQ_ENABLE

VP_CPU_IRQ_ENABLE register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PORT_CMD_END rw	PORT_CMD_START rw		PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: CPU virtual port grant interrupt enable.

PORT_RELEASE

Bit 1: CPU virtual port release interrupt enable.

PORT_CMD_START

Bit 3: CPU virtual port command start interrup enable.

PORT_CMD_END

Bit 4: CPU virtual port command end interrup enable.

VP_CPU_IRQ_STATUS

VP_CPU_IRQ_STATUS register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMD_END rw	CMD_START rw	PORT_PREEMPT rw	PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: CPU virtual port granted interrupt status..

PORT_RELEASE

Bit 1: virtual port released interrupt status..

PORT_PREEMPT

Bit 2: CPU virtual port preemption (at semaphore level) interrupt status..

CMD_START

Bit 3: CPU virtual port command start interrupt status..

CMD_END

Bit 4: CPU virtual port command end interrupt status..

RTC

0x40004000:

5/67 fields covered.

Toggle register map

Offset	Name	31	30	29	27	23	22	21	20	19	18	17	16	15	14	13	12	11	10	8	7	6	5	4	3	2	0
0x0	TR						PM	HT		HU					MNT			MNU				ST			SU
0x4	DR					YT				YU				WDU			MT	MU					DT		DU
0x8	CR					COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H		WUTIE		ALRAIE		WUTE	ALRAE		FMT	BYPSHAD			WUCKSEL
0xc	ISR												RECALPF						WUTF	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUTWF	ALRAWF
0x10	PRER						PREDIV_A								PREDIV_S
0x14	WUTR													WUT
0x1c	ALRMAR	MSK4	WDSEL	DT	DU	MSK3	PM	HT		HU				MSK2	MNT			MNU			MSK1	ST			SU
0x24	WPR																				KEY
0x28	SSR													SS
0x2c	SHIFTR	ADD1S													SUBFS
0x3c	CALR													CALP	CALW8	CALW16				CALM
0x44	ALRMASSR				MASKSS										SS
0x50	BKP0R	BKP												BKP
0x54	BKP1R	BKP												BKP

Toggle registers

TR

RTC_TR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation. 0: AM or 24-hour format 1: PM.

DR

RTC_DR register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format..

DT

Bits 4-5: Date tens in BCD format..

MU

Bits 8-11: Month units in BCD format..

MT

Bit 12: Month tens in BCD format..

WDU

Bits 13-15: Week day units 000: forbidden 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Sunday.

YU

Bits 16-19: Year units in BCD format..

YT

Bits 20-23: Year tens in BCD format..

CR

RTC_CR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H w	ADD1H w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WUTIE rw		ALRAIE rw		WUTE rw		ALRAE rw		FMT rw	BYPSHAD rw			WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value.

BYPSHAD

Bit 5: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters..

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable 0: Alarm A disabled 1: Alarm A enabled.

WUTE

Bit 10: Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled.

ALRAIE

Bit 12: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled.

WUTIE

Bit 14: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled.

ADD1H

Bit 16: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change.

SUB1H

Bit 17: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change..

BKP

Bit 18: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not..

COSEL

Bit 19: Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255)..

POL

Bit 20: Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0])..

OSEL

Bits 21-22: Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Reserved 11: Wakeup output enabled.

COE

Bit 23: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled.

ISR

RTC_ISR register

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

4/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					WUTF rw		ALRAF rw	INIT rw	INITF r	RSF rw	INITS r	SHPF rw	WUTWF r		ALRAWF r

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ALRAWF

Bit 0: Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed..

WUTWF

Bit 2: Wakeup timer write flag This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed..

SHPF

Bit 3: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect..

INITS

Bit 4: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). 0: Calendar has not been initialized 1: Calendar has been initialized.

RSF

Bit 5: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized..

INITF

Bit 6: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed..

INIT

Bit 7: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset..

ALRAF

Bit 8: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0..

WUTF

Bit 10: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again..

RECALPF

Bit 16: Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0..

PRER

RTC_PRER register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

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PREDIV_S

Bits 0-14: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1).

PREDIV_A

Bits 16-22: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1).

WUTR

RTC_WUTR register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden..

ALRMAR

RTC_ALRMAR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MSK1

Bit 7: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds dont care in Alarm A comparison.

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

MSK2

Bit 15: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes dont care in Alarm A comparison.

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation 0: AM or 24-hour format 1: PM.

MSK3

Bit 23: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours dont care in Alarm A comparison.

DU

Bits 24-27: Date units or day in BCD format..

DT

Bits 28-29: Date tens in BCD format..

WDSEL

Bit 30: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is dont care..

MSK4

Bit 31: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day dont care in Alarm A comparison.

WPR

RTC_WPR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

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KEY

Bits 0-7: Write protection key This byte is written by software. Reading this byte always returns 0x00.

SSR

RTC_SSR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

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SS

Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ).

SHIFTR

RTC_SHIFTR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

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SUBFS

Bits 0-14: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescalers counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) ..

ADD1S

Bit 31: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation..

CALR

RTC_CALR register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

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CALM

Bits 0-8: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP..

CALW16

Bit 13: Use a 16-second calibration cycle period When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stucked at 0 when CALW16=1..

CALW8

Bit 14: Use an 8-second calibration cycle period When CALW8 is set to 1 , the 8-second calibration cycle period is selected. Note: CALM[1:0] are stucked at 00 when CALW8=1..

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM..

ALRMASSR

RTC_ALRMASSR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value This value is compared with the contents of the synchronous prescalers counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared..

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..

BKP0R

RTC_BKP0R register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

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BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only..

BKP1R

RTC_BKP1R register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

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BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only..

SPI1

0x41002000:

12/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc	DR	DR
0x10	CRCPR	CRCPOLY
0x14	RXCRCR	RXCRC
0x18	TXCRCR	TXCRC
0x1c	I2SCFGR				ASTREN	I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

SPI1_CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase - 0: The first clock transition is the first data capture edge - 1: The second clock transition is the first data capture edge.

CPOL

Bit 1: Clock polarity - 0: CK to 0 when idle - 1: CK to 1 when idle.

MSTR

Bit 2: Master selection - 0: Slave configuration - 1: Master configuration.

BR

Bits 3-5: Baud rate control - 000: fPCLK/2 - 001: fPCLK/4 - 010: fPCLK/8 - 011: fPCLK/16 - 100: fPCLK/32 - 101: fPCLK/64 - 110: fPCLK/128 - 111: fPCLK/256.

SPE

Bit 6: SPI enable - 0: Peripheral disabled - 1: Peripheral enabled.

LSBFIRST

Bit 7: Frame format - 0: data is transmitted / received with the MSB first - 1: data is transmitted / received with the LSB first.

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored..

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. - 0: Software slave management disabled - 1: Software slave management enabled.

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. - 0: Full duplex (Transmit and receive) - 1: Output disabled (Receive-only mode).

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. - 0: 8-bit CRC length - 1: 16-bit CRC length.

CRCNEXT

Bit 12: Transmit CRC next - 0: Next transmit value is from Tx buffer - 1: Next transmit value is from Tx CRC register.

CRCEN

Bit 13: Hardware CRC calculation enable - 0: CRC calculation disabled - 1: CRC calculation Enabled.

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode - 0: Output disabled (receive-only mode) - 1: Output enabled (transmit-only mode).

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. - 0: 2-line unidirectional data mode selected - 1: 1-line bidirectional data mode selected.

CR2

SPI1_CR2 register

Offset: 0x4, size: 32, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

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RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. - 0: Rx buffer DMA disabled - 1: Rx buffer DMA enabled.

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. - 0: Tx buffer DMA disabled - 1: Tx buffer DMA enabled.

SSOE

Bit 2: SS output enable - 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration - 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment..

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. - 0: No NSS pulse - 1: NSS pulse generated.

FRF

Bit 4: Frame format - 0: SPI Motorola mode - 1 SPI TI mode.

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). - 0: Error interrupt is masked - 1: Error interrupt is enabled.

RXNEIE

Bit 6: RX buffer not empty interrupt enable - 0: RXNE interrupt masked - 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set..

TXEIE

Bit 7: Tx buffer empty interrupt enable - 0: TXE interrupt masked - 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set..

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers: - 0000: Not used - 0001: Not used - 0010: Not used - 0011: 4-bit - 0100: 5-bit - 0101: 6-bit - 0110: 7-bit - 0111: 8-bit - 1000: 9-bit - 1001: 10-bit - 1010: 11-bit - 1011: 12-bit - 1100: 13-bit - 1101: 14-bit - 1110: 15-bit - 1111: 16-bit If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit)..

FRXTH

Bit 12: FIFO reception threshold FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. This bit is used to set the threshold of the RXFIFO that triggers an RXNE event - 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit).

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

SR

SPI1_SR register

Offset: 0x8, size: 32, reset: 0x00000002, access: read-write

10/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty - 0: Rx buffer empty - 1: Rx buffer not empty.

TXE

Bit 1: Transmit buffer empty - 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). - 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer)..

CHSIDE

Bit 2: Channel side - 0: Channel Left has to be transmitted or has been received - 1: Channel Right has to be transmitted or has been received.

UDR

Bit 3: Underrun flag - 0: No underrun occurred - 1: Underrun occurred.

CRCERR

Bit 4: CRC error flag - 0: CRC value received matches the SPIx_RXCRCR value - 1: CRC value received does not match the SPIx_RXCRCR value This flag is set by hardware and cleared by software writing 0..

MODF

Bit 5: Mode fault - 0: No mode fault occurred - 1: Mode fault occurred.

OVR

Bit 6: Overrun flag - 0: No overrun occurred - 1: Overrun occurred.

BSY

Bit 7: Busy flag - 0: SPI (or I2S) not busy - 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware..

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software. - 0: No frame format error - 1: A frame format error occurred.

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full.

FTLVL

Bits 11-12: FIFO Transmission Level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2).

DR

SPI1_DR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 18.5.8: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

CRCPR

SPI1_CRCPR register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

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CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required..

RXCRCR

SPI1_RXCRCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. A read to this register when the BSY Flag is set could return an incorrect value..

TXCRCR

SPI1_TXCRCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

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TXCRC

Bits 0-15: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..

I2SCFGR

SPI1_I2SCFGR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ASTREN rw	I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

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CHLEN

Bit 0: Channel length (number of bits per audio channel) - 0: 16-bit wide - 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in..

DATLEN

Bits 1-2: Data length to be transferred - 00: 16-bit data length - 01: 24-bit data length - 10: 32-bit data length - 11: Not allowed.

CKPOL

Bit 3: Steady state clock polarity - 0: I2S clock steady state is low level - 1: I2S clock steady state is high level.

I2SSTD

Bits 4-5: I2S standard selection - 00: I2S Philips standard. - 01: MSB justified standard (left justified) - 10: LSB justified standard (right justified) - 11: PCM standard.

PCMSYNC

Bit 7: PCM frame synchronization - 0: Short frame synchronization - 1: Long frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode..

I2SCFG

Bits 8-9: I2S configuration mode - 00: Slave - transmit - 01: Slave - receive - 10: Master - transmit - 11: Master - receive.

I2SE

Bit 10: I2S enable - 0: I2S peripheral is disabled - 1: I2S peripheral is enabled Note: This bit is not used in SPI mode..

I2SMOD

Bit 11: I2S mode selection - 0: SPI mode is selected - 1: I2S mode is selected Note: This bit should be configured when the SPI is disabled..

ASTREN

Bit 12: Asynchronous start enable. - 0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. - 1: The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards..

I2SPR

SPI1_I2SPR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

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I2SDIV

Bits 0-7: I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values..

ODD

Bit 8: Odd factor for the prescaler - 0: Real divider value is = I2SDIV *2 - 1: Real divider value is = (I2SDIV * 2)+1.

MCKOE

Bit 9: Master clock output enable - 0: Master clock output is disabled - 1: Master clock output is enabled.

SPI2

0x41003000:

12/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc	DR	DR
0x10	CRCPR	CRCPOLY
0x14	RXCRCR	RXCRC
0x18	TXCRCR	TXCRC
0x1c	I2SCFGR				ASTREN	I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

SPI2_CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

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CPHA

Bit 0: Clock phase - 0: The first clock transition is the first data capture edge - 1: The second clock transition is the first data capture edge.

CPOL

Bit 1: Clock polarity - 0: CK to 0 when idle - 1: CK to 1 when idle.

MSTR

Bit 2: Master selection - 0: Slave configuration - 1: Master configuration.

BR

Bits 3-5: Baud rate control - 000: fPCLK/2 - 001: fPCLK/4 - 010: fPCLK/8 - 011: fPCLK/16 - 100: fPCLK/32 - 101: fPCLK/64 - 110: fPCLK/128 - 111: fPCLK/256.

SPE

Bit 6: SPI enable - 0: Peripheral disabled - 1: Peripheral enabled.

LSBFIRST

Bit 7: Frame format - 0: data is transmitted / received with the MSB first - 1: data is transmitted / received with the LSB first.

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored..

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. - 0: Software slave management disabled - 1: Software slave management enabled.

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. - 0: Full duplex (Transmit and receive) - 1: Output disabled (Receive-only mode).

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. - 0: 8-bit CRC length - 1: 16-bit CRC length.

CRCNEXT

Bit 12: Transmit CRC next - 0: Next transmit value is from Tx buffer - 1: Next transmit value is from Tx CRC register.

CRCEN

Bit 13: Hardware CRC calculation enable - 0: CRC calculation disabled - 1: CRC calculation Enabled.

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode - 0: Output disabled (receive-only mode) - 1: Output enabled (transmit-only mode).

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. - 0: 2-line unidirectional data mode selected - 1: 1-line bidirectional data mode selected.

CR2

SPI2_CR2 register

Offset: 0x4, size: 32, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

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RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. - 0: Rx buffer DMA disabled - 1: Rx buffer DMA enabled.

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. - 0: Tx buffer DMA disabled - 1: Tx buffer DMA enabled.

SSOE

Bit 2: SS output enable - 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration - 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment..

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. - 0: No NSS pulse - 1: NSS pulse generated.

FRF

Bit 4: Frame format - 0: SPI Motorola mode - 1 SPI TI mode.

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). - 0: Error interrupt is masked - 1: Error interrupt is enabled.

RXNEIE

Bit 6: RX buffer not empty interrupt enable - 0: RXNE interrupt masked - 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set..

TXEIE

Bit 7: Tx buffer empty interrupt enable - 0: TXE interrupt masked - 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set..

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers: - 0000: Not used - 0001: Not used - 0010: Not used - 0011: 4-bit - 0100: 5-bit - 0101: 6-bit - 0110: 7-bit - 0111: 8-bit - 1000: 9-bit - 1001: 10-bit - 1010: 11-bit - 1011: 12-bit - 1100: 13-bit - 1101: 14-bit - 1110: 15-bit - 1111: 16-bit If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit)..

FRXTH

Bit 12: FIFO reception threshold FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. This bit is used to set the threshold of the RXFIFO that triggers an RXNE event - 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit).

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

SR

SPI2_SR register

Offset: 0x8, size: 32, reset: 0x00000002, access: read-write

10/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

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RXNE

Bit 0: Receive buffer not empty - 0: Rx buffer empty - 1: Rx buffer not empty.

TXE

Bit 1: Transmit buffer empty - 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). - 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer)..

CHSIDE

Bit 2: Channel side - 0: Channel Left has to be transmitted or has been received - 1: Channel Right has to be transmitted or has been received.

UDR

Bit 3: Underrun flag - 0: No underrun occurred - 1: Underrun occurred.

CRCERR

Bit 4: CRC error flag - 0: CRC value received matches the SPIx_RXCRCR value - 1: CRC value received does not match the SPIx_RXCRCR value This flag is set by hardware and cleared by software writing 0..

MODF

Bit 5: Mode fault - 0: No mode fault occurred - 1: Mode fault occurred.

OVR

Bit 6: Overrun flag - 0: No overrun occurred - 1: Overrun occurred.

BSY

Bit 7: Busy flag - 0: SPI (or I2S) not busy - 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware..

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software. - 0: No frame format error - 1: A frame format error occurred.

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full.

FTLVL

Bits 11-12: FIFO Transmission Level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2).

DR

SPI2_DR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

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DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 18.5.8: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

CRCPR

SPI2_CRCPR register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

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CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required..

RXCRCR

SPI2_RXCRCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

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RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. A read to this register when the BSY Flag is set could return an incorrect value..

TXCRCR

SPI2_TXCRCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

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TXCRC

Bits 0-15: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..

I2SCFGR

SPI2_I2SCFGR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ASTREN rw	I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

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CHLEN

Bit 0: Channel length (number of bits per audio channel) - 0: 16-bit wide - 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in..

DATLEN

Bits 1-2: Data length to be transferred - 00: 16-bit data length - 01: 24-bit data length - 10: 32-bit data length - 11: Not allowed.

CKPOL

Bit 3: Steady state clock polarity - 0: I2S clock steady state is low level - 1: I2S clock steady state is high level.

I2SSTD

Bits 4-5: I2S standard selection - 00: I2S Philips standard. - 01: MSB justified standard (left justified) - 10: LSB justified standard (right justified) - 11: PCM standard.

PCMSYNC

Bit 7: PCM frame synchronization - 0: Short frame synchronization - 1: Long frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode..

I2SCFG

Bits 8-9: I2S configuration mode - 00: Slave - transmit - 01: Slave - receive - 10: Master - transmit - 11: Master - receive.

I2SE

Bit 10: I2S enable - 0: I2S peripheral is disabled - 1: I2S peripheral is enabled Note: This bit is not used in SPI mode..

I2SMOD

Bit 11: I2S mode selection - 0: SPI mode is selected - 1: I2S mode is selected Note: This bit should be configured when the SPI is disabled..

ASTREN

Bit 12: Asynchronous start enable. - 0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. - 1: The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards..

I2SPR

SPI2_I2SPR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

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I2SDIV

Bits 0-7: I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values..

ODD

Bit 8: Odd factor for the prescaler - 0: Real divider value is = I2SDIV *2 - 1: Real divider value is = (I2SDIV * 2)+1.

MCKOE

Bit 9: Master clock output enable - 0: Master clock output is disabled - 1: Master clock output is enabled.

SPI3

0x41007000: SPI address block description

12/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RXCRC
0x18 (16-bit)	TXCRCR	TXCRC
0x1c (16-bit)	I2SCFGR				ASTRTEN	I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

SPI control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..

CPOL

Bit 1: Clock polarity Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..

MSTR

Bit 2: Master selection Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I2S mode..

BR

Bits 3-5: Baud rate control Note: These bits should not be changed when communication is ongoing. Note: These bits are not used in I2S mode..

SPE

Bit 6: SPI enable Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. Note: This bit is not used in I2S mode..

LSBFIRST

Bit 7: Frame format Note: 1. This bit should not be changed when communication is ongoing. Note: 2. This bit is not used in I2S mode and SPI TI mode..

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode..

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode..

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode..

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I2S mode..

CRCNEXT

Bit 12: Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. Note: This bit is not used in I2S mode..

CRCEN

Bit 13: Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I2S mode..

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. Note: This bit is not used in I2S mode..

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode..

CR2

SPI control register 2

Offset: 0x4, size: 16, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set..

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set..

SSOE

Bit 2: SS output enable Note: This bit is not used in I2S mode and SPI TI mode..

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1 , or FRF = 1 . Note: 1. This bit must be written only when the SPI is disabled (SPE=0). Note: 2. This bit is not used in I2S mode and SPI TI mode..

FRF

Bit 4: Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). Note: This bit is not used in I2S mode..

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode)..

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I2S mode..

FRXTH

Bit 12: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode..

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode..

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode..

SR

SPI status register

Offset: 0x8, size: 16, reset: 0x00000002, access: read-write

10/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode..

UDR

Bit 3: Underrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. Note: This bit is not used in SPI mode..

CRCERR

Bit 4: CRC error flag Note: This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I2S mode..

MODF

Bit 5: Mode fault This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. Note: This bit is not used in I2S mode..

OVR

Bit 6: Overrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence..

BSY

Bit 7: Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789..

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software..

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled..

FTLVL

Bits 11-12: FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode..

DR

SPI data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

CRCPR

SPI CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required..

RXCRCR

SPI Rx CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. Note: These bits are not used in I2S mode..

TXCRCR

SPI Tx CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-15: Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. Note: These bits are not used in I2S mode..

I2SCFGR

SPIx_I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ASTRTEN rw	I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode..

DATLEN

Bits 1-2: Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode..

CKPOL

Bit 3: Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode. Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals..

I2SSTD

Bits 4-5: I2S standard selection For more details on I2S standards, refer to Section 27.7.2 on page 805 Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode..

PCMSYNC

Bit 7: PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). Note: It is not used in SPI mode..

I2SCFG

Bits 8-9: I2S configuration mode Note: These bits should be configured when the I2S is disabled. Note: They are not used in SPI mode..

I2SE

Bit 10: I2S enable Note: This bit is not used in SPI mode..

I2SMOD

Bit 11: I2S mode selection Note: This bit should be configured when the SPI is disabled..

ASTRTEN

Bit 12: Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. Note: The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Note: Please refer to Section 27.7.3: Start-up description for additional information..

I2SPR

SPIx_I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to Section 27.7.3 on page 812. Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. Note: They are not used in SPI mode..

ODD

Bit 8: Odd factor for the prescaler Refer to Section 27.7.3 on page 812. Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode..

MCKOE

Bit 9: Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode..

SYSTEM_CTRL

0x40000000:

6/180 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DIE_ID																					PRODUCT				VERSION				REVISION
0x4	JTAG_ID	VERSION_NUMBER				PART_NUMBER												PART_NUMBER				MANUF_ID
0x8	I2C_FMP_CTRL																													I2C1_PB7_FMP	I2C1_PB6_FMP	I2C1_PA1_FMP	I2C1_PA0_FMP
0xc	IO_DTR	PB15_DT	PB14_DT	PB13_DT	PB12_DT	PB11_DT	PB10_DT	PB9_DT	PB8_DT	PB7_DT	PB6_DT	PB5_DT	PB4_DT	PB3_DT	PB2_DT	PB1_DT	PB0_DT					PA11_DT	PA10_DT	PA9_DT	PA8_DT	PA7_DT	PA6_DT	PA5_DT	PA4_DT	PA3_DT	PA2_DT	PA1_DT	PA0_DT
0x10	IO_IBER	PB15_IBE	PB14_IBE	PB13_IBE	PB12_IBE	PB11_IBE	PB10_IBE	PB9_IBE	PB8_IBE	PB7_IBE	PB6_IBE	PB5_IBE	PB4_IBE	PB3_IBE	PB2_IBE	PB1_IBE	PB0_IBE	PA15_IBE	PA14_IBE	PA13_IBE	PA12_IBE	PA11_IBE	PA10_IBE	PA9_IBE	PA8_IBE	PA7_IBE	PA6_IBE	PA5_IBE	PA4_IBE	PA3_IBE	PA2_IBE	PA1_IBE	PA0_IBE
0x14	IO_IEVR	PB15_IEV	PB14_IEV	PB13_IEV	PB12_IEV	PB11_IEV	PB10_IEV	PB9_IEV	PB8_IEV	PB7_IEV	PB6_IEV	PB5_IEV	PB4_IEV	PB3_IEV	PB2_IEV	PB1_IEV	PB0_IEV	PA15_IEV	PA14_IEV	PA13_IEV	PA12_IEV	PA11_IEV	PA10_IEV	PA9_IEV	PA8_IEV	PA7_IEV	PA6_IEV	PA5_IEV	PA4_IEV	PA3_IEV	PA2_IEV	PA1_IEV	PA0_IEV
0x18	IO_IER	PB15_IE	PB14_IE	PB13_IE	PB12_IE	PB11_IE	PB10_IE	PB9_IE	PB8_IE	PB7_IE	PB6_IE	PB5_IE	PB4_IE	PB3_IE	PB2_IE	PB1_IE	PB0_IE	PA15_IE	PA14_IE	PA13_IE	PA12_IE	PA11_IE	PA10_IE	PA9_IE	PA8_IE	PA7_IE	PA6_IE	PA5_IE	PA4_IE	PA3_IE	PA2_IE	PA1_IE	PA0_IE
0x1c	IO_ISCR	PB15_ISC	PB14_ISC	PB13_ISC	PB12_ISC	PB11_ISC	PB10_ISC	PB9_ISC	PB8_ISC	PB7_ISC	PB6_ISC	PB5_ISC	PB4_ISC	PB3_ISC	PB2_ISC	PB1_ISC	PB0_ISC	PA15_ISC	PA14_ISC	PA13_ISC	PA12_ISC	PA11_ISC	PA10_ISC	PA9_ISC	PA8_ISC	PA7_ISC	PA6_ISC	PA5_ISC	PA4_ISC	PA3_ISC	PA2_ISC	PA1_ISC	PA0_ISC
0x20	PWRC_IER																														WKUP_IE	PVD_IE
0x24	PWRC_ISCR																														WKUP_ISC	PVD_ISC
0x2c	BLERXTX_DTR																															RX_DT	TX_DT
0x30	BLERXTX_IBER																															RX_IBE	TX_IBE
0x34	BLERXTX_IEVR																															RX_IEV	TX_IEV
0x38	BLERXTX_IER																															RX_IE	TX_IE
0x3c (8-bit)	BLERXTX_ISCR																															RX_ISC	TX_ISC

Toggle registers

DIE_ID

DIE_ID register

Offset: 0x0, size: 32, reset: 0x00000120, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PRODUCT r				VERSION r				REVISION r

Toggle fields

REVISION

Bits 0-3: Cut revision (metal fix).

VERSION

Bits 4-7: Cut version.

PRODUCT

Bits 8-11: Product version. May be used to discriminate several version of a same digital BLE LPH device embedding different analog versions.

JTAG_ID

JTAG_ID register

Offset: 0x4, size: 32, reset: 0x0201E041, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VERSION_NUMBER r				PART_NUMBER r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PART_NUMBER r				MANUF_ID r

Toggle fields

MANUF_ID

Bits 1-11: Manufacturer ID.

PART_NUMBER

Bits 12-27: Part number.

VERSION_NUMBER

Bits 28-31: Version.

I2C_FMP_CTRL

I2C_FMP_CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												I2C1_PB7_FMP rw	I2C1_PB6_FMP rw	I2C1_PA1_FMP rw	I2C1_PA0_FMP rw

Toggle fields

I2C1_PA0_FMP

Bit 0: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. 0: PA0 pin operated in standard mode. 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed.

I2C1_PA1_FMP

Bit 1: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. 0: PA1 pin operated in standard mode. 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed.

I2C1_PB6_FMP

Bit 2: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. 0: PB6 pin operated in standard mode. 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed..

I2C1_PB7_FMP

Bit 3: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. 0: PB7 pin operated in standard mode. 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed.

IO_DTR

IO_DTR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_DT rw	PB14_DT rw	PB13_DT rw	PB12_DT rw	PB11_DT rw	PB10_DT rw	PB9_DT rw	PB8_DT rw	PB7_DT rw	PB6_DT rw	PB5_DT rw	PB4_DT rw	PB3_DT rw	PB2_DT rw	PB1_DT rw	PB0_DT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PA11_DT rw	PA10_DT rw	PA9_DT rw	PA8_DT rw	PA7_DT rw	PA6_DT rw	PA5_DT rw	PA4_DT rw	PA3_DT rw	PA2_DT rw	PA1_DT rw	PA0_DT rw

Toggle fields

PA0_DT

Bit 0: PA0_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA1_DT

Bit 1: PA1_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA2_DT

Bit 2: PA2_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA3_DT

Bit 3: PA3_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA4_DT

Bit 4: PA4_DT:Interrupt Detection Type for port A I/Os..

PA5_DT

Bit 5: PA5_DT:Interrupt Detection Type for port A I/Os..

PA6_DT

Bit 6: PA6_DT:Interrupt Detection Type for port A I/Os..

PA7_DT

Bit 7: PA7_DT:Interrupt Detection Type for port A I/Os..

PA8_DT

Bit 8: PA8_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA9_DT

Bit 9: PA9_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA10_DT

Bit 10: PA10_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA11_DT

Bit 11: PA11_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PB0_DT

Bit 16: PB0_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB1_DT

Bit 17: PB1_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB2_DT

Bit 18: PB2_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB3_DT

Bit 19: PB3_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB4_DT

Bit 20: PB4_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB5_DT

Bit 21: PB5_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB6_DT

Bit 22: PB6_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB7_DT

Bit 23: PB7_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB8_DT

Bit 24: PB8_DT:Interrupt Detection Type for port B I/Os..

PB9_DT

Bit 25: PB9_DT:Interrupt Detection Type for port B I/Os..

PB10_DT

Bit 26: PB10_DT:Interrupt Detection Type for port B I/Os..

PB11_DT

Bit 27: PB11_DT:Interrupt Detection Type for port B I/Os..

PB12_DT

Bit 28: PB12_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB13_DT

Bit 29: PB13_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB14_DT

Bit 30: PB14_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB15_DT

Bit 31: PB15_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

IO_IBER

IO_IBER register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IBE rw	PB14_IBE rw	PB13_IBE rw	PB12_IBE rw	PB11_IBE rw	PB10_IBE rw	PB9_IBE rw	PB8_IBE rw	PB7_IBE rw	PB6_IBE rw	PB5_IBE rw	PB4_IBE rw	PB3_IBE rw	PB2_IBE rw	PB1_IBE rw	PB0_IBE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_IBE rw	PA14_IBE rw	PA13_IBE rw	PA12_IBE rw	PA11_IBE rw	PA10_IBE rw	PA9_IBE rw	PA8_IBE rw	PA7_IBE rw	PA6_IBE rw	PA5_IBE rw	PA4_IBE rw	PA3_IBE rw	PA2_IBE rw	PA1_IBE rw	PA0_IBE rw

Toggle fields

PA0_IBE

Bit 0: PA0_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA1_IBE

Bit 1: PA1_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA2_IBE

Bit 2: PA2_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA3_IBE

Bit 3: PA3_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA4_IBE

Bit 4: PA4_IBE: Interrupt edge selection for Port A I/Os..

PA5_IBE

Bit 5: PA5_IBE: Interrupt edge selection for Port A I/Os..

PA6_IBE

Bit 6: PA6_IBE: Interrupt edge selection for Port A I/Os..

PA7_IBE

Bit 7: PA7_IBE: Interrupt edge selection for Port A I/Os..

PA8_IBE

Bit 8: PA8_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA9_IBE

Bit 9: PA9_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA10_IBE

Bit 10: PA10_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA11_IBE

Bit 11: PA11_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA12_IBE

Bit 12: PA12_IBE: Interrupt edge selection for Port A I/Os..

PA13_IBE

Bit 13: PA13_IBE: Interrupt edge selection for Port A I/Os..

PA14_IBE

Bit 14: PA14_IBE: Interrupt edge selection for Port A I/Os..

PA15_IBE

Bit 15: PA15_IBE: Interrupt edge selection for Port A I/Os..

PB0_IBE

Bit 16: PB0_IBE: Interrupt edge selection for port B I/Os..

PB1_IBE

Bit 17: PB1_IBE: Interrupt edge selection for port B I/Os..

PB2_IBE

Bit 18: PB2_IBE: Interrupt edge selection for port B I/Os..

PB3_IBE

Bit 19: PB3_IBE: Interrupt edge selection for port B I/Os..

PB4_IBE

Bit 20: PB4_IBE: Interrupt edge selection for port B I/Os..

PB5_IBE

Bit 21: PB5_IBE: Interrupt edge selection for port B I/Os..

PB6_IBE

Bit 22: PB6_IBE: Interrupt edge selection for port B I/Os..

PB7_IBE

Bit 23: PB7_IBE: Interrupt edge selection for port B I/Os..

PB8_IBE

Bit 24: PB8_IBE: Interrupt edge selection for port B I/Os..

PB9_IBE

Bit 25: PB9_IBE: Interrupt edge selection for port B I/Os..

PB10_IBE

Bit 26: PB10_IBE: Interrupt edge selection for port B I/Os..

PB11_IBE

Bit 27: PB11_IBE: Interrupt edge selection for port B I/Os..

PB12_IBE

Bit 28: PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB13_IBE

Bit 29: PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB14_IBE

Bit 30: PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB15_IBE

Bit 31: PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

IO_IEVR

IO_IEVR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IEV rw	PB14_IEV rw	PB13_IEV rw	PB12_IEV rw	PB11_IEV rw	PB10_IEV rw	PB9_IEV rw	PB8_IEV rw	PB7_IEV rw	PB6_IEV rw	PB5_IEV rw	PB4_IEV rw	PB3_IEV rw	PB2_IEV rw	PB1_IEV rw	PB0_IEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_IEV rw	PA14_IEV rw	PA13_IEV rw	PA12_IEV rw	PA11_IEV rw	PA10_IEV rw	PA9_IEV rw	PA8_IEV rw	PA7_IEV rw	PA6_IEV rw	PA5_IEV rw	PA4_IEV rw	PA3_IEV rw	PA2_IEV rw	PA1_IEV rw	PA0_IEV rw

Toggle fields

PA0_IEV

Bit 0: PA0_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA1_IEV

Bit 1: PA1_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA2_IEV

Bit 2: PA2_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA3_IEV

Bit 3: PA3_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA4_IEV

Bit 4: PA4_IEV : Interrupt polarity event for Port A I/Os..

PA5_IEV

Bit 5: PA5_IEV : Interrupt polarity event for Port A I/Os..

PA6_IEV

Bit 6: PA6_IEV : Interrupt polarity event for Port A I/Os..

PA7_IEV

Bit 7: PA7_IEV : Interrupt polarity event for Port A I/Os..

PA8_IEV

Bit 8: PA8_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA9_IEV

Bit 9: PA9_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA10_IEV

Bit 10: PA10_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA11_IEV

Bit 11: PA11_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA12_IEV

Bit 12: PA12_IEV : Interrupt polarity event for Port A I/Os..

PA13_IEV

Bit 13: PA13_IEV : Interrupt polarity event for Port A I/Os..

PA14_IEV

Bit 14: PA14_IEV : Interrupt polarity event for Port A I/Os..

PA15_IEV

Bit 15: PA15_IEV : Interrupt polarity event for Port A I/Os..

PB0_IEV

Bit 16: PB0_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB1_IEV

Bit 17: PB1_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB2_IEV

Bit 18: PB2_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB3_IEV

Bit 19: PB3_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB4_IEV

Bit 20: PB4_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB5_IEV

Bit 21: PB5_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB6_IEV

Bit 22: PB6_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB7_IEV

Bit 23: PB7_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB8_IEV

Bit 24: PB8_IEV : Interrupt polarity event for Port B I/Os..

PB9_IEV

Bit 25: PB9_IEV : Interrupt polarity event for Port B I/Os..

PB10_IEV

Bit 26: PB10_IEV : Interrupt polarity event for Port B I/Os..

PB11_IEV

Bit 27: PB11_IEV : Interrupt polarity event for Port B I/Os..

PB12_IEV

Bit 28: PB12_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB13_IEV

Bit 29: PB13_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB14_IEV

Bit 30: PB14_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB15_IEV

Bit 31: PB15_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

IO_IER

IO_IER register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IE rw	PB14_IE rw	PB13_IE rw	PB12_IE rw	PB11_IE rw	PB10_IE rw	PB9_IE rw	PB8_IE rw	PB7_IE rw	PB6_IE rw	PB5_IE rw	PB4_IE rw	PB3_IE rw	PB2_IE rw	PB1_IE rw	PB0_IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_IE rw	PA14_IE rw	PA13_IE rw	PA12_IE rw	PA11_IE rw	PA10_IE rw	PA9_IE rw	PA8_IE rw	PA7_IE rw	PA6_IE rw	PA5_IE rw	PA4_IE rw	PA3_IE rw	PA2_IE rw	PA1_IE rw	PA0_IE rw

Toggle fields

PA0_IE

Bit 0: PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA1_IE

Bit 1: PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA2_IE

Bit 2: PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA3_IE

Bit 3: PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA4_IE

Bit 4: PA4_IE: Interrupt enable for port A I/Os..

PA5_IE

Bit 5: PA5_IE: Interrupt enable for port A I/Os..

PA6_IE

Bit 6: PA6_IE: Interrupt enable for port A I/Os..

PA7_IE

Bit 7: PA7_IE: Interrupt enable for port A I/Os..

PA8_IE

Bit 8: PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA9_IE

Bit 9: PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA10_IE

Bit 10: PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA11_IE

Bit 11: PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA12_IE

Bit 12: PA12_IE: Interrupt enable for port A I/Os..

PA13_IE

Bit 13: PA13_IE: Interrupt enable for port A I/Os..

PA14_IE

Bit 14: PA14_IE: Interrupt enable for port A I/Os..

PA15_IE

Bit 15: PA15_IE: Interrupt enable for port A I/Os..

PB0_IE

Bit 16: PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB1_IE

Bit 17: PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB2_IE

Bit 18: PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB3_IE

Bit 19: PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB4_IE

Bit 20: PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB5_IE

Bit 21: PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB6_IE

Bit 22: PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB7_IE

Bit 23: PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB8_IE

Bit 24: PB8_IE: Interrupt enable for port B I/Os..

PB9_IE

Bit 25: PB9_IE: Interrupt enable for port B I/Os..

PB10_IE

Bit 26: PB10_IE: Interrupt enable for port B I/Os..

PB11_IE

Bit 27: PB11_IE: Interrupt enable for port B I/Os..

PB12_IE

Bit 28: PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB13_IE

Bit 29: PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB14_IE

Bit 30: PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB15_IE

Bit 31: PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

IO_ISCR

IO_ISCR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_ISC rw	PB14_ISC rw	PB13_ISC rw	PB12_ISC rw	PB11_ISC rw	PB10_ISC rw	PB9_ISC rw	PB8_ISC rw	PB7_ISC rw	PB6_ISC rw	PB5_ISC rw	PB4_ISC rw	PB3_ISC rw	PB2_ISC rw	PB1_ISC rw	PB0_ISC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_ISC rw	PA14_ISC rw	PA13_ISC rw	PA12_ISC rw	PA11_ISC rw	PA10_ISC rw	PA9_ISC rw	PA8_ISC rw	PA7_ISC rw	PA6_ISC rw	PA5_ISC rw	PA4_ISC rw	PA3_ISC rw	PA2_ISC rw	PA1_ISC rw	PA0_ISC rw

Toggle fields

PA0_ISC

Bit 0: PA0_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA1_ISC

Bit 1: PA1_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA2_ISC

Bit 2: PA2_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA3_ISC

Bit 3: PA3_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA4_ISC

Bit 4: PA4_ISC: Interrupt status (before mask) for port a I/Os...

PA5_ISC

Bit 5: PA5_ISC: Interrupt status (before mask) for port a I/Os...

PA6_ISC

Bit 6: PA6_ISC: Interrupt status (before mask) for port a I/Os...

PA7_ISC

Bit 7: PA7_ISC: Interrupt status (before mask) for port a I/Os...

PA8_ISC

Bit 8: PA8_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA9_ISC

Bit 9: PA9_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA10_ISC

Bit 10: PA10_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA11_ISC

Bit 11: PA11_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA12_ISC

Bit 12: PA12_ISC: Interrupt status (before mask) for port a I/Os..

PA13_ISC

Bit 13: PA13_ISC: Interrupt status (before mask) for port a I/Os..

PA14_ISC

Bit 14: PA14_ISC: Interrupt status (before mask) for port a I/Os..

PA15_ISC

Bit 15: PA15_ISC: Interrupt status (before mask) for port a I/Os..

PB0_ISC

Bit 16: PB0_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB1_ISC

Bit 17: PB1_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB2_ISC

Bit 18: PB2_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB3_ISC

Bit 19: PB3_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB4_ISC

Bit 20: PB4_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB5_ISC

Bit 21: PB5_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB6_ISC

Bit 22: PB6_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB7_ISC

Bit 23: PB7_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB8_ISC

Bit 24: PB8_ISC: Interrupt status (before mask) for port B I/Os...

PB9_ISC

Bit 25: PB9_ISC: Interrupt status (before mask) for port B I/Os...

PB10_ISC

Bit 26: PB10_ISC: Interrupt status (before mask) for port B I/Os...

PB11_ISC

Bit 27: PB11_ISC: Interrupt status (before mask) for port B I/Os...

PB12_ISC

Bit 28: PB12_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB13_ISC

Bit 29: PB13_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB14_ISC

Bit 30: PB14_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB15_ISC

Bit 31: PB15_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PWRC_IER

PWRC_IER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WKUP_IE rw	PVD_IE rw

Toggle fields

PVD_IE

Bit 1: PVD_IE: Programmable Voltage Detector interrupt enable. 0: PVD interrupt is disabled. 1: PVD interrupt is enabled..

WKUP_IE

Bit 2: WKUP_IE: Power Controller Wakeup event interrupt enable. 0: Interrupt on wakeup event seen by the PWRC is disabled. 1: Interrupt on wakeup event seen by the PWRC is enabled..

PWRC_ISCR

PWRC_ISCR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WKUP_ISC rw	PVD_ISC rw

Toggle fields

PVD_ISC

Bit 1: PVD_ISC: Programmable Voltage Detector status. 0: no pending interrupt. 1: voltage went under programmed threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

WKUP_ISC

Bit 2: WKUP_ISC: Indicates the Power Controller receives a Wakeup event. 0: no pending interrupt. 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). Cleared by writing 1 in the bit. This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry requests that the PWRC aborts before shutting down the system..

BLERXTX_DTR

BLERXTX_DTR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_DT rw	TX_DT rw

Toggle fields

TX_DT

Bit 0: TX_DT: detection type on TX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level.

RX_DT

Bit 1: RX_DT: detection type on RX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level.

BLERXTX_IBER

BLERXTX_IBER register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_IBE rw	TX_IBE rw

Toggle fields

TX_IBE

Bit 0: TX_IBE: interrupt edge register on TX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges.

RX_IBE

Bit 1: RX_IBE: interrupt edge register on RX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges.

BLERXTX_IEVR

BLERXTX_IEVR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_IEV rw	TX_IEV rw

Toggle fields

TX_IEV

Bit 0: TX_IEV: interrupt polarity event on TX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

RX_IEV

Bit 1: RX_IEV: interrupt polarity event on RX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

BLERXTX_IER

BLERXTX_IER register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_IE rw	TX_IE rw

Toggle fields

TX_IE

Bit 0: TX_IE: interrupt enable on TX_SEQUENCE signal: 0: TX_SEQUENCE interrupt is disabled (default). 1: TX_SEQUENCE interrupt is enabled.

RX_IE

Bit 1: RX_IE: interrupt enable on RX_SEQUENCE signal: 0: RX_SEQUENCE interrupt is disabled (default). 1: RX_SEQUENCE interrupt is enabled.

BLERXTX_ISCR

BLERXTX_ISCR register

Offset: 0x3c, size: 8, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_ISC rw	TX_ISC rw

Toggle fields

TX_ISC

Bit 0: TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on TX_SEQUENCE detected. 1: activity on TX_SEQUENCE occurred.

RX_ISC

Bit 1: RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on RX_SEQUENCE detected. 1: activity on RX_SEQUENCE occurred.

TIM1

0x40002000:

1/169 fields covered.

Toggle register map

Offset	Name	31	30	29	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2										OIS6		OIS5		OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S					CCUS		CCPC
0x8	SMCR												SMS_3	ETP	ECE	ETPS		ETF					TS			OCCS	SMS_2_0
0xc	DIER																					BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR											CC6IF	CC5IF				CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																				B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1					OC2M_3							OC1M	OC2CE	OC2M_2_0			OC2PE	OC2FE	CC2S		OC1CE	OC1M_2_0			OC1PE	OC1FE	CC1S
0x18	CCMR1_in													IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x1c	CCMR2					OC4M_3							OC3M_3	OC4CE	OC4M_2_0			OC4PE	OC4FE	CC4S		OC3CE	OC3M_2_0			OC3PE	OC3FE	CC3S
0x1c	CCMR2_in													IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x20	CCER							CC6P	CC6E			CC5P	CC5E	CC4NP	CC4NE	CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY												CNT
0x28	PSC													PSC
0x2c	ARR													ARR
0x30	RCR													REP
0x34	CCR1													CCR1
0x38	CCR2													CCR2
0x3c	CCR3													CCR3
0x40	CCR4													CCR4
0x44	BDTR				BK2P	BK2E	BK2F			BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x54	CCMR3					OC6M_3							OC5M_3	OC6CE	OC6M_2_0			OC6PE	OC6FE			OC5CE	OC5M_2_0			OC5PE	OC5FE
0x54	CCMR3_in													IC6F				IC6PSC				IC5F				IC5PSC
0x58	CCR5	GC5C3	GC5C2	GC5C1										CCR5
0x5c	CCR6													CCR6
0x60	AF1																	BKCMP2P	BKCMP1P	BKINP							BKCMP2E	BKCMP1E	BKINE
0x64	AF2																	BK2CMP2P	BK2CMP1P	BK2INP							BK2CMP2E	BK2CMP1E	BK2INE

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: - Counter overflow/underflow - Setting the UG bit - Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller..

URS

Bit 2: URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: - Counter overflow/underflow - Setting the UG bit - Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled..

OPM

Bit 3: OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN).

DIR

Bit 4: DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

CMS

Bits 5-6: CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

ARPE

Bit 7: ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered.

CKD

Bits 8-9: CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value.

UIFREMAP

Bit 11: UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw					CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control..

CCUS

Bit 2: Capture/compare control update selection..

TI1S

Bit 7: TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination).

OIS1

Bit 8: Output idle state 1 (OC1 output)..

OIS1N

Bit 9: Output idle state 1 (OC1N output)..

OIS2

Bit 10: Output idle state 2 (OC2 output). Refer to OIS1 bit..

OIS2N

Bit 11: Output idle state 2 (OC2N output). Refer to OIS1N bit..

OIS3

Bit 12: Output idle state 3 (OC3 output). Refer to OIS1 bit..

OIS3N

Bit 13: Output idle state 3 (OC3N output). Refer to OIS1N bit..

OIS4

Bit 14: Output idle state 4 (OC4 output). Refer to OIS1 bit..

OIS5

Bit 16: Output idle state 5 (OC5 output). Refer to OIS1 bit..

OIS6

Bit 18: Output idle state 6 (OC6 output). Refer to OIS1 bit..

SMCR

SMCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw					TS rw			OCCS rw	SMS_2_0 rw

Toggle fields

SMS_2_0

Bits 0-2: SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. 0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal..

OCCS

Bit 3: OCCS: OCREF clear selection This bit is used to select the OCREF clear source. 0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) 1: OCREF_CLR_INT is connected to ETRF.

TS

Bits 4-6: TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) others: Reserved Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

ETF

Bits 8-11: ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8.

ETPS

Bits 12-13: ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8.

ECE

Bit 14: ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

ETP

Bit 15: ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge..

SMS_3

Bit 16: SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits2:0.

DIER

DIER register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled.

CC1IE

Bit 1: CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled.

CC2IE

Bit 2: CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled.

CC3IE

Bit 3: CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled.

CC4IE

Bit 4: CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled 1: CC4 interrupt enabled.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled.

BIE

Bit 7: Break interrupt enable..

SR

SR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity).

CC2IF

Bit 2: CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description.

CC3IF

Bit 3: CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description.

CC4IF

Bit 4: CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag..

TIF

Bit 6: TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.. 0: No trigger event occurred. 1: Trigger interrupt pending..

BIF

Bit 7: Break interrupt flag..

B2IF

Bit 8: Break 2 interrupt flag..

CC1OF

Bit 9: CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set.

CC2OF

Bit 10: CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description.

CC3OF

Bit 11: CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description.

CC4OF

Bit 12: CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description.

CC5IF

Bit 16: Compare 5 interrupt flag..

CC6IF

Bit 17: Compare 6 interrupt flag..

EGR

EGR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)..

CC1G

Bit 1: CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: CC2G: Capture/Compare 2 generation refer to CC1G description.

CC3G

Bit 3: CC3G: Capture/Compare 3 generation refer to CC1G description.

CC4G

Bit 4: CC4G: Capture/Compare 4 generation refer to CC1G description.

COMG

Bit 5: Capture/compare control update generation..

TG

Bit 6: TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled..

BG

Bit 7: Break generation..

B2G

Bit 8: Break 2 generation..

CCMR1

CCMR1 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M_2_0 rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M_2_0 rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

OC1FE

Bit 2: OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode..

OC1PE

Bit 3: OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note: 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M_2_0

Bits 4-6: OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. 1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved 1011: Reserved 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from 'frozen' mode to 'PWM' mode..

OC1CE

Bit 7: OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF Input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input.

CC2S

Bits 8-9: CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. . 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER)..

OC2FE

Bit 10: OC2FE: Output Compare 2 fast enable.

OC2PE

Bit 11: OC2PE: Output Compare 2 preload enable.

OC2M_2_0

Bits 12-14: OC2M[2:0]: Output Compare 2 mode.

OC2CE

Bit 15: OC2CE: Output Compare 2 clear enable.

OC1M

Bit 16: OC1M[3]: Output Compare 1 mode (bit 3).

OC2M_3

Bit 24: OC2M[3]: Output Compare 2 mode (bit 3).

CCMR1_in

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

IC1PSC

Bits 2-3: IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events.

IC1F

Bits 4-7: Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N= 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8.

CC2S

Bits 8-9: CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER)..

IC2PSC

Bits 10-11: IC2PSC[1:0]: Input capture 2 prescaler.

IC2F

Bits 12-15: IC2F: Input capture 2 filter.

CCMR2

CCMR2 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M_2_0 rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M_2_0 rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER)..

OC3FE

Bit 2: OC3FE: Output compare 3 fast enable.

OC3PE

Bit 3: OC3PE: Output compare 3 preload enable.

OC3M_2_0

Bits 4-6: OC3M: Output compare 3 mode.

OC3CE

Bit 7: OC3CE: Output compare 3 clear enable.

CC4S

Bits 8-9: CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER)..

OC4FE

Bit 10: OC4FE: Output Compare 4 fast enable.

OC4PE

Bit 11: OC4PE: Output Compare 4 preload enable.

OC4M_2_0

Bits 12-14: OC4M[2:0]: Output Compare 4 mode.

OC4CE

Bit 15: OC4CE: Output Compare 4 clear enable.

OC3M_3

Bit 16: OC3M[3]: Output Compare 3 mode (bit 3).

OC4M_3

Bit 24: OC4M[3]: Output Compare 4 mode (bit 3).

CCMR2_in

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER)..

IC3PSC

Bits 2-3: IC3PSC: Input capture 3 prescaler.

IC3F

Bits 4-7: IC3F: Input capture 3 filter.

CC4S

Bits 8-9: CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER)..

IC4PSC

Bits 10-11: IC4PSC: Input capture 4 prescaler.

IC4F

Bits 12-15: IC4F: Input capture 4 filter.

CCER

CCER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw	CC4NE rw	CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled.

CC1P

Bit 1: CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. 00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). 01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode. 10: Reserved, do not use this configuration. 11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: .

CC1NP

Bit 3: CC1NP: Capture/Compare 1 Complementary output Polarity. This field is not used in Blue51. Not available in IUM Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output)..

CC2E

Bit 4: CC2E: Capture/Compare 2 output enable refer to CC1E description.

CC2P

Bit 5: CC2P: Capture/Compare 2 output polarity refer to CC1P description.

CC2NE

Bit 6: Capture/compare 2 complementary output enable. Refer to CC1NE description..

CC2NP

Bit 7: CC2NP: Capture/Compare 2 Complementary output Polarity. This field is not used in Blue51. Not available in IUM refer to CC1NP description.

CC3E

Bit 8: CC3E: Capture/Compare 3 output enable refer to CC1E description.

CC3P

Bit 9: CC3P: Capture/Compare 3 output polarity refer to CC1P description.

CC3NE

Bit 10: Capture/compare 3 complementary output enable. Refer to CC1NE description..

CC3NP

Bit 11: CC3NP: Capture/Compare 3 Complementary output Polarity. This field is not used in Blue51. Not available in IUM refer to CC1NP description.

CC4E

Bit 12: CC4E: Capture/Compare 4 output enable refer to CC1E description.

CC4P

Bit 13: CC4P: Capture/Compare 4 output polarity refer to CC1P description.

CC4NE

Bit 14: Capture/compare 4 complementary output enable. Refer to CC1NE description..

CC4NP

Bit 15: CC4NP: Capture/Compare 4 Complementary output Polarity. This field is not used in Blue51. Not available in IUM refer to CC1NP description.

CC5E

Bit 16: Capture/compare 5 output enable. Refer to CC1E description..

CC5P

Bit 17: Capture/compare 5 output polarity. Refer to CC1P description..

CC6E

Bit 20: Capture/compare 6 output enable. Refer to CC1E description..

CC6P

Bit 21: Capture/compare 6 output polarity. Refer to CC1P description..

CNT

CNT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: CNT[15:0]: Counter value.

UIFCPY

Bit 31: UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

PSC register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode')..

ARR

ARR register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

RCR

RCR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REP rw

Toggle fields

REP

Bits 0-15: REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..

CCR1

CCR1 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)..

CCR2

CCR2 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2)..

CCR3

CCR3 register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3 rw

Toggle fields

CCR3

Bits 0-15: CCR3[15:0]: Capture/Compare 3 value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3)..

CCR4

CCR4 register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4 rw

Toggle fields

CCR4

Bits 0-15: CCR4[15:0]: Capture/Compare 4 value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4)..

BDTR

BDTR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Deadtime generator setup..

LOCK

Bits 8-9: Lock configuration..

OSSI

Bit 10: Off-state selection for Idle mode..

OSSR

Bit 11: Off-state selection for Run mode..

BKE

Bit 12: Break enable..

BKP

Bit 13: Break polarity..

AOE

Bit 14: Automatic output enable..

MOE

Bit 15: Main output enable..

BKF

Bits 16-19: Break filter..

BK2F

Bits 20-23: Break 2 filter..

BK2E

Bit 24: Break 2 enable..

BK2P

Bit 25: Break 2 polarity..

CCMR3

CCMR3 register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M_3 rw								OC5M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M_2_0 rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M_2_0 rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable..

OC5M_2_0

Bits 4-6: Output compare 5 mode..

OC5CE

Bit 7: Output compare 5 clear enable..

OC6FE

Bit 10: Output compare 6 fast enable..

OC6PE

Bit 11: Output compare 6 preload enable..

OC6M_2_0

Bits 12-14: Output compare 6 mode..

OC6CE

Bit 15: Output compare 6 clear enable..

OC5M_3

Bit 16: Output compare 5 mode - bit 3..

OC6M_3

Bit 24: Output compare 6 mode - bit 3..

CCMR3_in

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC6F rw				IC6PSC rw				IC5F rw				IC5PSC rw

Toggle fields

IC5PSC

Bits 2-3: IC5PSC: Input capture 1 prescaler.

IC5F

Bits 4-7: Bits 7:4 IC1F[3:0]: Input capture 1 filter.

IC6PSC

Bits 10-11: IC6PSC[1:0]: Input capture 2 prescaler.

IC6F

Bits 12-15: IC2F: Input capture 2 filter.

CCR5

CCR5 register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-15: Capture/compare 5 value.

GC5C1

Bit 29: Group channel 5 and channel 1 distortion on channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: It is also possible to apply this distortion on combined PWM signals..

GC5C2

Bit 30: Group channel 5 and channel 2 distortion on channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: It is also possible to apply this distortion on combined PWM signals..

GC5C3

Bit 31: Group channel 5 and channel 3 distortion on channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: It is also possible to apply this distortion on combined PWM signals..

CCR6

CCR6 register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-15: Capture/compare 6 value.

AF1

AF1 register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

AF2

AF2 register

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BK2CMP2P rw	BK2CMP1P rw	BK2INP rw							BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable..

BK2CMP1E

Bit 1: BRK2 COMP1 enable..

BK2CMP2E

Bit 2: BRK2 COMP2 enable..

BK2INP

Bit 9: BRK2 BKIN2 input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity..

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity..

USART

0x41004000: USART address block description

53/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_ALTERNATE1			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_ALTERNATE1							TCBGT			REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

USART control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR1_ALTERNATE1

USART control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR2

USART control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure589 and Figure590) This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

ADD

Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE=0) or when the USART is disabled (UE=0)..

CR3

USART control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE=0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE=0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

USART baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared..

GTPR

USART guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

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PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]=Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE=0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. Note: This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA modes are not supported. Refer to Section 53.4: USART implementation on page 2587..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RTOR

USART receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

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RTO

Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..

BLEN

Bits 24-31: Block Length This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..

RQR

USART request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1' to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR

USART interrupt and status register

Offset: 0x1c, size: 32, reset: 0x008000C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE=1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section53.5.8: Tolerance of the USART receiver to clock deviation on page2604). Note: This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFOsize+1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 53.4: USART implementation on page 2587..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register..

ISR_ALTERNATE1

USART interrupt and status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE=1 in the USART_CR3 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section53.5.8: Tolerance of the USART receiver to clock deviation on page2604)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE=1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE=1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 53.4: USART implementation on page 2587..

ICR

USART interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587..

RDR

USART receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

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RDR

Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure583). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

TDR

USART transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

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TDR

Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure583). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1..

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

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PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

WAKEUP

0x60001800:

6/20 fields covered.

Toggle register map

Offset	Name	31	30	29	15	13	7	3	1	0
0x8	OFFSET						WAKEUP_OFFSET
0x10	ABSOLUTE_TIME	ABSOLUTE_TIME			ABSOLUTE_TIME
0x14	MINIMUM_PERIOD_LENGTH					LENGTH
0x18	AVERAGE_PERIOD_LENGTH	AVERAGE_COUNT				LENGTH_INT		LENGTH_FRACT
0x1c	MAXIMUM_PERIOD_LENGTH					LENGTH
0x20	STATISTICS_RESTART								CLR_AVR	CLR_MIN_MAX
0x24	BLUE_WAKEUP_TIME	WAKEUP_TIME			WAKEUP_TIME
0x28	BLUE_SLEEP_REQUEST_MODE	FORCE_SLEEPING	BLE_WAKEUP_EN	SLEEP_EN
0x2c	CM0_WAKEUP_TIME	WAKEUP_TIME			WAKEUP_TIME
0x30	CM0_SLEEP_REQUEST_MODE	FORCE_SLEEPING	CPU_WAKEUP_EN
0x40	BLE_IRQ_ENABLE									WAKEUP_IT
0x44	BLE_IRQ_STATUS									WAKEUP_IT
0x48	CM0_IRQ_ENABLE									WAKEUP_IT
0x4c	CM0_IRQ_STATUS									WAKEUP_IT

Toggle registers

OFFSET

WAKEUP_OFFSET register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WAKEUP_OFFSET rw

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WAKEUP_OFFSET

Bits 0-7: delay of anticipation of the Soc device to settle power and clock.

ABSOLUTE_TIME

ABSOLUTE_TIME register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ABSOLUTE_TIME r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABSOLUTE_TIME r

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ABSOLUTE_TIME

Bits 0-31: absolute time.

MINIMUM_PERIOD_LENGTH

MINIMUM_PERIOD_LENGTH register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LENGTH r

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LENGTH

Bits 4-13: minimum period length computed by Time Interpolator.

AVERAGE_PERIOD_LENGTH

AVERAGE_PERIOD_LENGTH register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AVERAGE_COUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LENGTH_INT r										LENGTH_FRACT r

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LENGTH_FRACT

Bits 0-3: additional information/precision on slow clock frequency..

LENGTH_INT

Bits 4-13: average period length computed by Time Interpolator..

AVERAGE_COUNT

Bits 24-31: Number of slow clock cycles..

MAXIMUM_PERIOD_LENGTH

MAXIMUM_PERIOD_LENGTH register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LENGTH r

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LENGTH

Bits 4-13: maximum period length computed by Time Interpolator.

STATISTICS_RESTART

STATISTICS_RESTART register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLR_AVR rw	CLR_MIN_MAX rw

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CLR_MIN_MAX

Bit 0: Write '1' to clear the minimum and maximum registers..

CLR_AVR

Bit 1: Write '1' to clear the AVERAGE_PERIOD_LENGTH register value..

BLUE_WAKEUP_TIME

BLUE_WAKEUP_TIME register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WAKEUP_TIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WAKEUP_TIME rw

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WAKEUP_TIME

Bits 0-31: programmed wakeup time for the IP_BLE..

BLUE_SLEEP_REQUEST_MODE

BLUE_SLEEP_REQUEST_MODE register

Offset: 0x28, size: 32, reset: 0x00000007, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FORCE_SLEEPING rw	BLE_WAKEUP_EN rw	SLEEP_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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SLEEP_EN

Bit 29: IP_BLE sleeping mode enable:.

BLE_WAKEUP_EN

Bit 30: IP_BLE wakeup enable:.

FORCE_SLEEPING

Bit 31: IP_BLE sleeping control:.

CM0_WAKEUP_TIME

CM0_WAKEUP_TIME register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WAKEUP_TIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WAKEUP_TIME rw

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WAKEUP_TIME

Bits 4-31: programmed wakeup time for CPU..

CM0_SLEEP_REQUEST_MODE

CM0_SLEEP_REQUEST_MODE register

Offset: 0x30, size: 32, reset: 0x80000007, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FORCE_SLEEPING rw	CPU_WAKEUP_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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CPU_WAKEUP_EN

Bit 30: CPU wakeup enable:.

FORCE_SLEEPING

Bit 31: CPU sleeping control:.

BLE_IRQ_ENABLE

WAKEUP_BLE_IRQ_ENABLE register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: IP_BLE wakeup interrupt enable:.

BLE_IRQ_STATUS

WAKEUP_BLE_IRQ_STATUS register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: On read, returns the IP_BLE wakeup interrupt status..

CM0_IRQ_ENABLE

WAKEUP_CM0_IRQ_ENABLE register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: CPU wakeup interrupt enable:.

CM0_IRQ_STATUS

WAKEUP_CM0_IRQ_STATUS register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: On read, returns the CPU wakeup interrupt status..