STM32WB09 Peripheral Coverage

ADC

0x41006000:

2/75 fields covered.

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Offset	Name	31	27	23	19	18	17	15	13	12	11	10	9	7	6	5	4	3	2	1	0
0x0	VERSION_ID													VERSION_ID
0x4	CONF			SAMPLE_RATE_MSB	ADC_CONT_1V2	BIT_INVERT_DIFF	BIT_INVERT_SN	OVR_DS_CFG	DMA_DS_ENA	SAMPLE_RATE		SAMPLE_RATE_LSB			SMPS_SYNCHRO_ENA	SEQ_LEN				SEQUENCE	CONT
0x8	CTRL															ADC_LDO_ENA	TEST_MODE		STOP_OP_MODE	START_CONV	ADC_ON_OFF
0x14	SWITCH							SE_VIN_7	SE_VIN_6		SE_VIN_5		SE_VIN_4	SE_VIN_3		SE_VIN_2		SE_VIN_1		SE_VIN_0
0x1c	DS_CONF															DS_WIDTH			DS_RATIO
0x20	SEQ_1	SEQ7	SEQ6	SEQ5	SEQ4			SEQ3			SEQ2			SEQ1				SEQ0
0x24	SEQ_2	SEQ15	SEQ14	SEQ13	SEQ12			SEQ11			SEQ10			SEQ9				SEQ8
0x28	COMP_1				OFFSET1			OFFSET1			GAIN1
0x2c	COMP_2				OFFSET2			OFFSET2			GAIN2
0x30	COMP_3				OFFSET3			OFFSET3			GAIN3
0x34	COMP_4				OFFSET4			OFFSET4			GAIN4
0x38	COMP_SEL						OFFSET_GAIN8	OFFSET_GAIN7	OFFSET_GAIN6		OFFSET_GAIN5		OFFSET_GAIN4	OFFSET_GAIN3		OFFSET_GAIN2		OFFSET_GAIN1		OFFSET_GAIN0
0x3c	WD_TH		WD_HT								WD_LT
0x40	WD_CONF							AWD_CHX
0x44	DS_DATAOUT							DS_DATA
0x4c	IRQ_STATUS															OVR_DS_IRQ	AWD_IRQ	EOS_IRQ		EODS_IRQ	EOC_IRQ
0x50	IRQ_ENABLE															OVR_DS_IRQ	AWD_IRQ	EOS_IRQ		EODS_IRQ	EOC_IRQ

Toggle registers

VERSION_ID

VERSION_ID register

Offset: 0x0, size: 32, reset: 0x00000030, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								VERSION_ID r

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VERSION_ID

Bits 0-7: VERSION_ID[7:0]: version of the embedded IP..

CONF

CONF register

Offset: 0x4, size: 32, reset: 0x00020002, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SAMPLE_RATE_MSB rw				ADC_CONT_1V2 rw	BIT_INVERT_DIFF rw	BIT_INVERT_SN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVR_DS_CFG rw		DMA_DS_ENA rw	SAMPLE_RATE rw		SAMPLE_RATE_LSB rw				SMPS_SYNCHRO_ENA rw	SEQ_LEN rw				SEQUENCE rw	CONT rw

Toggle fields

CONT

Bit 0: CONT: regular sequence runs continuously when ADC mode is enabled: 0: enable the single conversion: when the sequence is over, the conversion stops 1: enable the continuous conversion: when the sequence is over, the sequence starts again until the software sets the CTRL.STOP_OP_MODE bit..

SEQUENCE

Bit 1: SEQUENCE: enable the sequence mode (active by default): 0: sequence mode is disabled, only SEQ0 is selected 1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can be kept high as redundant with keeping high and setting SEQ_LEN=0000..

SEQ_LEN

Bits 2-5: SEQ_LEN[3:0]: number of conversions in a regular sequence: 0000: 1 conversion, starting from SEQ0 0001: 2 conversions, starting from SEQ0 ... 1111: 16 conversions, starting from SEQ0.

SMPS_SYNCHRO_ENA

Bit 6: SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the SMPS: 0: SMPS synchronization is disabled for all ADC clock frequencies 1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when PWRC_CR5.NOSMPS = 1..

SAMPLE_RATE_LSB

Bits 9-10: SAMPLE_RATE_LSB: Sample Rate LSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. When this field is set to a value different than 0, SMPS synchronization is not feasible. This value is hidden to the user.

SAMPLE_RATE

Bits 11-12: SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency..

DMA_DS_ENA

Bit 13: DMA_DS_EN: enable the DMA mode for the Down Sampler data path: 0: DMA mode is disabled 1: DMA mode is enabled.

OVR_DS_CFG

Bit 15: OVR_DS_CFG: Down Sampler overrun configuration: 0: the previous data is kept, the new one is lost 1: the previous data is lost, the new one is kept.

BIT_INVERT_SN

Bit 17: BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single negative input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.

BIT_INVERT_DIFF

Bit 18: BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.

ADC_CONT_1V2

Bit 19: ADC_CONT_1V2: select the input sampling method: 0: sampling only at conversion start (default) 1: sampling starts at the end of conversion.

SAMPLE_RATE_MSB

Bits 21-23: SAMPLE_RATE_MSB: Sample Rate MSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description.

CTRL

CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ADC_LDO_ENA rw	TEST_MODE rw		STOP_OP_MODE w	START_CONV w	ADC_ON_OFF rw

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ADC_ON_OFF

Bit 0: ADC_ON_OFF: 0: power off the ADC 1: power on the ADC.

START_CONV

Bit 1: START_CONV (1): generate a start pulse to initiate an ADC conversion: 0: no effect 1: start the ADC conversion Note: this bit is set by software and cleared by hardware..

STOP_OP_MODE

Bit 2: STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full mode): 0: no effect 1: stop on-going ADC mode Note: this bit is set by software and cleared by hardware. When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit..

TEST_MODE

Bit 4: TEST_MODE: select the functional or the test mode of the ADC: 0: functional mode (one of the four main functional modes is used) 1: test mode (for debug, test, calibration).

ADC_LDO_ENA

Bit 5: ADC_LDO_ENA: enable the LDO associated to the ADC block: 0: disable the ADC LDO 1: enable the ADC LDO.

SWITCH

SWITCH register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SE_VIN_7 rw		SE_VIN_6 rw		SE_VIN_5 rw		SE_VIN_4 rw		SE_VIN_3 rw		SE_VIN_2 rw		SE_VIN_1 rw		SE_VIN_0 rw

Toggle fields

SE_VIN_0

Bits 0-1: SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_1

Bits 2-3: SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_2

Bits 4-5: SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_3

Bits 6-7: SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_4

Bits 8-9: SE_VIN_4[1:0]: input voltage for VINP[0] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_5

Bits 10-11: SE_VIN_5[1:0]: input voltage for VINP[1] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_6

Bits 12-13: SE_VIN_6[1:0]: input voltage for VINP[2] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_7

Bits 14-15: SE_VIN_7[1:0]: input voltage for VINP[3] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

DS_CONF

DS_CONF register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DS_WIDTH rw			DS_RATIO rw

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DS_RATIO

Bits 0-2: DS_RATIO[2:0]: program the Down Sampler ratio (N factor) 000: ratio = 1, no down sampling (default) 001: ratio = 2 010: ratio = 4 011: ratio = 8 100: ratio = 16 101: ratio = 32 110: ratio = 64 111: ratio = 128.

DS_WIDTH

Bits 3-5: DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) 000: DS_DATA output on 12-bit (default) 001: DS_DATA output on 13-bit 010: DS_DATA output on 14-bit 011: DS_DATA output on 15-bit 100: DS_DATA output on 16-bit 1xx: reserved.

SEQ_1

SEQ_1 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ7 rw				SEQ6 rw				SEQ5 rw				SEQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ3 rw				SEQ2 rw				SEQ1 rw				SEQ0 rw

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SEQ0

Bits 0-3: SEQ0[3:0]: channel number code for first conversion of the sequence 0000: VINM[0] to ADC single negative input 0001: VINM[1] to ADC single negative input 0010: VINM[2] to ADC single negative input 0011: VINM[3] to ADC single negative input 0100: VINP[0] to ADC single positive input 0101: VINP[1] to ADC single positive input 0110: VINP[2] to ADC single positive input 0111: VINP[3] to ADC single positive input 1000: VINP[0]-VINM[0] to ADC differential input 1001: VINP[1]-VINM[1] to ADC differential input 1010: VINP[2]-VINM[2] to ADC differential input 1011: VINP[3]-VINM[3] to ADC differential input 1100: VBAT Battery level detector 1101: Temperature sensor 111x: reserved.

SEQ1

Bits 4-7: SEQ1[3:0]: channel number code for second conversion of the sequence. See SEQ0 for code detail..

SEQ2

Bits 8-11: SEQ2[3:0]: channel number code for 3rd conversion of the sequence. See SEQ0 for code detail..

SEQ3

Bits 12-15: SEQ3[3:0]: channel number code for 4th conversion of the sequence. See SEQ0 for code detail..

SEQ4

Bits 16-19: SEQ4[3:0]: channel number code for 5th conversion of the sequence. See SEQ0 for code detail..

SEQ5

Bits 20-23: SEQ5[3:0]: channel number code for 6th conversion of the sequence. See SEQ0 for code detail..

SEQ6

Bits 24-27: SEQ6[3:0]: channel number code for 7th conversion of the sequence. See SEQ0 for code detail..

SEQ7

Bits 28-31: SEQ7[3:0]: channel number code for 8th conversion of the sequence. See SEQ0 for code detail..

SEQ_2

SEQ_2 register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ15 rw				SEQ14 rw				SEQ13 rw				SEQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ11 rw				SEQ10 rw				SEQ9 rw				SEQ8 rw

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SEQ8

Bits 0-3: SEQ8[3:0]: channel number code for 9th conversion of the sequence 0000: VINM[0] to ADC single negative input 0001: VINM[1] to ADC single negative input 0010: VINM[2] to ADC single negative input 0011: VINM[3] to ADC single negative input 0100: VINP[0] to ADC single positive input 0101: VINP[1] to ADC single positive input 0110: VINP[2] to ADC single positive input 0111: VINP[3] to ADC single positive input 1000: VINP[0]-VINM[0] to ADC differential input 1001: VINP[1]-VINM[1] to ADC differential input 1010: VINP[2]-VINM[2] to ADC differential input 1011: VINP[3]-VINM[3] to ADC differential input 1100: VBAT Battery level detector 1101: Temperature sensor 111x: reserved.

SEQ9

Bits 4-7: SEQ9[3:0]: channel number code for 10th conversion of the sequence. See SEQ0 for code detail..

SEQ10

Bits 8-11: SEQ10[3:0]: channel number code for 11th conversion of the sequence. See SEQ0 for code detail..

SEQ11

Bits 12-15: SEQ11[3:0]: channel number code for 12th conversion of the sequence. See SEQ0 for code detail..

SEQ12

Bits 16-19: SEQ12[3:0]: channel number code for 13th conversion of the sequence. See SEQ0 for code detail..

SEQ13

Bits 20-23: SEQ13[3:0]: channel number code for 14th conversion of the sequence. See SEQ0 for code detail..

SEQ14

Bits 24-27: SEQ14[3:0]: channel number code for 15th conversion of the sequence. See SEQ0 for code detail..

SEQ15

Bits 28-31: SEQ15[3:0]: channel number code for 16th conversion of the sequence. See SEQ0 for code detail..

COMP_1

COMP_1 register

Offset: 0x28, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET1 rw				GAIN1 rw

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GAIN1

Bits 0-11: GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET1

Bits 12-19: OFFSET1[7:0]: first calibration point: offset compensation[7:0] with sign.

COMP_2

COMP_2 register

Offset: 0x2c, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET2 rw				GAIN2 rw

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GAIN2

Bits 0-11: GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET2

Bits 12-19: OFFSET2[7:0]: second calibration point: offset compensation[7:0] with sign.

COMP_3

COMP_3 register

Offset: 0x30, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET3 rw				GAIN3 rw

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GAIN3

Bits 0-11: GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET3

Bits 12-19: OFFSET3[7:0]: third calibration point: offset compensation[7:0] with sign.

COMP_4

COMP_4 register

Offset: 0x34, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET4 rw				GAIN4 rw

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GAIN4

Bits 0-11: GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET4

Bits 12-19: OFFSET4[7:0]: fourth calibration point: offset compensation[7:0] with sign.

COMP_SEL

COMP_SEL register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														OFFSET_GAIN8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET_GAIN7 rw		OFFSET_GAIN6 rw		OFFSET_GAIN5 rw		OFFSET_GAIN4 rw		OFFSET_GAIN3 rw		OFFSET_GAIN2 rw		OFFSET_GAIN1 rw		OFFSET_GAIN0 rw

Toggle fields

OFFSET_GAIN0

Bits 0-1: OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN1

Bits 2-3: OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN2

Bits 4-5: OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN3

Bits 6-7: OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN4

Bits 8-9: OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN5

Bits 10-11: OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN6

Bits 12-13: OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN7

Bits 14-15: OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN8

Bits 16-17: OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

WD_TH

WD_TH register

Offset: 0x3c, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				WD_HT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WD_LT rw

Toggle fields

WD_LT

Bits 0-11: WD_LT[11:0]: analog watchdog low level threshold..

WD_HT

Bits 16-27: WD_HT[11:0]: analog watchdog high level threshold..

WD_CONF

WD_CONF register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD_CHX rw

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AWD_CHX

Bits 0-15: AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog. Bit0: VINM[0] to ADC negative input Bit1: VINM[1] to ADC negative input Bit2: VINM[2] to ADC negative input Bit3: VINM[3] to ADC negative input Bit4: Not used Bit5: VBAT to ADC negative input Bit6: GND to ADC negative input Bit7: VDDA to ADC negative input Bit8: VINP[0] to ADC positive input Bit9: VINP[1] to ADC positive input Bit10: VINP[2] to ADC positive input Bit11: VINP[3] to ADC positive input Bit12: Not used Bit13: TEMP to ADC positive input Bit14: GND to ADC positive input Bit15: VDDA to ADC positive input.

DS_DATAOUT

DS_DATAOUT register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DS_DATA r

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DS_DATA

Bits 0-15: DS_DATA[15:0]: contain the converted data at the output of the Down Sampler..

IRQ_STATUS

IRQ_STATUS register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										OVR_DS_IRQ rw	AWD_IRQ rw	EOS_IRQ rw		EODS_IRQ rw	EOC_IRQ rw

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EOC_IRQ

Bit 0: EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. When read, provide the status of the interrupt: 0: ADC conversion is not completed 1: ADC conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EODS_IRQ

Bit 1: EODS_IRQ: set when the Down Sampler conversion is completed. When read, provide the status of the interrupt: 0: Down Sampler conversion is not completed 1: Down Sampler conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EOS_IRQ

Bit 3: EOS_IRQ: set when a sequence of conversion is completed. When read, provide the status of the interrupt: 0: sequence of conversion is not completed 1: sequence of conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

AWD_IRQ

Bit 4: AWD_IRQ: set when an analog watchdog event occurs. When read, provide the status of the interrupt: 0: no analog watchdog event occurred 1: analog watchdog event has occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

OVR_DS_IRQ

Bit 5: OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) When read, provide the status of the interrupt: 0: no overrun occurred 1: overrun occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

IRQ_ENABLE

IRQ_ENABLE register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										OVR_DS_IRQ rw	AWD_IRQ rw	EOS_IRQ rw		EODS_IRQ rw	EOC_IRQ rw

Toggle fields

EOC_IRQ

Bit 0: EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. When read, provide the status of the interrupt: 0: ADC conversion is not completed 1: ADC conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EODS_IRQ

Bit 1: EODS_IRQ: set when the Down Sampler conversion is completed. When read, provide the status of the interrupt: 0: Down Sampler conversion is not completed 1: Down Sampler conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EOS_IRQ

Bit 3: EOS_IRQ: set when a sequence of conversion is completed. When read, provide the status of the interrupt: 0: sequence of conversion is not completed 1: sequence of conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

AWD_IRQ

Bit 4: AWD_IRQ: set when an analog watchdog event occurs. When read, provide the status of the interrupt: 0: no analog watchdog event occurred 1: analog watchdog event has occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

OVR_DS_IRQ

Bit 5: OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) When read, provide the status of the interrupt: 0: no overrun occurred 1: overrun occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

BLUE

0x60000000:

68/115 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	19	18	16	15	14	13	12	11	10	9	8	7	6	5	4	3	1	0
0x4	INTERRUPT1REG	RCVOK	RCVCRCERR	TIMECAPTURETRIG	RCVCMD	RCVNOMD	RCVTIMEOUT	DONE	TXOK	CONFIGERROR	ACTIVE2ERROR	TXRXSKIP	SEMATIMEOUTERROR	RCVLENGTHERROR	NOACTIVELERROR	TXDATAREADYERROR	ALLTABLEREADYERROR	ENCERROR	TXERROR_4	TXERROR_3	TXERROR_2	TXERROR_1	TXERROR_0	SEQDONE		RXOVERFLOWERROR	ADDPOINTERROR
0x8	INTERRUPT2REG																												AESLEPRIVINT	AESMANENCINT
0xc	TIMEOUTDESTREG																												DESTINATION
0x10	TIMEOUTREG	TIMEOUT														TIMEOUT
0x14	TIMERCAPTUREREG	TIMERCAPTURE														TIMERCAPTURE
0x18	CMDREG																											CLEARSEMAREQ		TXRXSKIP
0x1c	STATUSREG	RCVOK	RCVCRCERR	TIMECAPTURETRIG	RCVCMD	RCVNOMD	RCVTIMEOUT	DONE	TXOK	CONFIGERROR	ACTIVE2ERROR	TXRXSKIP	SEMATIMEOUTERROR	RCVLENGTHERROR	NOACTIVELERROR	TXDATAREADYERROR	ALLTABLEREADYERROR	ENCERROR	TXERROR_4	TXERROR_3	TXERROR_2	TXERROR_1	TXERROR_0	SEQDONE	PREVTRANSMIT	RXOVERFLOWERROR	ADDPOINTERROR	NOTSUPPORTED_FUNCTION		AESONFLYBUSY
0x20	INTERRUPT1ENABLEREG	RCVOK	RCVCRCERR	TIMECAPTURETRIG	RCVCMD	RCVNOMD	RCVTIMEOUT	DONE	TXOK	CONFIGERROR	ACTIVE2ERROR	TXRXSKIP	SEMATIMEOUTERROR	RCVLENGTHERROR	NOACTIVELERROR	TXDATAREADYERROR	ALLTABLEREADYERROR	ENCERROR	TXERROR_4	TXERROR_3	TXERROR_2	TXERROR_1	TXERROR_0	SEQDONE		RXOVERFLOWERROR	ADDPOINTERROR
0x24	INTERRUPT1LATENCYREG																							INTERRUPT1LATENCY
0x28	MANAESKEY0REG	MANAESKEY_31_0														MANAESKEY_31_0
0x2c	MANAESKEY1REG	MANAESKEY_63_32														MANAESKEY_63_32
0x30	MANAESKEY2REG	MANAESKEY_95_64														MANAESKEY_95_64
0x34	MANAESKEY3REG	MANAESKEY_127_96														MANAESKEY_127_96
0x38	MANAESCLEARTEXT0REG	AES														AES
0x3c	MANAESCLEARTEXT1REG	AES														AES
0x40	MANAESCLEARTEXT2REG	AES														AES
0x44	MANAESCLEARTEXT3REG	AES														AES
0x48	MANAESCIPHERTEXT0REG	AES														AES
0x4c	MANAESCIPHERTEXT1REG	AES														AES
0x50	MANAESCIPHERTEXT2REG	AES														AES
0x54	MANAESCIPHERTEXT3REG	AES														AES
0x58	MANAESCMDREG																												INTENA	START
0x5c	MANAESSTATREG																													BUSY
0x60	AESLEPRIVPOINTERREG									POINTER						POINTER
0x64	AESLEPRIVHASHREG									HASH						HASH
0x68	AESLEPRIVPRANDREG									PRAND						PRAND
0x6c	AESLEPRIVCMDREG																					NBKEYS							INTENA	START
0x70	AESLEPRIVSTATREG																					KEYFNDINDEX							KEYFND	BUSY
0x7c	STATUS2REG	ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR	ANTENNASWITCHINGPATTERNACCESSERROR	IQSAMPLESMISSINGERROR																				IQSAMPLESNUMBER						IQSAMPLESREADY

Toggle registers

INTERRUPT1REG

INTERRUPT1REG register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RCVOK rw	RCVCRCERR rw	TIMECAPTURETRIG rw	RCVCMD rw	RCVNOMD rw	RCVTIMEOUT rw	DONE rw	TXOK rw	CONFIGERROR rw	ACTIVE2ERROR rw	TXRXSKIP rw		SEMATIMEOUTERROR rw	RCVLENGTHERROR rw		NOACTIVELERROR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDATAREADYERROR rw	ALLTABLEREADYERROR rw	ENCERROR rw	TXERROR_4 rw	TXERROR_3 rw	TXERROR_2 rw	TXERROR_1 rw	TXERROR_0 rw	SEQDONE rw		RXOVERFLOWERROR rw	ADDPOINTERROR rw

Toggle fields

ADDPOINTERROR

Bit 4: Address Pointer Error..

RXOVERFLOWERROR

Bit 5: Receive Overflow error..

SEQDONE

Bit 7: Sequencer end of task..

TXERROR_0

Bit 8: Transmission error 0: transmit block missing data error..

TXERROR_1

Bit 9: Transmission error 1: a TX skip happened during an on-going transmission..

TXERROR_2

Bit 10: Transmission error 2: channel index is greater than 39..

TXERROR_3

Bit 11: Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state..

TXERROR_4

Bit 12: Transmission error 4: a CTE issue occurred..

ENCERROR

Bit 13: Encryption error on reception..

ALLTABLEREADYERROR

Bit 14: All RAM Table not ready on time..

TXDATAREADYERROR

Bit 15: Transmit data pack not ready error.

NOACTIVELERROR

Bit 16: GlobalStatMach..

RCVLENGTHERROR

Bit 18: Receive length error..

SEMATIMEOUTERROR

Bit 19: Semaphore timeout error.

TXRXSKIP

Bit 21: Transmission/Reception skip..

ACTIVE2ERROR

Bit 22: Active2 Radio state error..

CONFIGERROR

Bit 23: Data pointer configuration error..

TXOK

Bit 24: Previous transmitted packet received OK by the peer device..

DONE

Bit 25: Receive/Transmit done..

RCVTIMEOUT

Bit 26: Receive timeout (no preamble found)..

RCVNOMD

Bit 27: Received low MD bit..

RCVCMD

Bit 28: Received command.

TIMECAPTURETRIG

Bit 29: A time has been captured in TIMERCAPTUREREG..

RCVCRCERR

Bit 30: Receive data fail.

RCVOK

Bit 31: Receive data OK..

INTERRUPT2REG

INTERRUPT2REG register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														AESLEPRIVINT rw	AESMANENCINT rw

Toggle fields

AESMANENCINT

Bit 0: AES manual encryption..

AESLEPRIVINT

Bit 1: AES LE privacy engine..

TIMEOUTDESTREG

TIMEOUTDESTREG register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DESTINATION rw

Toggle fields

DESTINATION

Bits 0-1: Timeout timer Destination.

TIMEOUTREG

TIMEOUTREG register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIMEOUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUT rw

Toggle fields

TIMEOUT

Bits 0-31: Timer1 or Timer2 Timeout value (depending on Destination register).

TIMERCAPTUREREG

TIMERCAPTUREREG register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIMERCAPTURE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMERCAPTURE r

Toggle fields

TIMERCAPTURE

Bits 0-31: Interpolated absolute time capture register.

CMDREG

CMDREG register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CLEARSEMAREQ w			TXRXSKIP w

Toggle fields

TXRXSKIP

Bit 0: Transmission/Reception skip command..

CLEARSEMAREQ

Bit 3: Semaphore Clear command..

STATUSREG

STATUSREG register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RCVOK r	RCVCRCERR r	TIMECAPTURETRIG r	RCVCMD r	RCVNOMD r	RCVTIMEOUT r	DONE r	TXOK r	CONFIGERROR r	ACTIVE2ERROR r	TXRXSKIP r		SEMATIMEOUTERROR r	RCVLENGTHERROR r		NOACTIVELERROR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDATAREADYERROR r	ALLTABLEREADYERROR r	ENCERROR r	TXERROR_4 r	TXERROR_3 r	TXERROR_2 r	TXERROR_1 r	TXERROR_0 r	SEQDONE r	PREVTRANSMIT r	RXOVERFLOWERROR r	ADDPOINTERROR r	NOTSUPPORTED_FUNCTION r			AESONFLYBUSY r

Toggle fields

AESONFLYBUSY

Bit 0: AES on the fligh encryption busy status.

NOTSUPPORTED_FUNCTION

Bit 3: indicates the SW requests an unsupported feature..

ADDPOINTERROR

Bit 4: Address Pointer Error status.

RXOVERFLOWERROR

Bit 5: AHB arbiter is full and there is no more storage capability available in RX datapath.

PREVTRANSMIT

Bit 6: Previous event was a Transmission (1) or Reception (0) status.

SEQDONE

Bit 7: Sequencer end of task status..

TXERROR_0

Bit 8: Transmission error 0 status: Transmit block missing data error..

TXERROR_1

Bit 9: Transmission error 1 status.

TXERROR_2

Bit 10: Transmission error 2 status..

TXERROR_3

Bit 11: Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach..

TXERROR_4

Bit 12: Transmission error 4 status.

ENCERROR

Bit 13: Encryption error on receive status.

ALLTABLEREADYERROR

Bit 14: All RAM Table not ready status.

TXDATAREADYERROR

Bit 15: Transmit data pack not ready status..

NOACTIVELERROR

Bit 16: GlobalStatMach..

RCVLENGTHERROR

Bit 18: Receive length error status.

SEMATIMEOUTERROR

Bit 19: Semaphore timeout error status.

TXRXSKIP

Bit 21: Transmission/Reception skip status..

ACTIVE2ERROR

Bit 22: Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step..

CONFIGERROR

Bit 23: Data pointer configuration error status.

TXOK

Bit 24: Previous transmitted packet received OK by the peer device status..

DONE

Bit 25: Receive/Transmit done status..

RCVTIMEOUT

Bit 26: Receive timeout status (no access address found).

RCVNOMD

Bit 27: Received MD bit status (valid only on Data Physical Channel PDU reception).

RCVCMD

Bit 28: Received command status (valid only on Data Physical Channel PDU reception)..

TIMECAPTURETRIG

Bit 29: indicates a time has been captured in TIMERCAPTUREREG when set..

RCVCRCERR

Bit 30: Receive data fail (CRC error or invalid CI field) status..

RCVOK

Bit 31: Receive data OK status.

INTERRUPT1ENABLEREG

INTERRUPT1ENABLEREG register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

25/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RCVOK r	RCVCRCERR r	TIMECAPTURETRIG r	RCVCMD r	RCVNOMD r	RCVTIMEOUT r	DONE r	TXOK r	CONFIGERROR r	ACTIVE2ERROR r	TXRXSKIP r		SEMATIMEOUTERROR r	RCVLENGTHERROR r		NOACTIVELERROR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXDATAREADYERROR r	ALLTABLEREADYERROR r	ENCERROR r	TXERROR_4 r	TXERROR_3 r	TXERROR_2 r	TXERROR_1 r	TXERROR_0 r	SEQDONE r		RXOVERFLOWERROR r	ADDPOINTERROR r

Toggle fields

ADDPOINTERROR

Bit 4: Address Pointer Error enable interruption.

RXOVERFLOWERROR

Bit 5: Rx Overflow Error enable interruption.

SEQDONE

Bit 7: Sequencer end of task enable interruption.

TXERROR_0

Bit 8: Transmission error 0 enable interruption.

TXERROR_1

Bit 9: Transmission error 1 enable interruption.

TXERROR_2

Bit 10: Transmission error 2 enable interruption.

TXERROR_3

Bit 11: Transmission error 3 enable interruption.

TXERROR_4

Bit 12: Transmission error 4 enable interruption.

ENCERROR

Bit 13: Encryption error on receive enable interruption.

ALLTABLEREADYERROR

Bit 14: All RAM Table not ready enable interruption.

TXDATAREADYERROR

Bit 15: Transmit data pack not ready enable interruption.

NOACTIVELERROR

Bit 16: active bit error enable interruption.

RCVLENGTHERROR

Bit 18: Receive length error enable interruption.

SEMATIMEOUTERROR

Bit 19: Semaphore timeout error enable interruption.

TXRXSKIP

Bit 21: Transmission/Reception skip enable interruption.

ACTIVE2ERROR

Bit 22: Active2 Radio state error enable interruption.

CONFIGERROR

Bit 23: Data pointer configuration error enable interruption.

TXOK

Bit 24: Previous transmitted packet received OK enable interruption.

DONE

Bit 25: Receive/Transmit done interruption.

RCVTIMEOUT

Bit 26: Receive timeout enable interruption (no preamble found).

RCVNOMD

Bit 27: Received MD bit embedded in the PDU data packet header was zero enable interruption.

RCVCMD

Bit 28: Received command enable interruption.

TIMECAPTURETRIG

Bit 29: TimerCaptureReg time capture enable interruption.

RCVCRCERR

Bit 30: Receive data fail enable interruption.

RCVOK

Bit 31: Receive data OK enable interruption.

INTERRUPT1LATENCYREG

INTERRUPT1LATENCYREG register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								INTERRUPT1LATENCY r

Toggle fields

INTERRUPT1LATENCY

Bits 0-7: relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence..

MANAESKEY0REG

MANAESKEY0REG register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_31_0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_31_0 rw

Toggle fields

MANAESKEY_31_0

Bits 0-31: Manual mode AES key.

MANAESKEY1REG

MANAESKEY1REG register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_63_32 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_63_32 rw

Toggle fields

MANAESKEY_63_32

Bits 0-31: Manual mode AES key.

MANAESKEY2REG

MANAESKEY2REG register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_95_64 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_95_64 rw

Toggle fields

MANAESKEY_95_64

Bits 0-31: Manual mode AES key.

MANAESKEY3REG

MANAESKEY3REG register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MANAESKEY_127_96 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MANAESKEY_127_96 rw

Toggle fields

MANAESKEY_127_96

Bits 0-31: Manual mode AES key.

MANAESCLEARTEXT0REG

MANAESCLEARTEXT0REG register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCLEARTEXT1REG

MANAESCLEARTEXT1REG register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCLEARTEXT2REG

MANAESCLEARTEXT2REG register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCLEARTEXT3REG

MANAESCLEARTEXT3REG register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES rw

Toggle fields

AES

Bits 0-31: Manual Aes Clear Text.

MANAESCIPHERTEXT0REG

MANAESCIPHERTEXT0REG register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCIPHERTEXT1REG

MANAESCIPHERTEXT1REG register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCIPHERTEXT2REG

MANAESCIPHERTEXT2REG register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCIPHERTEXT3REG

MANAESCIPHERTEXT3REG register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES r

Toggle fields

AES

Bits 0-31: Manual AES Cipher Text.

MANAESCMDREG

MANAESCMDREG register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														INTENA rw	START w

Toggle fields

START

Bit 0: AES Manual encryption Start command..

INTENA

Bit 1: AES Manual encryption interrupt enable on Interrupt2Reg.

MANAESSTATREG

MANAESSTATREG register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															BUSY r

Toggle fields

BUSY

Bit 0: AES manual encryption busy status.

AESLEPRIVPOINTERREG

AESLEPRIVPOINTERREG register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								POINTER rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POINTER rw

Toggle fields

POINTER

Bits 0-23: AES Le privacy pointer.

AESLEPRIVHASHREG

AESLEPRIVHASHREG register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HASH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HASH rw

Toggle fields

HASH

Bits 0-23: AES Le privacy Reference Hash.

AESLEPRIVPRANDREG

AESLEPRIVPRANDREG register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRAND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRAND rw

Toggle fields

PRAND

Bits 0-23: AES Le privacy Prand.

AESLEPRIVCMDREG

AESLEPRIVCMDREG register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						NBKEYS rw								INTENA rw	START w

Toggle fields

START

Bit 0: AES Le privacy Start command..

INTENA

Bit 1: AES Le privacy interrupt enable on Interrupt2Reg.

NBKEYS

Bits 2-9: AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list..

AESLEPRIVSTATREG

AESLEPRIVSTATREG register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						KEYFNDINDEX r								KEYFND r	BUSY r

Toggle fields

BUSY

Bit 0: AES Le privacy busy status.

KEYFND

Bit 1: AES Le privacy key finding status.

KEYFNDINDEX

Bits 2-9: AES Le privacy index of the key found in the resolution key list..

STATUS2REG

STATUS2REG register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR r	ANTENNASWITCHINGPATTERNACCESSERROR r	IQSAMPLESMISSINGERROR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IQSAMPLESNUMBER r							IQSAMPLESREADY r

Toggle fields

IQSAMPLESREADY

Bit 0: indicates if IQ samples have been received on the last reception..

IQSAMPLESNUMBER

Bits 1-7: indicate the number of IQ samples stored in the RAM buffer addressed by StatMach..

IQSAMPLESMISSINGERROR

Bit 29: IQ sample internal buffer overflow error flag..

ANTENNASWITCHINGPATTERNACCESSERROR

Bit 30: timing error flag related to Antenna Pattern not read on-time..

ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR

Bit 31: AHB access error flag..

CRC

0x48200000: CRC address block description

10/10 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x0 (16-bit)	DR16		DR16
0x0 (8-bit)	DR8			DR8
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	INIT	INIT
0x14	POL	POL	POL

Toggle registers

DR

CRC data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

Allowed values: 0x0-0xffffffff

DR16

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR16 rw

Toggle fields

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR8 rw

Toggle fields

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

CRC independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle fields

IDR

Bits 0-31: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

Allowed values: 0x0-0xffffffff

CR

CRC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle fields

RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data This bitfield controls the reversal of the bit order of the input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

CRC initial value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INIT rw

Toggle fields

INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

Allowed values: 0x0-0xffffffff

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle fields

POL

Bits 0-31: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

Allowed values: 0x0-0xffffffff

DMA

0x48700000:

168/184 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR	TEIF[8]	HTIF[8]	TCIF[8]	GIF[8]	TEIF[7]	HTIF[7]	TCIF[7]	GIF[7]	TEIF[6]	HTIF[6]	TCIF[6]	GIF[6]	TEIF[5]	HTIF[5]	TCIF[5]	GIF[5]	TEIF[4]	HTIF[4]	TCIF[4]	GIF[4]	TEIF[3]	HTIF[3]	TCIF[3]	GIF[3]	TEIF[2]	HTIF[2]	TCIF[2]	GIF[2]	TEIF[1]	HTIF[1]	TCIF[1]	GIF[1]
0x4	IFCR	CTEIF[8]	CHTIF[8]	CTCIF[8]	CGIF[8]	CTEIF[7]	CHTIF[7]	CTCIF[7]	CGIF[7]	CTEIF[6]	CHTIF[6]	CTCIF[6]	CGIF[6]	CTEIF[5]	CHTIF[5]	CTCIF[5]	CGIF[5]	CTEIF[4]	CHTIF[4]	CTCIF[4]	CGIF[4]	CTEIF[3]	CHTIF[3]	CTCIF[3]	CGIF[3]	CTEIF[2]	CHTIF[2]	CTCIF[2]	CGIF[2]	CTEIF[1]	CHTIF[1]	CTCIF[1]	CGIF[1]
0x8	CR [1]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	NDTR [1]																	NDT
0x10	PAR [1]	PA																PA
0x14	MAR [1]	MA																MA
0x1c	CR [2]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	NDTR [2]																	NDT
0x24	PAR [2]	PA																PA
0x28	MAR [2]	MA																MA
0x30	CR [3]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	NDTR [3]																	NDT
0x38	PAR [3]	PA																PA
0x3c	MAR [3]	MA																MA
0x44	CR [4]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	NDTR [4]																	NDT
0x4c	PAR [4]	PA																PA
0x50	MAR [4]	MA																MA
0x58	CR [5]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	NDTR [5]																	NDT
0x60	PAR [5]	PA																PA
0x64	MAR [5]	MA																MA
0x6c	CR [6]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	NDTR [6]																	NDT
0x74	PAR [6]	PA																PA
0x78	MAR [6]	MA																MA
0x80	CR [7]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	NDTR [7]																	NDT
0x88	PAR [7]	PA																PA
0x8c	MAR [7]	MA																MA
0x94	CR [8]																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x98	NDTR [8]																	NDT
0x9c	PAR [8]	PA																PA
0xa0	MAR [8]	MA																MA

Toggle registers

ISR

DMA_ISR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEIF[8] r	HTIF[8] r	TCIF[8] r	GIF[8] r	TEIF[7] r	HTIF[7] r	TCIF[7] r	GIF[7] r	TEIF[6] r	HTIF[6] r	TCIF[6] r	GIF[6] r	TEIF[5] r	HTIF[5] r	TCIF[5] r	GIF[5] r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF[4] r	HTIF[4] r	TCIF[4] r	GIF[4] r	TEIF[3] r	HTIF[3] r	TCIF[3] r	GIF[3] r	TEIF[2] r	HTIF[2] r	TCIF[2] r	GIF[2] r	TEIF[1] r	HTIF[1] r	TCIF[1] r	GIF[1] r

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

DMA_IFCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTEIF[8] w	CHTIF[8] w	CTCIF[8] w	CGIF[8] w	CTEIF[7] w	CHTIF[7] w	CTCIF[7] w	CGIF[7] w	CTEIF[6] w	CHTIF[6] w	CTCIF[6] w	CGIF[6] w	CTEIF[5] w	CHTIF[5] w	CTCIF[5] w	CGIF[5] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF[4] w	CHTIF[4] w	CTCIF[4] w	CGIF[4] w	CTEIF[3] w	CHTIF[3] w	CTCIF[3] w	CGIF[3] w	CTEIF[2] w	CHTIF[2] w	CTCIF[2] w	CGIF[2] w	CTEIF[1] w	CHTIF[1] w	CTCIF[1] w	CGIF[1] w

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

DMA_CCRx register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

DMA_CNDTRx register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [1]

DMA_CPARx register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [1]

DMA_CMARx register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [2]

DMA_CCRx register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

DMA_CNDTRx register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [2]

DMA_CPARx register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [2]

DMA_CMARx register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

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MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [3]

DMA_CCRx register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

DMA_CNDTRx register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [3]

DMA_CPARx register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [3]

DMA_CMARx register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [4]

DMA_CCRx register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

DMA_CNDTRx register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [4]

DMA_CPARx register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [4]

DMA_CMARx register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [5]

DMA_CCRx register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

DMA_CNDTRx register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [5]

DMA_CPARx register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [5]

DMA_CMARx register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [6]

DMA_CCRx register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

DMA_CNDTRx register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [6]

DMA_CPARx register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [6]

DMA_CMARx register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [7]

DMA_CCRx register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

DMA_CNDTRx register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [7]

DMA_CPARx register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [7]

DMA_CMARx register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CR [8]

DMA_CCRx register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [8]

DMA_CNDTRx register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [8]

DMA_CPARx register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

MAR [8]

DMA_CMARx register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMAMUX

0x48800000:

8/8 fields covered.

Toggle register map

Offset	Name	4
0x0	C[0]CR	DMAREQ_ID
0x4	C[1]CR	DMAREQ_ID
0x8	C[2]CR	DMAREQ_ID
0xc	C[3]CR	DMAREQ_ID
0x10	C[4]CR	DMAREQ_ID
0x14	C[5]CR	DMAREQ_ID
0x18	C[6]CR	DMAREQ_ID
0x1c	C[7]CR	DMAREQ_ID

Toggle registers

C[0]CR

CxCR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[1]CR

CxCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[2]CR

CxCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[3]CR

CxCR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[4]CR

CxCR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[5]CR

CxCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[6]CR

CxCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

C[7]CR

CxCR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

Allowed values:
2: Spi3Rx: SPI3_RX
3: Spi3Tx: SPI3_TX
8: I2c1Rx: I2C1_RX
9: I2c1Tx: I2C1_TX
12: UsartRx: USART_RX
13: UsartTx: USART_TX
14: LpuartRx: LPUART_RX
15: LpuartTx: LPUART_TX
16: AdcCh0: ADC_CH0 (DS channel)
18: Tim2Ch1: TIM2_CH1
19: Tim2Ch2: TIM2_CH2
20: Tim2Ch3: TIM2_CH3
21: Tim2Ch4: TIM2_CH4
22: Tim2Up: TIM2_UP
23: Tim16Ch1: TIM16_CH1
24: Tim16Up: TIM16_UP
25: Tim17Ch1: TIM17_CH1
26: Tim17Up: TIM17_UP

FLASH_CTRL

0x40001000: 4kb addressable space

6/42 fields covered.

Toggle register map

Offset	Name	31	30	22	20	19	17	16	15	14	7	6	5	4	3	2	1	0
0x0	COMMAND										COMMAND
0x4	CONFIG												WAIT_STATE			DIS_GROUP_WRITE	REMAP
0x8	IRQSTAT												FNREADY_MIS	READOK_MIS	ILLCMD_MIS	CMDBUSYERR_MIS	CMDSTART_MIS	CMDDONE_MIS
0xc	IRQMASK												FNREADYM	READOKM	ILLCMDM	CMDBUSYERRM	CMDSTARTM	CMDDONEM
0x10	IRQRAW												CMDSLEEPERR_RIS	READOK_RIS	ILLCMD_RIS	CMDBUSYERR_RIS	CMDSTART_RIS	CMDDONE_RIS
0x14	SIZE			PACKAGE_SIZE	JTAG_DISABLE	FLASH_SECURE	RAM_SIZE	FLASH_SIZE	FLASH_SIZE
0x18	ADDRESS								XADDR				YADDR
0x24	LFSRVAL	LFSRVAL							LFSRVAL
0x34	PAGEPROT0		SEGOFFSET1	SEGSIZE1						SEGOFFSET0		SEGSIZE0
0x38	PAGEPROT1		SEGOFFSET3	SEGSIZE3						SEGOFFSET2		SEGSIZE2
0x40	DATA0	DATA0							DATA0
0x44	DATA1	DATA1							DATA1
0x48	DATA2	DATA2							DATA2
0x4c	DATA3	DATA3							DATA3

Toggle registers

COMMAND

COMMAND register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								COMMAND rw

Toggle fields

COMMAND

Bits 0-7: Macro commands for flash operations (may require DATA0...DATA3 to be set): 0x11 : ERASE 0x22 : MASSERASE 0x33 : WRITE 0x55 : MASSREAD 0xAA : SLEEP 0xBB : WAKEUP 0xCC : BURSTWRITE 0xEE : OTPWRITE 0xFF : KEYWRITE.

CONFIG

CONFIG register

Offset: 0x4, size: 32, reset: 0x00000010, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WAIT_STATE rw			DIS_GROUP_WRITE rw	REMAP rw

Toggle fields

REMAP

Bit 1: CPU access routing (it supersedes PREMAP configuration): 0 : FLASH memory addressed 1 : SRAM0 memory addressed.

DIS_GROUP_WRITE

Bit 2: Burst write Control: 0 : burst write allowed 1 : burst write forbidden.

WAIT_STATE

Bits 4-5: Add latency to flash read opeations: 00 : no latency 01 : 1 clock cycle latency 10 : 2 clock cycles latency 11 : 3 clock cycles latency.

IRQSTAT

IRQSTAT register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FNREADY_MIS rw	READOK_MIS rw	ILLCMD_MIS rw	CMDBUSYERR_MIS rw	CMDSTART_MIS rw	CMDDONE_MIS rw

Toggle fields

CMDDONE_MIS

Bit 0: (1: clear, 0: inactive) CMDDONE_MIS flag.

CMDSTART_MIS

Bit 1: (1: clear, 0: inactive) CMDSTART_MIS flag.

CMDBUSYERR_MIS

Bit 2: (1: clear, 0: inactive) CMDBUSYERR_MIS flag.

ILLCMD_MIS

Bit 3: (1: clear, 0: inactive) ILLCMD_MIS flag.

READOK_MIS

Bit 4: (1: clear, 0: inactive) READOK_MIS flag.

FNREADY_MIS

Bit 5: (1: clear, 0: inactive) FNREADY_MIS flag.

IRQMASK

IRQMASK register

Offset: 0xc, size: 32, reset: 0x0000003F, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FNREADYM rw	READOKM rw	ILLCMDM rw	CMDBUSYERRM rw	CMDSTARTM rw	CMDDONEM rw

Toggle fields

CMDDONEM

Bit 0: (1: mask, 0: inactive) CMDDONE_MIS mask.

CMDSTARTM

Bit 1: (1: mask, 0: inactive) CMDSTART_MIS mask.

CMDBUSYERRM

Bit 2: (1: mask, 0: inactive) CMDBUSYERR_MIS mask.

ILLCMDM

Bit 3: (1: mask, 0: inactive) ILLCMD_MIS mask.

READOKM

Bit 4: (1: mask, 0: inactive) READOK_MIS mask.

FNREADYM

Bit 5: (1: mask, 0: inactive) FNREADY_MIS mask.

IRQRAW

IRQRAW register

Offset: 0x10, size: 32, reset: 0x00000001, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CMDSLEEPERR_RIS rw	READOK_RIS rw	ILLCMD_RIS rw	CMDBUSYERR_RIS rw	CMDSTART_RIS rw	CMDDONE_RIS rw

Toggle fields

CMDDONE_RIS

Bit 0: (1: active, 0: inactive) COMMAND sequence ended.

CMDSTART_RIS

Bit 1: (1: active, 0: inactive) COMMAND sequence started.

CMDBUSYERR_RIS

Bit 2: (1: active, 0: inactive) COMMAND issued while flash busy.

ILLCMD_RIS

Bit 3: (1: active, 0: inactive) Illegal command issued.

READOK_RIS

Bit 4: (1: active, 0: inactive) READ COMMAND completed successfully.

CMDSLEEPERR_RIS

Bit 5: (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1).

SIZE

SIZE register

Offset: 0x14, size: 32, reset: 0x0006BFFF, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PACKAGE_SIZE r		JTAG_DISABLE r	FLASH_SECURE r		RAM_SIZE r	FLASH_SIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLASH_SIZE r

Toggle fields

FLASH_SIZE

Bits 0-16: Maximum valid address for flash memory: 00 : 0x03FFF (64kb) 01 : 0x07FFF (128kb) 10 : 0x09FFF (160kb) 11 : 0x0BFFF (192kb).

RAM_SIZE

Bit 17: RAM memory size selection: 0 : 16kb 1 : 32kb.

FLASH_SECURE

Bit 19: Flash memory protection (0: no key present, 1: key present).

JTAG_DISABLE

Bit 20: Flash+JTAG protection (0: no JTAG protection see FLASH_SECURE, 1: Flash and JTAG protected).

PACKAGE_SIZE

Bits 21-22: Package selection: 0: CSP 10 : 32pins 11 : 48pins.

ADDRESS

ADDRESS register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XADDR rw										YADDR rw

Toggle fields

YADDR

Bits 0-5: Flash column address offset to be used with some COMMAND.

XADDR

Bits 6-15: Flash row address offset to be used with some COMMAND.

LFSRVAL

LFSRVAL register

Offset: 0x24, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LFSRVAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LFSRVAL r

Toggle fields

LFSRVAL

Bits 0-31: Flash read data CRC signature.

PAGEPROT0

PAGEPROT0 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SEGOFFSET1 rw								SEGSIZE1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SEGOFFSET0 rw								SEGSIZE0 rw

Toggle fields

SEGSIZE0

Bits 0-6: First segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET0

Bits 8-14: First segment, 7-bit page protection offset (first page number in protected segment).

SEGSIZE1

Bits 16-22: Second segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET1

Bits 24-30: Second segment, 7-bit page protection offset (first page number in protected segment).

PAGEPROT1

PAGEPROT1 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SEGOFFSET3 rw								SEGSIZE3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SEGOFFSET2 rw								SEGSIZE2 rw

Toggle fields

SEGSIZE2

Bits 0-6: Third segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET2

Bits 8-14: Third segment, 7-bit page protection offset (first page number in protected segment).

SEGSIZE3

Bits 16-22: Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET3

Bits 24-30: Fourth segment, 7-bit page protection offset (first page number in protected segment).

DATA0

DATA0 register

Offset: 0x40, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA0 rw

Toggle fields

DATA0

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD.

DATA1

DATA1 register

Offset: 0x44, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA1 rw

Toggle fields

DATA1

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

DATA2

DATA2 register

Offset: 0x48, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA2 rw

Toggle fields

DATA2

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

DATA3

DATA3 register

Offset: 0x4c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA3 rw

Toggle fields

DATA3

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

GLOBALSTATMACH

0x200000c0:

0/31 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	22	21	20	15	7	6	2	0
0x0	WORD0	RadioConfigPtr											RadioConfigPtr
0x4	WORD1	Timer2InitDelayNoCal							Timer12InitDelayCal				WakeupInitDelay	Active	CurStMachNum
0x8	WORD2	ReceiveNoCalDelayChk							ReceiveCalDelayChk				TransmitNoCalDelayChk	TransmitCalDelayChk
0xc	WORD3	TimeCapture	TimeCaptureSel	TxdelayEnd					TxdelayStart				TxdataReadyCheck	ConfigEndDuration
0x10	WORD4					RcvTimeout							RcvTimeout	TxReadyTimeout
0x14	WORD5	IntConfigError	IntActive2Err	intTxRxSkip	IntSeqDone		IntSemaTimeoutError	IntRcvLengthError	IntNoActiveLError	IntTxDataReadyError	IntAllTableReadyError	IntAddPointError				ChkFlagAutoClearEna	AutoTxRxskipEn
0x18	WORD6														DefaultAntennaID

Toggle registers

WORD0

WORD0 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RadioConfigPtr rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RadioConfigPtr rw

Toggle fields

RadioConfigPtr

Bits 0-31: Radio Configuration address Pointer..

WORD1

WORD1 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Timer2InitDelayNoCal rw								Timer12InitDelayCal rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WakeupInitDelay rw								Active rw	CurStMachNum rw

Toggle fields

CurStMachNum

Bits 0-6: current connection machine number..

Active

Bit 7: Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence..

WakeupInitDelay

Bits 8-15: Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM..

Timer12InitDelayCal

Bits 16-23: Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM..

Timer2InitDelayNoCal

Bits 24-31: Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM..

WORD2

WORD2 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ReceiveNoCalDelayChk rw								ReceiveCalDelayChk rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TransmitNoCalDelayChk rw								TransmitCalDelayChk rw

Toggle fields

TransmitCalDelayChk

Bits 0-7: Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block..

TransmitNoCalDelayChk

Bits 8-15: Delay between TX request sent to the Radio FSM and the start pulse to the transmit block..

ReceiveCalDelayChk

Bits 16-23: Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block..

ReceiveNoCalDelayChk

Bits 24-31: Delay between RX request sent to the Radio FSM and the start pulse to the receive block..

WORD3

WORD3 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TimeCapture rw	TimeCaptureSel rw	TxdelayEnd rw						TxdelayStart rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxdataReadyCheck rw								ConfigEndDuration rw

Toggle fields

ConfigEndDuration

Bits 0-7: Duration for the Sequencer to execute the final configuration..

TxdataReadyCheck

Bits 8-15: Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table..

TxdelayStart

Bits 16-23: Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator..

TxdelayEnd

Bits 24-29: Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer..

TimeCaptureSel

Bit 30: - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event)..

TimeCapture

Bit 31: - 0: No capture is requested to monitor the Bluetooth LE sequence..

WORD4

WORD4 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				RcvTimeout rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RcvTimeout rw								TxReadyTimeout rw

Toggle fields

TxReadyTimeout

Bits 0-7: Transmission ready timeout..

RcvTimeout

Bits 8-27: Receive window timeout..

WORD5

WORD5 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IntConfigError rw	IntActive2Err rw	intTxRxSkip rw	IntSeqDone rw		IntSemaTimeoutError rw	IntRcvLengthError rw		IntNoActiveLError rw	IntTxDataReadyError rw	IntAllTableReadyError rw	IntAddPointError rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													ChkFlagAutoClearEna rw		AutoTxRxskipEn rw

Toggle fields

AutoTxRxskipEn

Bit 0: Automatic transfer (TX or RX) skip enable..

ChkFlagAutoClearEna

Bit 2: Active bit Auto Clear Enable..

IntAddPointError

Bit 20: Address pointer error interrupt enable..

IntAllTableReadyError

Bit 21: All table ready error interrupt enable..

IntTxDataReadyError

Bit 22: Transmission data payload ready error interrupt enable..

IntNoActiveLError

Bit 23: Active bit low value reading interrupt enable..

IntRcvLengthError

Bit 25: Too long received payload length interrupt enable..

IntSemaTimeoutError

Bit 26: Semaphore timeout error interrupt enable..

IntSeqDone

Bit 28: Sequencer end of task interrupt enable..

intTxRxSkip

Bit 29: Transmission or reception skip interrupt enable..

IntActive2Err

Bit 30: not in ACTIVE2 information from Radio FSM received on time interrupt enable..

IntConfigError

Bit 31: Configuration error interrupt enable..

WORD6

WORD6 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DefaultAntennaID rw

Toggle fields

DefaultAntennaID

Bits 0-6: Default Antenna ID corresponding to the number of the antenna used to receive/transmit:.

GPIOA

0x48000000:

129/129 fields covered.

Toggle register map

Offset	Name	27	26	25	24	23	22	21	20	19	18	17	16	15	13	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER					MODE[11]		MODE[10]		MODE[9]		MODE[8]		MODE[7]	MODE[6]	MODE[5]		MODE[4]		MODE[3]		MODE[2]		MODE[1]		MODE[0]
0x4	OTYPER															OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR					OSPEED[11]		OSPEED[10]		OSPEED[9]		OSPEED[8]		OSPEED[7]	OSPEED[6]	OSPEED[5]		OSPEED[4]		OSPEED[3]		OSPEED[2]		OSPEED[1]		OSPEED[0]
0xc	PUPDR					PUPD[11]		PUPD[10]		PUPD[9]		PUPD[8]		PUPD[7]	PUPD[6]	PUPD[5]		PUPD[4]		PUPD[3]		PUPD[2]		PUPD[1]		PUPD[0]
0x10	IDR															ID[11]	ID[10]	ID[9]	ID[8]	ID[7]	ID[6]	ID[5]	ID[4]	ID[3]	ID[2]	ID[1]	ID[0]
0x14	ODR															OD[11]	OD[10]	OD[9]	OD[8]	OD[7]	OD[6]	OD[5]	OD[4]	OD[3]	OD[2]	OD[1]	OD[0]
0x18	BSRR	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]			BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR												LCKK			LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL													AFSEL[3]		AFSEL[2]				AFSEL[1]				AFSEL[0]
0x24	AFRH													AFSEL[11]		AFSEL[10]				AFSEL[9]				AFSEL[8]
0x28	BRR															BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]

Toggle registers

MODER

MODER register

Offset: 0x0, size: 32, reset: 0x000000A0, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								MODE[11] rw		MODE[10] rw		MODE[9] rw		MODE[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE[7] rw		MODE[6] rw		MODE[5] rw		MODE[4] rw		MODE[3] rw		MODE[2] rw		MODE[1] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

OTYPER register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

OSPEEDR register

Offset: 0x8, size: 32, reset: 0x00000030, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								OSPEED[11] rw		OSPEED[10] rw		OSPEED[9] rw		OSPEED[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED[7] rw		OSPEED[6] rw		OSPEED[5] rw		OSPEED[4] rw		OSPEED[3] rw		OSPEED[2] rw		OSPEED[1] rw		OSPEED[0] rw

Toggle fields

OSPEED[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

PUPDR register

Offset: 0xc, size: 32, reset: 0x00550095, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PUPD[11] rw		PUPD[10] rw		PUPD[9] rw		PUPD[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD[7] rw		PUPD[6] rw		PUPD[5] rw		PUPD[4] rw		PUPD[3] rw		PUPD[2] rw		PUPD[1] rw		PUPD[0] rw

Toggle fields

PUPD[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

IDR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ID[11] r	ID[10] r	ID[9] r	ID[8] r	ID[7] r	ID[6] r	ID[5] r	ID[4] r	ID[3] r	ID[2] r	ID[1] r	ID[0] r

Toggle fields

ID[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

ODR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OD[11] rw	OD[10] rw	OD[9] rw	OD[8] rw	OD[7] rw	OD[6] rw	OD[5] rw	OD[4] rw	OD[3] rw	OD[2] rw	OD[1] rw	OD[0] rw

Toggle fields

OD[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

BSRR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

LCKR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. -0: Port configuration lock key not active -1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = 1' + LCKR[15:0] WR LCKR[16] = 0' + LCKR[15:0] WR LCKR[16] = 1' + LCKR[15:0] RD LCKR RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1' until the next MCU reset or peripheral reset.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[3] rw				AFSEL[2] rw				AFSEL[1] rw				AFSEL[0] rw

Toggle fields

AFSEL[0]

Bits 0-3: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[1]

Bits 4-7: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[2]

Bits 8-11: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[3]

Bits 12-15: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

AFRH register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[11] rw				AFSEL[10] rw				AFSEL[9] rw				AFSEL[8] rw

Toggle fields

AFSEL[8]

Bits 0-3: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[9]

Bits 4-7: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[10]

Bits 8-11: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[11]

Bits 12-15: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

BRR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOB

0x48100000:

141/141 fields covered.

Toggle register map

Offset	Name	31	29	27	26	25	24	23	22	21	20	19	18	17	16	15	13	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE[15]	MODE[14]	MODE[13]		MODE[12]		MODE[11]		MODE[10]		MODE[9]		MODE[8]		MODE[7]	MODE[6]	MODE[5]		MODE[4]		MODE[3]		MODE[2]		MODE[1]		MODE[0]
0x4	OTYPER																	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEED[15]	OSPEED[14]	OSPEED[13]		OSPEED[12]		OSPEED[11]		OSPEED[10]		OSPEED[9]		OSPEED[8]		OSPEED[7]	OSPEED[6]	OSPEED[5]		OSPEED[4]		OSPEED[3]		OSPEED[2]		OSPEED[1]		OSPEED[0]
0xc	PUPDR	PUPD[15]	PUPD[14]	PUPD[13]		PUPD[12]		PUPD[11]		PUPD[10]		PUPD[9]		PUPD[8]		PUPD[7]	PUPD[6]	PUPD[5]		PUPD[4]		PUPD[3]		PUPD[2]		PUPD[1]		PUPD[0]
0x10	IDR																	ID[11]	ID[10]	ID[9]	ID[8]	ID[7]	ID[6]	ID[5]	ID[4]	ID[3]	ID[2]	ID[1]	ID[0]
0x14	ODR																	OD[11]	OD[10]	OD[9]	OD[8]	OD[7]	OD[6]	OD[5]	OD[4]	OD[3]	OD[2]	OD[1]	OD[0]
0x18	BSRR			BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]			BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR														LCKK			LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL															AFSEL[3]		AFSEL[2]				AFSEL[1]				AFSEL[0]
0x24	AFRH															AFSEL[11]		AFSEL[10]				AFSEL[9]				AFSEL[8]
0x28	BRR																	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]

Toggle registers

MODER

MODER register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE[15] rw		MODE[14] rw		MODE[13] rw		MODE[12] rw		MODE[11] rw		MODE[10] rw		MODE[9] rw		MODE[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE[7] rw		MODE[6] rw		MODE[5] rw		MODE[4] rw		MODE[3] rw		MODE[2] rw		MODE[1] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODE[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

OTYPER register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

OSPEEDR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED[15] rw		OSPEED[14] rw		OSPEED[13] rw		OSPEED[12] rw		OSPEED[11] rw		OSPEED[10] rw		OSPEED[9] rw		OSPEED[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED[7] rw		OSPEED[6] rw		OSPEED[5] rw		OSPEED[4] rw		OSPEED[3] rw		OSPEED[2] rw		OSPEED[1] rw		OSPEED[0] rw

Toggle fields

OSPEED[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEED[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

PUPDR register

Offset: 0xc, size: 32, reset: 0x55005555, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD[15] rw		PUPD[14] rw		PUPD[13] rw		PUPD[12] rw		PUPD[11] rw		PUPD[10] rw		PUPD[9] rw		PUPD[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD[7] rw		PUPD[6] rw		PUPD[5] rw		PUPD[4] rw		PUPD[3] rw		PUPD[2] rw		PUPD[1] rw		PUPD[0] rw

Toggle fields

PUPD[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPD[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

IDR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ID[11] r	ID[10] r	ID[9] r	ID[8] r	ID[7] r	ID[6] r	ID[5] r	ID[4] r	ID[3] r	ID[2] r	ID[1] r	ID[0] r

Toggle fields

ID[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ID[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

ODR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OD[11] rw	OD[10] rw	OD[9] rw	OD[8] rw	OD[7] rw	OD[6] rw	OD[5] rw	OD[4] rw	OD[3] rw	OD[2] rw	OD[1] rw	OD[0] rw

Toggle fields

OD[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OD[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

BSRR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

LCKR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. -0: Port configuration lock key not active -1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = 1' + LCKR[15:0] WR LCKR[16] = 0' + LCKR[15:0] WR LCKR[16] = 1' + LCKR[15:0] RD LCKR RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1' until the next MCU reset or peripheral reset.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[3] rw				AFSEL[2] rw				AFSEL[1] rw				AFSEL[0] rw

Toggle fields

AFSEL[0]

Bits 0-3: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[1]

Bits 4-7: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[2]

Bits 8-11: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[3]

Bits 12-15: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

AFRH register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL[11] rw				AFSEL[10] rw				AFSEL[9] rw				AFSEL[8] rw

Toggle fields

AFSEL[8]

Bits 0-3: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[9]

Bits 4-7: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[10]

Bits 8-11: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL[11]

Bits 12-15: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

BRR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

I2C1

0x41000000: I2C address block description

76/76 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1
0xc	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

Toggle registers

CR1

I2C control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: Stop detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Note: Transfer Complete (TC) Note: Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Note: Arbitration Loss (ARLO) Note: Bus Error detection (BERR) Note: Overrun/Underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. Note: This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. Note: WUPEN can be set only when DNF = '0000'.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

I2C control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE r/w1s	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK r/w1s	STOP r/w1s	START r/w1s	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master mode: Note: Writing '0' to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing '0' to this bit has no effect. Note: This bit has no effect when RELOAD is set. Note: This bit has no effect is slave mode when SBC=0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

I2C own address 1 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

I2C own address 2 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own address 2 masks Note: These bits can be written only when OA2EN=0. Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

I2C timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

I2C timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

I2C interrupt and status register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS r/w1s	TXE r/w1s

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TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0..

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0..

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0..

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR = 1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

Allowed values: 0x0-0x7f

ICR

I2C interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w1c	TIMOUTCF w1c	PECCF w1c	OVRCF w1c	ARLOCF w1c	BERRCF w1c			STOPCF w1c	NACKCF w1c	ADDRCF w1c

Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register..

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation..

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

I2C PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0..

Allowed values: 0x0-0xff

RXDR

I2C receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

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RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus.

Allowed values: 0x0-0xff

TXDR

I2C transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

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TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE = 1..

Allowed values: 0x0-0xff

IWDG

0x40003000:

7/7 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0 (16-bit)	KR	KEY
0x4 (16-bit)	PR			PR
0x8 (16-bit)	RLR		RL
0xc (16-bit)	SR			WVU	RVU	PVU
0x10 (16-bit)	WINR		WIN

Toggle registers

KR

IWDG_KR register

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

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KEY

Bits 0-15: Key value. Software can only write these bits. Reading returns the reset value. These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. Writing the key value CCCCh starts the watchdog.

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

IWDG_PR register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

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PR

Bits 0-2: Prescaler divider. Set and reset by software. These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider/4 001: divider/8 010: divider/16 011: divider/32 100: divider/64 101: divider/128 110: divider/256 111: divider/256.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6 (+): DivideBy256: Divider /256

RLR

IWDG_RLR register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

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RL

Bits 0-11: Watchdog counter reload value. Set and reset by software. These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value..

Allowed values: 0x0-0xfff

SR

IWDG_SR register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

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PVU

Bit 0: Watchdog prescaler value update. Read only bit. This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset.

RVU

Bit 1: Watchdog counter reload value update. Read only bit. This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset.

WVU

Bit 2: Watchdog counter window value update. Read only bit. This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic 'window' = 1.

WINR

IWDG_WINR register

Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

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WIN

Bits 0-11: Watchdog counter window value. Set and reset by software. These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value..

Allowed values: 0x0-0xfff

LPUART

0x41005000:

80/84 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1			DEAT					DEDT						CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD												MSBFIRST	DATAINV	TXINV	RXINV	SWAP		STOP									ADDM7
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG				TXFTIE	WUFIE	WUS						DEP	DEM	DDRE	OVRDIS		CTSIE	CTSE	RTSE	DMAT	DMAR			HDSEL			EIE
0xc	BRR													BRR				BRR
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ
0x1c	ISR					TXFT	RXFT		RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF								CTSCF			TCCF		IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: UESM: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that the LPUART clock selection is LSE in the RCC. This bit is set and cleared by software. -0: LPUART not able to wake up the MCU from Stop mode. -1: LPUART able to wake up the MCU from Stop mode. When this function is active, the clock source for the LPUART must be LSE (see RCC chapter).

RE

Bit 2: RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0)..

Allowed values: 0x0-0x1f

M1

Bit 28: Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled..

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw												MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw		STOP rw									ADDM7 rw

Toggle fields

ADDM7

Bit 4: ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0).

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

STOP

Bits 12-13: STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bit

SWAP

Bit 15: SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).

Allowed values: 0x0-0xff

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw				TXFTIE rw	WUFIE rw	WUS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw		CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw			HDSEL rw			EIE rw

Toggle fields

EIE

Bit 0: EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register..

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0).

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). -00: WUF active on address match (as defined by ADD[7:0] and ADDM7) -01:Reserved. -10: WUF active on Start bit detection -11: WUF active on RXNE. This bit field can only be written when the LPUART is disabled (UE=0)..

WUFIE

Bit 22: WUFIE: Wakeup from Stop mode interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register.

TXFTIE

Bit 23: TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG..

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

RXFTCFG

Bits 25-27: RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved..

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG..

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved..

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

BRR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BRR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

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BRR

Bits 0-19: BRR[19:0].

Allowed values: 0x0-0xfffff

RQR

RQR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w

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SBKRQ

Bit 1: SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available..

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag..

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition..

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0' When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes..

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

ISR register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r		RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read..

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

CTSIF

Bit 9: CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

BUSY

Bit 16: BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode.

WUF

Bit 20: WUF: Wakeup from Stop mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=1 in the LPUART_CR3 register.

TEACK

Bit 21: TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode..

TXFE

Bit 23: TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty..

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full..

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

RXFT

Bit 26: RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesn't reach the programmed threshold. -1: Receive FIFO reached the programmed threshold.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesn't reach the programmed threshold. -1: TXFIFO reached the programmed threshold.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

ICR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w1c			CMCF w1c
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTSCF w1c			TCCF w1c		IDLECF w1c	ORECF w1c	NECF w1c	FECF w1c	PECF w1c

Toggle fields

PECF

Bit 0: PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NECF

Bit 2: NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register.

RDR

RDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

Allowed values: 0x0-0x1ff

TDR

TDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1..

Allowed values: 0x0-0x1ff

PRESC

PRESC register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be '1011' i.e. input clock divided by 256.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div6: /6
4: Div8: /8
5: Div10: /10
6: Div12: /12
7: Div16: /16
8: Div32: /32
9: Div64: /64
10: Div128: /128
11: Div256: /256

PKA

0x48300000:

6/18 fields covered.

Toggle register map

Offset	Name	23	22	20	19	17	16	13	2	1	0
0x0	CR	FAULTERRORCODEIE	FAULTFSMIE	ADDRERRIE	RAMERRIE	PROCENDIE		MODE	SECLVL	START	EN
0x4	SR	FAULTERRORCODEF	FAULTFSMF	ADDRERRF	RAMERRF	PROCENDF	BUSY
0x8	CLRFR			ADDRERRFC	RAMERRFC	PROCENDFC

Toggle registers

CR

PKA_CR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FAULTERRORCODEIE rw	FAULTFSMIE rw		ADDRERRIE rw	RAMERRIE rw		PROCENDIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MODE rw											SECLVL rw	START rw	EN rw

Toggle fields

EN

Bit 0: Peripheral enable. 0 : Disable PKA. 1 : Enable PKA..

START

Bit 1: Start the operation 0: No operation 1: Writing '1' to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as '0'. Nota: START is ignored if PKA is busy..

SECLVL

Bit 2: Security enable. 0: No side channel countermeasure 1: Square and Multiply always / Double and Add always.

MODE

Bits 8-13: PKA operation code 000000 : Compute Montgomery parameter and modular exponentiation 000001 : Compute Montgomery parameter 000010 : Compute modular exponentiation only (Montgomery parameter should be loaded) 100000 : Compute Montgomery parameter and compute ECC kP operation 100010 : Compute the ECC kP primitive only (Montgomery parameter should be loaded) 100100 : ECDSA sign 100110 : ECDSA Verification 101000 : Point Check 000111 : RSA CRT exponentiation 001000 : Modular inversion 001001 : Arithmetic addition 001010 : Arithmetic Subtraction 001011 : Arithmetic multiplication 001100 : Comparison 001101 : Modular Reduction 001110 : Modular Addition 001111 : Modular Subtraction 010000 : Montgomery Multiplication.

PROCENDIE

Bit 17: End of operation interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when PROCENDF (PKA_SR[17]) is set..

RAMERRIE

Bit 19: RAM error interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when RAMERRF (PKA_SR[19]) is set..

ADDRERRIE

Bit 20: Address error interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when ADDRERRF (PKA_SR[20]) is set..

FAULTFSMIE

Bit 22: Fault FSM interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when FAULTFSMF (PKA_SR[22]) is set..

FAULTERRORCODEIE

Bit 23: Fault error code interrupt enable 0: Interrupt is disabled. 1: An interrupt is generated when FAULTERRORCODEF (PKA_SR[23]) is set..

SR

PKA_SR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FAULTERRORCODEF r	FAULTFSMF r		ADDRERRF r	RAMERRF r		PROCENDF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

BUSY

Bit 16: PKA operation is in progress This bit is set to '1' whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. 0: No operation is in progress (default) 1: An operation is in progress Nota: if PKA is started with a wrong opcode the IP will be busy for a couple of cycles then it will abort automatically the operation and go back to ready (BUSY bit is set to '0')..

PROCENDF

Bit 17: PKA End of Operation flag 0: Operation in progress 1: PKA operation is completed. This flag is set when the BUSY bit is de-asserted..

RAMERRF

Bit 19: PKA RAM error flag 0: No PKA RAM access error 1: An AHB access to the PKA RAM occured while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress)..

ADDRERRF

Bit 20: Address error flag 0: No Address error 1: Address access is out of range (unmapped address).

FAULTFSMF

Bit 22: Fault fsm error flag 0: No fault has been detected 1: A fault on fsm has been detected.

FAULTERRORCODEF

Bit 23: Fault error code error flag 0: No fault has been detected 1: A fault has altered the execution of the operation and the internal fault check has been skipped.

CLRFR

PKA_CLRFR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRFC rw	RAMERRFC rw		PROCENDFC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PROCENDFC

Bit 17: Clear PKA End of Operation flag 0: No action 1: Clear the PROCENDF flag.

RAMERRFC

Bit 19: Clear PKA RAM error flag 0: No action 1: Clear the RAMERRF flag Bits 18 Reserved, must be kept at zero.

ADDRERRFC

Bit 20: Clear Address error flag 0: No action 1: Clear the ADDRERRF flag.

PWRC

0x48500000:

10/107 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1								ENBORL	SELBORH		ENBORH	APC	IBIAS_RUN_STATE	IBIAS_RUN_AUTO	ENSDNBOR	LPMS
0x4	CR2							ENTS	GPIORET			RAMRET1	DBGRET	PVDLS			PVDE
0x8	CR3	EIWL	EIWL2	EWBLEHCPU	EWBLE	EWU11	EWU10	EWU9	EWU8	EWU7	EWU6	EWU5	EWU4	EWU3	EWU2	EWU1	EWU0
0xc	CR4					WUP11	WUP10	WUP9	WUP8	WUP7	WUP6	WUP5	WUP4	WUP3	WUP2	WUP1	WUP0
0x10	SR1	IWUF	IWUF2	WBLEHCPUF	WBLEF	WUF11	WUF10	WUF9	WUF8	WUF7	WUF6	WUF5	WUF4	WUF3	WUF2	WUF1	WUF0
0x14	SR2	IOBOOTVAL				PVDO		REGMS	REGLPS	IOBOOTVAL2					SMPSRDY	SMPSENR	SMPSBYPR
0x1c	CR5		SMPS_PRECH_CUR_SEL		CLKDETR_DISABLE	SMPS_ENA_DCM	NOSMPS	SMPSFBYP	SMPSLPOPEN	SMPSFRDY		SMPSBOMSEL		SMPSLVL
0x20	PUCRA	PU
0x24	PDCRA	PD
0x28	PUCRB	PU
0x2c	PDCRB	PD
0x30	CR6									EWU19	EWU18	EWU17	EWU16	EWU15	EWU14	EWU13	EWU12
0x34	CR7									WUP19	WUP18	WUP17	WUP16	WUP15	WUP14	WUP13	WUP12
0x38	SR3									WUF19	WUF18	WUF17	WUF16	WUF15	WUF14	WUF13	WUF12
0x84	DBGR	DIS_PRECH															DEEPSTOP2
0x88	EXTSRR						RFPHASEF	DEEPSTOPF

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000114, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							ENBORL rw	SELBORH rw		ENBORH rw	APC rw	IBIAS_RUN_STATE rw	IBIAS_RUN_AUTO rw	ENSDNBOR rw	LPMS rw

Toggle fields

LPMS

Bit 0: LPMS Low Power Mode Selection Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep..

ENSDNBOR

Bit 1: ENSDNBOR: Enable BOR supply monitoring during shutdown mode..

IBIAS_RUN_AUTO

Bit 2: IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) 1: IBIAS control is automatic (default)..

IBIAS_RUN_STATE

Bit 3: IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is disabled. 0: IBIAS control is disabled (default). 1: IBIAS control is enabled..

APC

Bit 4: APC Apply Pull-up and pull-down configuration from CPU.

ENBORH

Bit 5: ENBORH: enable BORH configuration.

SELBORH

Bits 6-7: SELBORH[1:0]: BORH selection of Vbor threshold.

ENBORL

Bit 8: ENBORL: Enable BORL reset supervising during RUN mode. 0: No BORL is monitored during RUN mode. 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						ENTS rw	GPIORET rw			RAMRET1 rw	DBGRET rw	PVDLS rw			PVDE rw

Toggle fields

PVDE

Bit 0: PVDE Programmable Voltage Detector Enable When this bit is set the Power Voltage Detector is enabled.

PVDLS

Bits 1-3: PVDLS[2:0] Programmable Voltage Detector Level selection then PVDO=1).

DBGRET

Bit 4: DBGRET: PA2 and PA3 retention enable after DEEPSTOP 0: PA2, PA3 don't retain their status exiting from DEEPSTOP. (default) 1: PA2, PA3 retain their status exiting from DEEPSTOP..

RAMRET1

Bit 5: RAMRET1: RAM1 retention during low power mode.

GPIORET

Bit 8: GPIORET: GPIO retention enable. 0: GPIO don't retain their status during DEEPSTOP and exiting from DEEPSTOP (default) 1: GPIO retain their status during DEEPSTOP and exiting from DEEPSTOP. Note: it's mandatory to ensure this bit is set before entering DEEPSTOP unless DBRG.DEEPSTOP2 bit is set..

ENTS

Bit 9: ENTS: Enable Temperature Sensor.

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWL rw	EIWL2 rw	EWBLEHCPU rw	EWBLE rw	EWU11 rw	EWU10 rw	EWU9 rw	EWU8 rw	EWU7 rw	EWU6 rw	EWU5 rw	EWU4 rw	EWU3 rw	EWU2 rw	EWU1 rw	EWU0 rw

Toggle fields

EWU0

Bit 0: EWU0 Enable WakeUp line 0 (PB0) When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit..

EWU1

Bit 1: EWU1 Enable WakeUp line 1 (PB1) When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit..

EWU2

Bit 2: EWU2 Enable WakeUp line 2 (PB2) When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit..

EWU3

Bit 3: EWU3 Enable WakeUp line 3 (PB3) When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit..

EWU4

Bit 4: EWU4 Enable WakeUp line 4 (PB4) When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit..

EWU5

Bit 5: EWU5 Enable WakeUp line 5 (PB5) When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit..

EWU6

Bit 6: EWU6 Enable WakeUp line 6 (PB6) When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit..

EWU7

Bit 7: EWU7 Enable WakeUp line 7 (PB7) When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit..

EWU8

Bit 8: EWU8 Enable WakeUp line 8 (PA8) When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit..

EWU9

Bit 9: EWU9 Enable WakeUp line 9 (PA9) When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit..

EWU10

Bit 10: EWU10 Enable WakeUp line 10 (PA10) When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit..

EWU11

Bit 11: EWU11 Enable WakeUp line 11 (PA11) When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit..

EWBLE

Bit 12: EWBLE: Enable wakeup on BLE event. 0: Wakeup on BLE line is disabled (default). 1: Wakeup on BLE line is enabled..

EWBLEHCPU

Bit 13: EWBLEHCPU: Enable wakeup on BLE Host CPU event. 0: Wakeup on BLE Host CPU line is disabled (default). 1: Wakeup on BLE Host CPU line is enabled..

EIWL2

Bit 14: EIWL2: Enable wakeup on Internal event (LPUART). 0: Wakeup on internal line is disabled (default). 1: Wakeup on internal line is enabled..

EIWL

Bit 15: EIWL: Enable wakeup on Internal event (RTC). 0: Wakeup on internal line is disabled (default). 1: Wakeup on internal line is enabled..

CR4

CR4 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WUP11 rw	WUP10 rw	WUP9 rw	WUP8 rw	WUP7 rw	WUP6 rw	WUP5 rw	WUP4 rw	WUP3 rw	WUP2 rw	WUP1 rw	WUP0 rw

Toggle fields

WUP0

Bit 0: WUP0 Wake-up Line Polarity 0 (PB0) This bit defines the polarity used for event detection on external wake-up line 0.

WUP1

Bit 1: WUP1 Wake-up Line Polarity 1 (PB1) This bit defines the polarity used for event detection on external wake-up line 1.

WUP2

Bit 2: WUP2 Wake-up Line Polarity 2 (PB2) This bit defines the polarity used for event detection on external wake-up line 2.

WUP3

Bit 3: WUP3 Wake-up Line Polarity 3 (PB3) This bit defines the polarity used for event detection on external wake-up line 3.

WUP4

Bit 4: WUP4 Wake-up Line Polarity 4 (PB4) This bit defines the polarity used for event detection on external wake-up line 4.

WUP5

Bit 5: WUP5 Wake-up Line Polarity 5 (PB5) This bit defines the polarity used for event detection on external wake-up line 5.

WUP6

Bit 6: WUP6 Wake-up Line Polarity 6 (PB6) This bit defines the polarity used for event detection on external wake-up line 6.

WUP7

Bit 7: WUP7 Wake-up Line Polarity 7 (PB7) This bit defines the polarity used for event detection on external wake-up line 7.

WUP8

Bit 8: WUP8 Wake-up Line Polarity 8 (PA8) This bit defines the polarity used for event detection on external wake-up line 8.

WUP9

Bit 9: WUP9 Wake-up Line Polarity 9 (PA9) This bit defines the polarity used for event detection on external wake-up line 9.

WUP10

Bit 10: WUP10 Wake-up Line Polarity 10 (PA10) This bit defines the polarity used for event detection on external wake-up line 10.

WUP11

Bit 11: WUP11 Wake-up Line Polarity 11 (PA11) This bit defines the polarity used for event detection on external wake-up line 11.

SR1

SR1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IWUF r	IWUF2 r	WBLEHCPUF rw	WBLEF rw	WUF11 rw	WUF10 rw	WUF9 rw	WUF8 rw	WUF7 rw	WUF6 rw	WUF5 rw	WUF4 rw	WUF3 rw	WUF2 rw	WUF1 rw	WUF0 rw

Toggle fields

WUF0

Bit 0: WUF0 WakeUp Flag 0 (PB0) This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF1

Bit 1: WUF1 WakeUp Flag 1 (PB1) This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF2

Bit 2: WUF2 WakeUp Flag 2 (PB2) This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF3

Bit 3: WUF3 WakeUp Flag 3 (PB3) This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF4

Bit 4: WUF4 WakeUp Flag 4 (PB4) This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF5

Bit 5: WUF5 WakeUp Flag 5 (PB5) This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF6

Bit 6: WUF6 WakeUp Flag 6 (PB6) This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF7

Bit 7: WUF7 WakeUp Flag 7 (PB7) This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF8

Bit 8: WUF8 WakeUp Flag 8 (PA8) This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF9

Bit 9: WUF9 WakeUp Flag 9 (PA9) This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF10

Bit 10: WUF10 WakeUp Flag 10 (PA10) This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF11

Bit 11: WUF11 WakeUp Flag 11 (PA11) This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WBLEF

Bit 12: WBLEF: BLE wakeup flag. 0: no wakeup from BLE occurred since last clear. 1: a wakeup from BLE occurred since last clear. Cleared by writing 1 in this bit..

WBLEHCPUF

Bit 13: WBLEHCPUF: BLE Host CPU wakeup flag. 0: no wakeup from BLE Host CPU occurred since last clear. 1: a wakeup from BLE Host CPU occurred since last clear. Cleared by writing 1 in this bit..

IWUF2

Bit 14: IWUF2: Internal wakeup 2 flag (LPUART). 0: no wakeup from LPUART occurred since last clear. 1: a wakeup from LPUART occurred since last clear. Note: The user must clear the LPUART wakeup flag inside the LPUART IP to clear this bit (mirror of the LPUART wakeup line on the PWRC block)..

IWUF

Bit 15: IWUF: Internal wakeup flag (RTC). 0: no wakeup from RTC occurred since last clear. 1: a wakeup from RTC occurred since last clear. Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of the RTC wakeup line on the PWRC block)..

SR2

SR2 register

Offset: 0x14, size: 32, reset: 0x00000306, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOBOOTVAL r				PVDO r		REGMS r	REGLPS r	IOBOOTVAL2 r					SMPSRDY r	SMPSENR r	SMPSBYPR r

Toggle fields

SMPSBYPR

Bit 0: SMPSBYPR: SMPS Force Bypass Control Replica This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state..

SMPSENR

Bit 1: SMPSENR: SMPS Enable Control Replica This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state..

SMPSRDY

Bit 2: SMPSRDY: SMPS Ready Status This bit provides the information whether SMPS is ready..

IOBOOTVAL2

Bits 4-7: Bit3: PB15 input value on VDD33 latched at POR Bit2: PB14 input value on VDD33 latched at POR Bit1: PB13 input value on VDD33 latched at POR Bit0: PB12 input value on VDD33 latched at POR.

REGLPS

Bit 8: REGLPS: Regulator Low Power Started This bit provides the information whether low power regulator is ready..

REGMS

Bit 9: REGMS: Regulator Main LDO Started This bit provides the information whether main regulator is ready..

PVDO

Bit 11: PVDO: Power Voltage Detector Output When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is lower than the selected PVD threshold (CR2.PVDLS).

IOBOOTVAL

Bits 12-15: Bit3: PA11 input value on VDD33 latched at POR Bit2: PA10 input value on VDD33 latched at POR Bit1: PA9 input value on VDD33 latched at POR Bit0: PA8 input value on VDD33 latched at POR.

CR5

CR5 register

Offset: 0x1c, size: 32, reset: 0x00006014, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SMPS_PRECH_CUR_SEL rw		CLKDETR_DISABLE rw	SMPS_ENA_DCM rw	NOSMPS rw	SMPSFBYP rw	SMPSLPOPEN rw	SMPSFRDY rw		SMPSBOMSEL rw		SMPSLVL rw

Toggle fields

SMPSLVL

Bits 0-3: SMPSLVL[3:0] SMPS Output Level Voltage Selection Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) Vout = 1.2 + 0.05*SMPSOUT (V).

SMPSBOMSEL

Bits 4-5: SMPSBOMSEL: SMPS BOM Selection:.

SMPSFRDY

Bit 7: SMPSFB Force ready check When this bit is set, the SMPS FSM will consider the SMPS ready ..

SMPSLPOPEN

Bit 8: SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed..

SMPSFBYP

Bit 9: SMPSFB Force SMPS Regulator in bypass mode When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR..

NOSMPS

Bit 10: NOSMPS: No SMPS Mode When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM..

SMPS_ENA_DCM

Bit 11: SMPS_ENA_DCM: enable discontinuous conduction mode.

CLKDETR_DISABLE

Bit 12: CLKDETR_DISABLE: disable SMPS clock detection The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock..

SMPS_PRECH_CUR_SEL

Bits 13-14: SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current.

PUCRA

PUCRA register

Offset: 0x20, size: 32, reset: 0x00000F07, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU rw

Toggle fields

PU

Bits 0-15: PU[x] : Pull Up Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set.

PDCRA

PDCRA register

Offset: 0x24, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD rw

Toggle fields

PD

Bits 0-15: PD[x]: Pull Down Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set.

PUCRB

PUCRB register

Offset: 0x28, size: 32, reset: 0x0000F0FF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU rw

Toggle fields

PU

Bits 0-15: PU[x] : Pull Up Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set.

PDCRB

PDCRB register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD rw

Toggle fields

PD

Bits 0-15: PD[x]: Pull Down Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set.

CR6

CR6 register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EWU19 rw	EWU18 rw	EWU17 rw	EWU16 rw	EWU15 rw	EWU14 rw	EWU13 rw	EWU12 rw

Toggle fields

EWU12

Bit 0: EWU12 Enable WakeUp line 12 (PA0) When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit..

EWU13

Bit 1: EWU13 Enable WakeUp line 13 (PA1) When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit..

EWU14

Bit 2: EWU14 Enable WakeUp line 14 (PA2) When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit..

EWU15

Bit 3: EWU15 Enable WakeUp line 15 (PA3) When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit..

EWU16

Bit 4: EWU16 Enable WakeUp line 16 (PB12) When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit..

EWU17

Bit 5: EWU17 Enable WakeUp line 17 (PB13) When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit..

EWU18

Bit 6: EWU18 Enable WakeUp line 18 (PB14) When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit..

EWU19

Bit 7: EWU19 Enable WakeUp line 19 (PB15) When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit..

CR7

CR7 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUP19 rw	WUP18 rw	WUP17 rw	WUP16 rw	WUP15 rw	WUP14 rw	WUP13 rw	WUP12 rw

Toggle fields

WUP12

Bit 0: WUP12 Wake-up Line Polarity 12 (PA0) This bit defines the polarity used for event detection on external wake-up line 12.

WUP13

Bit 1: WUP13 Wake-up Line Polarity 13 (PA1) This bit defines the polarity used for event detection on external wake-up line 13.

WUP14

Bit 2: WUP14 Wake-up Line Polarity 14 (PA2) This bit defines the polarity used for event detection on external wake-up line 14.

WUP15

Bit 3: WUP15 Wake-up Line Polarity 15 (PA3) This bit defines the polarity used for event detection on external wake-up line 15.

WUP16

Bit 4: WUP16 Wake-up Line Polarity 16 (PB12) This bit defines the polarity used for event detection on external wake-up line 16.

WUP17

Bit 5: WUP17 Wake-up Line Polarity 17 (PB13) This bit defines the polarity used for event detection on external wake-up line 17.

WUP18

Bit 6: WUP18 Wake-up Line Polarity 18 (PB14) This bit defines the polarity used for event detection on external wake-up line 18.

WUP19

Bit 7: WUP19 Wake-up Line Polarity 19 (PB15) This bit defines the polarity used for event detection on external wake-up line 19.

SR3

SR3 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WUF19 rw	WUF18 rw	WUF17 rw	WUF16 rw	WUF15 rw	WUF14 rw	WUF13 rw	WUF12 rw

Toggle fields

WUF12

Bit 0: WUF12 WakeUp Flag 12 PA0 This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF13

Bit 1: WUF13 WakeUp Flag 13 PA1 This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF14

Bit 2: WUF14 WakeUp Flag 14 PA2 This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF15

Bit 3: WUF15 WakeUp Flag 15 PA3 This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF16

Bit 4: WUF16 WakeUp Flag 16 PB12 This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF17

Bit 5: WUF17 WakeUp Flag 17 PB13 This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF18

Bit 6: WUF18 WakeUp Flag 18 PB14 This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

WUF19

Bit 7: WUF19 WakeUp Flag 19 PB15 This bit is set when a wakeup is detected on wakeup line 19. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:.

DBGR

DBGR register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIS_PRECH rw															DEEPSTOP2 rw

Toggle fields

DEEPSTOP2

Bit 0: DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. 0: normal DEEPSTOP will be applied 1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP..

DIS_PRECH

Bits 13-15: DIS_PRECH[2:0]: disable precharge during deepstop (debug) 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) else: No effect (default 0x0).

EXTSRR

EXTSRR register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					RFPHASEF rw	DEEPSTOPF rw

Toggle fields

DEEPSTOPF

Bit 9: DEEPSTOPF System DeepStop Flag This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field.

RFPHASEF

Bit 10: RFPHASEF RFPHASE Flag This bit is set by hardware after a Radio wake-up event (BLE activation); it is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP..

RADIO

0x60001500:

20/99 fields covered.

Toggle register map

Offset	Name	7	6	5	4	3	2	1	0
0x0	AA0_DIG_USR	AA_7_0
0x4	AA1_DIG_USR	AA_15_8
0x8	AA2_DIG_USR	AA_23_16
0xc	AA3_DIG_USR	AA_31_24
0x10	DEM_MOD_DIG_USR	CHANNEL_NUM
0x14	FSM_USR	PA_POWER					EN_CALIB_SYNTH	EN_CALIB_CBP
0x18	PHYCTRL_DIG_USR						RXTXPHY
0x48	AFC1_DIG_ENG	AFC_DELAY_BEFORE				AFC_DELAY_AFTER
0x54	CR0_DIG_ENG	CR_GAIN_BEFORE				CR_GAIN_AFTER
0x68	CR0_LR	CR_LR_GAIN_BEFORE				CR_LR_GAIN_AFTER
0x6c	VIT_CONF_DIG_ENG	SPARE							VIT_EN
0x84	LR_PD_THR_DIG_ENG	LR_PD_THR
0x88	LR_RSSI_THR_DIG_ENG	LR_RSSI_THR
0x8c	LR_AAC_THR_DIG_ENG	LR_AAC_THR
0xa8	SYNTHCAL0_DIG_ENG	SYNTH_IF_FREQ_CAL				SYNTHCAL_DEBUG_BUS_SEL
0xf0	DTB5_DIG_ENG			PORT_SELECTED_0	PORT_SELECTED_EN	INITIALIZE	RX_ACTIVE	TX_ACTIVE	RXTX_START_SEL
0x148	RXADC_ANA_USR	RXADC_DELAYTRIM_Q_TST_SEL	RXADC_DELAYTRIM_I_TST_SEL	RFD_RXADC_DELAYTRIM_Q			RFD_RXADC_DELAYTRIM_I
0x154	LDO_ANA_ENG								RFD_RF_REG_BYPASS
0x174	CBIAS0_ANA_ENG	RFD_CBIAS_IPTAT_TRIM				RFD_CBIAS_IBIAS_TRIM
0x178	CBIAS1_ANA_ENG	CBIAS0_TRIM_TST_SEL
0x180	SYNTHCAL0_DIG_OUT		VCO_CALAMP_OUT_6_0
0x184	SYNTHCAL1_DIG_OUT					VCO_CALAMP_OUT_10_7
0x188	SYNTHCAL2_DIG_OUT		VCO_CALFREQ_OUT
0x18c	SYNTHCAL3_DIG_OUT	SYNTHCAL_DEBUG_BUS
0x190	SYNTHCAL4_DIG_OUT			MOD_REF_DAC_WORD_OUT
0x194	SYNTHCAL5_DIG_OUT					CBP_CALIB_WORD
0x198	FSM_STATUS_DIG_OUT	SYNTH_CAL_ERROR			STATUS
0x1a4	RSSI0_DIG_OUT	RSSI_MEAS_OUT_7_0
0x1a8	RSSI1_DIG_OUT	RSSI_MEAS_OUT_15_8
0x1ac	AGC_DIG_OUT					AGC_ATT_OUT
0x1b0	DEMOD_DIG_OUT				RX_END	PD_FOUND	AAC_FOUND	CI_FIELD
0x1bc	AGC2_ANA_TST					AGC_ANTENNAE_USR_TRIM			AGC2_ANA_TST_SEL
0x1c0	AGC0_DIG_ENG		AGC_ENABLE	AGC_THR_HIGH
0x1c4	AGC1_DIG_ENG	AGC_LOCK_SYNC	AGC_AUTOLOCK	AGC_THR_LOW_6
0x1e8	AGC10_DIG_ENG			ATT_ANT_0		ATT_LNA_0	ATT_IF_0
0x1ec	AGC11_DIG_ENG			ATT_ANT_1		ATT_LNA_1	ATT_IF_1
0x1f0	AGC12_DIG_ENG			ATT_ANT_2		ATT_LNA_2	ATT_IF_2
0x1f4	AGC13_DIG_ENG			ATT_ANT_3		ATT_LNA_3	ATT_IF_3
0x1f8	AGC14_DIG_ENG			ATT_ANT_4		ATT_LNA_4	ATT_IF_4
0x1fc	AGC15_DIG_ENG			ATT_ANT_5		ATT_LNA_5	ATT_IF_5
0x200	AGC16_DIG_ENG			ATT_ANT_6		ATT_LNA_6	ATT_IF_6
0x204	AGC17_DIG_ENG			ATT_ANT_7		ATT_LNA_7	ATT_IF_7
0x208	AGC18_DIG_ENG			ATT_ANT_8		ATT_LNA_8	ATT_IF_8
0x20c	AGC19_DIG_ENG			ATT_ANT_9		ATT_LNA_9	ATT_IF_9
0x224	RXADC_HW_TRIM_OUT			HW_RXADC_DELAYTRIM_Q			HW_RXADC_DELAYTRIM_I
0x228	CBIAS0_HW_TRIM_OUT	HW_CBIAS_IPTAT_TRIM				HW_CBIAS_IBIAS_TRIM
0x230	AGC_HW_TRIM_OUT					HW_AGC_ANTENNAE_TRIM
0x23c	DEMOD_IQ2_DIG_TST					EXTCFG_TRIG_SELECTION		EXTCFG_SAMPLING_TIME
0x240	ANTSW0_DIG_USR		RX_TIME_TO_SAMPLE
0x244	ANTSW1_DIG_USR			RX_TIME_TO_SWITCH
0x248	ANTSW2_DIG_USR		TX_TIME_TO_SWITCH
0x24c	ANTSW3_DIG_USR		TX_TIME_TO_SWITCH_2M

Toggle registers

AA0_DIG_USR

AA0_DIG_USR register

Offset: 0x0, size: 32, reset: 0x000000D6, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_7_0 rw

Toggle fields

AA_7_0

Bits 0-7: Least significant byte of the Bluetooth LE Access Address code.

AA1_DIG_USR

AA1_DIG_USR register

Offset: 0x4, size: 32, reset: 0x000000BE, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_15_8 rw

Toggle fields

AA_15_8

Bits 0-7: Next byte of the Bluetooth LE Access Address code..

AA2_DIG_USR

AA2_DIG_USR register

Offset: 0x8, size: 32, reset: 0x00000089, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_23_16 rw

Toggle fields

AA_23_16

Bits 0-7: Next byte of the Bluetooth LE Access Address code.

AA3_DIG_USR

AA3_DIG_USR register

Offset: 0xc, size: 32, reset: 0x0000008E, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AA_31_24 rw

Toggle fields

AA_31_24

Bits 0-7: Most significant byte of the Bluetooth LE Access Address code..

DEM_MOD_DIG_USR

DEM_MOD_DIG_USR register

Offset: 0x10, size: 32, reset: 0x00000026, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CHANNEL_NUM rw

Toggle fields

CHANNEL_NUM

Bits 1-7: Index for internal lock up table in which the synthesizer setup is contained..

FSM_USR

RADIO_FSM_USR register

Offset: 0x14, size: 32, reset: 0x00000004, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PA_POWER rw					EN_CALIB_SYNTH rw	EN_CALIB_CBP rw

Toggle fields

EN_CALIB_CBP

Bit 1: CBP calibration enable bit..

EN_CALIB_SYNTH

Bit 2: SYNTH calibration enable bit..

PA_POWER

Bits 3-7: PA Power coefficient..

PHYCTRL_DIG_USR

PHYCTRL_DIG_USR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													RXTXPHY rw

Toggle fields

RXTXPHY

Bits 0-2: RXTXPHY selection..

AFC1_DIG_ENG

AFC1_DIG_ENG register

Offset: 0x48, size: 32, reset: 0x00000044, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AFC_DELAY_BEFORE rw				AFC_DELAY_AFTER rw

Toggle fields

AFC_DELAY_AFTER

Bits 0-3: Set the decay factor of the AFC loop after Access Address detection.

AFC_DELAY_BEFORE

Bits 4-7: Set the decay factor of the AFC loop before Access Address detection.

CR0_DIG_ENG

CR0_DIG_ENG register

Offset: 0x54, size: 32, reset: 0x00000044, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CR_GAIN_BEFORE rw				CR_GAIN_AFTER rw

Toggle fields

CR_GAIN_AFTER

Bits 0-3: Set the gain of the clock recovery loop before Access Address detection to the value.

CR_GAIN_BEFORE

Bits 4-7: Set the gain of the clock recovery loop before Access Address detection to the value.

CR0_LR

CR0_LR register

Offset: 0x68, size: 32, reset: 0x00000066, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CR_LR_GAIN_BEFORE rw				CR_LR_GAIN_AFTER rw

Toggle fields

CR_LR_GAIN_AFTER

Bits 0-3: Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use.

CR_LR_GAIN_BEFORE

Bits 4-7: Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use.

VIT_CONF_DIG_ENG

VIT_CONF_DIG_ENG register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SPARE rw							VIT_EN rw

Toggle fields

VIT_EN

Bit 0: Viterbi enable.

SPARE

Bits 2-7: spare.

LR_PD_THR_DIG_ENG

LR_PD_THR_DIG_ENG register

Offset: 0x84, size: 32, reset: 0x00000050, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LR_PD_THR rw

Toggle fields

LR_PD_THR

Bits 0-7: preamble detect threshold value.

LR_RSSI_THR_DIG_ENG

LR_RSSI_THR_DIG_ENG register

Offset: 0x88, size: 32, reset: 0x0000001B, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LR_RSSI_THR rw

Toggle fields

LR_RSSI_THR

Bits 0-7: RSSI or peak threshold value.

LR_AAC_THR_DIG_ENG

LR_AAC_THR_DIG_ENG register

Offset: 0x8c, size: 32, reset: 0x00000038, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LR_AAC_THR rw

Toggle fields

LR_AAC_THR

Bits 0-7: address coded correlation threshold.

SYNTHCAL0_DIG_ENG

SYNTHCAL0_DIG_ENG register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTH_IF_FREQ_CAL rw				SYNTHCAL_DEBUG_BUS_SEL rw

Toggle fields

SYNTHCAL_DEBUG_BUS_SEL

Bits 0-3: for Debug purpose.

SYNTH_IF_FREQ_CAL

Bits 6-7: Define the frequency applied on the PLL during calibration phase.

DTB5_DIG_ENG

DTB5_DIG_ENG register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										PORT_SELECTED_0 rw	PORT_SELECTED_EN rw	INITIALIZE rw	RX_ACTIVE rw	TX_ACTIVE rw	RXTX_START_SEL rw

Toggle fields

RXTX_START_SEL

Bit 0: enable the possibility to control some signals by the other register bits instead of system design:.

TX_ACTIVE

Bit 1: Force TX_ACTIVE signal.

RX_ACTIVE

Bit 2: Force RX_ACTIVE signal.

INITIALIZE

Bit 3: Force INITIALIZE signal (emulate a token request of the IP_BLE).

PORT_SELECTED_EN

Bit 4: enable port selection.

PORT_SELECTED_0

Bit 5: force port_selected[0] signal.

RXADC_ANA_USR

RXADC_ANA_USR register

Offset: 0x148, size: 32, reset: 0x0000001B, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXADC_DELAYTRIM_Q_TST_SEL rw	RXADC_DELAYTRIM_I_TST_SEL rw	RFD_RXADC_DELAYTRIM_Q rw			RFD_RXADC_DELAYTRIM_I rw

Toggle fields

RFD_RXADC_DELAYTRIM_I

Bits 0-2: ADC loop delay control bits for I channel to apply when SW overload is enabled.

RFD_RXADC_DELAYTRIM_Q

Bits 3-5: ADC loop delay control bits for Q channel to apply when SW overload is enabled.

RXADC_DELAYTRIM_I_TST_SEL

Bit 6: Enable the SW overload on RXADX delay trimming.

RXADC_DELAYTRIM_Q_TST_SEL

Bit 7: Enable the SW overload on RXADX delay trimming.

LDO_ANA_ENG

LDO_ANA_ENG register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RFD_RF_REG_BYPASS rw

Toggle fields

RFD_RF_REG_BYPASS

Bit 0: RF_REG Bypass mode:.

CBIAS0_ANA_ENG

CBIAS0_ANA_ENG register

Offset: 0x174, size: 32, reset: 0x00000088, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RFD_CBIAS_IPTAT_TRIM rw				RFD_CBIAS_IBIAS_TRIM rw

Toggle fields

RFD_CBIAS_IBIAS_TRIM

Bits 0-3: overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1).

RFD_CBIAS_IPTAT_TRIM

Bits 4-7: overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1).

CBIAS1_ANA_ENG

CBIAS1_ANA_ENG register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CBIAS0_TRIM_TST_SEL rw

Toggle fields

CBIAS0_TRIM_TST_SEL

Bit 7: When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings.

SYNTHCAL0_DIG_OUT

SYNTHCAL0_DIG_OUT register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VCO_CALAMP_OUT_6_0 r

Toggle fields

VCO_CALAMP_OUT_6_0

Bits 0-6: VCO CALAMP value.

SYNTHCAL1_DIG_OUT

SYNTHCAL1_DIG_OUT register

Offset: 0x184, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VCO_CALAMP_OUT_10_7 r

Toggle fields

VCO_CALAMP_OUT_10_7

Bits 0-3: VCO CALAMP value.

SYNTHCAL2_DIG_OUT

SYNTHCAL2_DIG_OUT register

Offset: 0x188, size: 32, reset: 0x00000040, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									VCO_CALFREQ_OUT r

Toggle fields

VCO_CALFREQ_OUT

Bits 0-6: VCO CALFREQ value.

SYNTHCAL3_DIG_OUT

SYNTHCAL3_DIG_OUT register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTHCAL_DEBUG_BUS r

Toggle fields

SYNTHCAL_DEBUG_BUS

Bits 0-7: Calibration debug bus..

SYNTHCAL4_DIG_OUT

SYNTHCAL4_DIG_OUT register

Offset: 0x190, size: 32, reset: 0x00000018, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										MOD_REF_DAC_WORD_OUT r

Toggle fields

MOD_REF_DAC_WORD_OUT

Bits 0-5: Calibration word.

SYNTHCAL5_DIG_OUT

SYNTHCAL5_DIG_OUT register

Offset: 0x194, size: 32, reset: 0x00000007, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CBP_CALIB_WORD r

Toggle fields

CBP_CALIB_WORD

Bits 0-3: CBP Calibration word.

FSM_STATUS_DIG_OUT

FSM_STATUS_DIG_OUT register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTH_CAL_ERROR r			STATUS r

Toggle fields

STATUS

Bits 0-4: RF FSM state:.

SYNTH_CAL_ERROR

Bit 7: PLL calibration error.

RSSI0_DIG_OUT

RSSI0_DIG_OUT register

Offset: 0x1a4, size: 32, reset: 0x00000008, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RSSI_MEAS_OUT_7_0 r

Toggle fields

RSSI_MEAS_OUT_7_0

Bits 0-7: Measure of the received signal strength..

RSSI1_DIG_OUT

RSSI1_DIG_OUT register

Offset: 0x1a8, size: 32, reset: 0x00000008, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RSSI_MEAS_OUT_15_8 r

Toggle fields

RSSI_MEAS_OUT_15_8

Bits 0-7: Measure of the received signal strength.

AGC_DIG_OUT

AGC_DIG_OUT register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_ATT_OUT r

Toggle fields

AGC_ATT_OUT

Bits 0-3: AGC attenuation value.

DEMOD_DIG_OUT

DEMOD_DIG_OUT register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RX_END r	PD_FOUND r	AAC_FOUND r	CI_FIELD r

Toggle fields

CI_FIELD

Bits 0-1: CI field.

AAC_FOUND

Bit 2: aac_found.

PD_FOUND

Bit 3: pd_found.

RX_END

Bit 4: rx_end.

AGC2_ANA_TST

AGC2_ANA_TST register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_ANTENNAE_USR_TRIM rw			AGC2_ANA_TST_SEL rw

Toggle fields

AGC2_ANA_TST_SEL

Bit 0: Selection:.

AGC_ANTENNAE_USR_TRIM

Bits 1-3: the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1).

AGC0_DIG_ENG

AGC0_DIG_ENG register

Offset: 0x1c0, size: 32, reset: 0x0000004A, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									AGC_ENABLE rw	AGC_THR_HIGH rw

Toggle fields

AGC_THR_HIGH

Bits 0-5: High AGC threshold.

AGC_ENABLE

Bit 6: Enable AGC.

AGC1_DIG_ENG

AGC1_DIG_ENG register

Offset: 0x1c4, size: 32, reset: 0x00000084, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AGC_LOCK_SYNC rw	AGC_AUTOLOCK rw	AGC_THR_LOW_6 rw

Toggle fields

AGC_THR_LOW_6

Bits 0-5: Low threshold for 6dB steps.

AGC_AUTOLOCK

Bit 6: AGC locks when level is steady between high threshold and lock threshold.

AGC_LOCK_SYNC

Bit 7: AGC locks when Access Address is detected (recommended).

AGC10_DIG_ENG

AGC10_DIG_ENG register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_0 rw		ATT_LNA_0 rw	ATT_IF_0 rw

Toggle fields

ATT_IF_0

Bits 0-2: Attenuation at IF Level for the AGC step 0:.

ATT_LNA_0

Bit 3: Attenuation at LNA Level for the AGC step 0:.

ATT_ANT_0

Bits 4-5: Attenuation at Antenna Level for the AGC step 0:.

AGC11_DIG_ENG

AGC11_DIG_ENG register

Offset: 0x1ec, size: 32, reset: 0x00000010, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_1 rw		ATT_LNA_1 rw	ATT_IF_1 rw

Toggle fields

ATT_IF_1

Bits 0-2: Attenuation at IF Level for the AGC step 1.

ATT_LNA_1

Bit 3: Attenuation at LNA Level for the AGC step 1.

ATT_ANT_1

Bits 4-5: Attenuation at Antenna Level for the AGC step 1.

AGC12_DIG_ENG

AGC12_DIG_ENG register

Offset: 0x1f0, size: 32, reset: 0x00000020, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_2 rw		ATT_LNA_2 rw	ATT_IF_2 rw

Toggle fields

ATT_IF_2

Bits 0-2: Attenuation at IF Level for the AGC step 2.

ATT_LNA_2

Bit 3: Attenuation at LNA Level for the AGC step 2.

ATT_ANT_2

Bits 4-5: Attenuation at Antenna Level for the AGC step 2.

AGC13_DIG_ENG

AGC13_DIG_ENG register

Offset: 0x1f4, size: 32, reset: 0x00000030, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_3 rw		ATT_LNA_3 rw	ATT_IF_3 rw

Toggle fields

ATT_IF_3

Bits 0-2: Attenuation at IF Level for the AGC step 3.

ATT_LNA_3

Bit 3: Attenuation at LNA Level for the AGC step 3.

ATT_ANT_3

Bits 4-5: Attenuation at Antenna Level for the AGC step 3.

AGC14_DIG_ENG

AGC14_DIG_ENG register

Offset: 0x1f8, size: 32, reset: 0x00000038, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_4 rw		ATT_LNA_4 rw	ATT_IF_4 rw

Toggle fields

ATT_IF_4

Bits 0-2: Attenuation at IF Level for the AGC step 4.

ATT_LNA_4

Bit 3: Attenuation at LNA Level for the AGC step 4.

ATT_ANT_4

Bits 4-5: Attenuation at Antenna Level for the AGC step 4.

AGC15_DIG_ENG

AGC15_DIG_ENG register

Offset: 0x1fc, size: 32, reset: 0x00000039, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_5 rw		ATT_LNA_5 rw	ATT_IF_5 rw

Toggle fields

ATT_IF_5

Bits 0-2: Attenuation at IF Level for the AGC step 5.

ATT_LNA_5

Bit 3: Attenuation at LNA Level for the AGC step 5.

ATT_ANT_5

Bits 4-5: Attenuation at Antenna Level for the AGC step 5.

AGC16_DIG_ENG

AGC16_DIG_ENG register

Offset: 0x200, size: 32, reset: 0x0000003A, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_6 rw		ATT_LNA_6 rw	ATT_IF_6 rw

Toggle fields

ATT_IF_6

Bits 0-2: Attenuation at IF Level for the AGC step 6.

ATT_LNA_6

Bit 3: Attenuation at LNA Level for the AGC step 6.

ATT_ANT_6

Bits 4-5: Attenuation at Antenna Level for the AGC step 6.

AGC17_DIG_ENG

AGC17_DIG_ENG register

Offset: 0x204, size: 32, reset: 0x0000003B, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_7 rw		ATT_LNA_7 rw	ATT_IF_7 rw

Toggle fields

ATT_IF_7

Bits 0-2: Attenuation at IF Level for the AGC step 7.

ATT_LNA_7

Bit 3: Attenuation at LNA Level for the AGC step 7.

ATT_ANT_7

Bits 4-5: Attenuation at Antenna Level for the AGC step 7.

AGC18_DIG_ENG

AGC18_DIG_ENG register

Offset: 0x208, size: 32, reset: 0x0000003C, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_8 rw		ATT_LNA_8 rw	ATT_IF_8 rw

Toggle fields

ATT_IF_8

Bits 0-2: Attenuation at IF Level for the AGC step 8.

ATT_LNA_8

Bit 3: Attenuation at LNA Level for the AGC step 8.

ATT_ANT_8

Bits 4-5: Attenuation at Antenna Level for the AGC step 8.

AGC19_DIG_ENG

AGC19_DIG_ENG register

Offset: 0x20c, size: 32, reset: 0x0000003D, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										ATT_ANT_9 rw		ATT_LNA_9 rw	ATT_IF_9 rw

Toggle fields

ATT_IF_9

Bits 0-2: Attenuation at IF Level for the AGC step 9.

ATT_LNA_9

Bit 3: Attenuation at LNA Level for the AGC step 9.

ATT_ANT_9

Bits 4-5: Attenuation at Antenna Level for the AGC step 9.

RXADC_HW_TRIM_OUT

RXADC_HW_TRIM_OUT register

Offset: 0x224, size: 32, reset: 0x0000001B, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										HW_RXADC_DELAYTRIM_Q r			HW_RXADC_DELAYTRIM_I r

Toggle fields

HW_RXADC_DELAYTRIM_I

Bits 0-2: control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR)..

HW_RXADC_DELAYTRIM_Q

Bits 3-5: control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR)..

CBIAS0_HW_TRIM_OUT

CBIAS0_HW_TRIM_OUT register

Offset: 0x228, size: 32, reset: 0x00000088, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								HW_CBIAS_IPTAT_TRIM r				HW_CBIAS_IBIAS_TRIM r

Toggle fields

HW_CBIAS_IBIAS_TRIM

Bits 0-3: CBIAS current (provided by the HW trimming, automatically loaded on POR)..

HW_CBIAS_IPTAT_TRIM

Bits 4-7: CBIAS current (provided by the HW trimming, automatically loaded on POR)..

AGC_HW_TRIM_OUT

AGC_HW_TRIM_OUT register

Offset: 0x230, size: 32, reset: 0x00000006, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												HW_AGC_ANTENNAE_TRIM r

Toggle fields

HW_AGC_ANTENNAE_TRIM

Bits 1-3: AGC trim value (provided by the HW trimming, automatically loaded on POR)..

DEMOD_IQ2_DIG_TST

DEMOD_IQ2_DIG_TST register

Offset: 0x23c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EXTCFG_TRIG_SELECTION rw		EXTCFG_SAMPLING_TIME rw

Toggle fields

EXTCFG_SAMPLING_TIME

Bits 0-1: Defines the sampling time, when extended configuration is enabled:.

EXTCFG_TRIG_SELECTION

Bits 2-3: Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled:.

ANTSW0_DIG_USR

ANTSW0_DIG_USR register

Offset: 0x240, size: 32, reset: 0x0000001C, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									RX_TIME_TO_SAMPLE rw

Toggle fields

RX_TIME_TO_SAMPLE

Bits 0-6: specifies the exact timing of the first I/Q sampling in the reference period..

ANTSW1_DIG_USR

ANTSW1_DIG_USR register

Offset: 0x244, size: 32, reset: 0x0000000B, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RX_TIME_TO_SWITCH rw

Toggle fields

RX_TIME_TO_SWITCH

Bits 0-5: specifies the exact timing of the antenna switching at receiver level (in AoA)..

ANTSW2_DIG_USR

ANTSW2_DIG_USR register

Offset: 0x248, size: 32, reset: 0x00000029, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TX_TIME_TO_SWITCH rw

Toggle fields

TX_TIME_TO_SWITCH

Bits 0-6: specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD)..

ANTSW3_DIG_USR

ANTSW3_DIG_USR register

Offset: 0x24c, size: 32, reset: 0x00000023, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TX_TIME_TO_SWITCH_2M rw

Toggle fields

TX_TIME_TO_SWITCH_2M

Bits 0-6: specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD)..

RADIO_CONTROL

0x60001000:

5/10 fields covered.

Toggle register map

Offset	Name	26	18	15	13	11	8	7	0
0x0	ID			PRODUCT		VERSION		REVISION
0x4	CLK32COUNT_REG						SLOW_COUNT
0x8	CLK32PERIOD_REG		SLOW_PERIOD	SLOW_PERIOD
0xc	CLK32FREQUENCY_REG	SLOW_FREQUENCY		SLOW_FREQUENCY
0x10	IRQ_STATUS				RADIO_FSM_IRQ				SLOW_CLK_IRQ
0x14	IRQ_ENABLE				RADIO_FSM_IRQ_MASK				SLOW_CLK_IRQ_MASK

Toggle registers

ID

RADIO_CONTROL_ID register

Offset: 0x0, size: 32, reset: 0x00003000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRODUCT r				VERSION r				REVISION r

Toggle fields

REVISION

Bits 4-7: Incremented for metal fix version.

VERSION

Bits 8-11: Cut Number.

PRODUCT

Bits 12-15: incremented on major features add-on like new Bluetooth LE SIG version support.

CLK32COUNT_REG

CLK32COUNT_REG register

Offset: 0x4, size: 32, reset: 0x00000017, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SLOW_COUNT rw

Toggle fields

SLOW_COUNT

Bits 0-8: program the window length (in slow clock period) for slow clock measurement..

CLK32PERIOD_REG

CLK32PERIOD_REG register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SLOW_PERIOD r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SLOW_PERIOD r

Toggle fields

SLOW_PERIOD

Bits 0-18: indicates slow clock period information..

CLK32FREQUENCY_REG

CLK32FREQUENCY_REG register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SLOW_FREQUENCY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SLOW_FREQUENCY r

Toggle fields

SLOW_FREQUENCY

Bits 0-26: value equal to (2^39/ SLOW_PERIOD)..

IRQ_STATUS

RADIO_CONTROL_IRQ_STATUS register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RADIO_FSM_IRQ rw													SLOW_CLK_IRQ rw

Toggle fields

SLOW_CLK_IRQ

Bit 0: slow clock measurement end of calculation interrupt status.

RADIO_FSM_IRQ

Bits 8-13: Radio FSM interrupt status (aka RfFsm_event_irq)..

IRQ_ENABLE

RADIO_CONTROL_IRQ_ENABLE register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		RADIO_FSM_IRQ_MASK rw													SLOW_CLK_IRQ_MASK rw

Toggle fields

SLOW_CLK_IRQ_MASK

Bit 0: mask slow clock measurement interrupt.

RADIO_FSM_IRQ_MASK

Bits 8-13: mask for each RfFsm_event (Radio FSM) interrupt..

RCC

0x48400000:

14/101 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	21	19	18	17	16	15	14	13	12	10	9	8	7	6	5	4	3	2	1	0
0x0	CR												HSERDY	HSEON	FMRAT	HSIPLLRDY	HSIPLLON	HSEPLLBUFON	HSIRDY	LOCKDET_NSTOP			LSEBYP	LSERDY	LSEON	LSIRDY	LSION
0x8	CFGR	CCOPRE			MCOSEL			LCOSEL	SPI3I2SCLKSEL		LCOEN	IOBOOSTCLKEXTEN	IOBOOSTEN	CLKSLOWSEL	CLKSLOWSEL		LPUCLKSEL	SMPSDIV	CLKSYSDIV_STATUS			CLKSYSDIV				HSESEL_STATUS	STOPHSI	HSESEL	SMPSINV
0x18	CIER																			LPURSTIE	WDGRSTIE	RTCRSTIE	HSIPLLUNLOCKDETIE	HSIPLLRDYIE	HSERDYIE	HSIRDYIE		LSERDYIE	LSIRDYIE
0x1c	CIFR																			LPURSTF	WDGRSTIF	RTCRSTIF	HSIPLLUNLOCKDETIF	HSIPLLRDYIF	HSERDYIF	HSIRDYIF		LSERDYIF	LSIRDYIF
0x20	CSCMDR																					EOFSEQ_IRQ	EOFSEQ_IE	STATUS		CLKSYSDIV_REQ			REQUEST
0x30	AHBRSTR											RNGRST		PKARST				CRCRST								GPIOBRST	GPIOARST		DMARST
0x34	APB0RSTR															WDRST		RTCRST			SYSCFGRST						TIM17RST	TIM16RST	TIM1RST
0x38	APB1RSTR									I2C21RST						SPI3RST			USARTRST		LPUARTRST				AUXADCRST
0x40	APB2RSTR																												BLERST
0x50	AHBENR											RNGEN		PKAEN				CRCEN								GPIOBEN	GPIOAEN		DMAEN
0x54	APB0ENR															WDGEN		RTCEN			SYSCFGEN						TIM17EN	TIM16EN	TIM2EN
0x58	APB1ENR									I2C1EN						SPI3EN			USART1EN		LPUARTEN			ADCANAEN	ADCDIGEN
0x60	APB2ENR																										CLKBLEDIV		MRBLEEN
0x94	CSR		LOCKUPRSTF	WDGRSTF	SFTRSTF	PORRSTF	PADRSTF		RMVF
0x98	RFSWHSECR																SWXOTUNE					SWXOTUNEEN	GMC			SATRG
0x9c	RFHSECR																							XOTUNE

Toggle registers

CR

CR register

Offset: 0x0, size: 32, reset: 0x00001400, access: read-write

5/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FMRAT rw	HSIPLLRDY r	HSIPLLON rw	HSEPLLBUFON rw		HSIRDY r	LOCKDET_NSTOP rw			LSEBYP rw	LSERDY r	LSEON rw	LSIRDY r	LSION rw

Toggle fields

LSION

Bit 2: Internal Low Speed oscillator enable Set and reset by software. Reset source only for this field: PORESETn.

LSIRDY

Bit 3: Internal Low Speed oscillator Ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. Reset source only for this field: PORESETn.

LSEON

Bit 4: External Low Speed Clock enable. Set and reset by software. Reset source only for this field: PORESETn.

LSERDY

Bit 5: External Low Speed Clock ready flag. Set by hardware to indicate that LSE oscillator is stable..

LSEBYP

Bit 6: External Low Speed Clock bypass. Set and reset by software. Reset source only for this field: PORESETn.

LOCKDET_NSTOP

Bits 7-9: Lock detector Nstop value When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0..

HSIRDY

Bit 10: Internal High Speed clock ready flag. Set by hardware to indicate that internal RC 64MHz oscillator is stable. This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request)..

HSEPLLBUFON

Bit 12: External High Speed Clock Buffer for PLL RF2G4 enable. Set and reset by software..

HSIPLLON

Bit 13: Internal High Speed Clock PLL enable.

HSIPLLRDY

Bit 14: Internal High Speed Clock PLL ready flag..

FMRAT

Bit 15: Force MR_BLE active transmission status (for debug purpose).

HSEON

Bit 16: External High Speed Clock enable. Set and reset by software. in low power mode, HSE is turned off..

HSERDY

Bit 17: External High Speed Clock ready flag. Set by hardware to indicate that HSE oscillator is stable..

CFGR

CFGR register

Offset: 0x8, size: 32, reset: 0x00000240, access: read-write

2/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCOPRE rw			MCOSEL rw			LCOSEL rw		SPI3I2SCLKSEL rw				LCOEN rw	IOBOOSTCLKEXTEN rw	IOBOOSTEN rw	CLKSLOWSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKSLOWSEL rw		LPUCLKSEL rw	SMPSDIV rw		CLKSYSDIV_STATUS r			CLKSYSDIV rw				HSESEL_STATUS r	STOPHSI rw	HSESEL rw	SMPSINV rw

Toggle fields

SMPSINV

Bit 0: bit to control inversion of the SMPS clock.

HSESEL

Bit 1: Clock source selection request:.

STOPHSI

Bit 2: Stop HSI clock source request.

HSESEL_STATUS

Bit 3: Clock source selection Status.

CLKSYSDIV

Bits 5-7: CLKSYSDIV: system clock divided factor from HSI_64M. 000: system clock frequency is 64 MHz (not available when HSESEL=1) 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz * 100: system clock frequency is 4 MHz * 101: system clock frequency is 2 MHz * 110: system clock frequency is 1 MHz * 111: not used. *: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. Warning: if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio..

CLKSYSDIV_STATUS

Bits 8-10: CLKSYSDIV_STATUS: system clock frequency status Set and cleared by hardware to indicate the actual system clock frequency. This register must be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. 000: system clock frequency is 64 MHz 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz 100: system clock frequency is 4 MHz 101: system clock frequency is 2 MHz 110: system clock frequency is 1 MHz 111: not used. The actual clock frequency switching can be delayed of up to 128 system clock cycles, depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied.

SMPSDIV

Bit 12: SMPS clock prescaling factor to generate 4MHz or 8MHz.

LPUCLKSEL

Bit 13: Selection of LPUART clock:.

CLKSLOWSEL

Bits 15-16: slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn.

IOBOOSTEN

Bit 17: IO BOOSTER enable Set and reset by software..

IOBOOSTCLKEXTEN

Bit 18: IO BOOSTER clock enable as external clock Set and reset by software..

LCOEN

Bit 19: LCO output enable.

SPI3I2SCLKSEL

Bits 22-23: Selection of I2S1 clock: 1x:64MHz peripheral clock.

LCOSEL

Bits 24-25: Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn.

MCOSEL

Bits 26-28: Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible..

CCOPRE

Bits 29-31: Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used.

CIER

CIER register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						LPURSTIE rw	WDGRSTIE rw	RTCRSTIE rw	HSIPLLUNLOCKDETIE rw	HSIPLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw		LSERDYIE rw	LSIRDYIE rw

Toggle fields

LSIRDYIE

Bit 0: LSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization..

LSERDYIE

Bit 1: LSE Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization..

HSIRDYIE

Bit 3: HSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization..

HSERDYIE

Bit 4: HSE Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization..

HSIPLLRDYIE

Bit 5: HSI PLL Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE..

HSIPLLUNLOCKDETIE

Bit 6: HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock..

RTCRSTIE

Bit 7: RTCRSTIE: RTC reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the RTC reset end..

WDGRSTIE

Bit 8: WDGRSTIE: Watchdog reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the watchdog reset end..

LPURSTIE

Bit 9: LPURSTIE: LPUART reset release interrupt enable..

CIFR

CIFR register

Offset: 0x1c, size: 32, reset: 0x00000008, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						LPURSTF rw	WDGRSTIF rw	RTCRSTIF rw	HSIPLLUNLOCKDETIF rw	HSIPLLRDYIF rw	HSERDYIF rw	HSIRDYIF rw		LSERDYIF rw	LSIRDYIF rw

Toggle fields

LSIRDYIF

Bit 0: LSI Ready Interrupt flag Set by hardware when LSI clock becomes stable..

LSERDYIF

Bit 1: LSE Ready Interrupt Flag. Set by hardware when LSE clock becomes stable..

HSIRDYIF

Bit 3: HSI Ready Interrupt Flag. Set by hardware when HSI becomes stable..

HSERDYIF

Bit 4: HSE Ready Interrupt Flag. Set by hardware when HSE becomes stable..

HSIPLLRDYIF

Bit 5: HSI PLL Ready Interrupt Flag. Set by hardware when HSI PLL 64MHz becomes stable..

HSIPLLUNLOCKDETIF

Bit 6: HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag..

RTCRSTIF

Bit 7: RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

WDGRSTIF

Bit 8: WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

LPURSTF

Bit 9: LPUART reset release flag.

CSCMDR

CSCMDR register

Offset: 0x20, size: 32, reset: 0x00000080, access: read-write

1/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EOFSEQ_IRQ rw	EOFSEQ_IE rw	STATUS r		CLKSYSDIV_REQ rw			REQUEST rw

Toggle fields

REQUEST

Bit 0: Request for system clock switching Cleared by hardware when system clock frequency switch is done.

CLKSYSDIV_REQ

Bits 1-3: system clock dividing factor from HSI_64M requested Note: behavior depends on BLEEN in APB2ENR register.

STATUS

Bits 4-5: Status of clock switch sequence.

EOFSEQ_IE

Bit 6: End of sequence Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the clock system switch..

EOFSEQ_IRQ

Bit 7: End of Sequence flag Set by hardware when clock system swtich is ended.

AHBRSTR

AHBRSTR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													RNGRST rw		PKARST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw									GPIOBRST rw	GPIOARST rw		DMARST rw

Toggle fields

DMARST

Bit 0: DMA and DMAMUX reset Set and reset by software..

GPIOARST

Bit 2: GPIOA reset Set and reset by software..

GPIOBRST

Bit 3: GPIOB reset Set and reset by software..

CRCRST

Bit 12: CRC reset Set and reset by software..

PKARST

Bit 16: PKA reset Set and reset by software..

RNGRST

Bit 18: RNG reset Set and reset by software..

APB0RSTR

APB0RSTR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WDRST rw		RTCRST rw				SYSCFGRST rw						TIM17RST rw	TIM16RST rw	TIM1RST rw

Toggle fields

TIM1RST

Bit 0: TIM1: Advanced Timer reset Set and reset by software..

TIM16RST

Bit 1: TIM16 reset.

TIM17RST

Bit 2: TIM17 reset.

SYSCFGRST

Bit 8: SYSTEM CONFIG reset Set and reset by software..

RTCRST

Bit 12: RTC reset Set and reset by software..

WDRST

Bit 14: WATCHDOG reset Set and reset by software..

APB1RSTR

APB1RSTR register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										I2C21RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3RST rw				USARTRST rw		LPUARTRST rw				AUXADCRST rw

Toggle fields

AUXADCRST

Bit 4: AUXADC reset for Aux-ADC digital clock Set and reset by software..

LPUARTRST

Bit 8: LPUART reset Set and reset by software..

USARTRST

Bit 10: USART reset Set and reset by software..

SPI3RST

Bit 14: SPI3 reset Set and reset by software..

I2C21RST

Bit 21: I2C1 reset Set and reset by software..

APB2RSTR

APB2RSTR register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															BLERST rw

Toggle fields

BLERST

Bit 0: BLE reset..

AHBENR

AHBENR register

Offset: 0x50, size: 32, reset: 0x0000000C, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													RNGEN rw		PKAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw									GPIOBEN rw	GPIOAEN rw		DMAEN rw

Toggle fields

DMAEN

Bit 0: DMA and DMAMUX enable Set and enable by software..

GPIOAEN

Bit 2: GPIOA enable. It must be enabled by default.

GPIOBEN

Bit 3: GPIOB enable. It must be enabled by default.

CRCEN

Bit 12: CRC enable Set and enable by software..

PKAEN

Bit 16: PKA clock enable Set and enable by software..

RNGEN

Bit 18: RNG clock enable Set and enable by software..

APB0ENR

APB0ENR register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WDGEN rw		RTCEN rw				SYSCFGEN rw						TIM17EN rw	TIM16EN rw	TIM2EN rw

Toggle fields

TIM2EN

Bit 0: TIM2: Advanced Timer clock enable Set and enable by software..

TIM16EN

Bit 1: TIM16 enable.

TIM17EN

Bit 2: TIM17 enable.

SYSCFGEN

Bit 8: SYSTEM CONFIG enable Set and enable by software..

RTCEN

Bit 12: RTC clock enable Set and enable by software. Reset source only for this field: PORESETn.

WDGEN

Bit 14: Watchdog clock enable. Set and enable by software..

APB1ENR

APB1ENR register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3EN rw				USART1EN rw		LPUARTEN rw			ADCANAEN rw	ADCDIGEN rw

Toggle fields

ADCDIGEN

Bit 4: AUXADC clock enable for Aux-ADC digital clock Set and enable by software..

ADCANAEN

Bit 5: ADC clock enable for Aux-ADC analog clock Set and enable by software..

LPUARTEN

Bit 8: LPUART clock enable Set and enable by software..

USART1EN

Bit 10: USART clock enable Set and enable by software..

SPI3EN

Bit 14: SPI3 clock enable Set and enable by software..

I2C1EN

Bit 21: I2C1 clock enable Set and enable by software..

APB2ENR

APB2ENR register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKBLEDIV rw		MRBLEEN rw

Toggle fields

MRBLEEN

Bit 0: MR_BLE enable.

CLKBLEDIV

Bit 2: MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1.

CSR

CSR register

Offset: 0x94, size: 32, reset: 0x0C000000, access: read-write

5/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	LOCKUPRSTF r	WDGRSTF r	SFTRSTF r	PORRSTF r	PADRSTF r			RMVF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

RMVF

Bit 23: Remove reset flag Set by software to clear the value of the reset flags. It auto clears by HW after clearing reason flags.

PADRSTF

Bit 26: SYSTEM reset flag Reset by software by writing the RMVF bit. Set by hardware when a reset from pad occurs..

PORRSTF

Bit 27: POWER reset flag Reset by software by writing the RMVF bit. Set by hardware when a power reset occurs from LPMURESET block..

SFTRSTF

Bit 28: Software reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs..

WDGRSTF

Bit 29: Watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a watchdog reset from V33 domain occurs..

LOCKUPRSTF

Bit 30: LOCK UP reset flag from CM0 Reset by software by writing the RMVF bit. Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals..

RFSWHSECR

RFSWHSECR register

Offset: 0x98, size: 32, reset: 0x00000030, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SWXOTUNE rw						SWXOTUNEEN rw	GMC rw			SATRG rw

Toggle fields

SATRG

Bit 3: Sense Amplifier threshold Set by software..

GMC

Bits 4-6: High Speed External XO current control Set by software..

SWXOTUNEEN

Bit 7: RF-HSE capacitor bank tuning by SW enable Set by software.

SWXOTUNE

Bits 8-13: RF-HSE capacitor bank tuning value by SW Set by software.

RFHSECR

RFHSECR register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										XOTUNE r

Toggle fields

XOTUNE

Bits 0-5: RF-HSE capacitor bank tuning Set by option byte loading soon after Power On Reset..

RRM

0x60001400:

1/33 fields covered.

Toggle register map

Offset	Name	31	15	4	3	2	1	0
0x10	UDRA_CTRL0							RELOAD_RDCFGPTR
0x14	UDRA_IRQ_ENABLE					CMD_END	CMD_START	RADIO_CFG_PTR_RELOADED
0x18	UDRA_IRQ_STATUS					CMD_END	CMD_STARD	RADIO_CFG_PTR_RELOADED
0x1c	UDRA_RADIO_CFG_PTR	RADIO_CONFIG_ADDRESS	RADIO_CONFIG_ADDRESS
0x20	SEMA_IRQ_ENABLE						UNLOCK	LOCK
0x24	SEMA_IRQ_STATUS						UNLOCK	LOCK
0x28	BLE_IRQ_ENABLE			PORT_CMD_END	PORT_CMD_START		PORT_RELEASE	PORT_GRANT
0x2c	BLE_IRQ_STATUS			CMD_END	CMD_START		PORT_RELEASE	PORT_GRANT
0x60	VP_CPU_CMD_BUS				COMMAND_REQ	COMMAND
0x64	VP_CPU_SEMA_BUS				TAKE_REQ	TAKE_PRIO
0x68	VP_CPU_IRQ_ENABLE			PORT_CMD_END	PORT_CMD_START		PORT_RELEASE	PORT_GRANT
0x6c	VP_CPU_IRQ_STATUS			CMD_END	CMD_START	PORT_PREEMPT	PORT_RELEASE	PORT_GRANT

Toggle registers

UDRA_CTRL0

UDRA_CTRL0 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RELOAD_RDCFGPTR rw

Toggle fields

RELOAD_RDCFGPTR

Bit 0: reload the radio configuration pointer from RAM..

UDRA_IRQ_ENABLE

UDRA_IRQ_ENABLE register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CMD_END rw	CMD_START rw	RADIO_CFG_PTR_RELOADED rw

Toggle fields

RADIO_CFG_PTR_RELOADED

Bit 0: UDRA interrupt enable (reload radio config pointer).

CMD_START

Bit 1: UDRA interrupt enable (command start).

CMD_END

Bit 2: UDRA interrupt enable (command end).

UDRA_IRQ_STATUS

UDRA_IRQ_STATUS register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CMD_END rw	CMD_STARD rw	RADIO_CFG_PTR_RELOADED rw

Toggle fields

RADIO_CFG_PTR_RELOADED

Bit 0: On read, returns the UDRA reload radio configuration pointer interrupt status..

CMD_STARD

Bit 1: On read, returns the UDRA command start interrupt status..

CMD_END

Bit 2: On read, returns the UDRA command end interrupt status.

UDRA_RADIO_CFG_PTR

UDRA_RADIO_CFG_PTR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RADIO_CONFIG_ADDRESS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RADIO_CONFIG_ADDRESS r

Toggle fields

RADIO_CONFIG_ADDRESS

Bits 0-31: UDRA radio configuration address..

SEMA_IRQ_ENABLE

SEMA_IRQ_ENABLE register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UNLOCK rw	LOCK rw

Toggle fields

LOCK

Bit 0: semaphore locked (= one port granted) interrupt enable.

UNLOCK

Bit 1: semaphore unlocked (=no port selected) interrupt enable.

SEMA_IRQ_STATUS

SEMA_IRQ_STATUS register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														UNLOCK rw	LOCK rw

Toggle fields

LOCK

Bit 0: On read, returns the semaphore locked interrupt status..

UNLOCK

Bit 1: On read, returns the semaphore unlocked interrupt status..

BLE_IRQ_ENABLE

BLE_IRQ_ENABLE register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PORT_CMD_END rw	PORT_CMD_START rw		PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: IP_BLE Port grant interrupt enable.

PORT_RELEASE

Bit 1: IP_BLE Port release interrupt enable.

PORT_CMD_START

Bit 3: IP_BLE Port command start interrup enable.

PORT_CMD_END

Bit 4: IP_BLE Port command end interrup enable.

BLE_IRQ_STATUS

BLE_IRQ_STATUS register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMD_END rw	CMD_START rw		PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: IP_BLE hardware port granted interrupt status:.

PORT_RELEASE

Bit 1: IP_BLE hardware port released interrupt status..

CMD_START

Bit 3: IP_BLE hardware port command start interrupt status..

CMD_END

Bit 4: IP_BLE hardware port command end interrupt status..

VP_CPU_CMD_BUS

VP_CPU_CMD_BUS register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												COMMAND_REQ rw	COMMAND rw

Toggle fields

COMMAND

Bits 0-2: command number.

COMMAND_REQ

Bit 3: CPU Virtual port command request:.

VP_CPU_SEMA_BUS

VP_CPU_SEMA_BUS register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TAKE_REQ rw	TAKE_PRIO rw

Toggle fields

TAKE_PRIO

Bits 0-2: semaphore priority: priority value (between 0 and 7) of the take request..

TAKE_REQ

Bit 3: semaphore token request:.

VP_CPU_IRQ_ENABLE

VP_CPU_IRQ_ENABLE register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PORT_CMD_END rw	PORT_CMD_START rw		PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: CPU virtual port grant interrupt enable.

PORT_RELEASE

Bit 1: CPU virtual port release interrupt enable.

PORT_CMD_START

Bit 3: CPU virtual port command start interrup enable.

PORT_CMD_END

Bit 4: CPU virtual port command end interrup enable.

VP_CPU_IRQ_STATUS

VP_CPU_IRQ_STATUS register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CMD_END rw	CMD_START rw	PORT_PREEMPT rw	PORT_RELEASE rw	PORT_GRANT rw

Toggle fields

PORT_GRANT

Bit 0: CPU virtual port granted interrupt status..

PORT_RELEASE

Bit 1: virtual port released interrupt status..

PORT_PREEMPT

Bit 2: CPU virtual port preemption (at semaphore level) interrupt status..

CMD_START

Bit 3: CPU virtual port command start interrupt status..

CMD_END

Bit 4: CPU virtual port command end interrupt status..

RTC

0x40004000:

1/67 fields covered.

Toggle register map

Offset	Name	31	30	29	27	23	22	21	20	19	18	17	16	15	14	13	12	11	10	8	7	6	5	4	3	2	0
0x0	TR						PM	HT		HU					MNT			MNU				ST			SU
0x4	DR					YT				YU				WDU			MT	MU					DT		DU
0x8	CR					COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H		WUTIE		ALRAIE		WUTE	ALRAE		FMT	BYPSHAD			WUCKSEL
0xc	ISR												RECALPF						WUTF	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUTWF	ALRAWF
0x10	PRER						PREDIV_A								PREDIV_S
0x14	WUTR													WUT
0x1c	ALRMAR	MSK4	WDSEL	DT	DU	MSK3	PM	HT		HU				MSK2	MNT			MNU			MSK1	ST			SU
0x24	WPR																				KEY
0x28	SSR													SS
0x2c	SHIFTR	ADD1S													SUBFS
0x3c	CALR													CALP	CALW8	CALW16				CALM
0x44	ALRMASSR				MASKSS										SS
0x50	BKP0R	BKP												BKP
0x54	BKP1R	BKP												BKP

Toggle registers

TR

RTC_TR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation. 0: AM or 24-hour format 1: PM.

DR

RTC_DR register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format..

DT

Bits 4-5: Date tens in BCD format..

MU

Bits 8-11: Month units in BCD format..

MT

Bit 12: Month tens in BCD format..

WDU

Bits 13-15: Week day units 000: forbidden 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Sunday.

YU

Bits 16-19: Year units in BCD format..

YT

Bits 20-23: Year tens in BCD format..

CR

RTC_CR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H w	ADD1H w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	WUTIE rw		ALRAIE rw		WUTE rw		ALRAE rw		FMT rw	BYPSHAD rw			WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value.

BYPSHAD

Bit 5: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters..

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable 0: Alarm A disabled 1: Alarm A enabled.

WUTE

Bit 10: Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled.

ALRAIE

Bit 12: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled.

WUTIE

Bit 14: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled.

ADD1H

Bit 16: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change.

SUB1H

Bit 17: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change..

BKP

Bit 18: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not..

COSEL

Bit 19: Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255)..

POL

Bit 20: Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0])..

OSEL

Bits 21-22: Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Reserved 11: Wakeup output enabled.

COE

Bit 23: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled.

ISR

RTC_ISR register

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					WUTF rw		ALRAF rw	INIT rw	INITF rw	RSF rw	INITS rw	SHPF rw	WUTWF rw		ALRAWF rw

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ALRAWF

Bit 0: Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed..

WUTWF

Bit 2: Wakeup timer write flag This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed..

SHPF

Bit 3: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect..

INITS

Bit 4: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). 0: Calendar has not been initialized 1: Calendar has been initialized.

RSF

Bit 5: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized..

INITF

Bit 6: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed..

INIT

Bit 7: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset..

ALRAF

Bit 8: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0..

WUTF

Bit 10: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again..

RECALPF

Bit 16: Recalibration pending Flag The RECALPF status flag is automatically set to 1' when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0'..

PRER

RTC_PRER register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

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PREDIV_S

Bits 0-14: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1).

PREDIV_A

Bits 16-22: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1).

WUTR

RTC_WUTR register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

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WUT

Bits 0-15: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden..

ALRMAR

RTC_ALRMAR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

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SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MSK1

Bit 7: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don't care in Alarm A comparison.

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

MSK2

Bit 15: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes don't care in Alarm A comparison.

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation 0: AM or 24-hour format 1: PM.

MSK3

Bit 23: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours don't care in Alarm A comparison.

DU

Bits 24-27: Date units or day in BCD format..

DT

Bits 28-29: Date tens in BCD format..

WDSEL

Bit 30: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don't care..

MSK4

Bit 31: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day don't care in Alarm A comparison.

WPR

RTC_WPR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

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KEY

Bits 0-7: Write protection key This byte is written by software. Reading this byte always returns 0x00.

SSR

RTC_SSR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

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SS

Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescaler's counter. The fraction of a second is given by the formula below: Second fraction = ( PREDIV_S SS ) / ( PREDIV_S + 1 ).

SHIFTR

RTC_SHIFTR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

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SUBFS

Bits 0-14: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler's counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : Advance (seconds) = ( 1 ( SUBFS / ( PREDIV_S + 1 ) ) ) ..

ADD1S

Bit 31: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation..

CALR

RTC_CALR register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

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CALM

Bits 0-8: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP..

CALW16

Bit 13: Use a 16-second calibration cycle period When CALW16 is set to 1' , the 16-second calibration cycle period is selected.This bit must not be set to 1' if CALW8=1. Note: CALM[0] is stucked at 0' when CALW16='1'..

CALW8

Bit 14: Use an 8-second calibration cycle period When CALW8 is set to 1' , the 8-second calibration cycle period is selected. Note: CALM[1:0] are stucked at '00' when CALW8='1'..

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) CALM..

ALRMASSR

RTC_ALRMASSR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

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SS

Bits 0-14: Sub seconds value This value is compared with the contents of the synchronous prescaler's counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared..

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are don't care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are don't care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..

BKP0R

RTC_BKP0R register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

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BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only..

BKP1R

RTC_BKP1R register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

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BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only..

SPI3

0x41007000: SPI address block description

54/54 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RXCRC
0x18 (16-bit)	TXCRCR	TXCRC
0x1c (16-bit)	I2SCFGR				ASTRTEN	I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

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CR1

SPI control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

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CPHA

Bit 0: Clock phase Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I2S mode..

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control Note: These bits should not be changed when communication is ongoing. Note: These bits are not used in I2S mode..

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. Note: This bit is not used in I2S mode..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format Note: 1. This bit should not be changed when communication is ongoing. Note: 2. This bit is not used in I2S mode and SPI TI mode..

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode..

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode..

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode..

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I2S mode..

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. Note: This bit is not used in I2S mode..

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I2S mode..

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. Note: This bit is not used in I2S mode..

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode..

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

SPI control register 2

Offset: 0x4, size: 16, reset: 0x00000700, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set..

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set..

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable Note: This bit is not used in I2S mode and SPI TI mode..

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1 , or FRF = 1 . Note: 1. This bit must be written only when the SPI is disabled (SPE=0). Note: 2. This bit is not used in I2S mode and SPI TI mode..

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). Note: This bit is not used in I2S mode..

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode)..

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I2S mode..

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode..

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode..

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode..

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

SPI status register

Offset: 0x8, size: 16, reset: 0x00000002, access: read-write

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR r/w0c	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode..

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. Note: This bit is not used in SPI mode..

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag Note: This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I2S mode..

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. Note: This bit is not used in I2S mode..

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence..

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789..

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software..

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled..

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode..

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

SPI data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

SPI CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required..

Allowed values: 0x0-0xffff

RXCRCR

SPI Rx CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. Note: These bits are not used in I2S mode..

Allowed values: 0x0-0xffff

TXCRCR

SPI Tx CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-15: Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. Note: These bits are not used in I2S mode..

Allowed values: 0x0-0xffff

I2SCFGR

SPIx_I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ASTRTEN rw	I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode..

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode..

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode. Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals..

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection For more details on I2S standards, refer to Section 27.7.2 on page 805 Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode..

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). Note: It is not used in SPI mode..

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode Note: These bits should be configured when the I2S is disabled. Note: They are not used in SPI mode..

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S enable Note: This bit is not used in SPI mode..

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection Note: This bit should be configured when the SPI is disabled..

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

ASTRTEN

Bit 12: Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. Note: The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Note: Please refer to Section 27.7.3: Start-up description for additional information..

Allowed values:
0: AsyncStartDisabled: Asynchronous start disabled
1: AsyncStartEnabled: Asynchronous start enabled

I2SPR

SPIx_I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to Section 27.7.3 on page 812. Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. Note: They are not used in SPI mode..

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler Refer to Section 27.7.3 on page 812. Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode..

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode..

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SYSTEM_CTRL

0x40000000:

8/128 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	23	22	21	20	19	18	17	16	15	11	10	9	8	7	3	2	1	0
0x0	DIE_ID															PRODUCT				VERSION	REVISION
0x4	JTAG_ID	VERSION_NUMBER				PART_NUMBER									PART_NUMBER	MANUF_ID
0x8	I2C_FMP_CTRL																				I2C1_PB7_FMP	I2C1_PB6_FMP	I2C1_PA1_FMP	I2C1_PA0_FMP
0xc	IO_DTR	PB15_DT	PB14_DT	PB13_DT	PB12_DT		PB7_DT	PB6_DT	PB5_DT	PB4_DT	PB3_DT	PB2_DT	PB1_DT	PB0_DT		PA11_DT	PA10_DT	PA9_DT	PA8_DT		PA3_DT	PA2_DT	PA1_DT	PA0_DT
0x10	IO_IBER	PB15_IBE	PB14_IBE	PB13_IBE	PB12_IBE		PB7_IBE	PB6_IBE	PB5_IBE	PB4_IBE	PB3_IBE	PB2_IBE	PB1_IBE	PB0_IBE		PA11_IBE	PA10_IBE	PA9_IBE	PA8_IBE		PA3_IBE	PA2_IBE	PA1_IBE	PA0_IBE
0x14	IO_IEVR	PB15_IEV	PB14_IEV	PB13_IEV	PB12_IEV		PB7_IEV	PB6_IEV	PB5_IEV	PB4_IEV	PB3_IEV	PB2_IEV	PB1_IEV	PB0_IEV		PA11_IEV	PA10_IEV	PA9_IEV	PA8_IEV		PA3_IEV	PA2_IEV	PA1_IEV	PA0_IEV
0x18	IO_IER	PB15_IE	PB14_IE	PB13_IE	PB12_IE		PB7_IE	PB6_IE	PB5_IE	PB4_IE	PB3_IE	PB2_IE	PB1_IE	PB0_IE		PA11_IE	PA10_IE	PA9_IE	PA8_IE		PA3_IE	PA2_IE	PA1_IE	PA0_IE
0x1c	IO_ISCR	PB15_ISC	PB14_ISC	PB13_ISC	PB12_ISC		PB7_ISC	PB6_ISC	PB5_ISC	PB4_ISC	PB3_ISC	PB2_ISC	PB1_ISC	PB0_ISC		PA11_ISC	PA10_ISC	PA9_ISC	PA8_ISC		PA3_ISC	PA2_ISC	PA1_ISC	PA0_ISC
0x20	PWRC_IER																					WKUP_IE	PVD_IE	BORH_IE
0x24	PWRC_ISCR																					WKUP_ISC	PVD_ISC	BORH_ISC
0x2c	BLERXTX_DTR																						RX_DT	TX_DT
0x30	BLERXTX_IBER																						RX_IBE	TX_IBE
0x34	BLERXTX_IEVR																						RX_IEV	TX_IEV
0x38	BLERXTX_IER																						RX_IE	TX_IE
0x3c (8-bit)	BLERXTX_ISCR																				RX_ISEDGE	TX_ISEDGE	RX_ISC	TX_ISC

Toggle registers

DIE_ID

DIE_ID register

Offset: 0x0, size: 32, reset: 0x00000120, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PRODUCT r				VERSION r				REVISION r

Toggle fields

REVISION

Bits 0-3: Cut revision (metal fix).

VERSION

Bits 4-7: Cut version.

PRODUCT

Bits 8-11: Product version. May be used to discriminate several version of a same digital BLE LPH device embedding different analog versions.

JTAG_ID

JTAG_ID register

Offset: 0x4, size: 32, reset: 0x02028041, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VERSION_NUMBER r				PART_NUMBER r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PART_NUMBER r				MANUF_ID r

Toggle fields

MANUF_ID

Bits 1-11: Manufacturer ID.

PART_NUMBER

Bits 12-27: Part number.

VERSION_NUMBER

Bits 28-31: Version.

I2C_FMP_CTRL

I2C_FMP_CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												I2C1_PB7_FMP rw	I2C1_PB6_FMP rw	I2C1_PA1_FMP rw	I2C1_PA0_FMP rw

Toggle fields

I2C1_PA0_FMP

Bit 0: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. 0: PA0 pin operated in standard mode. 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed.

I2C1_PA1_FMP

Bit 1: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. 0: PA1 pin operated in standard mode. 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed.

I2C1_PB6_FMP

Bit 2: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. 0: PB6 pin operated in standard mode. 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed..

I2C1_PB7_FMP

Bit 3: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. 0: PB7 pin operated in standard mode. 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed.

IO_DTR

IO_DTR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_DT rw	PB14_DT rw	PB13_DT rw	PB12_DT rw					PB7_DT rw	PB6_DT rw	PB5_DT rw	PB4_DT rw	PB3_DT rw	PB2_DT rw	PB1_DT rw	PB0_DT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PA11_DT rw	PA10_DT rw	PA9_DT rw	PA8_DT rw					PA3_DT rw	PA2_DT rw	PA1_DT rw	PA0_DT rw

Toggle fields

PA0_DT

Bit 0: PA0_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA1_DT

Bit 1: PA1_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA2_DT

Bit 2: PA2_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA3_DT

Bit 3: PA3_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA8_DT

Bit 8: PA8_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA9_DT

Bit 9: PA9_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA10_DT

Bit 10: PA10_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA11_DT

Bit 11: PA11_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PB0_DT

Bit 16: PB0_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB1_DT

Bit 17: PB1_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB2_DT

Bit 18: PB2_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB3_DT

Bit 19: PB3_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB4_DT

Bit 20: PB4_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB5_DT

Bit 21: PB5_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB6_DT

Bit 22: PB6_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB7_DT

Bit 23: PB7_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB12_DT

Bit 28: PB12_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB13_DT

Bit 29: PB13_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB14_DT

Bit 30: PB14_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB15_DT

Bit 31: PB15_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

IO_IBER

IO_IBER register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IBE rw	PB14_IBE rw	PB13_IBE rw	PB12_IBE rw					PB7_IBE rw	PB6_IBE rw	PB5_IBE rw	PB4_IBE rw	PB3_IBE rw	PB2_IBE rw	PB1_IBE rw	PB0_IBE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PA11_IBE rw	PA10_IBE rw	PA9_IBE rw	PA8_IBE rw					PA3_IBE rw	PA2_IBE rw	PA1_IBE rw	PA0_IBE rw

Toggle fields

PA0_IBE

Bit 0: PA0_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA1_IBE

Bit 1: PA1_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA2_IBE

Bit 2: PA2_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA3_IBE

Bit 3: PA3_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA8_IBE

Bit 8: PA8_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA9_IBE

Bit 9: PA9_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA10_IBE

Bit 10: PA10_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA11_IBE

Bit 11: PA11_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PB0_IBE

Bit 16: PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB1_IBE

Bit 17: PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB2_IBE

Bit 18: PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB3_IBE

Bit 19: PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB4_IBE

Bit 20: PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB5_IBE

Bit 21: PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB6_IBE

Bit 22: PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB7_IBE

Bit 23: PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB12_IBE

Bit 28: PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB13_IBE

Bit 29: PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB14_IBE

Bit 30: PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB15_IBE

Bit 31: PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

IO_IEVR

IO_IEVR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IEV rw	PB14_IEV rw	PB13_IEV rw	PB12_IEV rw					PB7_IEV rw	PB6_IEV rw	PB5_IEV rw	PB4_IEV rw	PB3_IEV rw	PB2_IEV rw	PB1_IEV rw	PB0_IEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PA11_IEV rw	PA10_IEV rw	PA9_IEV rw	PA8_IEV rw					PA3_IEV rw	PA2_IEV rw	PA1_IEV rw	PA0_IEV rw

Toggle fields

PA0_IEV

Bit 0: PA0_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA1_IEV

Bit 1: PA1_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA2_IEV

Bit 2: PA2_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA3_IEV

Bit 3: PA3_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA8_IEV

Bit 8: PA8_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA9_IEV

Bit 9: PA9_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA10_IEV

Bit 10: PA10_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA11_IEV

Bit 11: PA11_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB0_IEV

Bit 16: PB0_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB1_IEV

Bit 17: PB1_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB2_IEV

Bit 18: PB2_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB3_IEV

Bit 19: PB3_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB4_IEV

Bit 20: PB4_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB5_IEV

Bit 21: PB5_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB6_IEV

Bit 22: PB6_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB7_IEV

Bit 23: PB7_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB12_IEV

Bit 28: PB12_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB13_IEV

Bit 29: PB13_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB14_IEV

Bit 30: PB14_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB15_IEV

Bit 31: PB15_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

IO_IER

IO_IER register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IE rw	PB14_IE rw	PB13_IE rw	PB12_IE rw					PB7_IE rw	PB6_IE rw	PB5_IE rw	PB4_IE rw	PB3_IE rw	PB2_IE rw	PB1_IE rw	PB0_IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PA11_IE rw	PA10_IE rw	PA9_IE rw	PA8_IE rw					PA3_IE rw	PA2_IE rw	PA1_IE rw	PA0_IE rw

Toggle fields

PA0_IE

Bit 0: PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA1_IE

Bit 1: PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA2_IE

Bit 2: PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA3_IE

Bit 3: PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA8_IE

Bit 8: PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA9_IE

Bit 9: PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA10_IE

Bit 10: PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA11_IE

Bit 11: PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB0_IE

Bit 16: PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB1_IE

Bit 17: PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB2_IE

Bit 18: PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB3_IE

Bit 19: PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB4_IE

Bit 20: PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB5_IE

Bit 21: PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB6_IE

Bit 22: PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB7_IE

Bit 23: PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB12_IE

Bit 28: PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB13_IE

Bit 29: PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB14_IE

Bit 30: PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB15_IE

Bit 31: PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

IO_ISCR

IO_ISCR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_ISC rw	PB14_ISC rw	PB13_ISC rw	PB12_ISC rw					PB7_ISC rw	PB6_ISC rw	PB5_ISC rw	PB4_ISC rw	PB3_ISC rw	PB2_ISC rw	PB1_ISC rw	PB0_ISC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PA11_ISC rw	PA10_ISC rw	PA9_ISC rw	PA8_ISC rw					PA3_ISC rw	PA2_ISC rw	PA1_ISC rw	PA0_ISC rw

Toggle fields

PA0_ISC

Bit 0: PA0_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA1_ISC

Bit 1: PA1_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA2_ISC

Bit 2: PA2_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA3_ISC

Bit 3: PA3_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA8_ISC

Bit 8: PA8_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA9_ISC

Bit 9: PA9_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA10_ISC

Bit 10: PA10_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA11_ISC

Bit 11: PA11_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB0_ISC

Bit 16: PB0_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB1_ISC

Bit 17: PB1_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB2_ISC

Bit 18: PB2_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB3_ISC

Bit 19: PB3_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB4_ISC

Bit 20: PB4_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB5_ISC

Bit 21: PB5_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB6_ISC

Bit 22: PB6_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB7_ISC

Bit 23: PB7_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB12_ISC

Bit 28: PB12_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB13_ISC

Bit 29: PB13_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB14_ISC

Bit 30: PB14_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB15_ISC

Bit 31: PB15_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PWRC_IER

PWRC_IER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WKUP_IE rw	PVD_IE rw	BORH_IE rw

Toggle fields

BORH_IE

Bit 0: BORH_IE: BORH interrupt enable. 0: BORH interrupt is disabled. 1: BORH interrupt is enabled..

PVD_IE

Bit 1: PVD_IE: Programmable Voltage Detector interrupt enable. 0: PVD interrupt is disabled. 1: PVD interrupt is enabled..

WKUP_IE

Bit 2: WKUP_IE: Power Controller Wakeup event interrupt enable. 0: Interrupt on wakeup event seen by the PWRC is disabled. 1: Interrupt on wakeup event seen by the PWRC is enabled..

PWRC_ISCR

PWRC_ISCR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WKUP_ISC rw	PVD_ISC rw	BORH_ISC rw

Toggle fields

BORH_ISC

Bit 0: BORH_ISC: BORH interrupt status. 0: no pending interrupt. 1: voltage went under BORH threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PVD_ISC

Bit 1: PVD_ISC: Programmable Voltage Detector status. 0: no pending interrupt. 1: voltage went under programmed threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

WKUP_ISC

Bit 2: WKUP_ISC: Indicates the Power Controller receives a Wakeup event. 0: no pending interrupt. 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). Cleared by writing 1 in the bit. This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry requests that the PWRC aborts before shutting down the system..

BLERXTX_DTR

BLERXTX_DTR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_DT rw	TX_DT rw

Toggle fields

TX_DT

Bit 0: TX_DT: detection type on TX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level.

RX_DT

Bit 1: RX_DT: detection type on RX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level.

BLERXTX_IBER

BLERXTX_IBER register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_IBE rw	TX_IBE rw

Toggle fields

TX_IBE

Bit 0: TX_IBE: interrupt edge register on TX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges.

RX_IBE

Bit 1: RX_IBE: interrupt edge register on RX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges.

BLERXTX_IEVR

BLERXTX_IEVR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_IEV rw	TX_IEV rw

Toggle fields

TX_IEV

Bit 0: TX_IEV: interrupt polarity event on TX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

RX_IEV

Bit 1: RX_IEV: interrupt polarity event on RX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

BLERXTX_IER

BLERXTX_IER register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RX_IE rw	TX_IE rw

Toggle fields

TX_IE

Bit 0: TX_IE: interrupt enable on TX_SEQUENCE signal: 0: TX_SEQUENCE interrupt is disabled (default). 1: TX_SEQUENCE interrupt is enabled.

RX_IE

Bit 1: RX_IE: interrupt enable on RX_SEQUENCE signal: 0: RX_SEQUENCE interrupt is disabled (default). 1: RX_SEQUENCE interrupt is enabled.

BLERXTX_ISCR

BLERXTX_ISCR register

Offset: 0x3c, size: 8, reset: 0x00000000, access: read-write

2/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												RX_ISEDGE r	TX_ISEDGE r	RX_ISC rw	TX_ISC rw

Toggle fields

TX_ISC

Bit 0: TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on TX_SEQUENCE detected. 1: activity on TX_SEQUENCE occurred.

RX_ISC

Bit 1: RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on RX_SEQUENCE detected. 1: activity on RX_SEQUENCE occurred.

TX_ISEDGE

Bit 2: TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: 0: falling edge on TX_SEQUENCE detected. 1: rising edge on TX_SEQUENCE detected..

RX_ISEDGE

Bit 3: RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: 0: falling edge on RX_SEQUENCE detected. 1: rising edge on RX_SEQUENCE detected..

TIM16

0x40005000:

52/70 fields covered.

Toggle register map

Offset	Name	31	28	26	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1									UIF_REMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2											OIS[1]N	OIS[1]					CCDS	CCUS		CCPC
0xc	DIER					BDE		CC[U]DE				CC[1]DE	UDE	BIE		COMIE				CC[1]IE	UIE
0x10	SR											CC[1]OF		BIF		COMIF				CC[1]IF	UIF
0x14	EGR													BG		COMG				CC[1]G	UG
0x18	CCMR1_Input													IC[1]F				IC[1]PSC		CC1S
0x18	CCMR1_Output				OC[1]M_3									OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER																	CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	UIF_CPY				CNT
0x28	PSC					PSC
0x2c	ARR					ARR
0x30	RCR													REP
0x34	CCR[1]					CCR
0x44	BDTR		BKBID	BKDSRM		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR								DBL								DBA
0x4c	DMAR					DMAB
0x60	AF1							AF1_13_12		BKCMP2P	BKCMP1P	BKINP	AF1_8_3						BKCMP2E	BKCMP1E	BKINE
0x68	TISEL																	TI1SEL

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIF_REMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled..

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN).

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIF_REMAP

Bit 11: UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS[1]N rw	OIS[1] rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DIER register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BDE rw		CC[U]DE rw				CC[1]DE rw	UDE rw	BIE rw		COMIE rw				CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[U]DE

Bit 13: Capture/Compare U DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

BDE

Bit 15: BDE: Break DMA request Enable. Not used in Blue51. Not available in IUM 0: Break DMA request disabled. 1: Break DMA request enabled..

SR

SR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF r/w0c		BIF r/w0c		COMIF r/w0c				CC[1]IF r/w0c	UIF r/w0c

Toggle fields

UIF

Bit 0: UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, CCxNE, OCxMhave been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

EGR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC[1]G w	UG w

Toggle fields

UG

Bit 0: UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output..

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled..

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

CCMR1 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC[1]M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

CCER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

CNT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF_CPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: CNT[15:0]: Counter value.

Allowed values: 0x0-0xffff

UIF_CPY

Bit 31: UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

PSC register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode')..

Allowed values: 0x0-0xffff

ARR

ARR register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

Allowed values: 0x0-0xffff

RCR

RCR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)..

Allowed values: 0x0-0xffff

BDTR

BDTR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63 us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values: 0x0-0xff

LOCK

Bits 8-9: LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in TIMx_AF1 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: BKE: Break enable 1; Break inputs (BRK) enabled Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: BKP: Break polarity 0: Break input BRK is active low. 1: Break input BRK is active high Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: AOE: Automatic output enable not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER))..

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: BKDSRM: Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (opendrain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

DCR register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers..

DMAR

DMAR register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

AF1

AF1 register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		AF1_13_12 rw		BKCMP2P rw	BKCMP1P rw	BKINP rw	AF1_8_3 rw						BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BKINE: BRK BKIN enable. This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is ORed with the other enabled BRK sources. 0: BKIN input disabled. 1: BKIN input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP1E

Bit 1: BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP2E

Bit 2: BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

AF1_8_3

Bits 3-8: AF1[13:12] Not used in Blue51. Not available in IUM.

BKINP

Bit 9: BKINP: BRK BKIN input polarity. This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low. 1: BKIN input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP1P

Bit 10: BKCMP1P: BRK COMP1 input polarity. This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low. 1: COMP1 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP2P

Bit 11: BKCMP2P: BRK COMP2 input polarity. This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low. 1: COMP2 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

AF1_13_12

Bits 12-13: AF1[13:12] Not used in Blue51. Not available in IUM.

TISEL

TISEL register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TIM17

0x40006000:

52/70 fields covered.

Toggle register map

Offset	Name	31	28	26	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1									UIF_REMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2											OIS[1]N	OIS[1]					CCDS	CCUS		CCPC
0xc	DIER					BDE		CC[U]DE				CC[1]DE	UDE	BIE		COMIE				CC[1]IE	UIE
0x10	SR											CC[1]OF		BIF		COMIF				CC[1]IF	UIF
0x14	EGR													BG		COMG				CC[1]G	UG
0x18	CCMR1_Input													IC[1]F				IC[1]PSC		CC1S
0x18	CCMR1_Output				OC[1]M_3									OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER																	CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	UIF_CPY				CNT
0x28	PSC					PSC
0x2c	ARR					ARR
0x30	RCR													REP
0x34	CCR[1]					CCR
0x44	BDTR		BKBID	BKDSRM		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR								DBL								DBA
0x4c	DMAR					DMAB
0x50	OR1																			TI1_RMP
0x60	AF1							AF1_13_12		BKCMP2P	BKCMP1P	BKINP	AF1_8_3						BKCMP2E	BKCMP1E	BKINE

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIF_REMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled..

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN).

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIF_REMAP

Bit 11: UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS[1]N rw	OIS[1] rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output..

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DIER register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BDE rw		CC[U]DE rw				CC[1]DE rw	UDE rw	BIE rw		COMIE rw				CC[1]IE rw	UIE rw

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UIE

Bit 0: UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[U]DE

Bit 13: Capture/Compare U DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

BDE

Bit 15: BDE: Break DMA request Enable. Not used in Blue51. Not available in IUM 0: Break DMA request disabled. 1: Break DMA request enabled..

SR

SR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF r/w0c		BIF r/w0c		COMIF r/w0c				CC[1]IF r/w0c	UIF r/w0c

Toggle fields

UIF

Bit 0: UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, CCxNE, OCxMhave been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

EGR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC[1]G w	UG w

Toggle fields

UG

Bit 0: UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output..

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled..

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

CCMR1 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC[1]M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

CCER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

CNT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF_CPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: CNT[15:0]: Counter value.

Allowed values: 0x0-0xffff

UIF_CPY

Bit 31: UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

PSC register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode')..

Allowed values: 0x0-0xffff

ARR

ARR register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

Allowed values: 0x0-0xffff

RCR

RCR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)..

Allowed values: 0x0-0xffff

BDTR

BDTR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63 us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values: 0x0-0xff

LOCK

Bits 8-9: LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in TIMx_AF1 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: BKE: Break enable 1; Break inputs (BRK) enabled Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: BKP: Break polarity 0: Break input BRK is active low. 1: Break input BRK is active high Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: AOE: Automatic output enable not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER))..

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: BKDSRM: Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (opendrain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

DCR register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers..

DMAR

DMAR register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

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DMAB

Bits 0-15: DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

OR1

OR1 register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TI1_RMP rw

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TI1_RMP

Bits 0-1: TI1_RMP[1:0]: Timer 17 input 1 connection This bit is set and cleared by software. 00: TIM17 TI1 is connected to GPIO 01: TIM17 TI1 is connected to LCO 1x: TIM17 TI1 is connected to MCO.

AF1

AF1 register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		AF1_13_12 rw		BKCMP2P rw	BKCMP1P rw	BKINP rw	AF1_8_3 rw						BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BKINE: BRK BKIN enable. This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is ORed with the other enabled BRK sources. 0: BKIN input disabled. 1: BKIN input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP1E

Bit 1: BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP2E

Bit 2: BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

AF1_8_3

Bits 3-8: AF1[13:12] Not used in Blue51. Not available in IUM.

BKINP

Bit 9: BKINP: BRK BKIN input polarity. This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low. 1: BKIN input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP1P

Bit 10: BKCMP1P: BRK COMP1 input polarity. This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low. 1: COMP1 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP2P

Bit 11: BKCMP2P: BRK COMP2 input polarity. This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low. 1: COMP2 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

AF1_13_12

Bits 12-13: AF1[13:12] Not used in Blue51. Not available in IUM.

TIM2

0x40002000:

97/114 fields covered.

Toggle register map

Offset	Name	31	27	24	21	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1											UIF_REMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2															TI1S	MMS			CCDS
0x8	SMCR				TS2		SMS_3	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER								TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR										CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR																TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input							IC[2]F				IC[2]PSC		CC2S		IC[1]F				IC[1]PSC		CC1S
0x18	CCMR1_Output			OC[2]M_3			OC[1]M_3	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input							IC[4]F				IC[4]PSC		CC4S		IC[3]F				IC[3]PSC		CC3S
0x1c	CCMR2_Output			OC[4]M_3			OC[3]M_3	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER							CC[4]NP		CC[4]P	CC[4]E	CC[3]NP		CC[3]P	CC[3]E	CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	UIF_CPY						CNT
0x28	PSC							PSC
0x2c	ARR							ARR
0x30	RCR															REP
0x34	CCR[1]							CCR
0x38	CCR[2]							CCR
0x3c	CCR[3]							CCR
0x40	CCR[4]							CCR
0x48	DCR										DBL								DBA
0x4c	DMAR							DMAB
0x68	TISEL		TI4SEL			TI3SEL						TI2SEL								TI1SEL

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIF_REMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller..

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled..

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN).

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIF_REMAP

Bit 11: UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: MMS: Master Mode Selection. This field is not available in IUM as Timer2 is not connected to ant other timer for master/slave synchronization. These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follow : is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in GPT_SMCR register). can then be used as a prescaler for a slave timer. (even if it was already high), as soon as a capture or a compare match occured. (TRGO)..

TI1S

Bit 7: TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination).

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

SMCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS2 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled if CEN = '1' then the prescaler is clocked directly by the internal clock. 0001: Encoder mode 1 Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0010: Encoder mode 2 Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0011: Encoder mode 3 Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal..

OCCS

Bit 3: OCCS: OCREF clear selection This bit is used to select the OCREF clear source. 0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) 1: OCREF_CLR_INT is connected to ETRF.

TS

Bits 4-6: TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) others: Reserved Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: MSM: Master/Slave mode Not vailable in IUM. Not used in Blue51 as TRGO is not connected to any slave timer 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event..

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge..

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: SMS[3]: Slave mode selection bit 3 Refer to SMS description bits2:0.

TS2

Bits 20-21: Extended trigger selection. Not used. Not available in IUM.

DIER

DIER register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: TDE: Trigger DMA request Enable. Not used in Blue51. Not available in IUM. 0: Trigger DMA request disabled. 1: Trigger DMA request enabled..

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

SR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF r/w0c	CC[3]OF r/w0c	CC[2]OF r/w0c	CC[1]OF r/w0c			TIF r/w0c		CC[4]IF r/w0c	CC[3]IF r/w0c	CC[2]IF r/w0c	CC[1]IF r/w0c	UIF r/w0c

Toggle fields

UIF

Bit 0: UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.. 0: No trigger event occurred. 1: Trigger interrupt pending..

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

EGR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)..

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled..

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC2S rw		IC[1]F rw				IC[1]PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER)..

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

CCMR1 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC[2]M_3 rw								OC[1]M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC4S rw		IC[3]F rw				IC[3]PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER)..

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER)..

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

CCMR2 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC[4]M_3 rw								OC[3]M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

CCER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC[4]NP rw		CC[4]P rw	CC[4]E rw	CC[3]NP rw		CC[3]P rw	CC[3]E rw	CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

CNT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF_CPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: CNT[15:0]: Counter value.

Allowed values: 0x0-0xffff

UIF_CPY

Bit 31: UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

PSC register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode')..

Allowed values: 0x0-0xffff

ARR

ARR register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

Allowed values: 0x0-0xffff

RCR

RCR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DCR register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers..

Allowed values: 0x0-0x12

DMAR

DMAR register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIM2_CR1 address) + (DBA + DMA index) x 4 where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM2_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR)..

TISEL

TISEL register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] inputt.

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input.

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input.

TRNG

0x48600000:

39/65 fields covered.

Toggle register map

Offset	Name	31	29	25	24	23	22	21	20	15	11	9	8	7	6	5	4	3	2	1	0
0x0	CR					CLKDIV				CLKDIV				RST_HEALTH_FLAGS	CLR_REVCLK_FLAG						DISABLE
0x4	SR			OSCS_ADAPT_ERROR	OSCS_REPET_ERROR	OSCS_HEALTH_DONE	ADAPT_ERROR	REPET_ERROR	SRC_HEALTH_DONE							FIFO_FULL	VAL_READY	ENTROPY_ERR	REVEAL_CLK_ERR	ALL_OSCS_DOWN	TRNG_DISABLED
0x8	VAL	RND_VAL								RND_VAL
0x30	OSCS_CR	SYNC_OSCS										PWRD3			PWRD2			PWRD1
0x34	POSTP_CR	NB_RND_REINIT									NB_LOOP_AES										AES_RESET
0x38	POSTP_SR														AES_DOUT_ERROR	AES_K12_ERROR	AES_HEALTH_DONE	AES_BUSY	AES_KEY_LD	AES_INIT
0x40	DEFKEY0	RNG_DEFKEY0								RNG_DEFKEY0
0x44	DEFKEY1	RNG_DEFKEY1								RNG_DEFKEY1
0x48	DEFKEY2	RNG_DEFKEY2								RNG_DEFKEY2
0x4c	DEFKEY3	RNG_DEFKEY3								RNG_DEFKEY3
0x60	HEALTH_CR		ITER_ADAP	ADAP_CUTOFF										REPET_CUTOFF
0x68	HEALTH_OSC1_CR			ADAP_CUTOFF_OSC1										REPET_CUTOFF_OSC1
0x6c	HEALTH_OSC2_CR			ADAP_CUTOFF_OSC2										REPET_CUTOFF_OSC2
0x70	HEALTH_OSC3_CR			ADAP_CUTOFF_OSC3										REPET_CUTOFF_OSC3
0x74	HEALTH_OSC1_SR															TO3_ADAPT_ERROR	TO3_REPET_ERROR	TO2_ADAPT_ERROR	TO2_REPET_ERROR	TO1_ADAPT_ERROR	TO1_REPET_ERROR
0x78	HEALTH_OSC2_SR															TO3_ADAPT_ERROR	TO3_REPET_ERROR	TO2_ADAPT_ERROR	TO2_REPET_ERROR	TO1_ADAPT_ERROR	TO1_REPET_ERROR
0x7c	HEALTH_OSC3_SR															TO3_ADAPT_ERROR	TO3_REPET_ERROR	TO2_ADAPT_ERROR	TO2_REPET_ERROR	TO1_ADAPT_ERROR	TO1_REPET_ERROR
0x80	IRQ_CR												EN_ERROR_IRQ								EN_FF_FULL_IRQ
0x84	IRQ_SR												ERROR_IRQ								FF_FULL_IRQ

Toggle registers

CR

TRNG_CR register

Offset: 0x0, size: 32, reset: 0x0000FF00, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CLKDIV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKDIV rw								RST_HEALTH_FLAGS rw	CLR_REVCLK_FLAG rw						DISABLE rw

Toggle fields

DISABLE

Bit 0: Disable Bit DISABLE can be used for reading or setting the state of the TRNG core. The value read is always the one available at the rng core clock domain. When changing the value, the change is effective when the value read is the same as the one written..

CLR_REVCLK_FLAG

Bit 6: Reset reveal clock error flags when writing a '1' without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset..

RST_HEALTH_FLAGS

Bit 7: Reset Health error flags when writing a '1' without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset..

CLKDIV

Bits 8-23: Sampling Clock Enable Divider. CLKDIV[15:0] control the sampling clock enable divider, dividing by a factor equal to CLKDIV[15:0] + 1, values being in the range of 1 to 65536..

SR

TRNG_SR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						OSCS_ADAPT_ERROR r	OSCS_REPET_ERROR r	OSCS_HEALTH_DONE r	ADAPT_ERROR r	REPET_ERROR r	SRC_HEALTH_DONE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FIFO_FULL r	VAL_READY r	ENTROPY_ERR r	REVEAL_CLK_ERR r	ALL_OSCS_DOWN r	TRNG_DISABLED r

Toggle fields

TRNG_DISABLED

Bit 0: TRNG is disabled..

ALL_OSCS_DOWN

Bit 1: All oscillators of the random source noise have been powered down. This can cause the rising of OEC3 flag..

REVEAL_CLK_ERR

Bit 2: The internal clock for the RNG core is not revealed..

ENTROPY_ERR

Bit 3: The error refers to a fault in the bit sequence detected by the Entropy Monitor. Failed test is given by REPET_ERROR, and ADAPT_ERROR, OSCS_REPET_ERROR and OSCS_ADAPT_ERROR status flags..

VAL_READY

Bit 4: TRNG Value ready At least one 32-bit random value is available in the data FIFO. Note that application must ensure that a random is available in internal FIFO before starting a read otherwise a bus error will be generated..

FIFO_FULL

Bit 5: Indicates whether random data FIFO is full..

SRC_HEALTH_DONE

Bit 20: First run of noise source health test is completed.

REPET_ERROR

Bit 21: Noise source Repetition health test error.

ADAPT_ERROR

Bit 22: Noise source Adaptive 1024 health test error.

OSCS_HEALTH_DONE

Bit 23: First run of source health tests of individual oscillators composing the noise source are completed.Reserved.

OSCS_REPET_ERROR

Bit 24: Logical OR of repetition health test errors of individual oscillators composing the noise source..

OSCS_ADAPT_ERROR

Bit 25: Logical OR of adaptive health test errors of individual oscillators composing the noise source..

VAL

TRNG_VAL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RND_VAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RND_VAL r

Toggle fields

RND_VAL

Bits 0-31: RND_VAL is a 32-bit Random Value. This is the output of the internal four-word FIFO. Note that application must ensure that a random is available in FIFO by ready VAL_READY flag before starting a read otherwise a null value will be returned..

OSCS_CR

TRNG_OSCS_CR register

Offset: 0x30, size: 32, reset: 0x80000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SYNC_OSCS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PWRD3 rw			PWRD2 rw			PWRD1 rw

Toggle fields

PWRD1

Bits 1-3: Power down of individual oscillators in triple-oscillator block number 1.

PWRD2

Bits 4-6: Power down of individual oscillators in triple-oscillator block number 2.

PWRD3

Bits 7-9: Power down of individual oscillators in triple-oscillator block number 3.

SYNC_OSCS

Bit 31: When set, selection of resynchronized output of oscillators..

POSTP_CR

TRNG_POSTP_CR register

Offset: 0x34, size: 32, reset: 0x00000F00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NB_RND_REINIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NB_LOOP_AES rw											AES_RESET rw

Toggle fields

AES_RESET

Bit 0: Reset AES post processing. When writing a 1, the AES post processing is reinitialized, resulting in a new key and new state generation before 128-bit random words generation. The '1' written is frozen until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. It also reruns analog source health tests..

NB_LOOP_AES

Bits 8-11: NB_LOOP_AES is the number of 128-bit words got from the noise source that have to be processed by AES for generating a single 128-bit random word. By default, this value is set to 2 (128 bits generated before an AES processing). 0 value means 16 loops. A new AES processing is started only when the previous one is completed..

NB_RND_REINIT

Bits 16-31: Number of 128-bit random words generated before AES automatically resets. This number is in the range of 1 to 65535 words. Value 0x0000 means that AES is never reinitialized..

POSTP_SR

TRNG_POSTP_SR register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									AES_DOUT_ERROR r	AES_K12_ERROR r	AES_HEALTH_DONE r	AES_BUSY r	AES_KEY_LD r	AES_INIT r

Toggle fields

AES_INIT

Bit 1: AES Post processing has been fully initialized (key and state) and is ready for generating 128-bit random words..

AES_KEY_LD

Bit 2: AES random key has been generated and loaded in AES key register..

AES_BUSY

Bit 3: AES core is busy, generating a random value..

AES_HEALTH_DONE

Bit 4: AES-CMAC health test is completed.

AES_K12_ERROR

Bit 5: Health test error on AES-CMAC sub-keys generation.

AES_DOUT_ERROR

Bit 6: Health test error on AES-CMAC output generation.

DEFKEY0

TRNG_DEFKEY0 register

Offset: 0x40, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNG_DEFKEY0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNG_DEFKEY0 rw

Toggle fields

RNG_DEFKEY0

Bits 0-31: Bits 31 to 0 of AES 128-bit Default Key..

DEFKEY1

TRNG_DEFKEY1 register

Offset: 0x44, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNG_DEFKEY1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNG_DEFKEY1 rw

Toggle fields

RNG_DEFKEY1

Bits 0-31: Bits 63 to 31 of AES 128-bit Default Key..

DEFKEY2

TRNG_DEFKEY2 register

Offset: 0x48, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNG_DEFKEY2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNG_DEFKEY2 rw

Toggle fields

RNG_DEFKEY2

Bits 0-31: Bits 95 to 64 of AES 128-bit Default Key..

DEFKEY3

TRNG_DEFKEY3 register

Offset: 0x4c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNG_DEFKEY3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNG_DEFKEY3 rw

Toggle fields

RNG_DEFKEY3

Bits 0-31: Bits 127 to 96 of AES 128-bit Default Key..

HEALTH_CR

TRNG_HEALTH_CR register

Offset: 0x60, size: 32, reset: 0x02BB0033, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ITER_ADAP rw				ADAP_CUTOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REPET_CUTOFF rw

Toggle fields

REPET_CUTOFF

Bits 0-7: Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

ADAP_CUTOFF

Bits 16-25: Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

ITER_ADAP

Bits 28-29: Number of iterations minus 1 of Adaptive test during initialization phase. Default value is set to 0 i.e. 1 iteration..

HEALTH_OSC1_CR

TRNG_HEALTH_OSC1_CR register

Offset: 0x68, size: 32, reset: 0x03E300FB, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						ADAP_CUTOFF_OSC1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REPET_CUTOFF_OSC1 rw

Toggle fields

REPET_CUTOFF_OSC1

Bits 0-7: Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

ADAP_CUTOFF_OSC1

Bits 16-25: Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

HEALTH_OSC2_CR

TRNG_HEALTH_OSC2_CR register

Offset: 0x6c, size: 32, reset: 0x03E300FB, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						ADAP_CUTOFF_OSC2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REPET_CUTOFF_OSC2 rw

Toggle fields

REPET_CUTOFF_OSC2

Bits 0-7: Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

ADAP_CUTOFF_OSC2

Bits 16-25: Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

HEALTH_OSC3_CR

TRNG_HEALTH_OSC3_CR register

Offset: 0x70, size: 32, reset: 0x03E300FB, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						ADAP_CUTOFF_OSC3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REPET_CUTOFF_OSC3 rw

Toggle fields

REPET_CUTOFF_OSC3

Bits 0-7: Cutoff value of Repetition Test. The default value is set to 51. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

ADAP_CUTOFF_OSC3

Bits 16-25: Cutoff value of Adaptive Test. The default value is set to 699. Caution: To be handled with care as any change can lead to misbehavior of TRNG..

HEALTH_OSC1_SR

TRNG_HEALTH_OSC1_SR register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TO3_ADAPT_ERROR r	TO3_REPET_ERROR r	TO2_ADAPT_ERROR r	TO2_REPET_ERROR r	TO1_ADAPT_ERROR r	TO1_REPET_ERROR r

Toggle fields

TO1_REPET_ERROR

Bit 0: Repetition error flag of first oscillator of first triple-oscillator cell..

TO1_ADAPT_ERROR

Bit 1: Adaptive error flag of first oscillator of first triple-oscillator cell..

TO2_REPET_ERROR

Bit 2: Repetition error flag of first oscillator of second triple-oscillator cell..

TO2_ADAPT_ERROR

Bit 3: Adaptive error flag of first oscillator of second triple-oscillator cell..

TO3_REPET_ERROR

Bit 4: Repetition error flag of first oscillator of third triple-oscillator cell..

TO3_ADAPT_ERROR

Bit 5: Adaptive error flag of first oscillator of third triple-oscillator cell..

HEALTH_OSC2_SR

TRNG_HEALTH_OSC2_SR register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TO3_ADAPT_ERROR r	TO3_REPET_ERROR r	TO2_ADAPT_ERROR r	TO2_REPET_ERROR r	TO1_ADAPT_ERROR r	TO1_REPET_ERROR r

Toggle fields

TO1_REPET_ERROR

Bit 0: Repetition error flag of first oscillator of first triple-oscillator cell..

TO1_ADAPT_ERROR

Bit 1: Adaptive error flag of first oscillator of first triple-oscillator cell..

TO2_REPET_ERROR

Bit 2: Repetition error flag of first oscillator of second triple-oscillator cell..

TO2_ADAPT_ERROR

Bit 3: Adaptive error flag of first oscillator of second triple-oscillator cell..

TO3_REPET_ERROR

Bit 4: Repetition error flag of first oscillator of third triple-oscillator cell..

TO3_ADAPT_ERROR

Bit 5: Adaptive error flag of first oscillator of third triple-oscillator cell..

HEALTH_OSC3_SR

TRNG_HEALTH_OSC3_SR register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TO3_ADAPT_ERROR r	TO3_REPET_ERROR r	TO2_ADAPT_ERROR r	TO2_REPET_ERROR r	TO1_ADAPT_ERROR r	TO1_REPET_ERROR r

Toggle fields

TO1_REPET_ERROR

Bit 0: Repetition error flag of third oscillator of first triple-oscillator cell..

TO1_ADAPT_ERROR

Bit 1: Adaptive error flag of first oscillator of first triple-oscillator cell..

TO2_REPET_ERROR

Bit 2: Repetition error flag of first oscillator of second triple-oscillator cell..

TO2_ADAPT_ERROR

Bit 3: Adaptive error flag of first oscillator of second triple-oscillator cell..

TO3_REPET_ERROR

Bit 4: Repetition error flag of first oscillator of third triple-oscillator cell..

TO3_ADAPT_ERROR

Bit 5: Adaptive error flag of first oscillator of third triple-oscillator cell..

IRQ_CR

TRNG_IRQ_CR register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							EN_ERROR_IRQ rw								EN_FF_FULL_IRQ rw

Toggle fields

EN_FF_FULL_IRQ

Bit 0: Enable the interrupt when the output fifo is full of new random..

EN_ERROR_IRQ

Bit 8: Enable the interrupt when an error is reported by the health tests..

IRQ_SR

TRNG_IRQ_SR register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							ERROR_IRQ r								FF_FULL_IRQ r

Toggle fields

FF_FULL_IRQ

Bit 0: Set to 1 when the output fifo is full of new random. Flag is cleared by writing a 1..

ERROR_IRQ

Bit 8: Set to 1 when an error is reported by the health tests. Flag is cleared by writing a 1..

USART

0x41004000:

119/119 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE		UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw		UE rw

Toggle fields

UE

Bit 0: UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

RE

Bit 2: RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: OVER8: Oversampling mode -0: Oversampling by 16 This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0)..

Allowed values: 0x0-0x1f

RTOIE

Bit 26: RTOIE: Receiver timeout interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: EOBIE: End of Block interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled..

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. -0: Slave mode disabled. -1: Slave mode enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored. -0: SPI slave selection depends on NSS input pin. -1: SPI slave will be always selected and NSS input pin will be ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0).

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. -0: 10-bit break detection -1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LBDIE: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). -0: Interrupt is inhibited -1: An interrupt is generated whenever LBDF=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: LBCL: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. -0: The clock pulse of the last data bit is not output to the SCLK pin -1: The clock pulse of the last data bit is output to the SCLK pin Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: CPHA: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 137 and Figure 138) -0: The first clock transition is the first data capture edge -1: The second clock transition is the first data capture edge This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: CPOL: Clock polarity This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship -0: Steady low value on SCLK pin outside transmission window -1: Steady high value on SCLK pin outside transmission window This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: CLKEN: Clock enable This bit allows the user to enable the SCLK pin. -0: SCLK pin disabled -1: SCLK pin enabled This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced by hardware to 0'. Please refer to Section 23.4: USART implementation on page 483. Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LINEN: LIN mode enable This bit is set and cleared by software. -0: LIN mode disabled -1: LIN mode enabled The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: ABREN: Auto baud rate enable This bit is set and cleared by software. -0: Auto baud rate detection is disabled. -1: Auto baud rate detection is enabled..

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: ABRMOD[1:0]: Auto baud rate mode These bits are set and cleared by software. -00: Measurement of the start bit is used to detect the baud rate. -01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) -10: 0x7F frame detection. -11: 0x55 frame detection This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0)..

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: RTOEN: Receiver timeout enable This bit is set and cleared by software. -0: Receiver timeout feature disabled. -1: Receiver timeout feature enabled. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register)..

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).

Allowed values: 0x0-0xff

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register..

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: IREN: IrDA mode enable This bit is set and cleared by software. -0: IrDA disabled -1: IrDA enabled This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes -0: Normal mode -1: Low-power mode This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: NACK: Smartcard NACK enable -0: NACK transmission in case of parity error is disabled -1: NACK transmission during parity error is enabled This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. -0: Smartcard Mode disabled -1: Smartcard Mode enabled This bit field can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0).

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: ONEBIT: One sample bit method enable This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NF) is disabled. -0: Three sample bit method -1: One sample bit method This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0)..

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: SCARCNT[2:0]: Smartcard auto-retry count This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bit field must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to stop retransmission. -0x0: retransmission disabled No automatic retransmission in transmit mode. -0x1 to 0x7: number of automatic retransmission attempts (before signaling error).

Allowed values: 0x0-0x7

TXFTIE

Bit 23: TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG..

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved..

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG..

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved..

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

BRR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR[15:4] BRR[15:4] = USARTDIV[15:4]BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared.

Allowed values: 0x0-0xffff

GTPR

GTPR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: PSC[7:0]: Prescaler value In IrDA Low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power Baud Rate Used for programming the prescaler for dividing the USART source clock to achieve the lowpower frequency: The source clock is divided by the value given in the register (8 significant bits): -00000000: Reserved do not program this value -00000001: divides the source clock by 1 -00000010: divides the source clock by 2 ... In Smartcard mode: PSC[4:0]: Prescaler value Used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: -00000: Reserved do not program this value -00001: divides the source clock by 2 -00010: divides the source clock by 4 -00011: divides the source clock by 6 ... This bit field can only be written when the USART is disabled (UE=0)..

Allowed values: 0x0-0xff

GT

Bits 8-15: GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bit field can only be written when the USART is disabled (UE=0)..

Allowed values: 0x0-0xff

RTOR

RTOR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

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RTO

Bits 0-23: RTO[23:0]: Receiver timeout value This bit-field gives the Receiver timeout value in terms of number of baud clocks. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the Start Bit of the last received character..

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) 1. Examples: BLEN = 0 -> 0 information characters + LEC BLEN = 1 -> 0 information characters + CRC BLEN = 255 -> 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bit-field can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1..

Allowed values: 0x0-0xff

RQR

RQR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

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ABRRQ

Bit 0: ABRRQ: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame..

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available..

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag..

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition..

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0' When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes..

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

ISR register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read..

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. -0: LIN Break not detected -1: LIN break detected.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. -0: Timeout value not reached -1: Timeout value reached without any data reception.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF: End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. -0: End of Block not reached -1: End of Block (number of characters) reached.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: UDR: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock for data transmission appears while the software has not yet loaded any value into USARTx_DR. -0: No underrun error -1: underrun error.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register.

ABRF

Bit 15: ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register..

BUSY

Bit 16: BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode.

TEACK

Bit 21: TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode..

TXFE

Bit 23: TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty..

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full..

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT: Transmission complete before guard time flagl This bit indicates when the last data written in the USART_TDR has been transmitted correctly out of the shift register . It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if there is no NACK from the smartcard. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. -0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is received from the card) -1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)..

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesn't reach the programmed threshold. -1: Receive FIFO reached the programmed threshold.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesn't reach the programmed threshold. -1: TXFIFO reached the programmed threshold.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

ICR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w1c
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w1c	EOBCF w1c	RTOCF w1c		CTSCF w1c	LBDCF w1c	TCBGTCF w1c	TCCF w1c	TXFECF w1c	IDLECF w1c	ORECF w1c	NECF w1c	FECF w1c	PECF w1c

Toggle fields

PECF

Bit 0: PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NECF

Bit 2: NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LBDCF: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: RTOCF: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register..

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: EOBCF: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF:SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

RDR

RDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

Allowed values: 0x0-0x1ff

TDR

TDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1..

Allowed values: 0x0-0x1ff

PRESC

PRESC register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be '1011' i.e. input clock divided by 256.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

WAKEUP

0x60001800:

6/20 fields covered.

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Offset	Name	31	30	29	15	13	7	3	1	0
0x8	OFFSET						WAKEUP_OFFSET
0x10	ABSOLUTE_TIME	ABSOLUTE_TIME			ABSOLUTE_TIME
0x14	MINIMUM_PERIOD_LENGTH					LENGTH
0x18	AVERAGE_PERIOD_LENGTH	AVERAGE_COUNT				LENGTH_INT		LENGTH_FRACT
0x1c	MAXIMUM_PERIOD_LENGTH					LENGTH
0x20	STATISTICS_RESTART								CLR_AVR	CLR_MIN_MAX
0x24	BLUE_WAKEUP_TIME	WAKEUP_TIME			WAKEUP_TIME
0x28	BLUE_SLEEP_REQUEST_MODE	FORCE_SLEEPING	BLE_WAKEUP_EN	SLEEP_EN
0x2c	CM0_WAKEUP_TIME	WAKEUP_TIME			WAKEUP_TIME
0x30	CM0_SLEEP_REQUEST_MODE	FORCE_SLEEPING	CPU_WAKEUP_EN
0x40	BLE_IRQ_ENABLE									WAKEUP_IT
0x44	BLE_IRQ_STATUS									WAKEUP_IT
0x48	CM0_IRQ_ENABLE									WAKEUP_IT
0x4c	CM0_IRQ_STATUS									WAKEUP_IT

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OFFSET

WAKEUP_OFFSET register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WAKEUP_OFFSET rw

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WAKEUP_OFFSET

Bits 0-7: delay of anticipation of the Soc device to settle power and clock.

ABSOLUTE_TIME

ABSOLUTE_TIME register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ABSOLUTE_TIME r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABSOLUTE_TIME r

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ABSOLUTE_TIME

Bits 0-31: absolute time.

MINIMUM_PERIOD_LENGTH

MINIMUM_PERIOD_LENGTH register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LENGTH r

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LENGTH

Bits 4-13: minimum period length computed by Time Interpolator.

AVERAGE_PERIOD_LENGTH

AVERAGE_PERIOD_LENGTH register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AVERAGE_COUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LENGTH_INT r										LENGTH_FRACT r

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LENGTH_FRACT

Bits 0-3: additional information/precision on slow clock frequency..

LENGTH_INT

Bits 4-13: average period length computed by Time Interpolator..

AVERAGE_COUNT

Bits 24-31: Number of slow clock cycles..

MAXIMUM_PERIOD_LENGTH

MAXIMUM_PERIOD_LENGTH register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LENGTH r

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LENGTH

Bits 4-13: maximum period length computed by Time Interpolator.

STATISTICS_RESTART

STATISTICS_RESTART register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CLR_AVR rw	CLR_MIN_MAX rw

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CLR_MIN_MAX

Bit 0: Write '1' to clear the minimum and maximum registers..

CLR_AVR

Bit 1: Write '1' to clear the AVERAGE_PERIOD_LENGTH register value..

BLUE_WAKEUP_TIME

BLUE_WAKEUP_TIME register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WAKEUP_TIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WAKEUP_TIME rw

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WAKEUP_TIME

Bits 0-31: programmed wakeup time for the IP_BLE..

BLUE_SLEEP_REQUEST_MODE

BLUE_SLEEP_REQUEST_MODE register

Offset: 0x28, size: 32, reset: 0x00000007, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FORCE_SLEEPING rw	BLE_WAKEUP_EN rw	SLEEP_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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SLEEP_EN

Bit 29: IP_BLE sleeping mode enable:.

BLE_WAKEUP_EN

Bit 30: IP_BLE wakeup enable:.

FORCE_SLEEPING

Bit 31: IP_BLE sleeping control:.

CM0_WAKEUP_TIME

CM0_WAKEUP_TIME register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WAKEUP_TIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WAKEUP_TIME rw

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WAKEUP_TIME

Bits 4-31: programmed wakeup time for CPU..

CM0_SLEEP_REQUEST_MODE

CM0_SLEEP_REQUEST_MODE register

Offset: 0x30, size: 32, reset: 0x80000007, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FORCE_SLEEPING rw	CPU_WAKEUP_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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CPU_WAKEUP_EN

Bit 30: CPU wakeup enable:.

FORCE_SLEEPING

Bit 31: CPU sleeping control:.

BLE_IRQ_ENABLE

WAKEUP_BLE_IRQ_ENABLE register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: IP_BLE wakeup interrupt enable:.

BLE_IRQ_STATUS

WAKEUP_BLE_IRQ_STATUS register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: On read, returns the IP_BLE wakeup interrupt status..

CM0_IRQ_ENABLE

WAKEUP_CM0_IRQ_ENABLE register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: CPU wakeup interrupt enable:.

CM0_IRQ_STATUS

WAKEUP_CM0_IRQ_STATUS register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WAKEUP_IT rw

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WAKEUP_IT

Bit 0: On read, returns the CPU wakeup interrupt status..