STM32WB55 Peripheral Coverage

ADC1

0x50040000: Analog to Digital Converter instance 1

7/131 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR																						JQOVF	AWD3	AWD2	AWD1	JEOS	JEOC	OVR	EOS	EOC	EOSMP	ADRDY
0x4	IER																						JQOVFIE	AWD3IE	AWD2IE	AWD1IE	JEOSIE	JEOCIE	OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	CR	ADCAL	ADCALDIF	DEEPPWD	ADVREGEN																							JADSTP	ADSTP	JADSTART	ADSTART	ADDIS	ADEN
0xc	CFGR	JQDIS	AWDCH1CH					JAUTO	JAWD1EN	AWD1EN	AWD1SGL	JQM	JDISCEN	DISCNUM			DISCEN		AUTDLY	CONT	OVRMOD	EXTEN		EXTSEL				ALIGN	RES			DMACFG	DMAEN
0x10	CFGR2																						ROVSM	TOVS	OVSS				OVSR			JOVSE	ROVSE
0x14	SMPR1			SMP9			SMP8			SMP7			SMP6			SMP5		SMP5	SMP4			SMP3			SMP2			SMP1			SMP0
0x18	SMPR2						SMP18			SMP17			SMP16			SMP15		SMP15	SMP14			SMP13			SMP12			SMP11			SMP10
0x20	TR1					HT1																LT1
0x24	TR2									HT2																LT2
0x28	TR3									HT3																LT3
0x30	SQR1				SQ4						SQ3						SQ2	SQ2					SQ1							L
0x34	SQR2				SQ9						SQ8						SQ7	SQ7					SQ6						SQ5
0x38	SQR3				SQ14						SQ13						SQ12	SQ12					SQ11						SQ10
0x3c	SQR4																						SQ16						SQ15
0x40	DR																	RDATA_7_15										RDATA_0_6
0x4c	JSQR		JSQ4						JSQ3						JSQ2			JSQ2			JSQ1					JEXTEN		JEXTSEL				JL
0x60	OFR1	OFFSET1_EN	OFFSET1_CH																			OFFSET1
0x64	OFR2	OFFSET2_EN	OFFSET2_CH																			OFFSET2
0x68	OFR3	OFFSET3_EN	OFFSET3_CH																			OFFSET3
0x6c	OFR4	OFFSET4_EN	OFFSET4_CH																			OFFSET4
0x80	JDR1																	JDATA1
0x84	JDR2																	JDATA2
0x88	JDR3																	JDATA3
0x8c	JDR4																	JDATA4
0xa0	AWD2CR														AWD2CH			AWD2CH
0xa4	AWD3CR														AWD3CH			AWD3CH
0xb0	DIFSEL														DIFSEL_16_18			DIFSEL_1_15															DIFSEL_0
0xb4	CALFACT										CALFACT_D																CALFACT_S

Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					JQOVF rw	AWD3 rw	AWD2 rw	AWD1 rw	JEOS rw	JEOC rw	OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle fields

ADRDY

Bit 0: ADC ready flag.

EOSMP

Bit 1: ADC group regular end of sampling flag.

EOC

Bit 2: ADC group regular end of unitary conversion flag.

EOS

Bit 3: ADC group regular end of sequence conversions flag.

OVR

Bit 4: ADC group regular overrun flag.

JEOC

Bit 5: ADC group injected end of unitary conversion flag.

JEOS

Bit 6: ADC group injected end of sequence conversions flag.

AWD1

Bit 7: ADC analog watchdog 1 flag.

AWD2

Bit 8: ADC analog watchdog 2 flag.

AWD3

Bit 9: ADC analog watchdog 3 flag.

JQOVF

Bit 10: ADC group injected contexts queue overflow flag.

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					JQOVFIE rw	AWD3IE rw	AWD2IE rw	AWD1IE rw	JEOSIE rw	JEOCIE rw	OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle fields

ADRDYIE

Bit 0: ADC ready interrupt.

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

OVRIE

Bit 4: ADC group regular overrun interrupt.

JEOCIE

Bit 5: ADC group injected end of unitary conversion interrupt.

JEOSIE

Bit 6: ADC group injected end of sequence conversions interrupt.

AWD1IE

Bit 7: ADC analog watchdog 1 interrupt.

AWD2IE

Bit 8: ADC analog watchdog 2 interrupt.

AWD3IE

Bit 9: ADC analog watchdog 3 interrupt.

JQOVFIE

Bit 10: ADC group injected contexts queue overflow interrupt.

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL rw	ADCALDIF rw	DEEPPWD rw	ADVREGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										JADSTP rw	ADSTP rw	JADSTART rw	ADSTART rw	ADDIS rw	ADEN rw

Toggle fields

ADEN

Bit 0: ADC enable.

ADDIS

Bit 1: ADC disable.

ADSTART

Bit 2: ADC group regular conversion start.

JADSTART

Bit 3: ADC group injected conversion start.

ADSTP

Bit 4: ADC group regular conversion stop.

JADSTP

Bit 5: ADC group injected conversion stop.

ADVREGEN

Bit 28: ADC voltage regulator enable.

DEEPPWD

Bit 29: ADC deep power down enable.

ADCALDIF

Bit 30: ADC differential mode for calibration.

ADCAL

Bit 31: ADC calibration.

CFGR

ADC configuration register 1

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JQDIS rw	AWDCH1CH rw					JAUTO rw	JAWD1EN rw	AWD1EN rw	AWD1SGL rw	JQM rw	JDISCEN rw	DISCNUM rw			DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	AUTDLY rw	CONT rw	OVRMOD rw	EXTEN rw		EXTSEL rw				ALIGN rw	RES rw			DMACFG rw	DMAEN rw

Toggle fields

DMAEN

Bit 0: ADC DMA transfer enable.

DMACFG

Bit 1: ADC DMA transfer configuration.

RES

Bits 3-4: ADC data resolution.

ALIGN

Bit 5: ADC data alignement.

EXTSEL

Bits 6-9: ADC group regular external trigger source.

EXTEN

Bits 10-11: ADC group regular external trigger polarity.

OVRMOD

Bit 12: ADC group regular overrun configuration.

CONT

Bit 13: ADC group regular continuous conversion mode.

AUTDLY

Bit 14: ADC low power auto wait.

DISCEN

Bit 16: ADC group regular sequencer discontinuous mode.

DISCNUM

Bits 17-19: ADC group regular sequencer discontinuous number of ranks.

JDISCEN

Bit 20: ADC group injected sequencer discontinuous mode.

JQM

Bit 21: ADC group injected contexts queue mode.

AWD1SGL

Bit 22: ADC analog watchdog 1 monitoring a single channel or all channels.

AWD1EN

Bit 23: ADC analog watchdog 1 enable on scope ADC group regular.

JAWD1EN

Bit 24: ADC analog watchdog 1 enable on scope ADC group injected.

JAUTO

Bit 25: ADC group injected automatic trigger mode.

AWDCH1CH

Bits 26-30: ADC analog watchdog 1 monitored channel selection.

JQDIS

Bit 31: ADC group injected contexts queue disable.

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					ROVSM rw	TOVS rw	OVSS rw				OVSR rw			JOVSE rw	ROVSE rw

Toggle fields

ROVSE

Bit 0: ADC oversampler enable on scope ADC group regular.

JOVSE

Bit 1: ADC oversampler enable on scope ADC group injected.

OVSR

Bits 2-4: ADC oversampling ratio.

OVSS

Bits 5-8: ADC oversampling shift.

TOVS

Bit 9: ADC oversampling discontinuous mode (triggered mode) for ADC group regular.

ROVSM

Bit 10: ADC oversampling mode managing interlaced conversions of ADC group regular and group injected.

SMPR1

ADC sampling time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP9 rw			SMP8 rw			SMP7 rw			SMP6 rw			SMP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5 rw	SMP4 rw			SMP3 rw			SMP2 rw			SMP1 rw			SMP0 rw

Toggle fields

SMP0

Bits 0-2: Channel 0 sampling time selection.

SMP1

Bits 3-5: Channel 1 sampling time selection.

SMP2

Bits 6-8: Channel 2 sampling time selection.

SMP3

Bits 9-11: Channel 3 sampling time selection.

SMP4

Bits 12-14: Channel 4 sampling time selection.

SMP5

Bits 15-17: Channel 5 sampling time selection.

SMP6

Bits 18-20: Channel 6 sampling time selection.

SMP7

Bits 21-23: Channel 7 sampling time selection.

SMP8

Bits 24-26: Channel 8 sampling time selection.

SMP9

Bits 27-29: Channel 9 sampling time selection.

SMPR2

ADC sampling time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SMP18 rw			SMP17 rw			SMP16 rw			SMP15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15 rw	SMP14 rw			SMP13 rw			SMP12 rw			SMP11 rw			SMP10 rw

Toggle fields

SMP10

Bits 0-2: Channel 10 sampling time selection.

SMP11

Bits 3-5: Channel 11 sampling time selection.

SMP12

Bits 6-8: Channel 12 sampling time selection.

SMP13

Bits 9-11: Channel 13 sampling time selection.

SMP14

Bits 12-14: Channel 14 sampling time selection.

SMP15

Bits 15-17: Channel 15 sampling time selection.

SMP16

Bits 18-20: Channel 16 sampling time selection.

SMP17

Bits 21-23: Channel 17 sampling time selection.

SMP18

Bits 24-26: Channel 18 sampling time selection.

TR1

ADC analog watchdog 1 threshold register

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT1 rw

Toggle fields

LT1

Bits 0-11: ADC analog watchdog 1 threshold low.

HT1

Bits 16-27: ADC analog watchdog 1 threshold high.

TR2

ADC analog watchdog 2 threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HT2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LT2 rw

Toggle fields

LT2

Bits 0-7: ADC analog watchdog 2 threshold low.

HT2

Bits 16-23: ADC analog watchdog 2 threshold high.

TR3

ADC analog watchdog 3 threshold register

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HT3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LT3 rw

Toggle fields

LT3

Bits 0-7: ADC analog watchdog 3 threshold low.

HT3

Bits 16-23: ADC analog watchdog 3 threshold high.

SQR1

ADC group regular sequencer ranks register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ4 rw						SQ3 rw						SQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ2 rw					SQ1 rw							L rw

Toggle fields

L

Bits 0-3: Regular channel sequence length.

SQ1

Bits 6-10: ADC group regular sequencer rank 1.

SQ2

Bits 12-16: ADC group regular sequencer rank 2.

SQ3

Bits 18-22: ADC group regular sequencer rank 3.

SQ4

Bits 24-28: ADC group regular sequencer rank 4.

SQR2

ADC group regular sequencer ranks register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ9 rw						SQ8 rw						SQ7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ7 rw					SQ6 rw						SQ5 rw

Toggle fields

SQ5

Bits 0-4: ADC group regular sequencer rank 5.

SQ6

Bits 6-10: ADC group regular sequencer rank 6.

SQ7

Bits 12-16: ADC group regular sequencer rank 7.

SQ8

Bits 18-22: ADC group regular sequencer rank 8.

SQ9

Bits 24-28: ADC group regular sequencer rank 9.

SQR3

ADC group regular sequencer ranks register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ14 rw						SQ13 rw						SQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ12 rw					SQ11 rw						SQ10 rw

Toggle fields

SQ10

Bits 0-4: ADC group regular sequencer rank 10.

SQ11

Bits 6-10: ADC group regular sequencer rank 11.

SQ12

Bits 12-16: ADC group regular sequencer rank 12.

SQ13

Bits 18-22: ADC group regular sequencer rank 13.

SQ14

Bits 24-28: ADC group regular sequencer rank 14.

SQR4

ADC group regular sequencer ranks register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SQ16 rw						SQ15 rw

Toggle fields

SQ15

Bits 0-4: ADC group regular sequencer rank 15.

SQ16

Bits 6-10: ADC group regular sequencer rank 16.

DR

ADC group regular conversion data register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_7_15 r										RDATA_0_6 rw

Toggle fields

RDATA_0_6

Bits 0-5: Regular Data converted 0_6.

RDATA_7_15

Bits 7-15: 15.

JSQR

ADC group injected sequencer register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	JSQ4 rw						JSQ3 rw						JSQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ2 rw			JSQ1 rw					JEXTEN rw		JEXTSEL rw				JL rw

Toggle fields

JL

Bits 0-1: ADC group injected sequencer scan length.

JEXTSEL

Bits 2-5: ADC group injected external trigger source.

JEXTEN

Bits 6-7: ADC group injected external trigger polarity.

JSQ1

Bits 8-12: ADC group injected sequencer rank 1.

JSQ2

Bits 14-18: ADC group injected sequencer rank 2.

JSQ3

Bits 20-24: ADC group injected sequencer rank 3.

JSQ4

Bits 26-30: ADC group injected sequencer rank 4.

OFR1

ADC offset number 1 register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET1_EN rw	OFFSET1_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET1 rw

Toggle fields

OFFSET1

Bits 0-11: ADC offset number 1 offset level.

OFFSET1_CH

Bits 26-30: ADC offset number 1 channel selection.

OFFSET1_EN

Bit 31: ADC offset number 1 enable.

OFR2

ADC offset number 2 register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET2_EN rw	OFFSET2_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET2 rw

Toggle fields

OFFSET2

Bits 0-11: ADC offset number 2 offset level.

OFFSET2_CH

Bits 26-30: ADC offset number 2 channel selection.

OFFSET2_EN

Bit 31: ADC offset number 2 enable.

OFR3

ADC offset number 3 register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET3_EN rw	OFFSET3_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET3 rw

Toggle fields

OFFSET3

Bits 0-11: ADC offset number 3 offset level.

OFFSET3_CH

Bits 26-30: ADC offset number 3 channel selection.

OFFSET3_EN

Bit 31: ADC offset number 3 enable.

OFR4

ADC offset number 4 register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET4_EN rw	OFFSET4_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET4 rw

Toggle fields

OFFSET4

Bits 0-11: ADC offset number 4 offset level.

OFFSET4_CH

Bits 26-30: ADC offset number 4 channel selection.

OFFSET4_EN

Bit 31: ADC offset number 4 enable.

JDR1

ADC group injected sequencer rank 1 register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA1 r

Toggle fields

JDATA1

Bits 0-15: ADC group injected sequencer rank 1 conversion data.

JDR2

ADC group injected sequencer rank 2 register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA2 r

Toggle fields

JDATA2

Bits 0-15: ADC group injected sequencer rank 2 conversion data.

JDR3

ADC group injected sequencer rank 3 register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA3 r

Toggle fields

JDATA3

Bits 0-15: ADC group injected sequencer rank 3 conversion data.

JDR4

ADC group injected sequencer rank 4 register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA4 r

Toggle fields

JDATA4

Bits 0-15: ADC group injected sequencer rank 4 conversion data.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AWD2CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH rw

Toggle fields

AWD2CH

Bits 0-18: ADC analog watchdog 2 monitored channel selection.

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AWD3CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH rw

Toggle fields

AWD3CH

Bits 0-18: ADC analog watchdog 3 monitored channel selection.

DIFSEL

ADC channel differential or single-ended mode selection register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DIFSEL_16_18 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIFSEL_1_15 rw															DIFSEL_0 r

Toggle fields

DIFSEL_0

Bit 0: ADC channel differential or single-ended mode for channel 0.

DIFSEL_1_15

Bits 1-15: ADC channel differential or single-ended mode for channels 1 to 15.

DIFSEL_16_18

Bits 16-18: ADC channel differential or single-ended mode for channels 18 to 16.

CALFACT

ADC calibration factors register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									CALFACT_D rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CALFACT_S rw

Toggle fields

CALFACT_S

Bits 0-6: ADC calibration factor in single-ended mode.

CALFACT_D

Bits 16-22: ADC calibration factor in differential mode.

ADC_Common

0x50040300: ADC common registers

11/16 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CSR																						JQOVF_MST	AWD3_MST	AWD2_MST	AWD1_MST	JEOS_MST	JEOC_MST	OVR_MST	EOS_MST	EOC_MST	EOSMP_MST	ADRDY_MST
0x8	CCR								CH18SEL	CH17SEL	VREFEN	PRESC				CKMODE

Toggle registers

CSR

ADC common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					JQOVF_MST r	AWD3_MST r	AWD2_MST r	AWD1_MST r	JEOS_MST r	JEOC_MST r	OVR_MST r	EOS_MST r	EOC_MST r	EOSMP_MST r	ADRDY_MST r

Toggle fields

ADRDY_MST

Bit 0: master ADC ready.

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC.

EOC_MST

Bit 2: End of regular conversion flag of the master ADC.

EOS_MST

Bit 3: End of regular sequence flag of the master ADC.

OVR_MST

Bit 4: Overrun flag of the master ADC.

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC.

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC.

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC.

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC.

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC.

JQOVF_MST

Bit 10: Injected Context Queue Overflow flag of the master ADC.

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							CH18SEL rw	CH17SEL rw	VREFEN rw	PRESC rw				CKMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: Vrefint enable.

CH17SEL

Bit 23: CH17 selection (temperature).

CH18SEL

Bit 24: CH18 selection (Vbat).

AES1

0x50060000: Advanced encryption standard hardware accelerator 1

13/48 fields covered.

Toggle register map

Offset	Name	31	23	18	16	15	14	12	11	10	9	8	7	6	4	3	2	1	0
0x0	CR		NPBLB	KEYSIZE	CHMOD2		GCMPH	DMAOUTEN	DMAINEN	ERRIE	CCFIE	ERRC	CCFC	CHMOD10	MODE		DATATYPE		EN
0x4	SR															BUSY	WRERR	RDERR	CCF
0x8	DINR	AES_DINR				AES_DINR
0xc	DOUTR	AES_DOUTR				AES_DOUTR
0x10	KEYR0	AES_KEYR0				AES_KEYR0
0x14	KEYR1	AES_KEYR1				AES_KEYR1
0x18	KEYR2	AES_KEYR2				AES_KEYR2
0x1c	KEYR3	AES_KEYR3				AES_KEYR3
0x20	IVR0	AES_IVR0				AES_IVR0
0x24	IVR1	AES_IVR1				AES_IVR1
0x28	IVR2	AES_IVR2				AES_IVR2
0x2c	IVR3	AES_IVR3				AES_IVR3
0x30	KEYR4	AES_KEYR4				AES_KEYR4
0x34	KEYR5	AES_KEYR5				AES_KEYR5
0x38	KEYR6	AES_KEYR6				AES_KEYR6
0x3c	KEYR7	AES_KEYR7				AES_KEYR7
0x40	SUSP0R	AES_SUSP0R				AES_SUSP0R
0x44	SUSP1R	AES_SUSP1R				AES_SUSP1R
0x48	SUSP2R	AES_SUSP2R				AES_SUSP2R
0x4c	SUSP3R	AES_SUSP3R				AES_SUSP3R
0x50	SUSP4R	AES_SUSP4R				AES_SUSP4R
0x54	SUSP5R	AES_SUSP5R				AES_SUSP5R
0x58	SUSP6R	AES_SUSP6R				AES_SUSP6R
0x5c	SUSP7R	AES_SUSP7R				AES_SUSP7R
0x3f0	HWCFR					CFG4			CFG3				CFG2			CFG1
0x3f4	VERR												MAJREV			MINREV
0x3f8	IPIDR	ID				ID
0x3fc	SIDR	ID				ID

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								NPBLB rw					KEYSIZE rw		CHMOD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	GCMPH rw		DMAOUTEN rw	DMAINEN rw	ERRIE rw	CCFIE rw	ERRC rw	CCFC rw	CHMOD10 rw		MODE rw		DATATYPE rw		EN rw

Toggle fields

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD10

Bits 5-6: AES chaining mode Bit1 Bit0.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

CHMOD2

Bit 16: AES chaining mode Bit2.

KEYSIZE

Bit 18: Key size selection.

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BUSY r	WRERR r	RDERR r	CCF r

Toggle fields

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

BUSY

Bit 3: Busy flag.

DINR

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DINR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DINR rw

Toggle fields

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DOUTR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DOUTR r

Toggle fields

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR0 rw

Toggle fields

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR1 rw

Toggle fields

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR2 rw

Toggle fields

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR3 rw

Toggle fields

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR0 rw

Toggle fields

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR1 rw

Toggle fields

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR2 rw

Toggle fields

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR3 rw

Toggle fields

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

KEYR4

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR4 rw

Toggle fields

AES_KEYR4

Bits 0-31: AES key register (MSB key [159:128]).

KEYR5

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR5 rw

Toggle fields

AES_KEYR5

Bits 0-31: AES key register (MSB key [191:160]).

KEYR6

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR6 rw

Toggle fields

AES_KEYR6

Bits 0-31: AES key register (MSB key [223:192]).

KEYR7

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR7 rw

Toggle fields

AES_KEYR7

Bits 0-31: AES key register (MSB key [255:224]).

SUSP0R

AES suspend register 0

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP0R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP0R rw

Toggle fields

AES_SUSP0R

Bits 0-31: AES suspend register 0.

SUSP1R

AES suspend register 1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP1R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP1R rw

Toggle fields

AES_SUSP1R

Bits 0-31: AES suspend register 1.

SUSP2R

AES suspend register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP2R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP2R rw

Toggle fields

AES_SUSP2R

Bits 0-31: AES suspend register 2.

SUSP3R

AES suspend register 3

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP3R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP3R rw

Toggle fields

AES_SUSP3R

Bits 0-31: AES suspend register 3.

SUSP4R

AES suspend register 4

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP4R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP4R rw

Toggle fields

AES_SUSP4R

Bits 0-31: AES suspend register 4.

SUSP5R

AES suspend register 5

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP5R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP5R rw

Toggle fields

AES_SUSP5R

Bits 0-31: AES suspend register 5.

SUSP6R

AES suspend register 6

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP6R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP6R rw

Toggle fields

AES_SUSP6R

Bits 0-31: AES suspend register 6.

SUSP7R

AES suspend register 7

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP7R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP7R rw

Toggle fields

AES_SUSP7R

Bits 0-31: AES suspend register 7.

HWCFR

AES hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000002, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CFG4 r				CFG3 r				CFG2 r				CFG1 r

Toggle fields

CFG1

Bits 0-3: HW Generic 1.

CFG2

Bits 4-7: HW Generic 2.

CFG3

Bits 8-11: HW Generic 3.

CFG4

Bits 12-15: HW Generic 4.

VERR

AES version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle fields

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

AES identification register

Offset: 0x3f8, size: 32, reset: 0x00170023, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle fields

ID

Bits 0-31: Identification code.

SIDR

AES size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle fields

ID

Bits 0-31: Size Identification code.

AES2

0x58001800: Advanced encryption standard hardware accelerator 1

13/48 fields covered.

Toggle register map

Offset	Name	31	23	18	16	15	14	12	11	10	9	8	7	6	4	3	2	1	0
0x0	CR		NPBLB	KEYSIZE	CHMOD2		GCMPH	DMAOUTEN	DMAINEN	ERRIE	CCFIE	ERRC	CCFC	CHMOD10	MODE		DATATYPE		EN
0x4	SR															BUSY	WRERR	RDERR	CCF
0x8	DINR	AES_DINR				AES_DINR
0xc	DOUTR	AES_DOUTR				AES_DOUTR
0x10	KEYR0	AES_KEYR0				AES_KEYR0
0x14	KEYR1	AES_KEYR1				AES_KEYR1
0x18	KEYR2	AES_KEYR2				AES_KEYR2
0x1c	KEYR3	AES_KEYR3				AES_KEYR3
0x20	IVR0	AES_IVR0				AES_IVR0
0x24	IVR1	AES_IVR1				AES_IVR1
0x28	IVR2	AES_IVR2				AES_IVR2
0x2c	IVR3	AES_IVR3				AES_IVR3
0x30	KEYR4	AES_KEYR4				AES_KEYR4
0x34	KEYR5	AES_KEYR5				AES_KEYR5
0x38	KEYR6	AES_KEYR6				AES_KEYR6
0x3c	KEYR7	AES_KEYR7				AES_KEYR7
0x40	SUSP0R	AES_SUSP0R				AES_SUSP0R
0x44	SUSP1R	AES_SUSP1R				AES_SUSP1R
0x48	SUSP2R	AES_SUSP2R				AES_SUSP2R
0x4c	SUSP3R	AES_SUSP3R				AES_SUSP3R
0x50	SUSP4R	AES_SUSP4R				AES_SUSP4R
0x54	SUSP5R	AES_SUSP5R				AES_SUSP5R
0x58	SUSP6R	AES_SUSP6R				AES_SUSP6R
0x5c	SUSP7R	AES_SUSP7R				AES_SUSP7R
0x60	HWCFR					CFG4			CFG3				CFG2			CFG1
0x64	VERR												MAJREV			MINREV
0x68	IPIDR	ID				ID
0x6c	SIDR	ID				ID

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								NPBLB rw					KEYSIZE rw		CHMOD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	GCMPH rw		DMAOUTEN rw	DMAINEN rw	ERRIE rw	CCFIE rw	ERRC rw	CCFC rw	CHMOD10 rw		MODE rw		DATATYPE rw		EN rw

Toggle fields

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD10

Bits 5-6: AES chaining mode Bit1 Bit0.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

CHMOD2

Bit 16: AES chaining mode Bit2.

KEYSIZE

Bit 18: Key size selection.

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BUSY r	WRERR r	RDERR r	CCF r

Toggle fields

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

BUSY

Bit 3: Busy flag.

DINR

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DINR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DINR rw

Toggle fields

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DOUTR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DOUTR r

Toggle fields

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR0 rw

Toggle fields

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR1 rw

Toggle fields

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR2 rw

Toggle fields

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR3 rw

Toggle fields

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR0 rw

Toggle fields

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR1 rw

Toggle fields

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR2 rw

Toggle fields

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR3 rw

Toggle fields

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

KEYR4

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR4 rw

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AES_KEYR4

Bits 0-31: AES key register (MSB key [159:128]).

KEYR5

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR5 rw

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AES_KEYR5

Bits 0-31: AES key register (MSB key [191:160]).

KEYR6

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR6 rw

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AES_KEYR6

Bits 0-31: AES key register (MSB key [223:192]).

KEYR7

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR7 rw

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AES_KEYR7

Bits 0-31: AES key register (MSB key [255:224]).

SUSP0R

AES suspend register 0

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP0R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP0R rw

Toggle fields

AES_SUSP0R

Bits 0-31: AES suspend register 0.

SUSP1R

AES suspend register 1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP1R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP1R rw

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AES_SUSP1R

Bits 0-31: AES suspend register 1.

SUSP2R

AES suspend register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP2R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP2R rw

Toggle fields

AES_SUSP2R

Bits 0-31: AES suspend register 2.

SUSP3R

AES suspend register 3

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP3R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP3R rw

Toggle fields

AES_SUSP3R

Bits 0-31: AES suspend register 3.

SUSP4R

AES suspend register 4

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP4R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP4R rw

Toggle fields

AES_SUSP4R

Bits 0-31: AES suspend register 4.

SUSP5R

AES suspend register 5

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP5R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP5R rw

Toggle fields

AES_SUSP5R

Bits 0-31: AES suspend register 5.

SUSP6R

AES suspend register 6

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP6R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP6R rw

Toggle fields

AES_SUSP6R

Bits 0-31: AES suspend register 6.

SUSP7R

AES suspend register 7

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP7R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP7R rw

Toggle fields

AES_SUSP7R

Bits 0-31: AES suspend register 7.

HWCFR

AES hardware configuration register

Offset: 0x60, size: 32, reset: 0x00000002, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CFG4 r				CFG3 r				CFG2 r				CFG1 r

Toggle fields

CFG1

Bits 0-3: HW Generic 1.

CFG2

Bits 4-7: HW Generic 2.

CFG3

Bits 8-11: HW Generic 3.

CFG4

Bits 12-15: HW Generic 4.

VERR

AES version register

Offset: 0x64, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

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MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

AES identification register

Offset: 0x68, size: 32, reset: 0x00170023, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

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ID

Bits 0-31: Identification code.

SIDR

AES size ID register

Offset: 0x6c, size: 32, reset: 0x00170023, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle fields

ID

Bits 0-31: Size Identification code.

COMP

0x40010200: Comparator instance 1

2/25 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	COMP1_CSR	COMP1_LOCK	COMP1_VALUE				COMP1_INMESEL			COMP1_SCALEN	COMP1_BRGEN		COMP1_BLANKING			COMP1_HYST		COMP1_POLARITY							COMP1_INPSEL		COMP1_INMSEL			COMP1_PWRMODE			COMP1_EN
0x4	COMP2_CSR	COMP2_LOCK	COMP2_VALUE				COMP2_INMESEL			COMP2_SCALEN	COMP2_BRGEN		COMP2_BLANKING			COMP2_HYST		COMP2_POLARITY						COMP2_WINMODE	COMP2_INPSEL			COMP2_INMSEL		COMP2_PWRMODE			COMP2_EN

Toggle registers

COMP1_CSR

Comparator control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP1_LOCK rw	COMP1_VALUE r				COMP1_INMESEL rw			COMP1_SCALEN rw	COMP1_BRGEN rw		COMP1_BLANKING rw			COMP1_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP1_POLARITY rw							COMP1_INPSEL rw		COMP1_INMSEL rw			COMP1_PWRMODE rw			COMP1_EN rw

Toggle fields

COMP1_EN

Bit 0: Comparator enable.

COMP1_PWRMODE

Bits 2-3: Comparator power mode.

COMP1_INMSEL

Bits 4-6: Comparator input minus selection.

COMP1_INPSEL

Bits 7-8: Comparator input plus selection.

COMP1_POLARITY

Bit 15: Comparator output polarity.

COMP1_HYST

Bits 16-17: Comparator hysteresis.

COMP1_BLANKING

Bits 18-20: Comparator blanking source.

COMP1_BRGEN

Bit 22: Comparator voltage scaler enable.

COMP1_SCALEN

Bit 23: Comparator scaler bridge enable.

COMP1_INMESEL

Bits 25-26: Comparator input minus extended selection.

COMP1_VALUE

Bit 30: Comparator output level.

COMP1_LOCK

Bit 31: Comparator lock.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP2_LOCK rw	COMP2_VALUE r				COMP2_INMESEL rw			COMP2_SCALEN rw	COMP2_BRGEN rw		COMP2_BLANKING rw			COMP2_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP2_POLARITY rw						COMP2_WINMODE rw	COMP2_INPSEL rw			COMP2_INMSEL rw		COMP2_PWRMODE rw			COMP2_EN rw

Toggle fields

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-5: Comparator 2 input minus selection bits.

COMP2_INPSEL

Bits 7-8: Comparator 1 input plus selection bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_INMESEL

Bits 25-26: comparator 2 input minus extended selection bits..

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	CRC_INIT	CRC_INIT
0x14	POL	POL	POL

Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

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DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle fields

IDR

Bits 0-31: General-purpose 32-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT rw

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CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle fields

POL

Bits 0-31: Programmable polynomial.

CRS

0x40006000: Clock recovery system

9/26 fields covered.

Toggle register map

Offset	Name	31	29	26	23	15	13	10	9	8	7	6	5	3	2	1	0
0x0	CR						TRIM				SWSYNC	AUTOTRIMEN	CEN	ESYNCIE	ERRIE	SYNCWARNIE	SYNCOKIE
0x4	CFGR	SYNCPOL	SYNCSRC	SYNCDIV	FELIM	RELOAD
0x8	ISR	FECAP				FEDIR		TRIMOVF	SYNCMISS	SYNCERR				ESYNCF	ERRF	SYNCWARNF	SYNCOKF
0xc	ICR													ESYNCC	ERRC	SYNCWARNC	SYNCOKC

Toggle registers

CR

CRS control register

Offset: 0x0, size: 32, reset: 0x00002000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		TRIM rw						SWSYNC rw	AUTOTRIMEN rw	CEN rw		ESYNCIE rw	ERRIE rw	SYNCWARNIE rw	SYNCOKIE rw

Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Automatic trimming enable.

TRIM

Bits 8-13: HSI48 oscillator smooth trimming.

CFGR

CRS configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SYNCPOL rw		SYNCSRC rw			SYNCDIV rw			FELIM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNCDIV.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

CRS interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FECAP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FEDIR r					TRIMOVF r	SYNCMISS r	SYNCERR r					ESYNCF r	ERRF r	SYNCWARNF r	SYNCOKF r

Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

CRS interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ESYNCC rw	ERRC rw	SYNCWARNC rw	SYNCOKC rw

Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DBGMCU

0xe0042000: Debug support

2/28 fields covered.

Toggle register map

Offset	Name	31	28	23	21	18	17	12	11	10	5	2	1	0
0x0	IDCODE	REV_ID							DEV_ID
0x4	CR		TRGOEN								TRACE_IOEN	DBG_STANDBY	DBG_STOP	DBG_SLEEP
0x3c	APB1FZR1	DBG_LPTIM1_STOP		DBG_I2C3_STOP	DBG_I2C1_STOP			DBG_IWDG_STOP	DBG_WWDG_STOP	DBG_RTC_STOP				DBG_TIMER2_STOP
0x40	C2AP_B1FZR1	DBG_LPTIM1_STOP		DBG_I2C3_STOP	DBG_I2C1_STOP			DBG_IWDG_STOP		DBG_RTC_STOP				DBG_LPTIM2_STOP
0x44	APB1FZR2										DBG_LPTIM2_STOP
0x48	C2APB1FZR2										DBG_LPTIM2_STOP
0x48	C2APB2FZR					DBG_TIM17_STOP	DBG_TIM16_STOP		DBG_TIM1_STOP
0x4c	APB2FZR					DBG_TIM17_STOP	DBG_TIM16_STOP		DBG_TIM1_STOP

Toggle registers

IDCODE

MCU Device ID Code Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DEV_ID r

Toggle fields

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

CR

Debug MCU Configuration Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			TRGOEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRACE_IOEN rw			DBG_STANDBY rw	DBG_STOP rw	DBG_SLEEP rw

Toggle fields

DBG_SLEEP

Bit 0: Debug Sleep Mode.

DBG_STOP

Bit 1: Debug Stop Mode.

DBG_STANDBY

Bit 2: Debug Standby Mode.

TRACE_IOEN

Bit 5: Trace port and clock enable.

TRGOEN

Bit 28: External trigger output enable.

APB1FZR1

APB1 Low Freeze Register CPU1

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DBG_LPTIM1_STOP rw								DBG_I2C3_STOP rw		DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw	DBG_WWDG_STOP rw	DBG_RTC_STOP rw										DBG_TIMER2_STOP rw

Toggle fields

DBG_TIMER2_STOP

Bit 0: Debug Timer 2 stopped when Core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_WWDG_STOP

Bit 11: WWDG counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: IWDG counter stopped when core is halted.

DBG_I2C1_STOP

Bit 21: Debug I2C1 SMBUS timeout stopped when Core is halted.

DBG_I2C3_STOP

Bit 23: Debug I2C3 SMBUS timeout stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: Debug LPTIM1 stopped when Core is halted.

C2AP_B1FZR1

APB1 Low Freeze Register CPU2

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DBG_LPTIM1_STOP rw								DBG_I2C3_STOP rw		DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw		DBG_RTC_STOP rw										DBG_LPTIM2_STOP rw

Toggle fields

DBG_LPTIM2_STOP

Bit 0: LPTIM2 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: IWDG stopped when core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout stopped when core is halted.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

APB1FZR2

APB1 High Freeze Register CPU1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DBG_LPTIM2_STOP rw

Toggle fields

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

C2APB1FZR2

APB1 High Freeze Register CPU2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DBG_LPTIM2_STOP rw

Toggle fields

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

C2APB2FZR

APB2 Freeze Register CPU2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DBG_TIM1_STOP rw

Toggle fields

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: TIM17 counter stopped when core is halted.

APB2FZR

APB2 Freeze Register CPU1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DBG_TIM1_STOP rw

Toggle fields

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: TIM17 counter stopped when core is halted.

DMA1

0x40020000: Direct memory access controller

28/161 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR		TEIF7	HTIF7	TCIF7	GIF7	TEIF6	HTIF6	TCIF6	GIF6	TEIF5	HTIF5	TCIF5	GIF5	TEIF4	HTIF4	TCIF4	GIF4	TEIF3	HTIF3	TCIF3	GIF3	TEIF2	HTIF2	TCIF2	GIF2	TEIF1	HTIF1	TCIF1	GIF1
0x4	IFCR		CTEIF7	CHTIF7	CTCIF7	CGIF7	CTEIF6	CHTIF6	CTCIF6	CGIF6	CTEIF5	CHTIF5	CTCIF5	CGIF5	CTEIF4	CHTIF4	CTCIF4	CGIF4	CTEIF3	CHTIF3	CTCIF3	CGIF3	CTEIF2	CHTIF2	CTCIF2	CGIF2	CTEIF1	CHTIF1	CTCIF1	CGIF1
0x8	CCR1															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	CNDTR1														NDT
0x10	CPAR1	PA													PA
0x14	CMAR1	MA													MA
0x1c	CCR2															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	CNDTR2														NDT
0x24	CPAR2	PA													PA
0x28	CMAR2	MA													MA
0x30	CCR3															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	CNDTR3														NDT
0x38	CPAR3	PA													PA
0x3c	CMAR3	MA													MA
0x44	CCR4															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	CNDTR4														NDT
0x4c	CPAR4	PA													PA
0x50	CMAR4	MA													MA
0x58	CCR5															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	CNDTR5														NDT
0x60	CPAR5	PA													PA
0x64	CMAR5	MA													MA
0x6c	CCR6															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	CNDTR6														NDT
0x74	CPAR6	PA													PA
0x78	CMAR6	MA													MA
0x80	CCR7															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	CNDTR7														NDT
0x88	CPAR7	PA													PA
0x8c	CMAR7	MA													MA

Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF7 r	HTIF7 r	TCIF7 r	GIF7 r	TEIF6 r	HTIF6 r	TCIF6 r	GIF6 r	TEIF5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF4 r	HTIF4 r	TCIF4 r	GIF4 r	TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF7 w	CHTIF7 w	CTCIF7 w	CGIF7 w	CTEIF6 w	CHTIF6 w	CTCIF6 w	CGIF6 w	CTEIF5 w	CHTIF5 w	CTCIF5 w	CGIF5 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF4 w	CTCIF4 w	CGIF4 w	CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CCR1

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR1

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR1

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR2

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR2

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR3

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR3

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR4

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR4

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR5

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR5

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR6

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR6

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR7

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR7

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

DMA2

0x40020400: Direct memory access controller

28/168 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR		TEIF7	HTIF7	TCIF7	GIF7	TEIF6	HTIF6	TCIF6	GIF6	TEIF5	HTIF5	TCIF5	GIF5	TEIF4	HTIF4	TCIF4	GIF4	TEIF3	HTIF3	TCIF3	GIF3	TEIF2	HTIF2	TCIF2	GIF2	TEIF1	HTIF1	TCIF1	GIF1
0x4	IFCR		CTEIF7	CHTIF7	CTCIF7	CGIF7	CTEIF6	CHTIF6	CTCIF6	CGIF6	CTEIF5	CHTIF5	CTCIF5	CGIF5	CTEIF4	CHTIF4	CTCIF4	CGIF4	CTEIF3	CHTIF3	CTCIF3	CGIF3	CTEIF2	CHTIF2	CTCIF2	CGIF2	CTEIF1	CHTIF1	CTCIF1	CGIF1
0x8	CCR1															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	CNDTR1														NDT
0x10	CPAR1	PA													PA
0x14	CMAR1	MA													MA
0x1c	CCR2															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	CNDTR2														NDT
0x24	CPAR2	PA													PA
0x28	CMAR2	MA													MA
0x30	CCR3															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	CNDTR3														NDT
0x38	CPAR3	PA													PA
0x3c	CMAR3	MA													MA
0x44	CCR4															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	CNDTR4														NDT
0x4c	CPAR4	PA													PA
0x50	CMAR4	MA													MA
0x58	CCR5															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	CNDTR5														NDT
0x60	CPAR5	PA													PA
0x64	CMAR5	MA													MA
0x6c	CCR6															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	CNDTR6														NDT
0x74	CPAR6	PA													PA
0x78	CMAR6	MA													MA
0x80	CCR7															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	CNDTR7														NDT
0x88	CPAR7	PA													PA
0x8c	CMAR7	MA													MA
0xa8	CSELR		C7S				C6S				C5S				C4S				C3S				C2S				C1S

Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF7 r	HTIF7 r	TCIF7 r	GIF7 r	TEIF6 r	HTIF6 r	TCIF6 r	GIF6 r	TEIF5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF4 r	HTIF4 r	TCIF4 r	GIF4 r	TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF7 w	CHTIF7 w	CTCIF7 w	CGIF7 w	CTEIF6 w	CHTIF6 w	CTCIF6 w	CGIF6 w	CTEIF5 w	CHTIF5 w	CTCIF5 w	CGIF5 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF4 w	CTCIF4 w	CGIF4 w	CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CCR1

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR1

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR1

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR2

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR2

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR3

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR3

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR4

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR4

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR5

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR5

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR6

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR6

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR7

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR7

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CSELR

channel selection register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				C7S rw				C6S rw				C5S rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C4S rw				C3S rw				C2S rw				C1S rw

Toggle fields

C1S

Bits 0-3: DMA channel 1 selection.

C2S

Bits 4-7: DMA channel 2 selection.

C3S

Bits 8-11: DMA channel 3 selection.

C4S

Bits 12-15: DMA channel 4 selection.

C5S

Bits 16-19: DMA channel 5 selection.

C6S

Bits 20-23: DMA channel 6 selection.

C7S

Bits 24-27: DMA channel 7 selection.

DMAMUX1

0x40020800: Direct memory access Multiplexer

22/154 fields covered.

Toggle register map

Offset	Name	28	23	18	16	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CCR[0]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x4	CCR[1]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x8	CCR[2]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0xc	CCR[3]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x10	CCR[4]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x14	CCR[5]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x18	CCR[6]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x1c	CCR[7]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x20	CCR[8]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x24	CCR[9]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x28	CCR[10]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x2c	CCR[11]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x30	CCR[12]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x34	CCR[13]	SYNC_ID	NBREQ	SPOL	SE					EGE	SOIE	DMAREQ_ID
0x80	CSR					SOF13	SOF12	SOF11	SOF10	SOF9	SOF8	SOF7	SOF6	SOF5	SOF4	SOF3	SOF2	SOF1	SOF0
0x84	CFR					CSOF13	CSOF12	CSOF11	CSOF10	CSOF9	CSOF8	CSOF7	CSOF6	CSOF5	CSOF4	CSOF3	CSOF2	CSOF1	CSOF0
0x100	RGCR[0]		GNBREQ	GPOL	GE						OIE				SIG_ID
0x104	RGCR[1]		GNBREQ	GPOL	GE						OIE				SIG_ID
0x108	RGCR[2]		GNBREQ	GPOL	GE						OIE				SIG_ID
0x10c	RGCR[3]		GNBREQ	GPOL	GE						OIE				SIG_ID
0x140	RGSR															OF3	OF2	OF1	OF0
0x144	RGCFR															CSOF3	CSOF2	CSOF1	CSOF0

Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

DMA Multiplexer Channel Status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SOF13 r	SOF12 r	SOF11 r	SOF10 r	SOF9 r	SOF8 r	SOF7 r	SOF6 r	SOF5 r	SOF4 r	SOF3 r	SOF2 r	SOF1 r	SOF0 r

Toggle fields

SOF0

Bit 0: Synchronization Overrun Flag 0.

SOF1

Bit 1: Synchronization Overrun Flag 1.

SOF2

Bit 2: Synchronization Overrun Flag 2.

SOF3

Bit 3: Synchronization Overrun Flag 3.

SOF4

Bit 4: Synchronization Overrun Flag 4.

SOF5

Bit 5: Synchronization Overrun Flag 5.

SOF6

Bit 6: Synchronization Overrun Flag 6.

SOF7

Bit 7: Synchronization Overrun Flag 7.

SOF8

Bit 8: Synchronization Overrun Flag 8.

SOF9

Bit 9: Synchronization Overrun Flag 9.

SOF10

Bit 10: Synchronization Overrun Flag 10.

SOF11

Bit 11: Synchronization Overrun Flag 11.

SOF12

Bit 12: Synchronization Overrun Flag 12.

SOF13

Bit 13: Synchronization Overrun Flag 13.

CFR

DMA Channel Clear Flag Register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CSOF13 w	CSOF12 w	CSOF11 w	CSOF10 w	CSOF9 w	CSOF8 w	CSOF7 w	CSOF6 w	CSOF5 w	CSOF4 w	CSOF3 w	CSOF2 w	CSOF1 w	CSOF0 w

Toggle fields

CSOF0

Bit 0: Synchronization Clear Overrun Flag 0.

CSOF1

Bit 1: Synchronization Clear Overrun Flag 1.

CSOF2

Bit 2: Synchronization Clear Overrun Flag 2.

CSOF3

Bit 3: Synchronization Clear Overrun Flag 3.

CSOF4

Bit 4: Synchronization Clear Overrun Flag 4.

CSOF5

Bit 5: Synchronization Clear Overrun Flag 5.

CSOF6

Bit 6: Synchronization Clear Overrun Flag 6.

CSOF7

Bit 7: Synchronization Clear Overrun Flag 7.

CSOF8

Bit 8: Synchronization Clear Overrun Flag 8.

CSOF9

Bit 9: Synchronization Clear Overrun Flag 9.

CSOF10

Bit 10: Synchronization Clear Overrun Flag 10.

CSOF11

Bit 11: Synchronization Clear Overrun Flag 11.

CSOF12

Bit 12: Synchronization Clear Overrun Flag 12.

CSOF13

Bit 13: Synchronization Clear Overrun Flag 13.

RGCR[0]

DMA Request Generator 0 Control Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[1]

DMA Request Generator 1 Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[2]

DMA Request Generator 2 Control Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[3]

DMA Request Generator 3 Control Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGSR

DMA Request Generator Status Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												OF3 r	OF2 r	OF1 r	OF0 r

Toggle fields

OF0

Bit 0: Generator Overrun Flag 0.

OF1

Bit 1: Generator Overrun Flag 1.

OF2

Bit 2: Generator Overrun Flag 2.

OF3

Bit 3: Generator Overrun Flag 3.

RGCFR

DMA Request Generator Clear Flag Register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CSOF3 r	CSOF2 r	CSOF1 r	CSOF0 r

Toggle fields

CSOF0

Bit 0: Generator Clear Overrun Flag 0.

CSOF1

Bit 1: Generator Clear Overrun Flag 1.

CSOF2

Bit 2: Generator Clear Overrun Flag 2.

CSOF3

Bit 3: Generator Clear Overrun Flag 3.

EXTI

0x58000800: External interrupt/event controller

13/217 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	RTSR1	RT31										RT21	RT20	RT19	RT18	RT17	RT16	RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
0x4	FTSR1	FT31										FT21	FT20	FT19	FT18	FT17	FT16	FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
0x8	SWIER1	SWI31										SWI21	SWI20	SWI19	SWI18	SWI17	SWI16	SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
0xc	PR1	PIF31										PIF21	PIF20	PIF19	PIF18	PIF17	PIF16	PIF15	PIF14	PIF13	PIF12	PIF11	PIF10	PIF9	PIF8	PIF7	PIF6	PIF5	PIF4	PIF3	PIF2	PIF1	PIF0
0x20	RTSR2																							RT40_41								RT33
0x24	FTSR2																							FT40_41								FT33
0x28	SWIER2																							SWI40_41								SWI33
0x2c	PR2																							PIF40_41								PIF33
0x80	IMR1	IM31	IM30	IM29	IM28	IM27	IM26	IM25	IM24	IM23	IM22	IM21	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x84	EMR1											EM17_21						EM0_15
0x90	IMR2																IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x94	EMR2																							EM
0xc0	C2IMR1	IM31	IM30	IM29	IM28	IM27	IM26	IM25	IM24	IM23	IM22	IM21	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0xc4	C2EMR1											EM17_21						EM0_15
0xd0	C2IMR2																IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0xd4	C2EMR2																							EM
0x3d8	HWCFGR7	CPUEVENT																CPUEVENT
0x3dc	HWCFGR6	CPUEVENT																CPUEVENT
0x3e0	HWCFGR5	CPUEVENT																CPUEVENT
0x3e4	HWCFGR4	EVENT_TRG																EVENT_TRG
0x3e8	HWCFGR3	EVENT_TRG																EVENT_TRG
0x3ec	HWCFGR2	EVENT_TRG																EVENT_TRG
0x3f0	HWCFGR1																	CPUEVTEN				NBCPUS				NBEVENTS
0x3f4	VERR																									MAJREV				MINREV
0x3f8	IPIDR	IPID																IPID
0x3fc	SIDR	SID																SID

Toggle registers

RTSR1

rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RT31 rw										RT21 rw	RT20 rw	RT19 rw	RT18 rw	RT17 rw	RT16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15 rw	RT14 rw	RT13 rw	RT12 rw	RT11 rw	RT10 rw	RT9 rw	RT8 rw	RT7 rw	RT6 rw	RT5 rw	RT4 rw	RT3 rw	RT2 rw	RT1 rw	RT0 rw

Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

RT1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

RT2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

RT3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

RT4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

RT5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

RT6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

RT7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

RT8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

RT9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

RT10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

RT11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

RT12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

RT13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

RT14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

RT15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

RT16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

RT17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

RT18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

RT19

Bit 19: Rising trigger event configuration bit of Configurable Event input.

RT20

Bit 20: Rising trigger event configuration bit of Configurable Event input.

RT21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

RT31

Bit 31: Rising trigger event configuration bit of Configurable Event input.

FTSR1

falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FT31 rw										FT21 rw	FT20 rw	FT19 rw	FT18 rw	FT17 rw	FT16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15 rw	FT14 rw	FT13 rw	FT12 rw	FT11 rw	FT10 rw	FT9 rw	FT8 rw	FT7 rw	FT6 rw	FT5 rw	FT4 rw	FT3 rw	FT2 rw	FT1 rw	FT0 rw

Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of Configurable Event input.

FT1

Bit 1: Falling trigger event configuration bit of Configurable Event input.

FT2

Bit 2: Falling trigger event configuration bit of Configurable Event input.

FT3

Bit 3: Falling trigger event configuration bit of Configurable Event input.

FT4

Bit 4: Falling trigger event configuration bit of Configurable Event input.

FT5

Bit 5: Falling trigger event configuration bit of Configurable Event input.

FT6

Bit 6: Falling trigger event configuration bit of Configurable Event input.

FT7

Bit 7: Falling trigger event configuration bit of Configurable Event input.

FT8

Bit 8: Falling trigger event configuration bit of Configurable Event input.

FT9

Bit 9: Falling trigger event configuration bit of Configurable Event input.

FT10

Bit 10: Falling trigger event configuration bit of Configurable Event input.

FT11

Bit 11: Falling trigger event configuration bit of Configurable Event input.

FT12

Bit 12: Falling trigger event configuration bit of Configurable Event input.

FT13

Bit 13: Falling trigger event configuration bit of Configurable Event input.

FT14

Bit 14: Falling trigger event configuration bit of Configurable Event input.

FT15

Bit 15: Falling trigger event configuration bit of Configurable Event input.

FT16

Bit 16: Falling trigger event configuration bit of Configurable Event input.

FT17

Bit 17: Falling trigger event configuration bit of Configurable Event input.

FT18

Bit 18: Falling trigger event configuration bit of Configurable Event input.

FT19

Bit 19: Falling trigger event configuration bit of Configurable Event input.

FT20

Bit 20: Falling trigger event configuration bit of Configurable Event input.

FT21

Bit 21: Falling trigger event configuration bit of Configurable Event input.

FT31

Bit 31: Falling trigger event configuration bit of Configurable Event input.

SWIER1

software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SWI31 rw										SWI21 rw	SWI20 rw	SWI19 rw	SWI18 rw	SWI17 rw	SWI16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15 rw	SWI14 rw	SWI13 rw	SWI12 rw	SWI11 rw	SWI10 rw	SWI9 rw	SWI8 rw	SWI7 rw	SWI6 rw	SWI5 rw	SWI4 rw	SWI3 rw	SWI2 rw	SWI1 rw	SWI0 rw

Toggle fields

SWI0

Bit 0: Software interrupt on event.

SWI1

Bit 1: Software interrupt on event.

SWI2

Bit 2: Software interrupt on event.

SWI3

Bit 3: Software interrupt on event.

SWI4

Bit 4: Software interrupt on event.

SWI5

Bit 5: Software interrupt on event.

SWI6

Bit 6: Software interrupt on event.

SWI7

Bit 7: Software interrupt on event.

SWI8

Bit 8: Software interrupt on event.

SWI9

Bit 9: Software interrupt on event.

SWI10

Bit 10: Software interrupt on event.

SWI11

Bit 11: Software interrupt on event.

SWI12

Bit 12: Software interrupt on event.

SWI13

Bit 13: Software interrupt on event.

SWI14

Bit 14: Software interrupt on event.

SWI15

Bit 15: Software interrupt on event.

SWI16

Bit 16: Software interrupt on event.

SWI17

Bit 17: Software interrupt on event.

SWI18

Bit 18: Software interrupt on event.

SWI19

Bit 19: Software interrupt on event.

SWI20

Bit 20: Software interrupt on event.

SWI21

Bit 21: Software interrupt on event.

SWI31

Bit 31: Software interrupt on event.

PR1

EXTI pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PIF31 rw										PIF21 rw	PIF20 rw	PIF19 rw	PIF18 rw	PIF17 rw	PIF16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PIF15 rw	PIF14 rw	PIF13 rw	PIF12 rw	PIF11 rw	PIF10 rw	PIF9 rw	PIF8 rw	PIF7 rw	PIF6 rw	PIF5 rw	PIF4 rw	PIF3 rw	PIF2 rw	PIF1 rw	PIF0 rw

Toggle fields

PIF0

Bit 0: Configurable event inputs Pending bit.

PIF1

Bit 1: Configurable event inputs Pending bit.

PIF2

Bit 2: Configurable event inputs Pending bit.

PIF3

Bit 3: Configurable event inputs Pending bit.

PIF4

Bit 4: Configurable event inputs Pending bit.

PIF5

Bit 5: Configurable event inputs Pending bit.

PIF6

Bit 6: Configurable event inputs Pending bit.

PIF7

Bit 7: Configurable event inputs Pending bit.

PIF8

Bit 8: Configurable event inputs Pending bit.

PIF9

Bit 9: Configurable event inputs Pending bit.

PIF10

Bit 10: Configurable event inputs Pending bit.

PIF11

Bit 11: Configurable event inputs Pending bit.

PIF12

Bit 12: Configurable event inputs Pending bit.

PIF13

Bit 13: Configurable event inputs Pending bit.

PIF14

Bit 14: Configurable event inputs Pending bit.

PIF15

Bit 15: Configurable event inputs Pending bit.

PIF16

Bit 16: Configurable event inputs Pending bit.

PIF17

Bit 17: Configurable event inputs Pending bit.

PIF18

Bit 18: Configurable event inputs Pending bit.

PIF19

Bit 19: Configurable event inputs Pending bit.

PIF20

Bit 20: Configurable event inputs Pending bit.

PIF21

Bit 21: Configurable event inputs Pending bit.

PIF31

Bit 31: Configurable event inputs Pending bit.

RTSR2

rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						RT40_41 rw								RT33 rw

Toggle fields

RT33

Bit 1: Rising trigger event configuration bit of Configurable Event input.

RT40_41

Bits 8-9: Rising trigger event configuration bit of Configurable Event input.

FTSR2

falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FT40_41 rw								FT33 rw

Toggle fields

FT33

Bit 1: Falling trigger event configuration bit of Configurable Event input.

FT40_41

Bits 8-9: Falling trigger event configuration bit of Configurable Event input.

SWIER2

software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						SWI40_41 rw								SWI33 rw

Toggle fields

SWI33

Bit 1: Software interrupt on event.

SWI40_41

Bits 8-9: Software interrupt on event.

PR2

pending register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PIF40_41 rw								PIF33 rw

Toggle fields

PIF33

Bit 1: Configurable event inputs x+32 Pending bit..

PIF40_41

Bits 8-9: Configurable event inputs x+32 Pending bit..

IMR1

CPUm wakeup with interrupt mask register

Offset: 0x80, size: 32, reset: 0x7FC00000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM31 rw	IM30 rw	IM29 rw	IM28 rw	IM27 rw	IM26 rw	IM25 rw	IM24 rw	IM23 rw	IM22 rw	IM21 rw	IM20 rw	IM19 rw	IM18 rw	IM17 rw	IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle fields

IM0

Bit 0: CPU(m) wakeup with interrupt Mask on Event input.

IM1

Bit 1: CPU(m) wakeup with interrupt Mask on Event input.

IM2

Bit 2: CPU(m) wakeup with interrupt Mask on Event input.

IM3

Bit 3: CPU(m) wakeup with interrupt Mask on Event input.

IM4

Bit 4: CPU(m) wakeup with interrupt Mask on Event input.

IM5

Bit 5: CPU(m) wakeup with interrupt Mask on Event input.

IM6

Bit 6: CPU(m) wakeup with interrupt Mask on Event input.

IM7

Bit 7: CPU(m) wakeup with interrupt Mask on Event input.

IM8

Bit 8: CPU(m) wakeup with interrupt Mask on Event input.

IM9

Bit 9: CPU(m) wakeup with interrupt Mask on Event input.

IM10

Bit 10: CPU(m) wakeup with interrupt Mask on Event input.

IM11

Bit 11: CPU(m) wakeup with interrupt Mask on Event input.

IM12

Bit 12: CPU(m) wakeup with interrupt Mask on Event input.

IM13

Bit 13: CPU(m) wakeup with interrupt Mask on Event input.

IM14

Bit 14: CPU(m) wakeup with interrupt Mask on Event input.

IM15

Bit 15: CPU(m) wakeup with interrupt Mask on Event input.

IM16

Bit 16: CPU(m) wakeup with interrupt Mask on Event input.

IM17

Bit 17: CPU(m) wakeup with interrupt Mask on Event input.

IM18

Bit 18: CPU(m) wakeup with interrupt Mask on Event input.

IM19

Bit 19: CPU(m) wakeup with interrupt Mask on Event input.

IM20

Bit 20: CPU(m) wakeup with interrupt Mask on Event input.

IM21

Bit 21: CPU(m) wakeup with interrupt Mask on Event input.

IM22

Bit 22: CPU(m) wakeup with interrupt Mask on Event input.

IM23

Bit 23: CPU(m) wakeup with interrupt Mask on Event input.

IM24

Bit 24: CPU(m) wakeup with interrupt Mask on Event input.

IM25

Bit 25: CPU(m) wakeup with interrupt Mask on Event input.

IM26

Bit 26: CPU(m) wakeup with interrupt Mask on Event input.

IM27

Bit 27: CPU(m) wakeup with interrupt Mask on Event input.

IM28

Bit 28: CPU(m) wakeup with interrupt Mask on Event input.

IM29

Bit 29: CPU(m) wakeup with interrupt Mask on Event input.

IM30

Bit 30: CPU(m) wakeup with interrupt Mask on Event input.

IM31

Bit 31: CPU(m) wakeup with interrupt Mask on Event input.

EMR1

CPUm wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										EM17_21 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM0_15 rw

Toggle fields

EM0_15

Bits 0-15: CPU(m) Wakeup with event generation Mask on Event input.

EM17_21

Bits 17-21: CPU(m) Wakeup with event generation Mask on Event input.

IMR2

CPUm wakeup with interrupt mask register

Offset: 0x90, size: 32, reset: 0x0001FCFD, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle fields

IM0

Bit 0: CPUm Wakeup with interrupt Mask on Event input.

IM1

Bit 1: CPUm Wakeup with interrupt Mask on Event input.

IM2

Bit 2: CPUm Wakeup with interrupt Mask on Event input.

IM3

Bit 3: CPUm Wakeup with interrupt Mask on Event input.

IM4

Bit 4: CPUm Wakeup with interrupt Mask on Event input.

IM5

Bit 5: CPUm Wakeup with interrupt Mask on Event input.

IM6

Bit 6: CPUm Wakeup with interrupt Mask on Event input.

IM7

Bit 7: CPUm Wakeup with interrupt Mask on Event input.

IM8

Bit 8: CPUm Wakeup with interrupt Mask on Event input.

IM9

Bit 9: CPUm Wakeup with interrupt Mask on Event input.

IM10

Bit 10: CPUm Wakeup with interrupt Mask on Event input.

IM11

Bit 11: CPUm Wakeup with interrupt Mask on Event input.

IM12

Bit 12: CPUm Wakeup with interrupt Mask on Event input.

IM13

Bit 13: CPUm Wakeup with interrupt Mask on Event input.

IM14

Bit 14: CPUm Wakeup with interrupt Mask on Event input.

IM15

Bit 15: CPUm Wakeup with interrupt Mask on Event input.

IM16

Bit 16: CPUm Wakeup with interrupt Mask on Event input.

EMR2

CPUm wakeup with event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EM rw

Toggle fields

EM

Bits 8-9: CPU(m) Wakeup with event generation Mask on Event input.

C2IMR1

CPUm wakeup with interrupt mask register

Offset: 0xc0, size: 32, reset: 0x7FC00000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM31 rw	IM30 rw	IM29 rw	IM28 rw	IM27 rw	IM26 rw	IM25 rw	IM24 rw	IM23 rw	IM22 rw	IM21 rw	IM20 rw	IM19 rw	IM18 rw	IM17 rw	IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle fields

IM0

Bit 0: CPU(m) wakeup with interrupt Mask on Event input.

IM1

Bit 1: CPU(m) wakeup with interrupt Mask on Event input.

IM2

Bit 2: CPU(m) wakeup with interrupt Mask on Event input.

IM3

Bit 3: CPU(m) wakeup with interrupt Mask on Event input.

IM4

Bit 4: CPU(m) wakeup with interrupt Mask on Event input.

IM5

Bit 5: CPU(m) wakeup with interrupt Mask on Event input.

IM6

Bit 6: CPU(m) wakeup with interrupt Mask on Event input.

IM7

Bit 7: CPU(m) wakeup with interrupt Mask on Event input.

IM8

Bit 8: CPU(m) wakeup with interrupt Mask on Event input.

IM9

Bit 9: CPU(m) wakeup with interrupt Mask on Event input.

IM10

Bit 10: CPU(m) wakeup with interrupt Mask on Event input.

IM11

Bit 11: CPU(m) wakeup with interrupt Mask on Event input.

IM12

Bit 12: CPU(m) wakeup with interrupt Mask on Event input.

IM13

Bit 13: CPU(m) wakeup with interrupt Mask on Event input.

IM14

Bit 14: CPU(m) wakeup with interrupt Mask on Event input.

IM15

Bit 15: CPU(m) wakeup with interrupt Mask on Event input.

IM16

Bit 16: CPU(m) wakeup with interrupt Mask on Event input.

IM17

Bit 17: CPU(m) wakeup with interrupt Mask on Event input.

IM18

Bit 18: CPU(m) wakeup with interrupt Mask on Event input.

IM19

Bit 19: CPU(m) wakeup with interrupt Mask on Event input.

IM20

Bit 20: CPU(m) wakeup with interrupt Mask on Event input.

IM21

Bit 21: CPU(m) wakeup with interrupt Mask on Event input.

IM22

Bit 22: CPU(m) wakeup with interrupt Mask on Event input.

IM23

Bit 23: CPU(m) wakeup with interrupt Mask on Event input.

IM24

Bit 24: CPU(m) wakeup with interrupt Mask on Event input.

IM25

Bit 25: CPU(m) wakeup with interrupt Mask on Event input.

IM26

Bit 26: CPU(m) wakeup with interrupt Mask on Event input.

IM27

Bit 27: CPU(m) wakeup with interrupt Mask on Event input.

IM28

Bit 28: CPU(m) wakeup with interrupt Mask on Event input.

IM29

Bit 29: CPU(m) wakeup with interrupt Mask on Event input.

IM30

Bit 30: CPU(m) wakeup with interrupt Mask on Event input.

IM31

Bit 31: CPU(m) wakeup with interrupt Mask on Event input.

C2EMR1

CPUm wakeup with event mask register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										EM17_21 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM0_15 rw

Toggle fields

EM0_15

Bits 0-15: CPU(m) Wakeup with event generation Mask on Event input.

EM17_21

Bits 17-21: CPU(m) Wakeup with event generation Mask on Event input.

C2IMR2

CPUm wakeup with interrupt mask register

Offset: 0xd0, size: 32, reset: 0x0001FCFD, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IM16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15 rw	IM14 rw	IM13 rw	IM12 rw	IM11 rw	IM10 rw	IM9 rw	IM8 rw	IM7 rw	IM6 rw	IM5 rw	IM4 rw	IM3 rw	IM2 rw	IM1 rw	IM0 rw

Toggle fields

IM0

Bit 0: CPUm Wakeup with interrupt Mask on Event input.

IM1

Bit 1: CPUm Wakeup with interrupt Mask on Event input.

IM2

Bit 2: CPUm Wakeup with interrupt Mask on Event input.

IM3

Bit 3: CPUm Wakeup with interrupt Mask on Event input.

IM4

Bit 4: CPUm Wakeup with interrupt Mask on Event input.

IM5

Bit 5: CPUm Wakeup with interrupt Mask on Event input.

IM6

Bit 6: CPUm Wakeup with interrupt Mask on Event input.

IM7

Bit 7: CPUm Wakeup with interrupt Mask on Event input.

IM8

Bit 8: CPUm Wakeup with interrupt Mask on Event input.

IM9

Bit 9: CPUm Wakeup with interrupt Mask on Event input.

IM10

Bit 10: CPUm Wakeup with interrupt Mask on Event input.

IM11

Bit 11: CPUm Wakeup with interrupt Mask on Event input.

IM12

Bit 12: CPUm Wakeup with interrupt Mask on Event input.

IM13

Bit 13: CPUm Wakeup with interrupt Mask on Event input.

IM14

Bit 14: CPUm Wakeup with interrupt Mask on Event input.

IM15

Bit 15: CPUm Wakeup with interrupt Mask on Event input.

IM16

Bit 16: CPUm Wakeup with interrupt Mask on Event input.

C2EMR2

CPUm wakeup with event mask register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EM rw

Toggle fields

EM

Bits 8-9: CPU(m) Wakeup with event generation Mask on Event input.

HWCFGR7

EXTI Hardware configuration registers

Offset: 0x3d8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT r

Toggle fields

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR6

Hardware configuration registers

Offset: 0x3dc, size: 32, reset: 0x00000300, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT r

Toggle fields

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR5

Hardware configuration registers

Offset: 0x3e0, size: 32, reset: 0x003EFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT r

Toggle fields

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR4

Hardware configuration registers

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG r

Toggle fields

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR3

Hardware configuration registers

Offset: 0x3e8, size: 32, reset: 0x00000302, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG r

Toggle fields

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR2

Hardware configuration registers

Offset: 0x3ec, size: 32, reset: 0x803FFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG r

Toggle fields

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR1

Hardware configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00003130, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVTEN r				NBCPUS r				NBEVENTS r

Toggle fields

NBEVENTS

Bits 0-7: HW configuration number of event.

NBCPUS

Bits 8-11: HW configuration number of CPUs.

CPUEVTEN

Bits 12-15: HW configuration of CPU(m) event output enable.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

Identification register

Offset: 0x3f8, size: 32, reset: 0x000E0001, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle fields

SID

Bits 0-31: Size Identification.

Flash

0x58004000: Flash

7/105 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACR															EMPTY	PES			DCRST	ICRST	DCEN	ICEN	PRFTEN						LATENCY
0x8	KEYR	KEYR															KEYR
0xc	OPTKEYR	OPTKEYR															OPTKEYR
0x10	SR												PESD	CFGBSY		BSY	OPTVERR	RDERR	OPTNV				FASTERR	MISERR	PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x14	CR	LOCK	OPTLOCK			OBL_LAUNCH	RDERRIE	ERRIE	EOPIE					FSTPG	OPTSTRT	STRT						PNB								MER	PER	PG
0x18	ECCR	ECCD	ECCC		CPUID				ECCCIE			SYSF_ECC				ADDR_ECC	ADDR_ECC
0x20	OPTR	AGC_TRIM				nBOOT0	nSWBOOT0	SRAM2_RST	SRAM2_PE	nBOOT1			WWDG_SW	IWDG_STDBY	IWDG_STOP	IDWG_SW		nRST_SHDW	nRST_STDBY	nRST_STOP	BOR_LEV			ESE	RDP
0x24	PCROP1ASR																							PCROP1A_STRT
0x28	PCROP1AER	PCROP_RDP																						PCROP1A_END
0x2c	WRP1AR									WRP1A_END															WRP1A_STRT
0x30	WRP1BR									WRP1B_STRT															WRP1B_END
0x34	PCROP1BSR																							PCROP1B_STRT
0x38	PCROP1BER																							PCROP1B_END
0x3c	IPCCBR																		IPCCDBA
0x5c	C2ACR																PES				ICRST		ICEN	PRFTEN
0x60	C2SR												PESD	CFGBSY		BSY		RDERR					FASTERR	MISSERR	PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x64	C2CR						RDERRIE	ERRIE	EOPIE					FSTPG		STRT						PNB								MER	PER	PG
0x80	SFR																			DDS				FSD	SFSA
0x84	SRRVR	C2OPT	NBRSD	SNBRSA						BRSD	SBRSA				SBRV		SBRV

Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000600, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															EMPTY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PES rw			DCRST rw	ICRST rw	DCEN rw	ICEN rw	PRFTEN rw						LATENCY rw

Toggle fields

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

PES

Bit 15: CPU1 CortexM4 program erase suspend request.

EMPTY

Bit 16: Flash User area empty.

KEYR

Flash key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEYR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEYR w

Toggle fields

KEYR

Bits 0-31: KEYR.

OPTKEYR

Option byte key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPTKEYR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTKEYR w

Toggle fields

OPTKEYR

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												PESD r	CFGBSY r		BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTVERR rw	RDERR rw	OPTNV r				FASTERR rw	MISERR rw	PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle fields

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: Write protected error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

OPTNV

Bit 13: User Option OPTVAL indication.

RDERR

Bit 14: PCROP read error.

OPTVERR

Bit 15: Option validity error.

BSY

Bit 16: Busy.

CFGBSY

Bit 18: Programming or erase configuration busy.

PESD

Bit 19: Programming or erase operation suspended.

CR

Flash control register

Offset: 0x14, size: 32, reset: 0xC0000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	OPTLOCK rw			OBL_LAUNCH rw	RDERRIE rw	ERRIE rw	EOPIE rw						FSTPG rw	OPTSTRT rw	STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					PNB rw								MER rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: This bit triggers the mass erase (all user pages) when set.

PNB

Bits 3-10: Page number selection.

STRT

Bit 16: Start.

OPTSTRT

Bit 17: Options modification start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

LOCK

Bit 31: FLASH_CR Lock.

ECCR

Flash ECC register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

3/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECCD rw	ECCC rw		CPUID r				ECCCIE rw				SYSF_ECC r				ADDR_ECC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_ECC r

Toggle fields

ADDR_ECC

Bits 0-16: ECC fail address.

SYSF_ECC

Bit 20: System Flash ECC fail.

ECCCIE

Bit 24: ECC correction interrupt enable.

CPUID

Bits 26-28: CPU identification.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x20, size: 32, reset: 0x10708000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AGC_TRIM rw				nBOOT0 rw	nSWBOOT0 rw	SRAM2_RST rw	SRAM2_PE rw	nBOOT1 rw				WWDG_SW rw	IWDG_STDBY rw	IWDG_STOP rw	IDWG_SW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	nRST_SHDW rw	nRST_STDBY rw	nRST_STOP rw	BOR_LEV rw			ESE rw	RDP rw

Toggle fields

RDP

Bits 0-7: Read protection level.

ESE

Bit 8: Security enabled.

BOR_LEV

Bits 9-11: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRST_SHDW.

IDWG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

nBOOT1

Bit 23: Boot configuration.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: Software Boot0.

nBOOT0

Bit 27: nBoot0 option bit.

AGC_TRIM

Bits 29-31: Radio Automatic Gain Control Trimming.

PCROP1ASR

Flash Bank 1 PCROP Start address zone A register

Offset: 0x24, size: 32, reset: 0xFFFFFE00, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1A_STRT rw

Toggle fields

PCROP1A_STRT

Bits 0-8: Bank 1 PCROPQ area start offset.

PCROP1AER

Flash Bank 1 PCROP End address zone A register

Offset: 0x28, size: 32, reset: 0x7FFFFE00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PCROP_RDP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1A_END rw

Toggle fields

PCROP1A_END

Bits 0-8: Bank 1 PCROP area end offset.

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x2c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								WRP1A_END rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WRP1A_STRT rw

Toggle fields

WRP1A_STRT

Bits 0-7: Bank 1 WRP first area A start offset.

WRP1A_END

Bits 16-23: Bank 1 WRP first area A end offset.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x30, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								WRP1B_STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WRP1B_END rw

Toggle fields

WRP1B_END

Bits 0-7: Bank 1 WRP second area B start offset.

WRP1B_STRT

Bits 16-23: Bank 1 WRP second area B end offset.

PCROP1BSR

Flash Bank 1 PCROP Start address area B register

Offset: 0x34, size: 32, reset: 0xFFFFFE00, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1B_STRT rw

Toggle fields

PCROP1B_STRT

Bits 0-8: Bank 1 PCROP area B start offset.

PCROP1BER

Flash Bank 1 PCROP End address area B register

Offset: 0x38, size: 32, reset: 0xFFFFFE00, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1B_END rw

Toggle fields

PCROP1B_END

Bits 0-8: Bank 1 PCROP area end area B offset.

IPCCBR

IPCC mailbox data buffer address register

Offset: 0x3c, size: 32, reset: 0xFFFFC000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IPCCDBA rw

Toggle fields

IPCCDBA

Bits 0-13: PCC mailbox data buffer base address.

C2ACR

CPU2 cortex M0 access control register

Offset: 0x5c, size: 32, reset: 0x00000600, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PES rw				ICRST rw		ICEN rw	PRFTEN rw

Toggle fields

PRFTEN

Bit 8: CPU2 cortex M0 prefetch enable.

ICEN

Bit 9: CPU2 cortex M0 instruction cache enable.

ICRST

Bit 11: CPU2 cortex M0 instruction cache reset.

PES

Bit 15: CPU2 cortex M0 program erase suspend request.

C2SR

CPU2 cortex M0 status register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												PESD rw	CFGBSY rw		BSY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	RDERR rw					FASTERR rw	MISSERR rw	PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle fields

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: write protection error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISSERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

RDERR

Bit 14: PCROP read error.

BSY

Bit 16: Busy.

CFGBSY

Bit 18: Programming or erase configuration busy.

PESD

Bit 19: Programming or erase operation suspended.

C2CR

CPU2 cortex M0 control register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					RDERRIE rw	ERRIE rw	EOPIE rw						FSTPG rw		STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					PNB rw								MER rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: Masse erase.

PNB

Bits 3-10: Page Number selection.

STRT

Bit 16: Start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

SFR

Secure flash start address register

Offset: 0x80, size: 32, reset: 0xFFFFEE00, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DDS rw				FSD rw	SFSA rw

Toggle fields

SFSA

Bits 0-7: Secure flash start address.

FSD

Bit 8: Flash security disable.

DDS

Bit 12: Disable Cortex M0 debug access.

SRRVR

Secure SRAM2 start address and cortex M0 reset vector register

Offset: 0x84, size: 32, reset: 0x01000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
C2OPT rw	NBRSD rw	SNBRSA rw						BRSD rw	SBRSA rw					SBRV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SBRV rw

Toggle fields

SBRV

Bits 0-17: cortex M0 access control register.

SBRSA

Bits 18-22: Secure backup SRAM2a start address.

BRSD

Bit 23: backup SRAM2a security disable.

SNBRSA

Bits 25-29: Secure non backup SRAM2a start address.

NBRSD

Bit 30: non-backup SRAM2b security disable.

C2OPT

Bit 31: CPU2 cortex M0 boot reset vector memory selection.

FPU

0xe000ef34: Floting point unit

0/24 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	15	8	7	6	5	4	3	2	1	0
0x0	FPCCR	ASPEN	LSPEN								MONRDY		BFRDY	MMRDY	HFRDY	THREAD		USER	LSPACT
0x4	FPCAR	ADDRESS								ADDRESS
0x8	FPSCR	N	Z	C	V	AHP	DN	FZ	RMode			IDC			IXC	UFC	OFC	DZC	IOC

Toggle registers

FPCCR

Floating-point context control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ASPEN rw	LSPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							MONRDY rw		BFRDY rw	MMRDY rw	HFRDY rw	THREAD rw		USER rw	LSPACT rw

Toggle fields

LSPACT

Bit 0: LSPACT.

USER

Bit 1: USER.

THREAD

Bit 3: THREAD.

HFRDY

Bit 4: HFRDY.

MMRDY

Bit 5: MMRDY.

BFRDY

Bit 6: BFRDY.

MONRDY

Bit 8: MONRDY.

LSPEN

Bit 30: LSPEN.

ASPEN

Bit 31: ASPEN.

FPCAR

Floating-point context address register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDRESS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS rw

Toggle fields

ADDRESS

Bits 3-31: Location of unpopulated floating-point.

FPSCR

Floating-point status control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
N rw	Z rw	C rw	V rw		AHP rw	DN rw	FZ rw	RMode rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IDC rw			IXC rw	UFC rw	OFC rw	DZC rw	IOC rw

Toggle fields

IOC

Bit 0: Invalid operation cumulative exception bit.

DZC

Bit 1: Division by zero cumulative exception bit..

OFC

Bit 2: Overflow cumulative exception bit.

UFC

Bit 3: Underflow cumulative exception bit.

IXC

Bit 4: Inexact cumulative exception bit.

IDC

Bit 7: Input denormal cumulative exception bit..

RMode

Bits 22-23: Rounding Mode control field.

FZ

Bit 24: Flush-to-zero mode control bit:.

DN

Bit 25: Default NaN mode control bit.

AHP

Bit 26: Alternative half-precision control bit.

V

Bit 28: Overflow condition code flag.

C

Bit 29: Carry condition code flag.

Z

Bit 30: Zero condition code flag.

N

Bit 31: Negative condition code flag.

FPU_CPACR

0xe000ed88: Floating point unit CPACR

0/1 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CPACR									CP

Toggle registers

CPACR

Coprocessor access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

CP

Bits 20-23: CP.

GPIOA

0x48000000: General-purpose I/Os

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xc	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOB

0x48000400: General-purpose I/Os

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xc	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOC

0x48000800: General-purpose I/Os

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xc	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOD

0x48000c00: General-purpose I/Os

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER15		MODER14		MODER13		MODER12		MODER11		MODER10		MODER9		MODER8		MODER7		MODER6		MODER5		MODER4		MODER3		MODER2		MODER1		MODER0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEEDR15		OSPEEDR14		OSPEEDR13		OSPEEDR12		OSPEEDR11		OSPEEDR10		OSPEEDR9		OSPEEDR8		OSPEEDR7		OSPEEDR6		OSPEEDR5		OSPEEDR4		OSPEEDR3		OSPEEDR2		OSPEEDR1		OSPEEDR0
0xc	PUPDR	PUPDR15		PUPDR14		PUPDR13		PUPDR12		PUPDR11		PUPDR10		PUPDR9		PUPDR8		PUPDR7		PUPDR6		PUPDR5		PUPDR4		PUPDR3		PUPDR2		PUPDR1		PUPDR0
0x10	IDR																	IDR15	IDR14	IDR13	IDR12	IDR11	IDR10	IDR9	IDR8	IDR7	IDR6	IDR5	IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR																	ODR15	ODR14	ODR13	ODR12	ODR11	ODR10	ODR9	ODR8	ODR7	ODR6	ODR5	ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOE

0x48001000: General-purpose I/Os

5/64 fields covered.

Toggle register map

Offset	Name	31	27	23	20	19	18	17	16	15	11	9	7	5	4	3	2	1	0
0x0	MODER											MODER4	MODER3	MODER2		MODER1		MODER0
0x4	OTYPER														OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR											OSPEEDR4	OSPEEDR3	OSPEEDR2		OSPEEDR1		OSPEEDR0
0xc	PUPDR											PUPDR4	PUPDR3	PUPDR2		PUPDR1		PUPDR0
0x10	IDR														IDR4	IDR3	IDR2	IDR1	IDR0
0x14	ODR														ODR4	ODR3	ODR2	ODR1	ODR0
0x18	BSRR				BR4	BR3	BR2	BR1	BR0						BS4	BS3	BS2	BS1	BS0
0x1c	LCKR								LCKK						LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL					AFSEL4				AFSEL3	AFSEL2		AFSEL1			AFSEL0
0x24	AFRH	AFSEL15	AFSEL14	AFSEL13		AFSEL12				AFSEL11	AFSEL10		AFSEL9			AFSEL8
0x28	BRR														BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x000003FF, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

GPIOH

0x48001c00: General-purpose I/Os

3/42 fields covered.

Toggle register map

Offset	Name	31	27	23	19	17	16	15	11	7	3	1	0
0x0	MODER									MODER3	MODER1	MODER0
0x4	OTYPER										OT3	OT1	OT0
0x8	OSPEEDR									OSPEEDR3	OSPEEDR1	OSPEEDR0
0xc	PUPDR									PUPDR3	PUPDR1	PUPDR0
0x10	IDR										IDR3	IDR1	IDR0
0x14	ODR										ODR3	ODR1	ODR0
0x18	BSRR				BR3	BR1	BR0				BS3	BS1	BS0
0x1c	LCKR						LCKK				LCK3	LCK1	LCK0
0x20	AFRL							AFSEL3		AFSEL1	AFSEL0
0x24	AFRH	AFSEL15	AFSEL14	AFSEL13	AFSEL12			AFSEL11	AFSEL10	AFSEL9	AFSEL8
0x28	BRR										BR3	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x000000CF, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MODER3 rw				MODER1 rw		MODER0 rw

Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												OT3 rw		OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OSPEEDR3 rw				OSPEEDR1 rw		OSPEEDR0 rw

Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PUPDR3 rw				PUPDR1 rw		PUPDR0 rw

Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												IDR3 r		IDR1 r	IDR0 r

Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ODR3 rw		ODR1 rw	ODR0 rw

Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BR3 w		BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BS3 w		BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												LCK3 rw		LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw								AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BR3 w		BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR3

Bit 3: Port Reset bit.

HSEM

0x58001400: HSEM

110/213 fields covered.

Toggle register map

Offset	Name	31	15	11	7	3
0x0	R[0]	LOCK		COREID	PROCID
0x4	R[1]	LOCK		COREID	PROCID
0x8	R[2]	LOCK		COREID	PROCID
0xc	R[3]	LOCK		COREID	PROCID
0x10	R[4]	LOCK		COREID	PROCID
0x14	R[5]	LOCK		COREID	PROCID
0x18	R[6]	LOCK		COREID	PROCID
0x1c	R[7]	LOCK		COREID	PROCID
0x20	R[8]	LOCK		COREID	PROCID
0x24	R[9]	LOCK		COREID	PROCID
0x28	R[10]	LOCK		COREID	PROCID
0x2c	R[11]	LOCK		COREID	PROCID
0x30	R[12]	LOCK		COREID	PROCID
0x34	R[13]	LOCK		COREID	PROCID
0x38	R[14]	LOCK		COREID	PROCID
0x3c	R[15]	LOCK		COREID	PROCID
0x40	R[16]	LOCK		COREID	PROCID
0x44	R[17]	LOCK		COREID	PROCID
0x48	R[18]	LOCK		COREID	PROCID
0x4c	R[19]	LOCK		COREID	PROCID
0x50	R[20]	LOCK		COREID	PROCID
0x54	R[21]	LOCK		COREID	PROCID
0x58	R[22]	LOCK		COREID	PROCID
0x5c	R[23]	LOCK		COREID	PROCID
0x60	R[24]	LOCK		COREID	PROCID
0x64	R[25]	LOCK		COREID	PROCID
0x68	R[26]	LOCK		COREID	PROCID
0x6c	R[27]	LOCK		COREID	PROCID
0x70	R[28]	LOCK		COREID	PROCID
0x74	R[29]	LOCK		COREID	PROCID
0x78	R[30]	LOCK		COREID	PROCID
0x7c	R[31]	LOCK		COREID	PROCID
0x80	RLR[0]	LOCK		COREID	PROCID
0x84	RLR[1]	LOCK		COREID	PROCID
0x88	RLR[2]	LOCK		COREID	PROCID
0x8c	RLR[3]	LOCK		COREID	PROCID
0x90	RLR[4]	LOCK		COREID	PROCID
0x94	RLR[5]	LOCK		COREID	PROCID
0x98	RLR[6]	LOCK		COREID	PROCID
0x9c	RLR[7]	LOCK		COREID	PROCID
0xa0	RLR[8]	LOCK		COREID	PROCID
0xa4	RLR[9]	LOCK		COREID	PROCID
0xa8	RLR[10]	LOCK		COREID	PROCID
0xac	RLR[11]	LOCK		COREID	PROCID
0xb0	RLR[12]	LOCK		COREID	PROCID
0xb4	RLR[13]	LOCK		COREID	PROCID
0xb8	RLR[14]	LOCK		COREID	PROCID
0xbc	RLR[15]	LOCK		COREID	PROCID
0xc0	RLR[16]	LOCK		COREID	PROCID
0xc4	RLR[17]	LOCK		COREID	PROCID
0xc8	RLR[18]	LOCK		COREID	PROCID
0xcc	RLR[19]	LOCK		COREID	PROCID
0xd0	RLR[20]	LOCK		COREID	PROCID
0xd4	RLR[21]	LOCK		COREID	PROCID
0xd8	RLR[22]	LOCK		COREID	PROCID
0xdc	RLR[23]	LOCK		COREID	PROCID
0xe0	RLR[24]	LOCK		COREID	PROCID
0xe4	RLR[25]	LOCK		COREID	PROCID
0xe8	RLR[26]	LOCK		COREID	PROCID
0xec	RLR[27]	LOCK		COREID	PROCID
0xf0	RLR[28]	LOCK		COREID	PROCID
0xf4	RLR[29]	LOCK		COREID	PROCID
0xf8	RLR[30]	LOCK		COREID	PROCID
0xfc	RLR[31]	LOCK		COREID	PROCID
0x100	C1IER	ISEm	ISEm
0x104	C1ICR	ISCm	ISCm
0x108	C1ISR	ISFm	ISFm
0x10c	C1MISR	MISFm	MISFm
0x110	C2IER	ISEm	ISEm
0x114	C2ICR	ISCm	ISCm
0x118	C2ISR	ISFm	ISFm
0x11c	C2MISR	MISFm	MISFm
0x140	CR	KEY		COREID
0x144	KEYR	KEY
0x3ec	HWCFGR2		MASTERID4	MASTERID3	MASTERID2	MASTERID1
0x3f0	HWCFGR1			NBINT	NBSEM
0x3f4	VERR				MAJREV	MINREV
0x3f8	IPIDR	ID	ID
0x3fc	SIDR	SID	SID

Toggle registers

R[0]

HSEM register HSEM_R0

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[1]

HSEM register HSEM_R1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[2]

HSEM register HSEM_R2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[3]

HSEM register HSEM_R3

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[4]

HSEM register HSEM_R4

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[5]

HSEM register HSEM_R5

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[6]

HSEM register HSEM_R6

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[7]

HSEM register HSEM_R7

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[8]

HSEM register HSEM_R8

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[9]

HSEM register HSEM_R9

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[10]

HSEM register HSEM_R10

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[11]

HSEM register HSEM_R11

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[12]

HSEM register HSEM_R12

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[13]

HSEM register HSEM_R13

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[14]

HSEM register HSEM_R14

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[15]

HSEM register HSEM_R15

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[16]

HSEM register HSEM_R16

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[17]

HSEM register HSEM_R17

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[18]

HSEM register HSEM_R18

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[19]

HSEM register HSEM_R19

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[20]

HSEM register HSEM_R20

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[21]

HSEM register HSEM_R21

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[22]

HSEM register HSEM_R22

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[23]

HSEM register HSEM_R23

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[24]

HSEM register HSEM_R24

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[25]

HSEM register HSEM_R25

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[26]

HSEM register HSEM_R26

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[27]

HSEM register HSEM_R27

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[28]

HSEM register HSEM_R28

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[29]

HSEM register HSEM_R29

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[30]

HSEM register HSEM_R30

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R[31]

HSEM register HSEM_R31

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[0]

Semaphore 0 read lock register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[1]

Semaphore 1 read lock register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[2]

Semaphore 2 read lock register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[3]

Semaphore 3 read lock register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[4]

Semaphore 4 read lock register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[5]

Semaphore 5 read lock register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[6]

Semaphore 6 read lock register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[7]

Semaphore 7 read lock register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[8]

Semaphore 8 read lock register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[9]

Semaphore 9 read lock register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[10]

Semaphore 10 read lock register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[11]

Semaphore 11 read lock register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[12]

Semaphore 12 read lock register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[13]

Semaphore 13 read lock register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[14]

Semaphore 14 read lock register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[15]

Semaphore 15 read lock register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[16]

Semaphore 16 read lock register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[17]

Semaphore 17 read lock register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[18]

Semaphore 18 read lock register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[19]

Semaphore 19 read lock register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[20]

Semaphore 20 read lock register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[21]

Semaphore 21 read lock register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[22]

Semaphore 22 read lock register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[23]

Semaphore 23 read lock register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[24]

Semaphore 24 read lock register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[25]

Semaphore 25 read lock register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[26]

Semaphore 26 read lock register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[27]

Semaphore 27 read lock register

Offset: 0xec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[28]

Semaphore 28 read lock register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[29]

Semaphore 29 read lock register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[30]

Semaphore 30 read lock register

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR[31]

Semaphore 31 read lock register

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

C1IER

HSEM Interrupt enable register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISEm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISEm rw

Toggle fields

ISEm

Bits 0-31: CPU(n) semaphore m enable bit.

C1ICR

HSEM Interrupt clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISCm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISCm rw

Toggle fields

ISCm

Bits 0-31: CPU(n) semaphore m clear bit.

C1ISR

HSEM Interrupt status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISFm r

Toggle fields

ISFm

Bits 0-31: CPU(n) semaphore m status bit before enable (mask).

C1MISR

HSEM Masked interrupt status register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISFm r

Toggle fields

MISFm

Bits 0-31: masked CPU(n) semaphore m status bit after enable (mask)..

C2IER

HSEM Interrupt enable register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISEm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISEm rw

Toggle fields

ISEm

Bits 0-31: CPU(2) semaphore m enable bit..

C2ICR

HSEM Interrupt clear register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISCm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISCm rw

Toggle fields

ISCm

Bits 0-31: CPU(2) semaphore m clear bit.

C2ISR

HSEM Interrupt status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISFm r

Toggle fields

ISFm

Bits 0-31: CPU(2) semaphore m status bit before enable (mask)..

C2MISR

HSEM Masked interrupt status register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISFm r

Toggle fields

MISFm

Bits 0-31: masked CPU(2) semaphore m status bit after enable (mask)..

CR

Semaphore Clear register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw

Toggle fields

COREID

Bits 8-11: CoreID of semaphore to be cleared.

KEY

Bits 16-31: Semaphore clear Key.

KEYR

Interrupt clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

KEY

Bits 16-31: Semaphore Clear Key.

HWCFGR2

Semaphore hardware configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000084, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MASTERID4 r				MASTERID3 r				MASTERID2 r				MASTERID1 r

Toggle fields

MASTERID1

Bits 0-3: Hardware Configuration valid bus masters ID1.

MASTERID2

Bits 4-7: Hardware Configuration valid bus masters ID2.

MASTERID3

Bits 8-11: Hardware Configuration valid bus masters ID3.

MASTERID4

Bits 12-15: Hardware Configuration valid bus masters ID4.

HWCFGR1

Semaphore hardware configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000220, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBINT r				NBSEM r

Toggle fields

NBSEM

Bits 0-7: Hardware Configuration number of semaphores.

NBINT

Bits 8-11: Hardware Configuration number of interrupts supported number of master IDs.

VERR

HSEM version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle fields

MINREV

Bits 0-3: Minor Revision.

MAJREV

Bits 4-7: Major Revision.

IPIDR

HSEM indentification register

Offset: 0x3f8, size: 32, reset: 0x00100072, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle fields

ID

Bits 0-31: Identification Code.

SIDR

HSEM size indentification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle fields

SID

Bits 0-31: Size Identification Code.

I2C1

0x40005400: Inter-integrated circuit

17/76 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1
0xc	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C3

0x40005c00: Inter-integrated circuit

17/76 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1
0xc	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

IPCC

0x58000c00: IPCC

17/69 fields covered.

Toggle register map

Offset	Name	31	21	20	19	18	17	16	15	7	5	4	3	2	1	0
0x0	C1CR							TXFIE								RXOIE
0x4	C1MR		CH6FM	CH5FM	CH4FM	CH3FM	CH2FM	CH1FM			CH6OM	CH5OM	CH4OM	CH3OM	CH2OM	CH1OM
0x8	C1SCR		CH6S	CH5S	CH4S	CH3S	CH2S	CH1S			CH6C	CH5C	CH4C	CH3C	CH2C	CH1C
0xc	C1TOC2SR										CH6F	CH5F	CH4F	CH3F	CH2F	CH1F
0x10	C2CR							TXFIE								RXOIE
0x14	C2MR		CH6FM	CH5FM	CH4FM	CH3FM	CH2FM	CH1FM			CH6OM	CH5OM	CH4OM	CH3OM	CH2OM	CH1OM
0x18	C2SCR		CH6S	CH5S	CH4S	CH3S	CH2S	CH1S			CH6C	CH5C	CH4C	CH3C	CH2C	CH1C
0x1c	C2TOC1SR										CH6F	CH5F	CH4F	CH3F	CH2F	CH1F
0x3f0	HWCFGR									CHANNELS
0x3f4	VERR									MAJREV			MINREV
0x3f8	IPIDR	IPID							IPID
0x3fc	SIDR	SID							SID

Toggle registers

C1CR

Control register CPU1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TXFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RXOIE rw

Toggle fields

RXOIE

Bit 0: processor 1 Receive channel occupied interrupt enable.

TXFIE

Bit 16: processor 1 Transmit channel free interrupt enable.

C1MR

Mask register CPU1

Offset: 0x4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6FM rw	CH5FM rw	CH4FM rw	CH3FM rw	CH2FM rw	CH1FM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6OM rw	CH5OM rw	CH4OM rw	CH3OM rw	CH2OM rw	CH1OM rw

Toggle fields

CH1OM

Bit 0: processor 1 Receive channel 1 occupied interrupt enable.

CH2OM

Bit 1: processor 1 Receive channel 2 occupied interrupt enable.

CH3OM

Bit 2: processor 1 Receive channel 3 occupied interrupt enable.

CH4OM

Bit 3: processor 1 Receive channel 4 occupied interrupt enable.

CH5OM

Bit 4: processor 1 Receive channel 5 occupied interrupt enable.

CH6OM

Bit 5: processor 1 Receive channel 6 occupied interrupt enable.

CH1FM

Bit 16: processor 1 Transmit channel 1 free interrupt mask.

CH2FM

Bit 17: processor 1 Transmit channel 2 free interrupt mask.

CH3FM

Bit 18: processor 1 Transmit channel 3 free interrupt mask.

CH4FM

Bit 19: processor 1 Transmit channel 4 free interrupt mask.

CH5FM

Bit 20: processor 1 Transmit channel 5 free interrupt mask.

CH6FM

Bit 21: processor 1 Transmit channel 6 free interrupt mask.

C1SCR

Status Set or Clear register CPU1

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6S w	CH5S w	CH4S w	CH3S w	CH2S w	CH1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6C w	CH5C w	CH4C w	CH3C w	CH2C w	CH1C w

Toggle fields

CH1C

Bit 0: processor 1 Receive channel 1 status clear.

CH2C

Bit 1: processor 1 Receive channel 2 status clear.

CH3C

Bit 2: processor 1 Receive channel 3 status clear.

CH4C

Bit 3: processor 1 Receive channel 4 status clear.

CH5C

Bit 4: processor 1 Receive channel 5 status clear.

CH6C

Bit 5: processor 1 Receive channel 6 status clear.

CH1S

Bit 16: processor 1 Transmit channel 1 status set.

CH2S

Bit 17: processor 1 Transmit channel 2 status set.

CH3S

Bit 18: processor 1 Transmit channel 3 status set.

CH4S

Bit 19: processor 1 Transmit channel 4 status set.

CH5S

Bit 20: processor 1 Transmit channel 5 status set.

CH6S

Bit 21: processor 1 Transmit channel 6 status set.

C1TOC2SR

CPU1 to CPU2 status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6F r	CH5F r	CH4F r	CH3F r	CH2F r	CH1F r

Toggle fields

CH1F

Bit 0: processor 1 transmit to process 2 Receive channel 1 status flag.

CH2F

Bit 1: processor 1 transmit to process 2 Receive channel 2 status flag.

CH3F

Bit 2: processor 1 transmit to process 2 Receive channel 3 status flag.

CH4F

Bit 3: processor 1 transmit to process 2 Receive channel 4 status flag.

CH5F

Bit 4: processor 1 transmit to process 2 Receive channel 5 status flag.

CH6F

Bit 5: processor 1 transmit to process 2 Receive channel 6 status flag.

C2CR

Control register CPU2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TXFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RXOIE rw

Toggle fields

RXOIE

Bit 0: processor 2 Receive channel occupied interrupt enable.

TXFIE

Bit 16: processor 2 Transmit channel free interrupt enable.

C2MR

Mask register CPU2

Offset: 0x14, size: 32, reset: 0xFFFFFFFF, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6FM rw	CH5FM rw	CH4FM rw	CH3FM rw	CH2FM rw	CH1FM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6OM rw	CH5OM rw	CH4OM rw	CH3OM rw	CH2OM rw	CH1OM rw

Toggle fields

CH1OM

Bit 0: processor 2 Receive channel 1 occupied interrupt enable.

CH2OM

Bit 1: processor 2 Receive channel 2 occupied interrupt enable.

CH3OM

Bit 2: processor 2 Receive channel 3 occupied interrupt enable.

CH4OM

Bit 3: processor 2 Receive channel 4 occupied interrupt enable.

CH5OM

Bit 4: processor 2 Receive channel 5 occupied interrupt enable.

CH6OM

Bit 5: processor 2 Receive channel 6 occupied interrupt enable.

CH1FM

Bit 16: processor 2 Transmit channel 1 free interrupt mask.

CH2FM

Bit 17: processor 2 Transmit channel 2 free interrupt mask.

CH3FM

Bit 18: processor 2 Transmit channel 3 free interrupt mask.

CH4FM

Bit 19: processor 2 Transmit channel 4 free interrupt mask.

CH5FM

Bit 20: processor 2 Transmit channel 5 free interrupt mask.

CH6FM

Bit 21: processor 2 Transmit channel 6 free interrupt mask.

C2SCR

Status Set or Clear register CPU2

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6S w	CH5S w	CH4S w	CH3S w	CH2S w	CH1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6C w	CH5C w	CH4C w	CH3C w	CH2C w	CH1C w

Toggle fields

CH1C

Bit 0: processor 2 Receive channel 1 status clear.

CH2C

Bit 1: processor 2 Receive channel 2 status clear.

CH3C

Bit 2: processor 2 Receive channel 3 status clear.

CH4C

Bit 3: processor 2 Receive channel 4 status clear.

CH5C

Bit 4: processor 2 Receive channel 5 status clear.

CH6C

Bit 5: processor 2 Receive channel 6 status clear.

CH1S

Bit 16: processor 2 Transmit channel 1 status set.

CH2S

Bit 17: processor 2 Transmit channel 2 status set.

CH3S

Bit 18: processor 2 Transmit channel 3 status set.

CH4S

Bit 19: processor 2 Transmit channel 4 status set.

CH5S

Bit 20: processor 2 Transmit channel 5 status set.

CH6S

Bit 21: processor 2 Transmit channel 6 status set.

C2TOC1SR

CPU2 to CPU1 status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6F r	CH5F r	CH4F r	CH3F r	CH2F r	CH1F r

Toggle fields

CH1F

Bit 0: processor 2 transmit to process 1 Receive channel 1 status flag.

CH2F

Bit 1: processor 2 transmit to process 1 Receive channel 2 status flag.

CH3F

Bit 2: processor 2 transmit to process 1 Receive channel 3 status flag.

CH4F

Bit 3: processor 2 transmit to process 1 Receive channel 4 status flag.

CH5F

Bit 4: processor 2 transmit to process 1 Receive channel 5 status flag.

CH6F

Bit 5: processor 2 transmit to process 1 Receive channel 6 status flag.

HWCFGR

IPCC Hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000006, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CHANNELS r

Toggle fields

CHANNELS

Bits 0-7: Number of channels per CPU supported by the IP, range 1 to 16.

VERR

IPCC version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle fields

MINREV

Bits 0-3: Minor Revision.

MAJREV

Bits 4-7: Major Revision.

IPIDR

IPCC indentification register

Offset: 0x3f8, size: 32, reset: 0x00100071, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle fields

IPID

Bits 0-31: Identification Code.

SIDR

IPCC size indentification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle fields

SID

Bits 0-31: Size Identification Code.

IWDG

0x40003000: Independent watchdog

3/7 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0	KR	KEY
0x4	PR			PR
0x8	RLR		RL
0xc	SR			WVU	RVU	PVU
0x10	WINR		WIN

Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

LCD

0x40002400: Liquid crystal display controller

5/280 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR																								BUFEN	MUX_SEG	BIAS		DUTY			VSEL	LCDEN
0x4	FCR							PS				DIV				BLINK		BLINKF			CC			DEAD			PON			UDDIE		SOFIE	HD
0x8	SR																											FCRSF	RDY	UDD	UDR	SOF	ENS
0xc	CLR																													UDDC		SOFC
0x14	RAM_COM0	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x1c	RAM_COM1	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x24	RAM_COM2	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x2c	RAM_COM3	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x34	RAM_COM4	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x3c	RAM_COM5	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x44	RAM_COM6	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00
0x4c	RAM_COM7	S31	S30	S29	S28	S27	S26	S25	S24	S23	S22	S21	S20	S19	S18	S17	S16	S15	S14	S13	S12	S11	S10	S09	S08	S07	S06	S05	S04	S03	S02	S01	S00

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							BUFEN rw	MUX_SEG rw	BIAS rw		DUTY rw			VSEL rw	LCDEN rw

Toggle fields

LCDEN

Bit 0: LCD controller enable.

VSEL

Bit 1: Voltage source selection.

DUTY

Bits 2-4: Duty selection.

BIAS

Bits 5-6: Bias selector.

MUX_SEG

Bit 7: Mux segment enable.

BUFEN

Bit 8: Voltage output buffer enable.

FCR

frame control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PS rw				DIV rw				BLINK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BLINKF rw			CC rw			DEAD rw			PON rw			UDDIE rw		SOFIE rw	HD rw

Toggle fields

HD

Bit 0: High drive enable.

SOFIE

Bit 1: Start of frame interrupt enable.

UDDIE

Bit 3: Update display done interrupt enable.

PON

Bits 4-6: Pulse ON duration.

DEAD

Bits 7-9: Dead time duration.

CC

Bits 10-12: Contrast control.

BLINKF

Bits 13-15: Blink frequency selection.

BLINK

Bits 16-17: Blink mode selection.

DIV

Bits 18-21: DIV clock divider.

PS

Bits 22-25: PS 16-bit prescaler.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000020, access: Unspecified

5/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FCRSF r	RDY r	UDD r	UDR rw	SOF r	ENS r

Toggle fields

ENS

Bit 0: ENS.

SOF

Bit 1: Start of frame flag.

UDR

Bit 2: Update display request.

UDD

Bit 3: Update Display Done.

RDY

Bit 4: Ready flag.

FCRSF

Bit 5: LCD Frame Control Register Synchronization flag.

CLR

clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												UDDC w		SOFC w

Toggle fields

SOFC

Bit 1: Start of frame flag clear.

UDDC

Bit 3: Update display done clear.

RAM_COM0

display memory

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM1

display memory

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM2

display memory

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM3

display memory

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM4

display memory

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM5

display memory

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM6

display memory

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM7

display memory

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

LPTIM1

0x40007c00: Low power timer

8/44 fields covered.

Toggle register map

Offset	Name	24	23	22	21	20	19	18	15	11	7	6	5	4	3	2	1	0
0x0	ISR											DOWN	UP	ARROK	CMPOK	EXTTRIG	ARRM	CMPM
0x4	ICR											DOWNCF	UPCF	ARROKCF	CMPOKCF	EXTTRIGCF	ARRMCF	CMPMCF
0x8	IER											DOWNIE	UPIE	ARROKIE	CMPOKIE	EXTTRIGIE	ARRMIE	CMPMIE
0xc	CFGR	ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN	TRIGSEL	PRESC	TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR													RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CMP								CMP
0x18	ARR								ARR
0x1c	CNT								CNT
0x20	OR																OR2	OR1

Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWN r	UP r	ARROK r	CMPOK r	EXTTRIG r	ARRM r	CMPM r

Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNCF w	UPCF w	ARROKCF w	CMPOKCF w	EXTTRIGCF w	ARRMCF w	CMPMCF w

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNIE rw	UPIE rw	ARROKIE rw	CMPOKIE rw	EXTTRIGIE rw	ARRMIE rw	CMPMIE rw

Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP rw

Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

OR

Option Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OR2 rw	OR1 rw

Toggle fields

OR1

Bit 0: Option register bit 1.

OR2

Bit 1: Option register bit 2.

LPTIM2

0x40009400: Low power timer

8/44 fields covered.

Toggle register map

Offset	Name	24	23	22	21	20	19	18	15	11	7	6	5	4	3	2	1	0
0x0	ISR											DOWN	UP	ARROK	CMPOK	EXTTRIG	ARRM	CMPM
0x4	ICR											DOWNCF	UPCF	ARROKCF	CMPOKCF	EXTTRIGCF	ARRMCF	CMPMCF
0x8	IER											DOWNIE	UPIE	ARROKIE	CMPOKIE	EXTTRIGIE	ARRMIE	CMPMIE
0xc	CFGR	ENC	COUNTMODE	PRELOAD	WAVPOL	WAVE	TIMOUT	TRIGEN	TRIGSEL	PRESC	TRGFLT			CKFLT		CKPOL		CKSEL
0x10	CR													RSTARE	COUNTRST	CNTSTRT	SNGSTRT	ENABLE
0x14	CMP								CMP
0x18	ARR								ARR
0x1c	CNT								CNT
0x20	OR																OR2	OR1

Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWN r	UP r	ARROK r	CMPOK r	EXTTRIG r	ARRM r	CMPM r

Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNCF w	UPCF w	ARROKCF w	CMPOKCF w	EXTTRIGCF w	ARRMCF w	CMPMCF w

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNIE rw	UPIE rw	ARROKIE rw	CMPOKIE rw	EXTTRIGIE rw	ARRMIE rw	CMPMIE rw

Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP rw

Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle fields

CNT

Bits 0-15: Counter value.

OR

Option Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OR2 rw	OR1 rw

Toggle fields

OR1

Bit 0: Option register bit 1.

OR2

Bit 1: Option register bit 2.

LPUART1

0x40008000: Universal synchronous asynchronous receiver transmitter

29/134 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT4	DEAT3	DEAT2	DEAT1	DEAT0	DEDT4	DEDT3	DEDT2	DEDT1	DEDT0	OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3				RTOEN	ABRMOD1	ABRMOD0	ABREN	MSBFIRST	TAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT4 rw	DEAT3 rw	DEAT2 rw	DEAT1 rw	DEAT0 rw	DEDT4 rw	DEDT3 rw	DEDT2 rw	DEDT1 rw	DEDT0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD1 rw	ABRMOD0 rw	ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

MPU

0xe000ed90: Memory protection unit

6/19 fields covered.

Toggle register map

Offset	Name	31	28	26	23	21	18	17	16	15	7	5	4	3	2	1	0
0x0	TYPER				IREGION					DREGION							SEPARATE
0x4	CTRL														PRIVDEFENA	HFNMIENA	ENABLE
0x8	RNR										REGION
0xc	RBAR	ADDR								ADDR			VALID	REGION
0x10	RASR		XN	AP		TEX	S	C	B	SRD		SIZE					ENABLE

Toggle registers

TYPER

MPU type register

Offset: 0x0, size: 32, reset: 0x00000800, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								IREGION r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DREGION r															SEPARATE r

Toggle fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

CTRL

MPU control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PRIVDEFENA r	HFNMIENA r	ENABLE r

Toggle fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

RNR

MPU region number register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REGION rw

Toggle fields

REGION

Bits 0-7: MPU region.

RBAR

MPU region base address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR rw											VALID rw	REGION rw

Toggle fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

RASR

MPU region attribute and size register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			XN rw		AP rw					TEX rw			S rw	C rw	B rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRD rw										SIZE rw					ENABLE rw

Toggle fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

2/82 fields covered.

Toggle register map

Offset	Name	31	23	15	7
0x0	ISER0	SETENA		SETENA
0x4	ISER1	SETENA		SETENA
0x80	ICER0	CLRENA		CLRENA
0x84	ICER1	CLRENA		CLRENA
0x100	ISPR0	SETPEND		SETPEND
0x104	ISPR1	SETPEND		SETPEND
0x180	ICPR0	CLRPEND		CLRPEND
0x184	ICPR1	CLRPEND		CLRPEND
0x200	IABR0	ACTIVE		ACTIVE
0x204	IABR1	ACTIVE		ACTIVE
0x300	IPR0	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x304	IPR1	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x308	IPR2	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x30c	IPR3	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x310	IPR4	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x314	IPR5	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x318	IPR6	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x31c	IPR7	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x320	IPR8	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x324	IPR9	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x328	IPR10	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x32c	IPR11	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x330	IPR12	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x334	IPR13	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x338	IPR14	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x33c	IPR15	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x340	IPR16	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x344	IPR17	IPR_N3	IPR_N2	IPR_N1	IPR_N0

Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	STIR																								INTID

Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							INTID rw

Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

PKA

0x58002000: PKA

8/18 fields covered.

Toggle register map

Offset	Name	31	20	19	17	16	15	13	7	3	2	1	0
0x0	CR		ADDRERRIE	RAMERRIE	PROCENDIE			MODE			SECLVL	START	EN
0x4	SR		ADDRERRF	RAMERRF	PROCENDF	BUSY
0x8	CLRFR		ADDRERRFC	RAMERRFC	PROCENDFC
0x1ff4	VERR								MAJREV	MINREV
0x1ff8	IPIDR	ID					ID
0x1ffc	SIDR	SID					SID

Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRIE rw	RAMERRIE rw		PROCENDIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MODE rw											SECLVL rw	START rw	EN rw

Toggle fields

EN

Bit 0: Peripheral Enable.

START

Bit 1: Start the operation.

SECLVL

Bit 2: Security Enable.

MODE

Bits 8-13: PKA Operation Mode.

PROCENDIE

Bit 17: End of operation interrupt enable.

RAMERRIE

Bit 19: RAM error interrupt enable.

ADDRERRIE

Bit 20: Address error interrupt enable.

SR

PKA status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRF r	RAMERRF r		PROCENDF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

BUSY

Bit 16: PKA Operation in progress.

PROCENDF

Bit 17: PKA End of Operation flag.

RAMERRF

Bit 19: RAM error flag.

ADDRERRF

Bit 20: Address error flag.

CLRFR

PKA clear flag register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRFC rw	RAMERRFC rw		PROCENDFC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PROCENDFC

Bit 17: Clear PKA End of Operation flag.

RAMERRFC

Bit 19: Clear RAM error flag.

ADDRERRFC

Bit 20: Clear Address error flag.

VERR

PKA version register

Offset: 0x1ff4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle fields

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

PKA identification register

Offset: 0x1ff8, size: 32, reset: 0x00170061, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle fields

ID

Bits 0-31: Identification Code.

SIDR

PKA size ID register

Offset: 0x1ffc, size: 32, reset: 0xA3C5DD08, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle fields

SID

Bits 0-31: Side Identification Code.

PWR

0x58000400: Power control

29/237 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1		LPR				VOS		DBP			FPDS	FPDR		LPMS
0x4	CR2						USV				PVME3		PVME1	PLS			PVDE
0x8	CR3	EIWUL	EC2H	E802A	ECRPE	EBLEA	APC	RRS	EBORHSDFB				EWUP5	EWUP4	EWUP3	EWUP2	EWUP1
0xc	CR4	C2BOOT						VBRS	VBE				WP5	WP4	WP3	WP2	WP1
0x10	SR1	WUFI	C2HF	AF802	BLEAF	CRPEF	_802WUF	BLEWUF	BORHF	SDFBF			CWUF5	CWUF4	CWUF3	CWUF2	CWUF1
0x14	SR2		PVMO3		PVMO1	PVDO	VOSF	REGLPF	REGLPS							SDSMPSF	SDBF
0x18	SCR		CC2HF	C802AF	CBLEAF	CCRPEF	C802WUF	CBLEWUF	CBORHF	CSMPSFBF			CWUF5	CWUF4	CWUF3	CWUF2	CWUF1
0x1c	CR5	SDEB	SDBEN					SMPSCFG	BORHC		SDSC			SDVOS
0x20	PUCRA	PU15		PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x24	PDCRA		PD14		PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x28	PUCRB	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x2c	PDCRB	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5		PD3	PD2	PD1	PD0
0x30	PUCRC	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x34	PDCRC	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x38	PUCRD	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x3c	PDCRD	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x40	PUCRE												PU4	PU3	PU2	PU1	PU0
0x44	PDCRE												PD4	PD3	PD2	PD1	PD0
0x58	PUCRH													PU3		PU1	PU0
0x5c	PDCRH													PD3		PD1	PD0
0x80	C2CR1	_802EWKUP	BLEEWKUP									FPDS	FPDR		LPMS
0x84	C2CR3	EIWUL			APC		E802WUP	EBLEWUP					EWUP5	EWUP4	EWUP3	EWUP2	EWUP1
0x88	EXTSCR	C2DS	C1DS	CRPF		C2STOPF	C2SBF	C1STOPF	C1SBF						CCRPF	C2CSSF	C1CSSF

Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LPR rw				VOS rw		DBP rw			FPDS rw	FPDR rw		LPMS rw

Toggle fields

LPMS

Bits 0-2: Low-power mode selection for CPU1.

FPDR

Bit 4: Flash power down mode during LPRun for CPU1.

FPDS

Bit 5: Flash power down mode during LPsSleep for CPU1.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					USV rw				PVME3 rw		PVME1 rw	PLS rw			PVDE rw

Toggle fields

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00008000, access: read-write

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWUL rw	EC2H rw	E802A rw	ECRPE rw	EBLEA rw	APC rw	RRS rw	EBORHSDFB rw				EWUP5 rw	EWUP4 rw	EWUP3 rw	EWUP2 rw	EWUP1 rw

Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

EBORHSDFB

Bit 8: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1.

RRS

Bit 9: SRAM2a retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

EBLEA

Bit 11: Enable BLE end of activity interrupt for CPU1.

ECRPE

Bit 12: Enable critical radio phase end of activity interrupt for CPU1.

E802A

Bit 13: Enable end of activity interrupt for CPU1.

EC2H

Bit 14: Enable CPU2 Hold interrupt for CPU1.

EIWUL

Bit 15: Enable internal wakeup line for CPU1.

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C2BOOT rw						VBRS rw	VBE rw				WP5 rw	WP4 rw	WP3 rw	WP2 rw	WP1 rw

Toggle fields

WP1

Bit 0: Wakeup pin WKUP1 polarity.

WP2

Bit 1: Wakeup pin WKUP2 polarity.

WP3

Bit 2: Wakeup pin WKUP3 polarity.

WP4

Bit 3: Wakeup pin WKUP4 polarity.

WP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

C2BOOT

Bit 15: BOOT CPU2 after reset or wakeup from Stop or Standby modes.

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUFI r	C2HF r	AF802 r	BLEAF r	CRPEF r	_802WUF r	BLEWUF r	BORHF r	SDFBF r			CWUF5 r	CWUF4 r	CWUF3 r	CWUF2 r	CWUF1 r

Toggle fields

CWUF1

Bit 0: Wakeup flag 1.

CWUF2

Bit 1: Wakeup flag 2.

CWUF3

Bit 2: Wakeup flag 3.

CWUF4

Bit 3: Wakeup flag 4.

CWUF5

Bit 4: Wakeup flag 5.

SDFBF

Bit 7: Step Down converter forced in Bypass interrupt flag.

BORHF

Bit 8: BORH interrupt flag.

BLEWUF

Bit 9: BLE wakeup interrupt flag.

_802WUF

Bit 10: 802.15.4 wakeup interrupt flag.

CRPEF

Bit 11: Enable critical radio phase end of activity interrupt flag.

BLEAF

Bit 12: BLE end of activity interrupt flag.

AF802

Bit 13: 802.15.4 end of activity interrupt flag.

C2HF

Bit 14: CPU2 Hold interrupt flag.

WUFI

Bit 15: Internal Wakeup interrupt flag.

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000002, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PVMO3 r		PVMO1 r	PVDO r	VOSF r	REGLPF r	REGLPS r							SDSMPSF r	SDBF r

Toggle fields

SDBF

Bit 0: Step Down converter Bypass mode flag.

SDSMPSF

Bit 1: Step Down converter SMPS mode flag.

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CC2HF w	C802AF w	CBLEAF w	CCRPEF w	C802WUF w	CBLEWUF w	CBORHF w	CSMPSFBF w			CWUF5 w	CWUF4 w	CWUF3 w	CWUF2 w	CWUF1 w

Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CSMPSFBF

Bit 7: Clear SMPS Step Down converter forced in Bypass interrupt flag.

CBORHF

Bit 8: Clear BORH interrupt flag.

CBLEWUF

Bit 9: Clear BLE wakeup interrupt flag.

C802WUF

Bit 10: Clear 802.15.4 wakeup interrupt flag.

CCRPEF

Bit 11: Clear critical radio phase end of activity interrupt flag.

CBLEAF

Bit 12: Clear BLE end of activity interrupt flag.

C802AF

Bit 13: Clear 802.15.4 end of activity interrupt flag.

CC2HF

Bit 14: Clear CPU2 Hold interrupt flag.

CR5

Power control register 5

Offset: 0x1c, size: 32, reset: 0x00004270, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SDEB rw	SDBEN rw					SMPSCFG rw	BORHC rw		SDSC rw			SDVOS rw

Toggle fields

SDVOS

Bits 0-3: Step Down converter voltage output scaling.

SDSC

Bits 4-6: Step Down converter supplt startup current selection.

BORHC

Bit 8: BORH configuration selection.

SMPSCFG

Bit 9: VOS configuration selection (non user).

SDBEN

Bit 14: Enable Step Down converter Bypass mode enabled.

SDEB

Bit 15: Enable Step Down converter SMPS mode enabled.

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw		PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PD14 rw		PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw		PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PU3 rw		PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port H pull-up bit y (y=0..1).

PU1

Bit 1: Port H pull-up bit y (y=0..1).

PU3

Bit 3: Port H pull-up bit y (y=0..1).

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PD3 rw		PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port H pull-down bit y (y=0..1).

PD1

Bit 1: Port H pull-down bit y (y=0..1).

PD3

Bit 3: Port H pull-down bit y (y=0..1).

C2CR1

CPU2 Power control register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
_802EWKUP rw	BLEEWKUP rw									FPDS rw	FPDR rw		LPMS rw

Toggle fields

LPMS

Bits 0-2: Low-power mode selection for CPU2.

FPDR

Bit 4: Flash power down mode during LPRun for CPU2.

FPDS

Bit 5: Flash power down mode during LPSleep for CPU2.

BLEEWKUP

Bit 14: BLE external wakeup signal.

_802EWKUP

Bit 15: 802.15.4 external wakeup signal.

C2CR3

CPU2 Power control register 3

Offset: 0x84, size: 32, reset: 0x00008000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWUL rw			APC rw		E802WUP rw	EBLEWUP rw					EWUP5 rw	EWUP4 rw	EWUP3 rw	EWUP2 rw	EWUP1 rw

Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1 for CPU2.

EWUP2

Bit 1: Enable Wakeup pin WKUP2 for CPU2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3 for CPU2.

EWUP4

Bit 3: Enable Wakeup pin WKUP4 for CPU2.

EWUP5

Bit 4: Enable Wakeup pin WKUP5 for CPU2.

EBLEWUP

Bit 9: Enable BLE host wakeup interrupt for CPU2.

E802WUP

Bit 10: Enable 802.15.4 host wakeup interrupt for CPU2.

APC

Bit 12: Apply pull-up and pull-down configuration for CPU2.

EIWUL

Bit 15: Enable internal wakeup line for CPU2.

EXTSCR

Power status clear register

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

7/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C2DS r	C1DS r	CRPF r		C2STOPF r	C2SBF r	C1STOPF r	C1SBF r						CCRPF w	C2CSSF w	C1CSSF w

Toggle fields

C1CSSF

Bit 0: Clear CPU1 Stop Standby flags.

C2CSSF

Bit 1: Clear CPU2 Stop Standby flags.

CCRPF

Bit 2: Clear Critical Radio system phase.

C1SBF

Bit 8: System Standby flag for CPU1.

C1STOPF

Bit 9: System Stop flag for CPU1.

C2SBF

Bit 10: System Standby flag for CPU2.

C2STOPF

Bit 11: System Stop flag for CPU2.

CRPF

Bit 13: Critical Radio system phase.

C1DS

Bit 14: CPU1 deepsleep mode.

C2DS

Bit 15: CPU2 deepsleep mode.

QUADSPI

0xa0001000: QuadSPI interface

7/47 fields covered.

Toggle register map

Offset	Name	31	28	27	25	23	22	20	19	18	17	16	15	13	12	11	10	9	7	5	4	3	2	1	0
0x0	CR	PRESCALER				PMM	APMS	TOIE	SMIE	FTIE	TCIE	TEIE				FTHRES					SSHIFT	TCEN	DMAEN	ABORT	EN
0x4	DCR							FSIZE									CSHT								CKMODE
0x8	SR														FLEVEL					BUSY	TOF	SMF	FTF	TCF	TEF
0xc	FCR																				CTOF	CSMF		CTCF	CTEF
0x10	DLR	DL											DL
0x14	CCR	DDRM	SIOO	FMODE	DMODE		DCYC				ABSIZE		ABMODE	ADSIZE		ADMODE		IMODE	INSTRUCTION
0x18	AR	ADDRESS											ADDRESS
0x1c	ABR	ALTERNATE											ALTERNATE
0x20	DR	DATA											DATA
0x24	PSMKR	MASK											MASK
0x28	PSMAR	MATCH											MATCH
0x2c	PIR												INTERVAL
0x30	LPTR												TIMEOUT

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESCALER rw								PMM rw	APMS rw		TOIE rw	SMIE rw	FTIE rw	TCIE rw	TEIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				FTHRES rw							SSHIFT rw	TCEN rw	DMAEN rw	ABORT rw	EN rw

Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

SSHIFT

Bit 4: Sample shift.

FTHRES

Bits 8-11: FIFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

PRESCALER

Bits 24-31: Clock prescaler.

DCR

device configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CSHT rw										CKMODE rw

Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

CSHT

Bits 8-10: Chip select high time.

FSIZE

Bits 16-20: FLASH memory size.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FLEVEL r							BUSY r	TOF r	SMF r	FTF r	TCF r	TEF r

Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: Busy.

FLEVEL

Bits 8-12: FIFO level.

FCR

flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CTOF rw	CSMF rw		CTCF rw	CTEF rw

Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DL rw

Toggle fields

DL

Bits 0-31: Data length.

CCR

communication configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DDRM rw			SIOO rw	FMODE rw		DMODE rw			DCYC rw					ABSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABMODE rw		ADSIZE rw		ADMODE rw		IMODE rw		INSTRUCTION rw

Toggle fields

INSTRUCTION

Bits 0-7: Instruction.

IMODE

Bits 8-9: Instruction mode.

ADMODE

Bits 10-11: Address mode.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 14-15: Alternate bytes mode.

ABSIZE

Bits 16-17: Alternate bytes size.

DCYC

Bits 18-22: Number of dummy cycles.

DMODE

Bits 24-25: Data mode.

FMODE

Bits 26-27: Functional mode.

SIOO

Bit 28: Send instruction only once mode.

DDRM

Bit 31: Double data rate mode.

AR

address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDRESS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS rw

Toggle fields

ADDRESS

Bits 0-31: Address.

ABR

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle fields

ALTERNATE

Bits 0-31: ALTERNATE.

DR

data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MASK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MASK rw

Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle fields

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INTERVAL rw

Toggle fields

INTERVAL

Bits 0-15: Polling interval.

LPTR

low-power timeout register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUT rw

Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

RCC

0x58000000: Reset and clock control

43/324 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR					PLLSAI1RDY	PLLSAI1ON	PLLRDY	PLLON			HSEPRE	CSSON	HSEBYP	HSERDY	HSEON				HSIKERDY	HSIASFS	HSIRDY	HSIKERON	HSION	MSIRANGE					MSIPLLEN	MSIRDY	MSION
0x4	ICSCR		HSITRIM							HSICAL							MSITRIM								MSICAL
0x8	CFGR		MCOPRE			MCOSEL								PPRE2F	PPRE1F	HPREF	STOPWUCK		PPRE2			PPRE1			HPRE				SWS		SW
0xc	PLLCFGR	PLLR			PLLREN	PLLQ			PLLQEN		PLLP					PLLPEN		PLLN								PLLM					PLLSRC
0x10	PLLSAI1CFGR	PLLR			PLLREN	PLLQ			PLLQEN		PLLP					PLLPEN		PLLN
0x18	CIER																				LSI2RDYIE	HSI48RDYIE	LSECSSIE			PLLSAI1RDYIE	PLLRDYIE	HSERDYIE	HSIRDYIE	MSIRDYIE	LSERDYIE	LSI1RDYIE
0x1c	CIFR																				LSI2RDYF	HSI48RDYF	LSECSSF	HSECSSF		PLLSAI1RDYF	PLLRDYF	HSERDYF	HSIRDYF	MSIRDYF	LSERDYF	LSI1RDYF
0x20	CICR																				LSI2RDYC	HSI48RDYC	LSECSSC	HSECSSC		PLLSAI1RDYC	PLLRDYC	HSERDYC	HSIRDYC	MSIRDYC	LSERDYC	LSI1RDYC
0x24	SMPSCR																						SMPSSWS				SMPSDIV				SMPSSEL
0x28	AHB1RSTR															TSCRST				CRCRST										DMAMUXRST	DMA2RST	DMA1RST
0x2c	AHB2RSTR															AES1RST			ADCRST						GPIOHRST			GPIOERST	GPIODRST	GPIOCRST	GPIOBRST	GPIOARST
0x30	AHB3RSTR							FLASHRST				IPCCRST	HSEMRST	RNGRST	AES2RST	PKARST								QSPIRST
0x38	APB1RSTR1	LPTIM1RST					USBFSRST		CRSRST	I2C3RST	I2C1RST							SPI2RST					LCDRST									TIM2RST
0x3c	APB1RSTR2																										LPTIM2RST					LPUART1RST
0x40	APB2RSTR										SAI1RST			TIM17RST	TIM16RST			USART1RST		SPI1RST	TIM1RST
0x44	APB3RSTR																															RFRST
0x48	AHB1ENR															TSCEN				CRCEN										DMAMUXEN	DMA2EN	DMA1EN
0x4c	AHB2ENR															AES1EN			ADCEN						GPIOHEN			GPIOEEN	GPIODEN	GPIOCEN	GPIOBEN	GPIOAEN
0x50	AHB3ENR							FLASHEN				IPCCEN	HSEMEN	RNGEN	AES2EN	PKAEN								QSPIEN
0x58	APB1ENR1	LPTIM1EN					USBEN		CRSEN	I2C3EN	I2C1EN							SPI2EN			WWDGEN	RTCAPBEN	LCDEN									TIM2EN
0x5c	APB1ENR2																										LPTIM2EN					LPUART1EN
0x60	APB2ENR										SAI1EN			TIM17EN	TIM16EN			USART1EN		SPI1EN	TIM1EN
0x68	AHB1SMENR															TSCSMEN				CRCSMEN			SRAM1SMEN							DMAMUXSMEN	DMA2SMEN	DMA1SMEN
0x6c	AHB2SMENR															AES1SMEN			ADCFSSMEN						GPIOHSMEN			GPIOESMEN	GPIODSMEN	GPIOCSMEN	GPIOBSMEN	GPIOASMEN
0x70	AHB3SMENR							FLASHSMEN	SRAM2SMEN					RNGSMEN	AES2SMEN	PKASMEN								QSPISMEN
0x78	APB1SMENR1	LPTIM1SMEN					USBSMEN		CRSMEN	I2C3SMEN	I2C1SMEN							SPI2SMEN			WWDGSMEN	RTCAPBSMEN	LCDSMEN									TIM2SMEN
0x7c	APB1SMENR2																										LPTIM2SMEN					LPUART1SMEN
0x80	APB2SMENR										SAI1SMEN			TIM17SMEN	TIM16SMEN			USART1SMEN		SPI1SMEN	TIM1SMEN
0x88	CCIPR	RNGSEL		ADCSEL		CLK48SEL				SAI1SEL	LPTIM2SEL		LPTIM1SEL		I2C3SEL				I2C1SEL		LPUART1SEL										USART1SEL
0x90	BDCR						LSCOSEL		LSCOEN							BDRST	RTCEN						RTCSEL			LSECSSD_	LSECSSON	LSEDRV		LSEBYP	LSERDY	LSEON
0x94	CSR	LPWRRSTF	WWDGRSTF	IWDGRSTF	SFTRSTF	BORRSTF	PINRSTF	OBLRSTF		RMVF						RFRSTS	RFWKPSEL				LSI2BW						LSI2TRIMOK	LSI2TRIMEN	LSI2RDY	LSI2ON	LSI1RDY	LSI1ON
0x98	CRRCR																HSI48CAL														HSI48RDY	HSI48ON
0x9c	HSECR																		HSETUNE							HSEGMC			HSES			UNLOCKED
0x108	EXTCFGR											RFCSS			C2HPREF	SHDHPREF									C2HPRE				SHDHPRE
0x148	C2AHB1ENR															TSCEN				CRCEN			SRAM1EN							DMAMUXEN	DMA2EN	DMA1EN
0x14c	C2AHB2ENR															AES1EN			ADCEN						GPIOHEN			GPIOEEN	GPIODEN	GPIOCEN	GPIOBEN	GPIOAEN
0x150	C2AHB3ENR							FLASHEN				IPCCEN	HSEMEN	RNGEN	AES2EN	PKAEN
0x158	C2APB1ENR1	LPTIM1EN					USBEN		CRSEN	I2C3EN	I2C1EN							SPI2EN				RTCAPBEN	LCDEN									TIM2EN
0x15c	C2APB1ENR2																										LPTIM2EN					LPUART1EN
0x160	C2APB2ENR										SAI1EN			TIM17EN	TIM16EN			USART1EN		SPI1EN	TIM1EN
0x164	C2APB3ENR																														EN802	BLEEN
0x168	C2AHB1SMENR															TSCSMEN				CRCSMEN			SRAM1SMEN							DMAMUXSMEN	DMA2SMEN	DMA1SMEN
0x16c	C2AHB2SMENR															AES1SMEN			ADCFSSMEN						GPIOHSMEN			GPIOESMEN	GPIODSMEN	GPIOCSMEN	GPIOBSMEN	GPIOASMEN
0x170	C2AHB3SMENR							FLASHSMEN	SRAM2SMEN					RNGSMEN	AES2SMEN	PKASMEN
0x178	C2APB1SMENR1	LPTIM1SMEN					USBSMEN		CRSMEN	I2C3SMEN	I2C1SMEN							SPI2SMEN				RTCAPBSMEN	LCDSMEN									TIM2SMEN
0x17c	C2APB1SMENR2																										LPTIM2SMEN					LPUART1SMEN
0x180	C2APB2SMENR										SAI1SMEN			TIM17SMEN	TIM16SMEN			USART1SMEN		SPI1SMEN	TIM1SMEN
0x184	C2APB3SMENR																														SMEN802	BLESMEN

Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000061, access: Unspecified

6/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				PLLSAI1RDY r	PLLSAI1ON rw	PLLRDY r	PLLON rw				HSEPRE rw	CSSON w	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSIKERDY r	HSIASFS rw	HSIRDY r	HSIKERON rw	HSION rw	MSIRANGE rw					MSIPLLEN rw	MSIRDY r	MSION rw

Toggle fields

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI clock enabled.

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

HSIASFS

Bit 11: HSI automatic start from Stop.

HSIKERDY

Bit 12: HSI kernel clock ready flag for peripherals requests.

HSEON

Bit 16: HSE clock enabled.

HSERDY

Bit 17: HSE clock ready flag.

HSEBYP

Bit 18: HSE crystal oscillator bypass.

CSSON

Bit 19: HSE Clock security system enable.

HSEPRE

Bit 20: HSE sysclk and PLL M divider prescaler.

PLLON

Bit 24: Main PLL enable.

PLLRDY

Bit 25: Main PLL clock ready flag.

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	HSITRIM rw							HSICAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSITRIM rw								MSICAL r

Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00070000, access: Unspecified

4/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCOPRE rw			MCOSEL rw									PPRE2F r	PPRE1F r	HPREF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
STOPWUCK rw		PPRE2 rw			PPRE1 rw			HPRE rw				SWS r		SW rw

Toggle fields

SW

Bits 0-1: System clock switch.

SWS

Bits 2-3: System clock switch status.

HPRE

Bits 4-7: AHB prescaler.

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

HPREF

Bit 16: AHB prescaler flag.

PPRE1F

Bit 17: APB1 prescaler flag.

PPRE2F

Bit 18: APB2 prescaler flag.

MCOSEL

Bits 24-27: Microcontroller clock output.

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

PLLCFGR

PLLSYS configuration register

Offset: 0xc, size: 32, reset: 0x22040100, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PLLR rw			PLLREN rw	PLLQ rw			PLLQEN rw			PLLP rw					PLLPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLN rw								PLLM rw					PLLSRC rw

Toggle fields

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-6: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLLSYS multiplication factor N.

PLLPEN

Bit 16: Main PLLSYSP output enable.

PLLP

Bits 17-21: Main PLL division factor P for PPLSYSSAICLK.

PLLQEN

Bit 24: Main PLLSYSQ output enable.

PLLQ

Bits 25-27: Main PLLSYS division factor Q for PLLSYSUSBCLK.

PLLREN

Bit 28: Main PLLSYSR PLLCLK output enable.

PLLR

Bits 29-31: Main PLLSYS division factor R for SYSCLK (system clock).

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, size: 32, reset: 0x22040100, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PLLR rw			PLLREN rw	PLLQ rw			PLLQEN rw			PLLP rw					PLLPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLN rw

Toggle fields

PLLN

Bits 8-14: SAIPLL multiplication factor for VCO.

PLLPEN

Bit 16: SAIPLL PLLSAI1CLK output enable.

PLLP

Bits 17-21: SAI1PLL division factor P for PLLSAICLK (SAI1clock).

PLLQEN

Bit 24: SAIPLL PLLSAIUSBCLK output enable.

PLLQ

Bits 25-27: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock).

PLLREN

Bit 28: PLLSAI PLLADC1CLK output enable.

PLLR

Bits 29-31: PLLSAI division factor R for PLLADC1CLK (ADC clock).

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LSI2RDYIE rw	HSI48RDYIE rw	LSECSSIE rw			PLLSAI1RDYIE rw	PLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw	MSIRDYIE rw	LSERDYIE rw	LSI1RDYIE rw

Toggle fields

LSI1RDYIE

Bit 0: LSI1 ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLLSYS ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

LSI2RDYIE

Bit 11: LSI2 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LSI2RDYF r	HSI48RDYF r	LSECSSF r	HSECSSF r		PLLSAI1RDYF r	PLLRDYF r	HSERDYF r	HSIRDYF r	MSIRDYF r	LSERDYF r	LSI1RDYF r

Toggle fields

LSI1RDYF

Bit 0: LSI1 ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

HSECSSF

Bit 8: HSE Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

LSI2RDYF

Bit 11: LSI2 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LSI2RDYC w	HSI48RDYC w	LSECSSC w	HSECSSC w		PLLSAI1RDYC w	PLLRDYC w	HSERDYC w	HSIRDYC w	MSIRDYC w	LSERDYC w	LSI1RDYC w

Toggle fields

LSI1RDYC

Bit 0: LSI1 ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

HSECSSC

Bit 8: HSE Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 ready interrupt clear.

LSI2RDYC

Bit 11: LSI2 ready interrupt clear.

SMPSCR

Step Down converter control register

Offset: 0x24, size: 32, reset: 0x00000301, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						SMPSSWS r				SMPSDIV rw				SMPSSEL rw

Toggle fields

SMPSSEL

Bits 0-1: Step Down converter clock selection.

SMPSDIV

Bits 4-5: Step Down converter clock prescaler.

SMPSSWS

Bits 8-9: Step Down converter clock switch status.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw										DMAMUXRST rw	DMA2RST rw	DMA1RST rw

Toggle fields

DMA1RST

Bit 0: DMA1 reset.

DMA2RST

Bit 1: DMA2 reset.

DMAMUXRST

Bit 2: DMAMUX reset.

CRCRST

Bit 12: CRC reset.

TSCRST

Bit 16: Touch Sensing Controller reset.

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCRST rw						GPIOHRST rw			GPIOERST rw	GPIODRST rw	GPIOCRST rw	GPIOBRST rw	GPIOARST rw

Toggle fields

GPIOARST

Bit 0: IO port A reset.

GPIOBRST

Bit 1: IO port B reset.

GPIOCRST

Bit 2: IO port C reset.

GPIODRST

Bit 3: IO port D reset.

GPIOERST

Bit 4: IO port E reset.

GPIOHRST

Bit 7: IO port H reset.

ADCRST

Bit 13: ADC reset.

AES1RST

Bit 16: AES1 hardware accelerator reset.

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHRST rw					IPCCRST rw	HSEMRST rw	RNGRST rw	AES2RST rw	PKARST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							QSPIRST rw

Toggle fields

QSPIRST

Bit 8: Quad SPI memory interface reset.

PKARST

Bit 16: PKA interface reset.

AES2RST

Bit 17: AES2 interface reset.

RNGRST

Bit 18: RNG interface reset.

HSEMRST

Bit 19: HSEM interface reset.

IPCCRST

Bit 20: IPCC interface reset.

FLASHRST

Bit 25: Flash interface reset.

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1RST rw					USBFSRST rw		CRSRST rw	I2C3RST rw		I2C1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2RST rw					LCDRST rw									TIM2RST rw

Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

LCDRST

Bit 9: LCD interface reset.

SPI2RST

Bit 14: SPI2 reset.

I2C1RST

Bit 21: I2C1 reset.

I2C3RST

Bit 23: I2C3 reset.

CRSRST

Bit 24: CRS reset.

USBFSRST

Bit 26: USB FS reset.

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2RST rw					LPUART1RST rw

Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

LPTIM2RST

Bit 5: Low-power timer 2 reset.

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1RST rw			TIM17RST rw	TIM16RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1RST rw		SPI1RST rw	TIM1RST rw

Toggle fields

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

USART1RST

Bit 14: USART1 reset.

TIM16RST

Bit 17: TIM16 timer reset.

TIM17RST

Bit 18: TIM17 timer reset.

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

APB3RSTR

APB3 peripheral reset register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RFRST rw

Toggle fields

RFRST

Bit 0: Radio system BLE reset.

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000100, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw										DMAMUXEN rw	DMA2EN rw	DMA1EN rw

Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

DMA2EN

Bit 1: DMA2 clock enable.

DMAMUXEN

Bit 2: DMAMUX clock enable.

CRCEN

Bit 12: CPU1 CRC clock enable.

TSCEN

Bit 16: Touch Sensing Controller clock enable.

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCEN rw						GPIOHEN rw			GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

GPIOBEN

Bit 1: IO port B clock enable.

GPIOCEN

Bit 2: IO port C clock enable.

GPIODEN

Bit 3: IO port D clock enable.

GPIOEEN

Bit 4: IO port E clock enable.

GPIOHEN

Bit 7: IO port H clock enable.

ADCEN

Bit 13: ADC clock enable.

AES1EN

Bit 16: AES1 accelerator clock enable.

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x02080000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHEN rw					IPCCEN rw	HSEMEN rw	RNGEN rw	AES2EN rw	PKAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							QSPIEN rw

Toggle fields

QSPIEN

Bit 8: QSPIEN.

PKAEN

Bit 16: PKAEN.

AES2EN

Bit 17: AES2EN.

RNGEN

Bit 18: RNGEN.

HSEMEN

Bit 19: HSEMEN.

IPCCEN

Bit 20: IPCCEN.

FLASHEN

Bit 25: FLASHEN.

APB1ENR1

Offset: 0x58, size: 32, reset: 0x00000400, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1EN rw					USBEN rw		CRSEN rw	I2C3EN rw		I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw			WWDGEN rw	RTCAPBEN rw	LCDEN rw									TIM2EN rw

Toggle fields

TIM2EN

Bit 0: CPU1 TIM2 timer clock enable.

LCDEN

Bit 9: CPU1 LCD clock enable.

RTCAPBEN

Bit 10: CPU1 RTC APB clock enable.

WWDGEN

Bit 11: CPU1 Window watchdog clock enable.

SPI2EN

Bit 14: CPU1 SPI2 clock enable.

I2C1EN

Bit 21: CPU1 I2C1 clock enable.

I2C3EN

Bit 23: CPU1 I2C3 clock enable.

CRSEN

Bit 24: CPU1 CRS clock enable.

USBEN

Bit 26: CPU1 USB clock enable.

LPTIM1EN

Bit 31: CPU1 Low power timer 1 clock enable.

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2EN rw					LPUART1EN rw

Toggle fields

LPUART1EN

Bit 0: CPU1 Low power UART 1 clock enable.

LPTIM2EN

Bit 5: CPU1 LPTIM2EN.

APB2ENR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1EN rw			TIM17EN rw	TIM16EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw		SPI1EN rw	TIM1EN rw

Toggle fields

TIM1EN

Bit 11: CPU1 TIM1 timer clock enable.

SPI1EN

Bit 12: CPU1 SPI1 clock enable.

USART1EN

Bit 14: CPU1 USART1clock enable.

TIM16EN

Bit 17: CPU1 TIM16 timer clock enable.

TIM17EN

Bit 18: CPU1 TIM17 timer clock enable.

SAI1EN

Bit 21: CPU1 SAI1 clock enable.

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, size: 32, reset: 0x00011207, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw			SRAM1SMEN rw							DMAMUXSMEN rw	DMA2SMEN rw	DMA1SMEN rw

Toggle fields

DMA1SMEN

Bit 0: CPU1 DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: CPU1 DMA2 clocks enable during Sleep and Stop modes.

DMAMUXSMEN

Bit 2: CPU1 DMAMUX clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CPU1 CRCSMEN.

TSCSMEN

Bit 16: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6c, size: 32, reset: 0x0001209F, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCFSSMEN rw						GPIOHSMEN rw			GPIOESMEN rw	GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle fields

GPIOASMEN

Bit 0: CPU1 IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: CPU1 IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: CPU1 IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: CPU1 IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: CPU1 IO port E clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: CPU1 IO port H clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: CPU1 ADC clocks enable during Sleep and Stop modes.

AES1SMEN

Bit 16: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x03070100, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHSMEN rw	SRAM2SMEN rw						RNGSMEN rw	AES2SMEN rw	PKASMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							QSPISMEN rw

Toggle fields

QSPISMEN

Bit 8: QSPISMEN.

PKASMEN

Bit 16: PKA accelerator clocks enable during CPU1 sleep mode.

AES2SMEN

Bit 17: AES2 accelerator clocks enable during CPU1 sleep mode.

RNGSMEN

Bit 18: True RNG clocks enable during CPU1 sleep mode.

SRAM2SMEN

Bit 24: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode.

FLASHSMEN

Bit 25: Flash interface clocks enable during CPU1 sleep mode.

APB1SMENR1

Offset: 0x78, size: 32, reset: 0x85A04E01, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1SMEN rw					USBSMEN rw		CRSMEN rw	I2C3SMEN rw		I2C1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw			WWDGSMEN rw	RTCAPBSMEN rw	LCDSMEN rw									TIM2SMEN rw

Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during CPU1 Sleep mode.

LCDSMEN

Bit 9: LCD clocks enable during CPU1 Sleep mode.

RTCAPBSMEN

Bit 10: RTC APB clocks enable during CPU1 Sleep mode.

WWDGSMEN

Bit 11: Window watchdog clocks enable during CPU1 Sleep mode.

SPI2SMEN

Bit 14: SPI2 clocks enable during CPU1 Sleep mode.

I2C1SMEN

Bit 21: I2C1 clocks enable during CPU1 Sleep mode.

I2C3SMEN

Bit 23: I2C3 clocks enable during CPU1 Sleep mode.

CRSMEN

Bit 24: CRS clocks enable during CPU1 Sleep mode.

USBSMEN

Bit 26: USB FS clocks enable during CPU1 Sleep mode.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during CPU1 Sleep mode.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7c, size: 32, reset: 0x00000021, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2SMEN rw					LPUART1SMEN rw

Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during CPU1 Sleep mode.

LPTIM2SMEN

Bit 5: Low power timer 2 clocks enable during CPU1 Sleep mode.

APB2SMENR

Offset: 0x80, size: 32, reset: 0x00265800, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1SMEN rw			TIM17SMEN rw	TIM16SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1SMEN rw		SPI1SMEN rw	TIM1SMEN rw

Toggle fields

TIM1SMEN

Bit 11: TIM1 timer clocks enable during CPU1 Sleep mode.

SPI1SMEN

Bit 12: SPI1 clocks enable during CPU1 Sleep mode.

USART1SMEN

Bit 14: USART1clocks enable during CPU1 Sleep mode.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during CPU1 Sleep mode.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during CPU1 Sleep mode.

SAI1SMEN

Bit 21: SAI1 clocks enable during CPU1 Sleep mode.

CCIPR

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNGSEL rw		ADCSEL rw		CLK48SEL rw				SAI1SEL rw		LPTIM2SEL rw		LPTIM1SEL rw		I2C3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		I2C1SEL rw		LPUART1SEL rw										USART1SEL rw

Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

SAI1SEL

Bits 22-23: SAI1 clock source selection.

CLK48SEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

RNGSEL

Bits 30-31: RNG clock source selection.

BDCR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

2/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					LSCOSEL rw		LSCOEN rw								BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw						RTCSEL rw			LSECSSD_ r	LSECSSON rw	LSEDRV rw		LSEBYP rw	LSERDY r	LSEON rw

Toggle fields

LSEON

Bit 0: LSE oscillator enable.

LSERDY

Bit 1: LSE oscillator ready.

LSEBYP

Bit 2: LSE oscillator bypass.

LSEDRV

Bits 3-4: SE oscillator drive capability.

LSECSSON

Bit 5: LSECSSON.

LSECSSD_

Bit 6: CSS on LSE failure detection.

RTCSEL

Bits 8-9: RTC clock source selection.

RTCEN

Bit 15: RTC clock enable.

BDRST

Bit 16: Backup domain software reset.

LSCOEN

Bit 24: Low speed clock output enable.

LSCOSEL

Bits 25-26: Low speed clock output selection.

CSR

Offset: 0x94, size: 32, reset: 0x0C000000, access: Unspecified

11/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF r	WWDGRSTF r	IWDGRSTF r	SFTRSTF r	BORRSTF r	PINRSTF r	OBLRSTF r		RMVF rw							RFRSTS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RFWKPSEL rw				LSI2BW rw						LSI2TRIMOK r	LSI2TRIMEN rw	LSI2RDY r	LSI2ON rw	LSI1RDY r	LSI1ON rw

Toggle fields

LSI1ON

Bit 0: LSI1 oscillator enabled.

LSI1RDY

Bit 1: LSI1 oscillator ready.

LSI2ON

Bit 2: LSI2 oscillator enabled.

LSI2RDY

Bit 3: LSI2 oscillator ready.

LSI2TRIMEN

Bit 4: LSI2 oscillator trimming enable.

LSI2TRIMOK

Bit 5: LSI2 oscillator trim OK.

LSI2BW

Bits 8-11: LSI2 oscillator bias configuration.

RFWKPSEL

Bits 14-15: RF system wakeup clock source selection.

RFRSTS

Bit 16: Radio system BLE and 802.15.4 reset status.

RMVF

Bit 23: Remove reset flag.

OBLRSTF

Bit 25: Option byte loader reset flag.

PINRSTF

Bit 26: Pin reset flag.

BORRSTF

Bit 27: BOR flag.

SFTRSTF

Bit 28: Software reset flag.

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRRSTF

Bit 31: Low-power reset flag.

CRRCR

Clock recovery RC register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSI48CAL r														HSI48RDY r	HSI48ON rw

Toggle fields

HSI48ON

Bit 0: HSI48 oscillator enabled.

HSI48RDY

Bit 1: HSI48 clock ready.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

HSECR

Clock HSE register

Offset: 0x9c, size: 32, reset: 0x00000030, access: Unspecified

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		HSETUNE r							HSEGMC rw			HSES rw			UNLOCKED rw

Toggle fields

UNLOCKED

Bit 0: Register lock system.

HSES

Bit 3: HSE Sense amplifier threshold.

HSEGMC

Bits 4-6: HSE current control.

HSETUNE

Bits 8-13: HSE capacitor tuning.

EXTCFGR

Extended clock recovery register

Offset: 0x108, size: 32, reset: 0x00030000, access: Unspecified

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											RFCSS r			C2HPREF r	SHDHPREF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								C2HPRE rw				SHDHPRE rw

Toggle fields

SHDHPRE

Bits 0-3: Shared AHB prescaler.

C2HPRE

Bits 4-7: CPU2 AHB prescaler.

SHDHPREF

Bit 16: Shared AHB prescaler flag.

C2HPREF

Bit 17: CPU2 AHB prescaler flag.

RFCSS

Bit 20: RF clock source selected.

C2AHB1ENR

CPU2 AHB1 peripheral clock enable register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw			SRAM1EN rw							DMAMUXEN rw	DMA2EN rw	DMA1EN rw

Toggle fields

DMA1EN

Bit 0: CPU2 DMA1 clock enable.

DMA2EN

Bit 1: CPU2 DMA2 clock enable.

DMAMUXEN

Bit 2: CPU2 DMAMUX clock enable.

SRAM1EN

Bit 9: CPU2 SRAM1 clock enable.

CRCEN

Bit 12: CPU2 CRC clock enable.

TSCEN

Bit 16: CPU2 Touch Sensing Controller clock enable.

C2AHB2ENR

CPU2 AHB2 peripheral clock enable register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCEN rw						GPIOHEN rw			GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle fields

GPIOAEN

Bit 0: CPU2 IO port A clock enable.

GPIOBEN

Bit 1: CPU2 IO port B clock enable.

GPIOCEN

Bit 2: CPU2 IO port C clock enable.

GPIODEN

Bit 3: CPU2 IO port D clock enable.

GPIOEEN

Bit 4: CPU2 IO port E clock enable.

GPIOHEN

Bit 7: CPU2 IO port H clock enable.

ADCEN

Bit 13: CPU2 ADC clock enable.

AES1EN

Bit 16: CPU2 AES1 accelerator clock enable.

C2AHB3ENR

CPU2 AHB3 peripheral clock enable register

Offset: 0x150, size: 32, reset: 0x02080000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHEN rw					IPCCEN rw	HSEMEN rw	RNGEN rw	AES2EN rw	PKAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PKAEN

Bit 16: CPU2 PKAEN.

AES2EN

Bit 17: CPU2 AES2EN.

RNGEN

Bit 18: CPU2 RNGEN.

HSEMEN

Bit 19: CPU2 HSEMEN.

IPCCEN

Bit 20: CPU2 IPCCEN.

FLASHEN

Bit 25: CPU2 FLASHEN.

C2APB1ENR1

CPU2 APB1ENR1

Offset: 0x158, size: 32, reset: 0x00000400, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1EN rw					USBEN rw		CRSEN rw	I2C3EN rw		I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw				RTCAPBEN rw	LCDEN rw									TIM2EN rw

Toggle fields

TIM2EN

Bit 0: CPU2 TIM2 timer clock enable.

LCDEN

Bit 9: CPU2 LCD clock enable.

RTCAPBEN

Bit 10: CPU2 RTC APB clock enable.

SPI2EN

Bit 14: CPU2 SPI2 clock enable.

I2C1EN

Bit 21: CPU2 I2C1 clock enable.

I2C3EN

Bit 23: CPU2 I2C3 clock enable.

CRSEN

Bit 24: CPU2 CRS clock enable.

USBEN

Bit 26: CPU2 USB clock enable.

LPTIM1EN

Bit 31: CPU2 Low power timer 1 clock enable.

C2APB1ENR2

CPU2 APB1 peripheral clock enable register 2

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2EN rw					LPUART1EN rw

Toggle fields

LPUART1EN

Bit 0: CPU2 Low power UART 1 clock enable.

LPTIM2EN

Bit 5: CPU2 LPTIM2EN.

C2APB2ENR

CPU2 APB2ENR

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1EN rw			TIM17EN rw	TIM16EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw		SPI1EN rw	TIM1EN rw

Toggle fields

TIM1EN

Bit 11: CPU2 TIM1 timer clock enable.

SPI1EN

Bit 12: CPU2 SPI1 clock enable.

USART1EN

Bit 14: CPU2 USART1clock enable.

TIM16EN

Bit 17: CPU2 TIM16 timer clock enable.

TIM17EN

Bit 18: CPU2 TIM17 timer clock enable.

SAI1EN

Bit 21: CPU2 SAI1 clock enable.

C2APB3ENR

CPU2 APB3ENR

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EN802 rw	BLEEN rw

Toggle fields

BLEEN

Bit 0: CPU2 BLE interface clock enable.

EN802

Bit 1: CPU2 802.15.4 interface clock enable.

C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x168, size: 32, reset: 0x00011207, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw			SRAM1SMEN rw							DMAMUXSMEN rw	DMA2SMEN rw	DMA1SMEN rw

Toggle fields

DMA1SMEN

Bit 0: CPU2 DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: CPU2 DMA2 clocks enable during Sleep and Stop modes.

DMAMUXSMEN

Bit 2: CPU2 DMAMUX clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clock enable during CPU1 CSleep mode.

CRCSMEN

Bit 12: CPU2 CRCSMEN.

TSCSMEN

Bit 16: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes.

C2AHB2SMENR

CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x16c, size: 32, reset: 0x0001209F, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCFSSMEN rw						GPIOHSMEN rw			GPIOESMEN rw	GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle fields

GPIOASMEN

Bit 0: CPU2 IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: CPU2 IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: CPU2 IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: CPU2 IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: CPU2 IO port E clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: CPU2 IO port H clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: CPU2 ADC clocks enable during Sleep and Stop modes.

AES1SMEN

Bit 16: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes.

C2AHB3SMENR

CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x170, size: 32, reset: 0x03070000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHSMEN rw	SRAM2SMEN rw						RNGSMEN rw	AES2SMEN rw	PKASMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PKASMEN

Bit 16: PKA accelerator clocks enable during CPU2 sleep modes.

AES2SMEN

Bit 17: AES2 accelerator clocks enable during CPU2 sleep modes.

RNGSMEN

Bit 18: True RNG clocks enable during CPU2 sleep modes.

SRAM2SMEN

Bit 24: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes.

FLASHSMEN

Bit 25: Flash interface clocks enable during CPU2 sleep modes.

C2APB1SMENR1

CPU2 APB1SMENR1

Offset: 0x178, size: 32, reset: 0x85A04601, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1SMEN rw					USBSMEN rw		CRSMEN rw	I2C3SMEN rw		I2C1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw				RTCAPBSMEN rw	LCDSMEN rw									TIM2SMEN rw

Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during CPU2 Sleep mode.

LCDSMEN

Bit 9: LCD clocks enable during CPU2 Sleep mode.

RTCAPBSMEN

Bit 10: RTC APB clocks enable during CPU2 Sleep mode.

SPI2SMEN

Bit 14: SPI2 clocks enable during CPU2 Sleep mode.

I2C1SMEN

Bit 21: I2C1 clocks enable during CPU2 Sleep mode.

I2C3SMEN

Bit 23: I2C3 clocks enable during CPU2 Sleep mode.

CRSMEN

Bit 24: CRS clocks enable during CPU2 Sleep mode.

USBSMEN

Bit 26: USB FS clocks enable during CPU2 Sleep mode.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during CPU2 Sleep mode.

C2APB1SMENR2

CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x17c, size: 32, reset: 0x00000021, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2SMEN rw					LPUART1SMEN rw

Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during CPU2 Sleep mode.

LPTIM2SMEN

Bit 5: Low power timer 2 clocks enable during CPU2 Sleep mode.

C2APB2SMENR

CPU2 APB2SMENR

Offset: 0x180, size: 32, reset: 0x00265800, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1SMEN rw			TIM17SMEN rw	TIM16SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1SMEN rw		SPI1SMEN rw	TIM1SMEN rw

Toggle fields

TIM1SMEN

Bit 11: TIM1 timer clocks enable during CPU2 Sleep mode.

SPI1SMEN

Bit 12: SPI1 clocks enable during CPU2 Sleep mode.

USART1SMEN

Bit 14: USART1clocks enable during CPU2 Sleep mode.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during CPU2 Sleep mode.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during CPU2 Sleep mode.

SAI1SMEN

Bit 21: SAI1 clocks enable during CPU2 Sleep mode.

C2APB3SMENR

CPU2 APB3SMENR

Offset: 0x184, size: 32, reset: 0x00000003, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SMEN802 rw	BLESMEN rw

Toggle fields

BLESMEN

Bit 0: BLE interface clocks enable during CPU2 Sleep mode.

SMEN802

Bit 1: 802.15.4 interface clocks enable during CPU2 Sleep modes.

RNG

0x58001000: Random number generator

4/9 fields covered.

Toggle register map

Offset	Name	31	15	6	5	3	2	1	0
0x0	CR			BYP		IE	RNGEN
0x4	SR			SEIS	CEIS		SECS	CECS	DRDY
0x8	DR	RNDATA	RNDATA

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									BYP rw			IE rw	RNGEN rw

Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

BYP

Bit 6: Bypass mode enable.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SEIS rw	CEIS rw			SECS r	CECS r	DRDY r

Toggle fields

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNDATA r

Toggle fields

RNDATA

Bits 0-31: Random data.

RTC

0x40002800: Real-time clock

8/154 fields covered.

Toggle register map

Offset	Name	31	30	29	27	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TR							PM	HT		HU					MNT			MNU					ST			SU
0x4	DR						YT				YU				WDU			MT	MU						DT		DU
0x8	CR					ITSE	COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE	WUTIE	ALRBIE	ALRAIE	TSE	WUTE	ALRBE	ALRAE		FMT	BYPSHAD	REFCKON	TSEDGE	WUCKSEL
0xc	ISR												ITSF	RECALPF	TAMP3F	TAMP2F	TAMP1F	TSOVF	TSF	WUTF	ALRBF	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUTWF	ALRBWF	ALRAWF
0x10	PRER							PREDIV_A								PREDIV_S
0x14	WUTR														WUT
0x1c	ALRM[A]R	MSK4	WDSEL	DT	DU		MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x20	ALRM[B]R	MSK4	WDSEL	DT	DU		MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x24	WPR																						KEY
0x28	SSR														SS
0x2c	SHIFTR	ADD1S														SUBFS
0x30	TSTR							PM	HT		HU					MNT			MNU					ST			SU
0x34	TSDR						YT				YU				WDU			MT	MU						DT		DU
0x38	TSSSR														SS
0x3c	CALR														CALP	CALW8	CALW16					CALM
0x40	TAMPCR					TAMP3MF	TAMP3NOERASE	TAMP3IE	TAMP2MF	TAMP2NOERASE	TAMP2IE	TAMP1MF	TAMP1NOERASE	TAMP1IE	TAMPPUDIS	TAMPPRCH		TAMPFLT		TAMPFREQ			TAMPTS	TAMP3TRG	TAMP3E	TAMP2TRG	TAMP2E	TAMPIE	TAMP1TRG	TAMP1E
0x44	ALRM[A]SSR				MASKSS											SS
0x48	ALRM[B]SSR				MASKSS											SS
0x4c	OR																												RTC_OUT_RMP	RTC_ALARM_TYPE
0x50	BKP[0]R	BKP													BKP
0x54	BKP[1]R	BKP													BKP
0x58	BKP[2]R	BKP													BKP
0x5c	BKP[3]R	BKP													BKP
0x60	BKP[4]R	BKP													BKP
0x64	BKP[5]R	BKP													BKP
0x68	BKP[6]R	BKP													BKP
0x6c	BKP[7]R	BKP													BKP
0x70	BKP[8]R	BKP													BKP
0x74	BKP[9]R	BKP													BKP
0x78	BKP[10]R	BKP													BKP
0x7c	BKP[11]R	BKP													BKP
0x80	BKP[12]R	BKP													BKP
0x84	BKP[13]R	BKP													BKP
0x88	BKP[14]R	BKP													BKP
0x8c	BKP[15]R	BKP													BKP
0x90	BKP[16]R	BKP													BKP
0x94	BKP[17]R	BKP													BKP
0x98	BKP[18]R	BKP													BKP
0x9c	BKP[19]R	BKP													BKP

Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ITSE rw	COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H rw	ADD1H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw	ALRBIE rw	ALRAIE rw	TSE rw	WUTE rw	ALRBE rw	ALRAE rw		FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw	WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

BYPSHAD

Bit 5: Bypass the shadow registers.

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

COSEL

Bit 19: Calibration output selection.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ITSE

Bit 24: timestamp on internal event enable.

ISR

initialization and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

6/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ITSF rw	RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAMP3F rw	TAMP2F rw	TAMP1F rw	TSOVF rw	TSF rw	WUTF rw	ALRBF rw	ALRAF rw	INIT rw	INITF r	RSF rw	INITS r	SHPF rw	WUTWF r	ALRBWF r	ALRAWF r

Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVF

Bit 12: Time-stamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

TAMP2F

Bit 14: RTC_TAMP2 detection flag.

TAMP3F

Bit 15: RTC_TAMP3 detection flag.

RECALPF

Bit 16: Recalibration pending Flag.

ITSF

Bit 17: INTERNAL TIME-STAMP FLAG.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

ALRM[A]R

Alarm A register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[B]R

Alarm B register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle fields

KEY

Bits 0-7: Write protection key.

SSR

sub second register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value.

CALR

calibration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

Toggle fields

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

TAMPCR

tamper configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TAMP3MF rw	TAMP3NOERASE rw	TAMP3IE rw	TAMP2MF rw	TAMP2NOERASE rw	TAMP2IE rw	TAMP1MF rw	TAMP1NOERASE rw	TAMP1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw			TAMPTS rw	TAMP3TRG rw	TAMP3E rw	TAMP2TRG rw	TAMP2E rw	TAMPIE rw	TAMP1TRG rw	TAMP1E rw

Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMP3E

Bit 5: Tamper 3 detection enable.

TAMP3TRG

Bit 6: Active level for tamper 3.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

TAMP1IE

Bit 16: Tamper 1 interrupt enable.

TAMP1NOERASE

Bit 17: Tamper 1 no erase.

TAMP1MF

Bit 18: Tamper 1 mask flag.

TAMP2IE

Bit 19: Tamper 2 interrupt enable.

TAMP2NOERASE

Bit 20: Tamper 2 no erase.

TAMP2MF

Bit 21: Tamper 2 mask flag.

TAMP3IE

Bit 22: Tamper 3 interrupt enable.

TAMP3NOERASE

Bit 23: Tamper 3 no erase.

TAMP3MF

Bit 24: Tamper 3 mask flag.

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

OR

option register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RTC_OUT_RMP rw	RTC_ALARM_TYPE rw

Toggle fields

RTC_ALARM_TYPE

Bit 0: RTC_ALARM on PC13 output type.

RTC_OUT_RMP

Bit 1: RTC_OUT remap.

BKP[0]R

backup register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

backup register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

backup register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

backup register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

backup register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

backup register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

backup register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

backup register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

backup register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

backup register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

backup register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

backup register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

backup register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

backup register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

backup register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

backup register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

backup register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

backup register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

backup register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

backup register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

SAI1

0x40015400: Serial audio interface

84/120 fields covered.

Toggle register map

Offset	Name	31	30	27	26	25	22	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x4	CR1 [A]			MCKEN	OSR	MCKDIV		NODIV		DMAEN	SAIEN			OUTDRIV	MONO	SYNCEN		CKSTR	LSBFIRST	DS				PRTCFG		MODE
0x8	CR2 [A]											COMP		CPL	MUTECNT						MUTEVAL	MUTE	TRIS	FFLUSH	FTH
0xc	FRCR [A]								FSOFF	FSPOL	FSDEF		FSALL							FRL
0x10	SLOTR [A]	SLOTEN														NBSLOT				SLOTSZ			FBOFF
0x14	IM [A]																				LFSDETIE	AFSDETIE	CNRDYIE	FREQIE	WCKCFGIE	MUTEDETIE	OVRUDRIE
0x18	SR [A]								FLVL												LFSDET	AFSDET	CNRDY	FREQ	WCKCFG	MUTEDET	OVRUDR
0x1c	CLRFR [A]																				CLFSDET	CAFSDET	CCNRDY		CWCKCFG	CMUTEDET	COVRUDR
0x20	DR [A]	DATA										DATA
0x24	CR1 [B]			MCKEN	OSR	MCKDIV		NODIV		DMAEN	SAIEN			OUTDRIV	MONO	SYNCEN		CKSTR	LSBFIRST	DS				PRTCFG		MODE
0x28	CR2 [B]											COMP		CPL	MUTECNT						MUTEVAL	MUTE	TRIS	FFLUSH	FTH
0x2c	FRCR [B]								FSOFF	FSPOL	FSDEF		FSALL							FRL
0x30	SLOTR [B]	SLOTEN														NBSLOT				SLOTSZ			FBOFF
0x34	IM [B]																				LFSDETIE	AFSDETIE	CNRDYIE	FREQIE	WCKCFGIE	MUTEDETIE	OVRUDRIE
0x38	SR [B]								FLVL												LFSDET	AFSDET	CNRDY	FREQ	WCKCFG	MUTEDET	OVRUDR
0x3c	CLRFR [B]																				CLFSDET	CAFSDET	CCNRDY		CWCKCFG	CMUTEDET	COVRUDR
0x40	DR [B]	DATA										DATA
0x44	PDMCR															CKEN4	CKEN3	CKEN2	CKEN1			MICNBR					PDMEN
0x48	PDMDLY		DLYM[4]R		DLYM[4]L		DLYM[3]R		DLYM[3]L				DLYM[2]R				DLYM[2]L				DLYM[1]R				DLYM[1]L

Toggle registers

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCKDIV rw						NODIV rw		DMAEN rw	SAIEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OUTDRIV rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block B enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECNT rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUSH w	FTH rw

Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFGIE rw	MUTEDETIE rw	OVRUDRIE rw

Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CLFSDET w	CAFSDET w	CCNRDY w		CWCKCFG w	CMUTEDET w	COVRUDR w

Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCKDIV rw						NODIV rw		DMAEN rw	SAIEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OUTDRIV rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block B enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECNT rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUSH w	FTH rw

Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFGIE rw	MUTEDETIE rw	OVRUDRIE rw

Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CLFSDET w	CAFSDET w	CCNRDY w		CWCKCFG w	CMUTEDET w	COVRUDR w

Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CKEN4 rw	CKEN3 rw	CKEN2 rw	CKEN1 rw			MICNBR rw					PDMEN rw

Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: Number of microphones.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: Clock enable of bitstream clock number 2.

CKEN3

Bit 10: Clock enable of bitstream clock number 3.

CKEN4

Bit 11: Clock enable of bitstream clock number 4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DLYM[4]R rw				DLYM[4]L rw				DLYM[3]R rw				DLYM[3]L rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DLYM[2]R rw				DLYM[2]L rw				DLYM[1]R rw				DLYM[1]L rw

Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SCB

0xe000ed00: System control block

5/74 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	19	18	17	16	15	14	13	12	11	10	9	8	7	5	4	3	2	1	0
0x0	CPUID	Implementer								Variant		Constant				PartNo											Revision
0x4	ICSR	NMIPENDSET			PENDSVSET	PENDSVCLR	PENDSTSET	PENDSTCLR			ISRPENDING		VECTPENDING			VECTPENDING				RETTOBASE			VECTACTIVE
0x8	VTOR			TBLOFF												TBLOFF
0xc	AIRCR	VECTKEYSTAT														ENDIANESS					PRIGROUP							SYSRESETREQ	VECTCLRACTIVE	VECTRESET
0x10	SCR																									SEVEONPEND		SLEEPDEEP	SLEEPONEXIT
0x14	CCR																					STKALIGN	BFHFNMIGN			DIV_0_TRP	UNALIGN__TRP		USERSETMPEND	NONBASETHRDENA
0x18	SHPR1									PRI_6						PRI_5								PRI_4
0x1c	SHPR2	PRI_11
0x20	SHPR3	PRI_15								PRI_14
0x24	SHCRS												USGFAULTENA	BUSFAULTENA	MEMFAULTENA	SVCALLPENDED	BUSFAULTPENDED	MEMFAULTPENDED	USGFAULTPENDED	SYSTICKACT	PENDSVACT		MONITORACT	SVCALLACT			USGFAULTACT		BUSFAULTACT	MEMFAULTACT
0x28	CFSR_UFSR_BFSR_MMFSR							DIVBYZERO	UNALIGNED			NOCP	INVPC	INVSTATE	UNDEFINSTR	BFARVALID		LSPERR	STKERR	UNSTKERR	IMPRECISERR	PRECISERR	IBUSERR	MMARVALID	MLSPERR	MSTKERR	MUNSTKERR		IACCVIOL
0x2c	HFSR	DEBUG_VT	FORCED																										VECTTBL
0x34	MMFAR	MMFAR														MMFAR
0x38	BFAR	BFAR														BFAR
0x3c	AFSR	IMPDEF														IMPDEF

Toggle registers

CPUID

CPUID base register

Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Implementer r								Variant r				Constant r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PartNo r												Revision r

Toggle fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NMIPENDSET rw			PENDSVSET rw	PENDSVCLR rw	PENDSTSET rw	PENDSTCLR rw			ISRPENDING rw				VECTPENDING rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VECTPENDING rw				RETTOBASE rw			VECTACTIVE rw

Toggle fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		TBLOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TBLOFF rw

Toggle fields

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VECTKEYSTAT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ENDIANESS rw					PRIGROUP rw								SYSRESETREQ rw	VECTCLRACTIVE rw	VECTRESET rw

Toggle fields

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											SEVEONPEND rw		SLEEPDEEP rw	SLEEPONEXIT rw

Toggle fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						STKALIGN rw	BFHFNMIGN rw				DIV_0_TRP rw	UNALIGN__TRP rw		USERSETMPEND rw	NONBASETHRDENA rw

Toggle fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRI_6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_5 rw								PRI_4 rw

Toggle fields

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_15 rw								PRI_14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													USGFAULTENA rw	BUSFAULTENA rw	MEMFAULTENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SVCALLPENDED rw	BUSFAULTPENDED rw	MEMFAULTPENDED rw	USGFAULTPENDED rw	SYSTICKACT rw	PENDSVACT rw		MONITORACT rw	SVCALLACT rw				USGFAULTACT rw		BUSFAULTACT rw	MEMFAULTACT rw

Toggle fields

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						DIVBYZERO rw	UNALIGNED rw					NOCP rw	INVPC rw	INVSTATE rw	UNDEFINSTR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFARVALID rw		LSPERR rw	STKERR rw	UNSTKERR rw	IMPRECISERR rw	PRECISERR rw	IBUSERR rw	MMARVALID rw		MLSPERR rw	MSTKERR rw	MUNSTKERR rw		IACCVIOL rw

Toggle fields

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DEBUG_VT rw	FORCED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														VECTTBL rw

Toggle fields

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MMFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MMFAR rw

Toggle fields

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFAR rw

Toggle fields

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IMPDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPDEF rw

Toggle fields

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xe000e008: System control block ACTLR

0/5 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACTRL																							DISOOFP	DISFPCA						DISFOLD	DISDEFWBUF	DISMCYCINT

Toggle registers

ACTRL

Auxiliary control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						DISOOFP rw	DISFPCA rw						DISFOLD rw	DISDEFWBUF rw	DISMCYCINT rw

Toggle fields

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

10/39 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SR				FTLVL		FRLVL		TIFRFE	BSY	OVR	MODF	CRCERR			TXE	RXNE
0xc	DR	DR
0x10	CRCPR	CRCPOLY
0x14	RXCRCR	RxCRC
0x18	TXCRCR	TxCRC

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		TIFRFE r	BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

10/39 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SR				FTLVL		FRLVL		TIFRFE	BSY	OVR	MODF	CRCERR			TXE	RXNE
0xc	DR	DR
0x10	CRCPR	CRCPOLY
0x14	RXCRCR	RxCRC
0x18	TXCRCR	TxCRC

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		TIFRFE r	BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

STK

0xe000e010: SysTick timer

0/9 fields covered.

Toggle register map

Offset	Name	31	30	23	16	15	2	1	0
0x0	CTRL				COUNTFLAG		CLKSOURCE	TICKINT	ENABLE
0x4	LOAD			RELOAD		RELOAD
0x8	VAL			CURRENT		CURRENT
0xc	CALIB	NOREF	SKEW	TENMS		TENMS

Toggle registers

CTRL

SysTick control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															COUNTFLAG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKSOURCE rw	TICKINT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								RELOAD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle fields

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CURRENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CURRENT rw

Toggle fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NOREF rw	SKEW rw							TENMS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TENMS rw

Toggle fields

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SYSCFG

0x40010000: System configuration controller

1/149 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MEMRMP																														MEM_MODE
0x4	CFGR1	FPU_IE									I2C3_FMP		I2C1_FMP	I2C_PB9_FMP	I2C_PB8_FMP	I2C_PB7_FMP	I2C_PB6_FMP								BOOSTEN
0x8	EXTICR1																		EXTI3				EXTI2				EXTI1				EXTI0
0xc	EXTICR2																		EXTI7				EXTI6				EXTI5				EXTI4
0x10	EXTICR3																		EXTI11				EXTI10				EXTI9				EXTI8
0x14	EXTICR4																		EXTI15				EXTI14				EXTI13				EXTI12
0x18	SCSR	C2RFD																														SRAM2BSY	SRAM2ER
0x1c	CFGR2																								SPF					ECCL	PVDL	SPL	CLL
0x20	SWPR	P31WP	P30WP	P29WP	P28WP	P27WP	P26WP	P25WP	P24WP	P23WP	P22WP	P21WP	P20WP	P19WP	P18WP	P17WP	P16WP	P15WP	P14WP	P13WP	P12WP	P11WP	P10WP	P9WP	P8WP	P7WP	P6WP	P5WP	P4WP	P3WP	P2WP	P1WP	P0WP
0x24	SKR																									KEY
0x28	SWPR2	P63WP	P62WP	P61WP	P60WP	P59WP	P58WP	P57WP	P56WP	P55WP	P54WP	P53WP	P52WP	P51WP	P50WP	P49WP	P48WP	P47WP	P46WP	P45WP	P44WP	P43WP	P42WP	P41WP	P40WP	P39WP	P38WP	P37WP	P36WP	P35WP	P34WP	P33WP	P32WP
0x100	IMR1	EXIT15IM	EXIT14IM	EXIT13IM	EXIT12IM	EXIT11IM	EXIT10IM	EXIT9IM	EXIT8IM	EXIT7IM	EXIT6IM	EXIT5IM						TIM17IM	TIM16IM	TIM1IM
0x104	IMR2												PVDIM		PVM3IM		PVM1IM
0x108	C2IMR1																				ADC	COMP	AES1	RNG	PKA		FLASH	RCC	RTCALARM	RTCWKUP			RTCSTAMP
0x10c	C2IMR2										LCDIM	TSCIM	PVDIM		PVM3IM		PVM1IM	DMAM_UX1_IM	DMA2_CH7_IM	DMA2_CH6_IM	DMA2_CH5_IM	DMA2_CH4_IM	DMA2_CH3_IM	DMA2_CH2_IM	DMA2_CH1_IM		DMA1_CH7_IM	DMA1_CH6_IM	DMA1_CH5_IM	DMA1_CH4_IM	DMA1_CH3_IM	DMA1_CH2_IM	DMA1_CH1_IM
0x110	SIPCR																													SRNG	SPKA	SAES2	SAES1

Toggle registers

MEMRMP

memory remap register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													MEM_MODE rw

Toggle fields

MEM_MODE

Bits 0-2: Memory mapping selection.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x7C000001, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FPU_IE rw									I2C3_FMP rw		I2C1_FMP rw	I2C_PB9_FMP rw	I2C_PB8_FMP rw	I2C_PB7_FMP rw	I2C_PB6_FMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							BOOSTEN rw

Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

FPU_IE

Bits 26-31: Floating Point Unit interrupts enable bits.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI3 rw				EXTI2 rw				EXTI1 rw				EXTI0 rw

Toggle fields

EXTI0

Bits 0-2: EXTI 0 configuration bits.

EXTI1

Bits 4-6: EXTI 1 configuration bits.

EXTI2

Bits 8-10: EXTI 2 configuration bits.

EXTI3

Bits 12-14: EXTI 3 configuration bits.

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI7 rw				EXTI6 rw				EXTI5 rw				EXTI4 rw

Toggle fields

EXTI4

Bits 0-2: EXTI 4 configuration bits.

EXTI5

Bits 4-6: EXTI 5 configuration bits.

EXTI6

Bits 8-10: EXTI 6 configuration bits.

EXTI7

Bits 12-14: EXTI 7 configuration bits.

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI11 rw				EXTI10 rw				EXTI9 rw				EXTI8 rw

Toggle fields

EXTI8

Bits 0-2: EXTI 8 configuration bits.

EXTI9

Bits 4-6: EXTI 9 configuration bits.

EXTI10

Bits 8-10: EXTI 10 configuration bits.

EXTI11

Bits 12-14: EXTI 11 configuration bits.

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI15 rw				EXTI14 rw				EXTI13 rw				EXTI12 rw

Toggle fields

EXTI12

Bits 0-2: EXTI12 configuration bits.

EXTI13

Bits 4-6: EXTI13 configuration bits.

EXTI14

Bits 8-10: EXTI14 configuration bits.

EXTI15

Bits 12-14: EXTI15 configuration bits.

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
C2RFD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SRAM2BSY r	SRAM2ER rw

Toggle fields

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

C2RFD

Bit 31: CPU2 SRAM fetch (execution) disable..

CFGR2

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SPF rw					ECCL w	PVDL w	SPL w	CLL w

Toggle fields

CLL

Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SWPR

SRAM2 write protection register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P31WP w	P30WP w	P29WP w	P28WP w	P27WP w	P26WP w	P25WP w	P24WP w	P23WP w	P22WP w	P21WP w	P20WP w	P19WP w	P18WP w	P17WP w	P16WP w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P15WP w	P14WP w	P13WP w	P12WP w	P11WP w	P10WP w	P9WP w	P8WP w	P7WP w	P6WP w	P5WP w	P4WP w	P3WP w	P2WP w	P1WP w	P0WP w

Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SKR

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

SWPR2

SRAM2 write protection register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P63WP w	P62WP w	P61WP w	P60WP w	P59WP w	P58WP w	P57WP w	P56WP w	P55WP w	P54WP w	P53WP w	P52WP w	P51WP w	P50WP w	P49WP w	P48WP w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P47WP w	P46WP w	P45WP w	P44WP w	P43WP w	P42WP w	P41WP w	P40WP w	P39WP w	P38WP w	P37WP w	P36WP w	P35WP w	P34WP w	P33WP w	P32WP w

Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: SRAM2 page 63 write protection.

IMR1

CPU1 interrupt mask register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXIT15IM rw	EXIT14IM rw	EXIT13IM rw	EXIT12IM rw	EXIT11IM rw	EXIT10IM rw	EXIT9IM rw	EXIT8IM rw	EXIT7IM rw	EXIT6IM rw	EXIT5IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM17IM rw	TIM16IM rw	TIM1IM rw

Toggle fields

TIM1IM

Bit 13: Peripheral TIM1 interrupt mask to CPU1.

TIM16IM

Bit 14: Peripheral TIM16 interrupt mask to CPU1.

TIM17IM

Bit 15: Peripheral TIM17 interrupt mask to CPU1.

EXIT5IM

Bit 21: Peripheral EXIT5 interrupt mask to CPU1.

EXIT6IM

Bit 22: Peripheral EXIT6 interrupt mask to CPU1.

EXIT7IM

Bit 23: Peripheral EXIT7 interrupt mask to CPU1.

EXIT8IM

Bit 24: Peripheral EXIT8 interrupt mask to CPU1.

EXIT9IM

Bit 25: Peripheral EXIT9 interrupt mask to CPU1.

EXIT10IM

Bit 26: Peripheral EXIT10 interrupt mask to CPU1.

EXIT11IM

Bit 27: Peripheral EXIT11 interrupt mask to CPU1.

EXIT12IM

Bit 28: Peripheral EXIT12 interrupt mask to CPU1.

EXIT13IM

Bit 29: Peripheral EXIT13 interrupt mask to CPU1.

EXIT14IM

Bit 30: Peripheral EXIT14 interrupt mask to CPU1.

EXIT15IM

Bit 31: Peripheral EXIT15 interrupt mask to CPU1.

IMR2

CPU1 interrupt mask register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											PVDIM rw		PVM3IM rw		PVM1IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PVM1IM

Bit 16: Peripheral PVM1 interrupt mask to CPU1.

PVM3IM

Bit 18: Peripheral PVM3 interrupt mask to CPU1.

PVDIM

Bit 20: Peripheral PVD interrupt mask to CPU1.

C2IMR1

CPU2 interrupt mask register 1

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADC rw	COMP rw	AES1 rw	RNG rw	PKA rw		FLASH rw	RCC rw	RTCALARM rw	RTCWKUP rw			RTCSTAMP rw

Toggle fields

RTCSTAMP

Bit 0: Peripheral RTCSTAMP interrupt mask to CPU2.

RTCWKUP

Bit 3: Peripheral RTCWKUP interrupt mask to CPU2.

RTCALARM

Bit 4: Peripheral RTCALARM interrupt mask to CPU2.

RCC

Bit 5: Peripheral RCC interrupt mask to CPU2.

FLASH

Bit 6: Peripheral FLASH interrupt mask to CPU2.

PKA

Bit 8: Peripheral PKA interrupt mask to CPU2.

RNG

Bit 9: Peripheral RNG interrupt mask to CPU2.

AES1

Bit 10: Peripheral AES1 interrupt mask to CPU2.

COMP

Bit 11: Peripheral COMP interrupt mask to CPU2.

ADC

Bit 12: Peripheral ADC interrupt mask to CPU2.

C2IMR2

CPU2 interrupt mask register 1

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									LCDIM rw	TSCIM rw	PVDIM rw		PVM3IM rw		PVM1IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAM_UX1_IM rw	DMA2_CH7_IM rw	DMA2_CH6_IM rw	DMA2_CH5_IM rw	DMA2_CH4_IM rw	DMA2_CH3_IM rw	DMA2_CH2_IM rw	DMA2_CH1_IM rw		DMA1_CH7_IM rw	DMA1_CH6_IM rw	DMA1_CH5_IM rw	DMA1_CH4_IM rw	DMA1_CH3_IM rw	DMA1_CH2_IM rw	DMA1_CH1_IM rw

Toggle fields

DMA1_CH1_IM

Bit 0: Peripheral DMA1 CH1 interrupt mask to CPU2.

DMA1_CH2_IM

Bit 1: Peripheral DMA1 CH2 interrupt mask to CPU2.

DMA1_CH3_IM

Bit 2: Peripheral DMA1 CH3 interrupt mask to CPU2.

DMA1_CH4_IM

Bit 3: Peripheral DMA1 CH4 interrupt mask to CPU2.

DMA1_CH5_IM

Bit 4: Peripheral DMA1 CH5 interrupt mask to CPU2.

DMA1_CH6_IM

Bit 5: Peripheral DMA1 CH6 interrupt mask to CPU2.

DMA1_CH7_IM

Bit 6: Peripheral DMA1 CH7 interrupt mask to CPU2.

DMA2_CH1_IM

Bit 8: Peripheral DMA2 CH1 interrupt mask to CPU1.

DMA2_CH2_IM

Bit 9: Peripheral DMA2 CH2 interrupt mask to CPU1.

DMA2_CH3_IM

Bit 10: Peripheral DMA2 CH3 interrupt mask to CPU1.

DMA2_CH4_IM

Bit 11: Peripheral DMA2 CH4 interrupt mask to CPU1.

DMA2_CH5_IM

Bit 12: Peripheral DMA2 CH5 interrupt mask to CPU1.

DMA2_CH6_IM

Bit 13: Peripheral DMA2 CH6 interrupt mask to CPU1.

DMA2_CH7_IM

Bit 14: Peripheral DMA2 CH7 interrupt mask to CPU1.

DMAM_UX1_IM

Bit 15: Peripheral DMAM UX1 interrupt mask to CPU1.

PVM1IM

Bit 16: Peripheral PVM1IM interrupt mask to CPU1.

PVM3IM

Bit 18: Peripheral PVM3IM interrupt mask to CPU1.

PVDIM

Bit 20: Peripheral PVDIM interrupt mask to CPU1.

TSCIM

Bit 21: Peripheral TSCIM interrupt mask to CPU1.

LCDIM

Bit 22: Peripheral LCDIM interrupt mask to CPU1.

SIPCR

secure IP control register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												SRNG rw	SPKA rw	SAES2 rw	SAES1 rw

Toggle fields

SAES1

Bit 0: Enable AES1 KEY[7:0] security..

SAES2

Bit 1: Enable AES2 security..

SPKA

Bit 2: Enable PKA security.

SRNG

Bit 3: Enable True RNG security.

TIM1

0x40012c00: Advanced-timers

13/183 fields covered.

Toggle register map

Offset	Name	31	30	29	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1																	UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2						MMS2				OIS6		OIS5		OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR												SMS_3	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER														TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR											CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																				B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input													IC2F				IC2PSC		CC2S		C1F				IC1PSC		CC1S
0x18	CCMR1_Output					OC2M_3							OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input													IC4F				IC4PSC		CC4S		IC3F				C3PSC		CC3S
0x1c	CCMR2_Output					OC4M_3							OC3M_3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER							CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY												CNT
0x28	PSC													PSC
0x2c	ARR													ARR
0x30	RCR													REP
0x34	CCR1													CCR1
0x38	CCR2													CCR2
0x3c	CCR3													CCR3
0x40	CCR4													CCR4
0x44	BDTR				BK2P	BK2E	BK2F			BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR																DBL								DBA
0x4c	DMAR													DMAB
0x50	OR																								TI1_RMP			TIM1_ETR_ADC1_RMP
0x54	CCMR3_Output					OC6M_3							OC5M_3	OC6CE	OC6M			OC6PE	OC6FE			OC5CE	OC5M			OC5PE	OC5FE
0x58	CCR5	GC5C3	GC5C2	GC5C1										CCR5
0x5c	CCR6													CCR6
0x60	AF1												ETRSEL	ETRSEL				BKCMP2P	BKCMP1P	BKINP							BKCMP2E	BKCMP1E	BKINE
0x64	AF2																	BK2CMP2P	BK2CMP1P	BK2INP	BK2DFBK0E						BK2CMP2E	BK2CMP1E	BK2INE

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 16: Output Idle state 5 (OC5 output).

OIS6

Bit 18: Output Idle state 6 (OC6 output).

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		C1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

C1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				C3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

C3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REP rw

Toggle fields

REP

Bits 0-15: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3 rw

Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4 rw

Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TI1_RMP rw			TIM1_ETR_ADC1_RMP rw

Toggle fields

TIM1_ETR_ADC1_RMP

Bits 0-1: TIM1_ETR_ADC1 remapping capability.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M_3 rw								OC5M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-15: Capture/Compare value.

AF1

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

AF2

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2DFBK0E rw						BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM16

0x40014400: General purpose timers

2/66 fields covered.

Toggle register map

Offset	Name	31	28	26	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1									UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2											OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER											CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR											CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR													BG		COMG				CC1G	UG
0x18	CCMR1_Input													IC1F				IC1PSC		CC1S
0x18	CCMR1_Output				OC1M_2										OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY				CNT
0x28	PSC					PSC
0x2c	ARR					ARR
0x30	RCR													REP
0x34	CCR1					CCR1
0x44	BDTR		BKBID	BKDSRM		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR								DBL								DBA
0x4c	DMAR					DMAB
0x50	OR																			TI1_RMP
0x60	AF1									BKCMP2P	BKCMP1P	BKINP							BKCMP2E	BKCMP1E	BKINE
0x68	TISEL																	TI1SEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable..

UDIS

Bit 1: Update disable..

URS

Bit 2: Update request source..

OPM

Bit 3: One pulse mode..

ARPE

Bit 7: Auto-reload preload enable..

CKD

Bits 8-9: Clock division..

UIFREMAP

Bit 11: UIF status bit remapping..

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable..

CC1IE

Bit 1: Capture/Compare 1 interrupt enable..

COMIE

Bit 5: COM interrupt enable..

BIE

Bit 7: Break interrupt enable..

UDE

Bit 8: Update DMA request enable..

CC1DE

Bit 9: Capture/Compare 1 DMA request enable..

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break disarm.

BKBID

Bit 28: Break bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TI1_RMP rw

Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

AF1

TIM16 Alternate function

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TISEL

Input Selection

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL N/A

Toggle fields

TI1SEL

Bits 0-3: Selects TI1 input.

TIM17

0x40014800: General purpose timers

2/66 fields covered.

Toggle register map

Offset	Name	31	28	26	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1									UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2											OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER											CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10	SR											CC1OF		BIF		COMIF				CC1IF	UIF
0x14	EGR													BG		COMG				CC1G	UG
0x18	CCMR1_Input													IC1F				IC1PSC		CC1S
0x18	CCMR1_Output				OC1M_2										OC1M			OC1PE	OC1FE	CC1S
0x20	CCER																	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY				CNT
0x28	PSC					PSC
0x2c	ARR					ARR
0x30	RCR													REP
0x34	CCR1					CCR1
0x44	BDTR		BKBID	BKDSRM		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR								DBL								DBA
0x4c	DMAR					DMAB
0x50	OR1																			TI1_RMP
0x60	AF1									BKCMP2P	BKCMP1P	BKINP							BKCMP2E	BKCMP1E	BKINE
0x68	TISEL																	TI1SEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable..

CC1IE

Bit 1: Capture/Compare 1 interrupt enable..

COMIE

Bit 5: COM interrupt enable..

BIE

Bit 7: Break interrupt enable..

UDE

Bit 8: Update DMA request enable..

CC1DE

Bit 9: Capture/Compare 1 DMA request enable..

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break disarm.

BKBID

Bit 28: Break bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM17 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TI1_RMP rw

Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

AF1

TIM17 Alternate function

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TISEL

Input Selection

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL N/A

Toggle fields

TI1SEL

Bits 0-3: Selects TI1 input.

TIM2

0x40000000: General-purpose-timers

9/112 fields covered.

Toggle register map

Offset	Name	31	30	24	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1									UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2													TI1S	MMS			CCDS
0x8	SMCR				SMS_3	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER								CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR								CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR														TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input					IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output			OC2M_3	OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input					IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output			OC4M_3	OC3M_3	OC4CE	OC4M			OC4PE	OC4FE	CC4S		OC3CE	OC3M			OC3PE	OC3FE	CC3S
0x20	CCER					CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	CNT	UIFREMAP_CNT			UIFREMAP_CNT
0x28	PSC					PSC
0x2c	ARR	ARR				ARR
0x34	CCR1	CCR1				CCR1
0x38	CCR2	CCR2				CCR2
0x3c	CCR3	CCR3				CCR3
0x40	CCR4	CCR4				CCR4
0x48	DCR								DBL								DBA
0x4c	DMAR					DMAB
0x50	OR																	TI4_RMP		ETR_RMP	ITR_RMP
0x60	AF				ETRSEL	ETRSEL

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT N/A	UIFREMAP_CNT N/A
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UIFREMAP_CNT N/A

Toggle fields

UIFREMAP_CNT

Bits 0-30: Counter value when CR1.UIFREMAP=1.

CNT

Bits 0-31: Counter value.

UIFCPY

Bit 31: Copy of ISR.UIF when CR1.UIFREMAP=1.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-31: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-31: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-31: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3 rw

Toggle fields

CCR3

Bits 0-31: Capture/Compare 3 value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4 rw

Toggle fields

CCR4

Bits 0-31: Capture/Compare 4 value.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI4_RMP rw		ETR_RMP rw	ITR_RMP rw

Toggle fields

ITR_RMP

Bit 0: Internal trigger remap.

ETR_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input capture 4 remap.

AF

TIM2 alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle fields

ETRSEL

Bits 14-16: External trigger source selection.

TSC

0x40024000: Touch sensing controller

14/151 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR	CTPH	CTPL				SSD							SSE	SSPSC	PGPSC							MCV			IODEF	SYNCPOL	AM	START	TSCE
0x4	IER																												MCEIE	EOAIE
0x8	ICR																												MCEIC	EOAIC
0xc	ISR																												MCEF	EOAF
0x10	IOHCR		G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x18	IOASCR		G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x20	IOSCR		G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x28	IOCCR		G7_IO4	G7_IO3	G7_IO2	G7_IO1	G6_IO4	G6_IO3	G6_IO2	G6_IO1	G5_IO4	G5_IO3	G5_IO2	G5_IO1	G4_IO4	G4_IO3	G4_IO2	G4_IO1	G3_IO4	G3_IO3	G3_IO2	G3_IO1	G2_IO4	G2_IO3	G2_IO2	G2_IO1	G1_IO4	G1_IO3	G1_IO2	G1_IO1
0x30	IOGCSR							G7S	G6S	G5S	G4S	G3S	G2S	G1S										G7E	G6E	G5E	G4E	G3E	G2E	G1E
0x34	IOG1CR																CNT
0x38	IOG2CR																CNT
0x3c	IOG3CR																CNT
0x40	IOG4CR																CNT
0x44	IOG5CR																CNT
0x48	IOG6CR																CNT
0x4c	IOG7CR																CNT

Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTPH rw				CTPL rw				SSD rw							SSE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSPSC rw	PGPSC rw							MCV rw			IODEF rw	SYNCPOL rw	AM rw	START rw	TSCE rw

Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIE rw	EOAIE rw

Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIC rw	EOAIC rw

Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEF rw	EOAF rw

Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

7/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									G7S r	G6S r	G5S r	G4S r	G3S r	G2S r	G1S r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									G7E rw	G6E rw	G5E rw	G4E rw	G3E rw	G2E rw	G1E rw

Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

IOG1CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

IOG2CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

IOG3CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

IOG4CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

IOG5CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

IOG6CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

IOG7CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle fields

CNT

Bits 0-13: Counter value.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

29/134 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT4	DEAT3	DEAT2	DEAT1	DEAT0	DEDT4	DEDT3	DEDT2	DEDT1	DEDT0	OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD4_7				ADD0_3				RTOEN	ABRMOD1	ABRMOD0	ABREN	MSBFIRST	TAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NCF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT4 rw	DEAT3 rw	DEAT2 rw	DEAT1 rw	DEAT0 rw	DEDT4 rw	DEDT3 rw	DEDT2 rw	DEDT1 rw	DEDT0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD1 rw	ABRMOD0 rw	ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

USB

0x40006800: Universal serial bus full-speed device interface

21/167 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	EP0R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x4 (16-bit)	EP1R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x8 (16-bit)	EP2R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0xc (16-bit)	EP3R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x10 (16-bit)	EP4R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x14 (16-bit)	EP5R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x18 (16-bit)	EP6R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x1c (16-bit)	EP7R	CTR_RX	DTOG_RX	STAT_RX		SETUP	EP_TYPE		EP_KIND	CTR_TX	DTOG_TX	STAT_TX		EA
0x40 (16-bit)	CNTR	CTRM	PMAOVRM	ERRM	WKUPM	SUSPM	RESETM	SOFM	ESOFM	L1REQM		L1RESUME	RESUME	FSUSP	LPMODE	PDWN	FRES
0x44 (16-bit)	ISTR	CTR	PMAOVR	ERR	WKUP	SUSP	RESET	SOF	ESOF	L1REQ			DIR	EP_ID
0x48 (16-bit)	FNR	RXDP	RXDM	LCK	LSOF		FN
0x4c (16-bit)	DADDR									EF	ADD
0x50 (16-bit)	BTABLE	BTABLE
0x52 (16-bit)	COUNT0_TX							COUNT0_TX
0x54 (16-bit)	ADDR0_RX	ADDR0_RX
0x54 (16-bit)	LPMCSR									BESL				REMWAKE		LPMACK	LPMEN
0x56 (16-bit)	COUNT0_RX	BL_SIZE	NUM_BLOCK					COUNT0_RX
0x58 (16-bit)	BCDR	DPPU								PS2DET	SDET	PDET	DCDET	SDEN	PDEN	DCDEN	BCDEN
0x5a (16-bit)	COUNT1_TX							COUNT1_TX
0x5c (16-bit)	ADDR1_RX	ADDR1_RX
0x5e (16-bit)	COUNT1_RX	BL_SIZE	NUM_BLOCK					COUNT1_RX
0x62 (16-bit)	COUNT2_TX							COUNT2_TX
0x64 (16-bit)	ADDR2_RX	ADDR2_RX
0x66 (16-bit)	COUNT2_RX	BL_SIZE	NUM_BLOCK					COUNT2_RX
0x6a (16-bit)	COUNT3_TX							COUNT3_TX
0x6c (16-bit)	ADDR3_RX	ADDR3_RX
0x6e (16-bit)	COUNT3_RX	BL_SIZE	NUM_BLOCK					COUNT3_RX
0x72 (16-bit)	COUNT4_TX							COUNT4_TX
0x74 (16-bit)	ADDR4_RX	ADDR4_RX
0x76 (16-bit)	COUNT4_RX	BL_SIZE	NUM_BLOCK					COUNT4_RX
0x7a (16-bit)	COUNT5_TX							COUNT5_TX
0x7c (16-bit)	ADDR5_RX	ADDR5_RX
0x7e (16-bit)	COUNT5_RX	BL_SIZE	NUM_BLOCK					COUNT5_RX
0x82 (16-bit)	COUNT6_TX							COUNT6_TX
0x84 (16-bit)	ADDR6_RX	ADDR6_RX
0x86 (16-bit)	COUNT6_RX	BL_SIZE	NUM_BLOCK					COUNT6_RX
0x8a (16-bit)	COUNT7_TX							COUNT7_TX
0x8c (16-bit)	ADDR7_RX	ADDR7_RX
0x8e (16-bit)	COUNT7_RX	BL_SIZE	NUM_BLOCK					COUNT7_RX

Toggle registers

EP0R

endpoint 0 register

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP1R

endpoint 1 register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP2R

endpoint 2 register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP3R

endpoint 3 register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP4R

endpoint 4 register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP5R

endpoint 5 register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP6R

endpoint 6 register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP7R

endpoint 7 register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 16, reset: 0x00000003, access: read-write

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTRM rw	PMAOVRM rw	ERRM rw	WKUPM rw	SUSPM rw	RESETM rw	SOFM rw	ESOFM rw	L1REQM rw		L1RESUME rw	RESUME rw	FSUSP rw	LPMODE rw	PDWN rw	FRES rw

Toggle fields

FRES

Bit 0: Force USB Reset.

PDWN

Bit 1: Power down.

LPMODE

Bit 2: Low-power mode.

FSUSP

Bit 3: Force suspend.

RESUME

Bit 4: Resume request.

L1RESUME

Bit 5: LPM L1 Resume request.

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RESETM

Bit 10: USB reset interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

ISTR

interrupt status register

Offset: 0x44, size: 16, reset: 0x00000000, access: Unspecified

3/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR r	PMAOVR rw	ERR rw	WKUP rw	SUSP rw	RESET rw	SOF rw	ESOF rw	L1REQ rw			DIR r	EP_ID r

Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 state request.

ESOF

Bit 8: Expected start frame.

SOF

Bit 9: start of frame.

RESET

Bit 10: reset request.

SUSP

Bit 11: Suspend mode request.

WKUP

Bit 12: Wakeup.

ERR

Bit 13: Error.

PMAOVR

Bit 14: Packet memory area over / underrun.

CTR

Bit 15: Correct transfer.

FNR

frame number register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDP r	RXDM r	LCK r	LSOF r		FN r

Toggle fields

FN

Bits 0-10: Frame number.

LSOF

Bits 11-12: Lost SOF.

LCK

Bit 13: Locked.

RXDM

Bit 14: Receive data - line status.

RXDP

Bit 15: Receive data + line status.

DADDR

device address

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EF rw	ADD rw

Toggle fields

ADD

Bits 0-6: Device address.

EF

Bit 7: Enable function.

BTABLE

Buffer table address

Offset: 0x50, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BTABLE rw

Toggle fields

BTABLE

Bits 3-15: Buffer table.

COUNT0_TX

Transmission byte count 0

Offset: 0x52, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT0_TX rw

Toggle fields

COUNT0_TX

Bits 0-9: Transmission byte count.

ADDR0_RX

Reception buffer address 0

Offset: 0x54, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR0_RX rw

Toggle fields

ADDR0_RX

Bits 1-15: Reception buffer address.

LPMCSR

control and status register

Offset: 0x54, size: 16, reset: 0x00000000, access: Unspecified

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BESL r				REMWAKE rw		LPMACK rw	LPMEN rw

Toggle fields

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM Token acknowledge enable.

REMWAKE

Bit 3: RemoteWake value.

BESL

Bits 4-7: BESL value.

COUNT0_RX

Reception byte count 0

Offset: 0x56, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT0_RX r

Toggle fields

COUNT0_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

BCDR

Battery charging detector(

Offset: 0x58, size: 16, reset: 0x00000000, access: Unspecified

4/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPPU rw								PS2DET r	SDET r	PDET r	DCDET r	SDEN rw	PDEN rw	DCDEN rw	BCDEN rw

Toggle fields

BCDEN

Bit 0: Battery charging detector (BCD) enable.

DCDEN

Bit 1: Data contact detection (DCD) mode enable.

PDEN

Bit 2: Primary detection (PD) mode enable.

SDEN

Bit 3: Secondary detection (SD) mode enable.

DCDET

Bit 4: Data contact detection (DCD) status.

PDET

Bit 5: Primary detection (PD) status.

SDET

Bit 6: Secondary detection (SD) status.

PS2DET

Bit 7: DM pull-up detection status.

DPPU

Bit 15: DP pull-up control.

COUNT1_TX

Transmission byte count 0

Offset: 0x5a, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT1_TX rw

Toggle fields

COUNT1_TX

Bits 0-9: Transmission byte count.

ADDR1_RX

Reception buffer address 0

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR1_RX rw

Toggle fields

ADDR1_RX

Bits 1-15: Reception buffer address.

COUNT1_RX

Reception byte count 0

Offset: 0x5e, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT1_RX r

Toggle fields

COUNT1_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT2_TX

Transmission byte count 0

Offset: 0x62, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT2_TX rw

Toggle fields

COUNT2_TX

Bits 0-9: Transmission byte count.

ADDR2_RX

Reception buffer address 0

Offset: 0x64, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR2_RX rw

Toggle fields

ADDR2_RX

Bits 1-15: Reception buffer address.

COUNT2_RX

Reception byte count 0

Offset: 0x66, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT2_RX r

Toggle fields

COUNT2_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT3_TX

Transmission byte count 0

Offset: 0x6a, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT3_TX rw

Toggle fields

COUNT3_TX

Bits 0-9: Transmission byte count.

ADDR3_RX

Reception buffer address 0

Offset: 0x6c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR3_RX rw

Toggle fields

ADDR3_RX

Bits 1-15: Reception buffer address.

COUNT3_RX

Reception byte count 0

Offset: 0x6e, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT3_RX r

Toggle fields

COUNT3_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT4_TX

Transmission byte count 0

Offset: 0x72, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT4_TX rw

Toggle fields

COUNT4_TX

Bits 0-9: Transmission byte count.

ADDR4_RX

Reception buffer address 0

Offset: 0x74, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR4_RX rw

Toggle fields

ADDR4_RX

Bits 1-15: Reception buffer address.

COUNT4_RX

Reception byte count 0

Offset: 0x76, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT4_RX r

Toggle fields

COUNT4_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT5_TX

Transmission byte count 0

Offset: 0x7a, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT5_TX rw

Toggle fields

COUNT5_TX

Bits 0-9: Transmission byte count.

ADDR5_RX

Reception buffer address 0

Offset: 0x7c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR5_RX rw

Toggle fields

ADDR5_RX

Bits 1-15: Reception buffer address.

COUNT5_RX

Reception byte count 0

Offset: 0x7e, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT5_RX r

Toggle fields

COUNT5_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT6_TX

Transmission byte count 0

Offset: 0x82, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT6_TX rw

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COUNT6_TX

Bits 0-9: Transmission byte count.

ADDR6_RX

Reception buffer address 0

Offset: 0x84, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR6_RX rw

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ADDR6_RX

Bits 1-15: Reception buffer address.

COUNT6_RX

Reception byte count 0

Offset: 0x86, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT6_RX r

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COUNT6_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT7_TX

Transmission byte count 0

Offset: 0x8a, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT7_TX rw

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COUNT7_TX

Bits 0-9: Transmission byte count.

ADDR7_RX

Reception buffer address 0

Offset: 0x8c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR7_RX rw

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ADDR7_RX

Bits 1-15: Reception buffer address.

COUNT7_RX

Reception byte count 0

Offset: 0x8e, size: 16, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT7_RX r

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COUNT7_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered.

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Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CSR																													VRR	VRS	HIZ	ENVR
0x4	CCR																											TRIM

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CSR

VREF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VRR r	VRS rw	HIZ rw	ENVR rw

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ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRIM rw

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TRIM

Bits 0-5: Trimming code.

WWDG

0x40002c00: System window watchdog

0/6 fields covered.

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Offset	Name	13	9	7	6	0
0x0	CR			WDGA	T
0x4	CFR	WDGTB	EWI		W
0x8	SR					EWIF

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CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

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T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		WDGTB rw				EWI rw			W rw

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W

Bits 0-6: 7-bit window value.

EWI

Bit 9: Early wakeup interrupt.

WDGTB

Bits 11-13: Timer base.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

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EWIF

Bit 0: Early wakeup interrupt flag.