STM32WL33 Peripheral Coverage

ADC

0x41006000: ADC address block description

4/83 fields covered.

Toggle register map

Offset	Name	31	27	26	23	22	21	19	18	17	15	13	12	11	10	9	7	6	5	4	3	2	1	0
0x0	VERSION_ID																VERSION_ID
0x4	CONF				SAMPLE_RATE_MSB			ADC_CONT_1V2	BIT_INVERT_DIFF	BIT_INVERT_SN	OVR_DS_CFG	DMA_DS_ENA	SAMPLE_RATE		SAMPLE_RATE_LSB			SMPS_SYNCHRO_ENA	SEQ_LEN				SEQUENCE	CONT
0x8	CTRL																			TEST_MODE		STOP_OP_MODE	START_CONV	ADC_ON_OFF
0x14	SWITCH										SE_VIN_7	SE_VIN_6		SE_VIN_5		SE_VIN_4	SE_VIN_3		SE_VIN_2		SE_VIN_1		SE_VIN_0
0x1c	DS_CONF																		DS_WIDTH			DS_RATIO
0x20	SEQ_1	SEQ7	SEQ6		SEQ5			SEQ4			SEQ3			SEQ2			SEQ1				SEQ0
0x24	SEQ_2	SEQ15	SEQ14		SEQ13			SEQ12			SEQ11			SEQ10			SEQ9				SEQ8
0x28	COMP_1							OFFSET1			OFFSET1			GAIN1
0x2c	COMP_2							OFFSET2			OFFSET2			GAIN2
0x30	COMP_3							OFFSET3			OFFSET3			GAIN3
0x34	COMP_4							OFFSET4			OFFSET4			GAIN4
0x38	COMP_SEL									OFFSET_GAIN8	OFFSET_GAIN7	OFFSET_GAIN6		OFFSET_GAIN5		OFFSET_GAIN4	OFFSET_GAIN3		OFFSET_GAIN2		OFFSET_GAIN1		OFFSET_GAIN0
0x3c	WD_TH		WD_HT											WD_LT
0x40	WD_CONF										AWD_CHX
0x44	DS_DATAOUT										DS_DATA
0x4c	IRQ_STATUS																		OVR_DS_IRQ	AWD_IRQ	EOS_IRQ		EODS_IRQ	EOC_IRQ
0x50	IRQ_ENABLE																		OVR_DS_IRQ	AWD_IRQ	EOS_IRQ		EODS_IRQ	EOC_IRQ
0x60	TEST_CONF					ADC_ENABLE	ADC_RUN	SEL_VIN_TYPE			ADC_SWITCH_EN
0x64	DTB_CONF			FSM_CUR_STATE	FSM_STATE										DTB_SER_SEL	ADC_DTB_CONF					ADC_DBG_CONF

Toggle registers

VERSION_ID

VERSION_ID register

Offset: 0x0, size: 32, reset: 0x00000021, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								VERSION_ID r

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VERSION_ID

Bits 0-7: VERSION_ID[7:0]: version of the embedded IP..

CONF

CONF register

Offset: 0x4, size: 32, reset: 0x00020002, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SAMPLE_RATE_MSB rw				ADC_CONT_1V2 rw	BIT_INVERT_DIFF rw	BIT_INVERT_SN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVR_DS_CFG rw		DMA_DS_ENA rw	SAMPLE_RATE rw		SAMPLE_RATE_LSB rw				SMPS_SYNCHRO_ENA rw	SEQ_LEN rw				SEQUENCE rw	CONT rw

Toggle fields

CONT

Bit 0: CONT: regular sequence runs continuously when ADC mode is enabled: 0: enable the single conversion: when the sequence is over, the conversion stops 1: enable the continuous conversion: when the sequence is over, the sequence starts again until the software sets the CTRL.STOP_OP_MODE bit..

SEQUENCE

Bit 1: SEQUENCE: enable the sequence mode (active by default): 0: sequence mode is disabled, only SEQ0 is selected 1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can be kept high as redundant with keeping high and setting SEQ_LEN=0000..

SEQ_LEN

Bits 2-5: SEQ_LEN[3:0]: number of conversions in a regular sequence: 0000: 1 conversion, starting from SEQ0 0001: 2 conversions, starting from SEQ0 ... 1111: 16 conversions, starting from SEQ0.

SMPS_SYNCHRO_ENA

Bit 6: SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the SMPS: 0: SMPS synchronization is disabled for all ADC clock frequencies 1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when PWRC_CR5.NOSMPS = 1..

SAMPLE_RATE_LSB

Bits 9-10: SAMPLE_RATE_LSB: Sample Rate LSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. When this field is set to a value different than 0, SMPS synchronization is not feasible. This value is hidden to the user.

SAMPLE_RATE

Bits 11-12: SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency..

DMA_DS_ENA

Bit 13: DMA_DS_EN: enable the DMA mode for the Down Sampler data path: 0: DMA mode is disabled 1: DMA mode is enabled.

OVR_DS_CFG

Bit 15: OVR_DS_CFG: Down Sampler overrun configuration: 0: the previous data is kept, the new one is lost 1: the previous data is lost, the new one is kept.

BIT_INVERT_SN

Bit 17: BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single negative input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.

BIT_INVERT_DIFF

Bit 18: BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.

ADC_CONT_1V2

Bit 19: ADC_CONT_1V2: select the input sampling method: 0: sampling only at conversion start (default) 1: sampling starts at the end of conversion.

SAMPLE_RATE_MSB

Bits 21-23: SAMPLE_RATE_MSB: Sample Rate MSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description.

CTRL

CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TEST_MODE rw		STOP_OP_MODE w	START_CONV w	ADC_ON_OFF rw

Toggle fields

ADC_ON_OFF

Bit 0: ADC_ON_OFF: 0: power off the ADC 1: power on the ADC.

START_CONV

Bit 1: START_CONV (1): generate a start pulse to initiate an ADC conversion: 0: no effect 1: start the ADC conversion Note: this bit is set by software and cleared by hardware..

STOP_OP_MODE

Bit 2: STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full mode): 0: no effect 1: stop on-going ADC mode Note: this bit is set by software and cleared by hardware. When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit..

TEST_MODE

Bit 4: TEST_MODE: select the functional or the test mode of the ADC: 0: functional mode (one of the four main functional modes is used) 1: test mode (for debug, test, calibration).

SWITCH

SWITCH register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SE_VIN_7 rw		SE_VIN_6 rw		SE_VIN_5 rw		SE_VIN_4 rw		SE_VIN_3 rw		SE_VIN_2 rw		SE_VIN_1 rw		SE_VIN_0 rw

Toggle fields

SE_VIN_0

Bits 0-1: SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_1

Bits 2-3: SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_2

Bits 4-5: SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_3

Bits 6-7: SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_4

Bits 8-9: SE_VIN_4[1:0]: input voltage for VINP[0] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_5

Bits 10-11: SE_VIN_5[1:0]: input voltage for VINP[1] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_6

Bits 12-13: SE_VIN_6[1:0]: input voltage for VINP[2] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

SE_VIN_7

Bits 14-15: SE_VIN_7[1:0]: input voltage for VINP[3] 00: Vinput = 1.2V 01: reserved (not used for this cut) 10: Vinput = 2.4V 11: Vinput = 3.6V.

DS_CONF

DS_CONF register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DS_WIDTH rw			DS_RATIO rw

Toggle fields

DS_RATIO

Bits 0-2: DS_RATIO[2:0]: program the Down Sampler ratio (N factor) 000: ratio = 1, no down sampling (default) 001: ratio = 2 010: ratio = 4 011: ratio = 8 100: ratio = 16 101: ratio = 32 110: ratio = 64 111: ratio = 128.

DS_WIDTH

Bits 3-5: DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) 000: DS_DATA output on 12-bit (default) 001: DS_DATA output on 13-bit 010: DS_DATA output on 14-bit 011: DS_DATA output on 15-bit 100: DS_DATA output on 16-bit 1xx: reserved.

SEQ_1

SEQ_1 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ7 rw				SEQ6 rw				SEQ5 rw				SEQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ3 rw				SEQ2 rw				SEQ1 rw				SEQ0 rw

Toggle fields

SEQ0

Bits 0-3: SEQ0[3:0]: channel number code for first conversion of the sequence 0000: VINM[0] to ADC single negative input 0001: VINM[1] to ADC single negative input 0010: VINM[2] to ADC single negative input 0011: VINM[3] to ADC single negative input 0100: VINP[0] to ADC single positive input 0101: VINP[1] to ADC single positive input 0110: VINP[2] to ADC single positive input 0111: VINP[3] to ADC single positive input 1000: VINP[0]-VINM[0] to ADC differential input 1001: VINP[1]-VINM[1] to ADC differential input 1010: VINP[2]-VINM[2] to ADC differential input 1011: VINP[3]-VINM[3] to ADC differential input 1100: VBAT - Battery level detector 1101: Temperature sensor 111x: reserved.

SEQ1

Bits 4-7: SEQ1[3:0]: channel number code for second conversion of the sequence. See SEQ0 for code detail..

SEQ2

Bits 8-11: SEQ2[3:0]: channel number code for 3rd conversion of the sequence. See SEQ0 for code detail..

SEQ3

Bits 12-15: SEQ3[3:0]: channel number code for 4th conversion of the sequence. See SEQ0 for code detail..

SEQ4

Bits 16-19: SEQ4[3:0]: channel number code for 5th conversion of the sequence. See SEQ0 for code detail..

SEQ5

Bits 20-23: SEQ5[3:0]: channel number code for 6th conversion of the sequence. See SEQ0 for code detail..

SEQ6

Bits 24-27: SEQ6[3:0]: channel number code for 7th conversion of the sequence. See SEQ0 for code detail..

SEQ7

Bits 28-31: SEQ7[3:0]: channel number code for 8th conversion of the sequence. See SEQ0 for code detail..

SEQ_2

SEQ_2 register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ15 rw				SEQ14 rw				SEQ13 rw				SEQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ11 rw				SEQ10 rw				SEQ9 rw				SEQ8 rw

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SEQ8

Bits 0-3: SEQ8[3:0]: channel number code for 9th conversion of the sequence 0000: VINM[0] to ADC single negative input 0001: VINM[1] to ADC single negative input 0010: VINM[2] to ADC single negative input 0011: VINM[3] to ADC single negative input 0100: VINP[0] to ADC single positive input 0101: VINP[1] to ADC single positive input 0110: VINP[2] to ADC single positive input 0111: VINP[3] to ADC single positive input 1000: VINP[0]-VINM[0] to ADC differential input 1001: VINP[1]-VINM[1] to ADC differential input 1010: VINP[2]-VINM[2] to ADC differential input 1011: VINP[3]-VINM[3] to ADC differential input 1100: VBAT - Battery level detector 1101: Temperature sensor 111x: reserved.

SEQ9

Bits 4-7: SEQ9[3:0]: channel number code for 10th conversion of the sequence. See SEQ0 for code detail..

SEQ10

Bits 8-11: SEQ10[3:0]: channel number code for 11th conversion of the sequence. See SEQ0 for code detail..

SEQ11

Bits 12-15: SEQ11[3:0]: channel number code for 12th conversion of the sequence. See SEQ0 for code detail..

SEQ12

Bits 16-19: SEQ12[3:0]: channel number code for 13th conversion of the sequence. See SEQ0 for code detail..

SEQ13

Bits 20-23: SEQ13[3:0]: channel number code for 14th conversion of the sequence. See SEQ0 for code detail..

SEQ14

Bits 24-27: SEQ14[3:0]: channel number code for 15th conversion of the sequence. See SEQ0 for code detail..

SEQ15

Bits 28-31: SEQ15[3:0]: channel number code for 16th conversion of the sequence. See SEQ0 for code detail..

COMP_1

COMP_1 register

Offset: 0x28, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET1 rw				GAIN1 rw

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GAIN1

Bits 0-11: GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET1

Bits 12-19: OFFSET1[7:0]: first calibration point.

COMP_2

COMP_2 register

Offset: 0x2c, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET2 rw				GAIN2 rw

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GAIN2

Bits 0-11: GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET2

Bits 12-19: OFFSET2[7:0]: second calibration point.

COMP_3

COMP_3 register

Offset: 0x30, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET3 rw				GAIN3 rw

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GAIN3

Bits 0-11: GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET3

Bits 12-19: OFFSET3[7:0]: third calibration point.

COMP_4

COMP_4 register

Offset: 0x34, size: 32, reset: 0x00000555, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												OFFSET4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET4 rw				GAIN4 rw

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GAIN4

Bits 0-11: GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0].

OFFSET4

Bits 12-19: OFFSET4[7:0]: fourth calibration point.

COMP_SEL

COMP_SEL register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														OFFSET_GAIN8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET_GAIN7 rw		OFFSET_GAIN6 rw		OFFSET_GAIN5 rw		OFFSET_GAIN4 rw		OFFSET_GAIN3 rw		OFFSET_GAIN2 rw		OFFSET_GAIN1 rw		OFFSET_GAIN0 rw

Toggle fields

OFFSET_GAIN0

Bits 0-1: OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN1

Bits 2-3: OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = 1.2V. This field also selects the gain/offset for Temperature Sensor input:: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN2

Bits 4-5: OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN3

Bits 6-7: OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN4

Bits 8-9: OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN5

Bits 10-11: OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN6

Bits 12-13: OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = 3.6V. This field also selects the gain/offset for VBAT input:: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN7

Bits 14-15: OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

OFFSET_GAIN8

Bits 16-17: OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: 00: OFFSET1 and GAIN1 from COMP_1 01: OFFSET2 and GAIN2 from COMP_2 10: OFFSET3 and GAIN3 from COMP_3 11: OFFSET4 and GAIN4 from COMP_4.

WD_TH

WD_TH register

Offset: 0x3c, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				WD_HT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WD_LT rw

Toggle fields

WD_LT

Bits 0-11: WD_LT[11:0]: analog watchdog low level threshold..

WD_HT

Bits 16-27: WD_HT[11:0]: analog watchdog high level threshold..

WD_CONF

WD_CONF register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD_CHX rw

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AWD_CHX

Bits 0-15: AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog. Bit0: VINM[0] to ADC negative input Bit1: VINM[1] to ADC negative input Bit2: VINM[2] to ADC negative input Bit3: VINM[3] to ADC negative input Bit4: Not used Bit5: VBAT to ADC negative input Bit6: GND to ADC negative input Bit7: VDDA to ADC negative input Bit8: VINP[0] to ADC positive input Bit9: VINP[1] to ADC positive input Bit10: VINP[2] to ADC positive input Bit11: VINP[3] to ADC positive input Bit12: Not used Bit13: TEMP to ADC positive input Bit14: GND to ADC positive input Bit15: VDDA to ADC positive input.

DS_DATAOUT

DS_DATAOUT register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DS_DATA r

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DS_DATA

Bits 0-15: DS_DATA[15:0]: contain the converted data at the output of the Down Sampler..

IRQ_STATUS

IRQ_STATUS register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										OVR_DS_IRQ rw	AWD_IRQ rw	EOS_IRQ rw		EODS_IRQ rw	EOC_IRQ rw

Toggle fields

EOC_IRQ

Bit 0: EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. When read, provide the status of the interrupt: 0: ADC conversion is not completed 1: ADC conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EODS_IRQ

Bit 1: EODS_IRQ: set when the Down Sampler conversion is completed. When read, provide the status of the interrupt: 0: Down Sampler conversion is not completed 1: Down Sampler conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EOS_IRQ

Bit 3: EOS_IRQ: set when a sequence of conversion is completed. When read, provide the status of the interrupt: 0: sequence of conversion is not completed 1: sequence of conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

AWD_IRQ

Bit 4: AWD_IRQ: set when an analog watchdog event occurs. When read, provide the status of the interrupt: 0: no analog watchdog event occurred 1: analog watchdog event has occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

OVR_DS_IRQ

Bit 5: OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) When read, provide the status of the interrupt: 0: no overrun occurred 1: overrun occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

IRQ_ENABLE

IRQ_ENABLE register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										OVR_DS_IRQ rw	AWD_IRQ rw	EOS_IRQ rw		EODS_IRQ rw	EOC_IRQ rw

Toggle fields

EOC_IRQ

Bit 0: EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. When read, provide the status of the interrupt: 0: ADC conversion is not completed 1: ADC conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EODS_IRQ

Bit 1: EODS_IRQ: set when the Down Sampler conversion is completed. When read, provide the status of the interrupt: 0: Down Sampler conversion is not completed 1: Down Sampler conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

EOS_IRQ

Bit 3: EOS_IRQ: set when a sequence of conversion is completed. When read, provide the status of the interrupt: 0: sequence of conversion is not completed 1: sequence of conversion is completed Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

AWD_IRQ

Bit 4: AWD_IRQ: set when an analog watchdog event occurs. When read, provide the status of the interrupt: 0: no analog watchdog event occurred 1: analog watchdog event has occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

OVR_DS_IRQ

Bit 5: OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) When read, provide the status of the interrupt: 0: no overrun occurred 1: overrun occurred Writing this bit clears the status of the interrupt: 0: no effect 1: clear the interrupt.

TEST_CONF

TEST_CONF register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									ADC_ENABLE rw	ADC_RUN rw		SEL_VIN_TYPE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADC_SWITCH_EN rw

Toggle fields

ADC_SWITCH_EN

Bits 0-15: ADC_SWITCH_EN[15:0]: enable individually each connection of the switching matrix at the ADC input. For each bit: 0: switch X is ON 1: switch X is OFF Bit mapping (corresponding to AUXADC_INSEL_1V2[15:0]): Bit 0: VINM[0] to ADC negative input Bit 1: VINM[1] to ADC negative input Bit 2: VINM[2] to ADC negative input Bit 3: VINM[3] to ADC negative input Bit4: GND to ADC negative input Bit5: VBAT to ADC negative input Bit6: GND to ADC negative input Bit7: VDDA to ADC negative input Bit8: VINP[0] to ADC positive input Bit9: VINP[1] to ADC positive input Bit10: VINP[2] to ADC positive input Bit11: VINP[3] to ADC positive input Bit12: VBAT to ADC positive input Bit13: TEMP to ADC positive input Bit14: GND to ADC positive input Bit15: VDDA to ADC positive input..

SEL_VIN_TYPE

Bits 18-19: SEL_VIN_TYPE[1:0]: operation mode of the selected VIN 00: ADC single negative input 01: ADC single positive input 10: ADC differential input mode 11: reserved.

ADC_RUN

Bit 21: ADC_RUN: Start/stop ADC conversion. 0: stop the ADC conversion, 1: starts the ADC conversion..

ADC_ENABLE

Bit 22: ADC_ENABLE: 0: disable the ADC (power OFF) 1: enable the ADC (power ON).

DTB_CONF

DTB_CONF register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					FSM_CUR_STATE r			FSM_STATE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTB_SER_SEL rw	ADC_DTB_CONF rw						ADC_DBG_CONF rw

Toggle fields

ADC_DBG_CONF

Bits 0-3: ADC_DBG_CONF[3:0]: use for debug purpose..

ADC_DTB_CONF

Bits 8-9: ADC_DTB_CONF[1:0]: configure the DTB output. 00: DTB bus is all 0 01: output the ADC_BUSY, ADC_EOC, offset compensation data[11:0] on the ADC_DTB 10: output the DS information on the ADC_DTB 11: select states of the FSM and enable ADC serial output Note: detailed DTB configurations are available in the Table 38 in IUM.

DTB_SER_SEL

Bit 10: DTB_SER_SEL: DTB serial output selection when ADC_DB_CONF[1:0]=3d 0: pre down-sampler with offset compensation data 1: post down-sampler data.

FSM_STATE

Bits 16-23: FSM_STATE[7:0]: show the state of the state machine. Bit 0: IDLE Bit 1: Reserved Bit 2: ADC setup phase Bit 3: Reserved Bit 4: ADC_START_CONV resynchronization Bit 5: Reserved Bit 6: ADC mode Bit 7: sequence mode.

FSM_CUR_STATE

Bits 24-26: FSM_CUR_STATE[2:0]: show the last executed state by the state machine. 000: IDLE mode 001: Reserved 010: ADC setup phase 011: Reserved 100: ADC_START_CONV resynchronization 101: Reserved 110: ADC mode 111: sequence mode.

AES

0x48900000:

5/28 fields covered.

Toggle register map

Offset	Name	31	23	18	16	15	14	12	11	10	9	8	7	6	4	3	2	1	0
0x0	CR		NPBLB	KEYSIZE	CHMOD_2		GCMPH	DMAOUTEN	DMAINEN	ERRIE	CCFIE	ERRC	CCFC	CHMOD_1_0	MODE		DATATYPE		EN
0x4	SR															BUSY	WRERR	RDERR	CCF
0x8	DINR	DINR				DINR
0xc	DOUTR	DOUTR				DOUTR
0x10	KEYR0	KEY				KEY
0x14	KEYR1	KEY				KEY
0x18	KEYR2	KEY				KEY
0x1c	KEYR3	KEY				KEY
0x20	IVR0	IVI				IVI
0x24	IVR1	IVI				IVI
0x28	IVR2	IVI				IVI
0x2c	IVR3	IVI				IVI

Toggle registers

CR

AES_CR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								NPBLB rw					KEYSIZE rw		CHMOD_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	GCMPH rw		DMAOUTEN rw	DMAINEN rw	ERRIE rw	CCFIE rw	ERRC rw	CCFC rw	CHMOD_1_0 rw		MODE rw		DATATYPE rw		EN rw

Toggle fields

EN

Bit 0: EN: AES IP enable.

DATATYPE

Bits 1-2: DATATYPE[1:0]: Data type selection.

MODE

Bits 3-4: MODE[1:0]: AES operating mode.

CHMOD_1_0

Bits 5-6: CHMOD[1:0]: AES Chaining Mode selection.

CCFC

Bit 7: CCFC: Computation Complete Flag Clear.

ERRC

Bit 8: ERRC: Error clear.

CCFIE

Bit 9: CCFIE: CCF Flag Interrupt Enable.

ERRIE

Bit 10: ERRIE: Error Interrupt Enable.

DMAINEN

Bit 11: DMAINEN: DMA Input Enable.

DMAOUTEN

Bit 12: DMAOUTEN: DMA Output Enable.

GCMPH

Bits 13-14: GCMPH[1:0]: GCM or CCM Phase selection.

CHMOD_2

Bit 16: CHMOD[2]: Chaining mode selection, bit [2].

KEYSIZE

Bit 18: KEYSIZE: Key Size selection..

NPBLB

Bits 20-23: NPBLB: Number of Padding Bytes in Last Block of payload..

SR

AES_SR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BUSY r	WRERR r	RDERR r	CCF r

Toggle fields

CCF

Bit 0: CCF: Computation complete flag.

RDERR

Bit 1: RDERR: Read error flag.

WRERR

Bit 2: WRERR: Write error flag.

BUSY

Bit 3: BUSY: Busy flag.

DINR

AES_DINR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DINR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DINR rw

Toggle fields

DINR

Bits 0-31: DINR[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral.

DOUTR

AES_DOUTR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DOUTR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DOUTR r

Toggle fields

DOUTR

Bits 0-31: DOUTR[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the.

KEYR0

AES_KEYRx register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY rw

Toggle fields

KEY

Bits 0-31: KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)].

KEYR1

AES_KEYRx register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY rw

Toggle fields

KEY

Bits 0-31: KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)].

KEYR2

AES_KEYRx register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY rw

Toggle fields

KEY

Bits 0-31: KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)].

KEYR3

AES_KEYRx register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY rw

Toggle fields

KEY

Bits 0-31: KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)].

IVR0

AES_IVRx register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI rw

Toggle fields

IVI

Bits 0-31: IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]).

IVR1

AES_IVRx register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI rw

Toggle fields

IVI

Bits 0-31: IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]).

IVR2

AES_IVRx register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI rw

Toggle fields

IVI

Bits 0-31: IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]).

IVR3

AES_IVRx register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IVI rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IVI rw

Toggle fields

IVI

Bits 0-31: IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]).

COMP

0x40009000: COMP address block description

2/11 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CSR	LOCK	VALUE							SCALEN	BRGEN		BLANKING			HYST		POLARITY							INPSEL		INMSEL			PWRMODE			EN

Toggle registers

CSR

CSR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

2/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r	VALUE r							SCALEN rw	BRGEN rw		BLANKING rw			HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY rw							INPSEL rw		INMSEL rw			PWRMODE rw			EN rw

Toggle fields

EN

Bit 0: EN: Comparator enable bit This bit is set and cleared by software (only if LOCK not set). It switches on Comparator. 0: Comparator switched OFF 1: Comparator switched ON.

PWRMODE

Bits 2-3: PWRMODE[1:0]: Power Mode of the comparator These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the Comparator. 00:High speed 01 or 10:Medium speed 11:Ultra low power.

INMSEL

Bits 4-6: INMSEL: Comparator input minus selection bits These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of comparator. 000: 1/4 VREFINT 001: 1/2 VREFINT 010: 3/4VREFINT 011: VREFINT 100: DAC OUT 101: PA13 110: PB0 111: PB3.

INPSEL

Bits 7-8: INPSEL[1:0]: Comparator input plus selection bit This bit is set and cleared by software (only if LOCK not set). 00: PA14 01: PB1 1x: PB2.

POLARITY

Bit 15: POLARITY: Comparator polarity selection bit This bit is set and cleared by software (only if LOCK not set). It inverts Comparator polarity. 0: Comparator output value not inverted 1: Comparator output value inverted.

HYST

Bits 16-17: HYST[1:0]: Comparator hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the comparator . 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis.

BLANKING

Bits 18-20: BLANKING[2:0]: Comparator blanking source selection bits These bits select which timer output controls the comparator output blanking. 000: No blanking 001: TIM2 OC4 selected as blanking source 010: TIM16 OC1 selected as blanking source All other values: reserved.

BRGEN

Bit 22: BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of the scaler. 0: Scaler resistor bridge disable 1: Scaler resistor bridge enable If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4BGAP, 1/2BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4BGAP, 1/2BGAP, 3/4 BGAP. If SCALEN and BRGEN are set, 1/4 BGAP 1/2BGAP 3/4BGAP and BGAP voltage references are available..

SCALEN

Bit 23: SCALEN: Voltage scaler enable bit This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider available on the minus input of the Comparator 0: scaler disable 1: scaler enable.

VALUE

Bit 30: VALUE: Comparator output status bit This bit is read-only. It reflects the current comparator output taking into account POLARITY bit effect..

LOCK

Bit 31: LOCK: COMP_CSR register lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator control register, COMP1_CSR[31:0]. 0: COMP1_CSR[31:0] are read/write 1: COMP1_CSR[31:0] are read-only.

CRC

0x48200000:

0/8 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x4	IDR	IDR	IDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	INIT	INIT
0x14	POL	POL	POL

Toggle registers

DR

CRC_DR register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

IDR

CRC_IDR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle fields

IDR

Bits 0-31: .

CR

CRC_CR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle fields

RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial. -00: 32 bit polynomial -01: 16 bit polynomial -10: 8 bit polynomial -11: 7 bit polynomial.

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data -00: Bit order not affected -01: Bit reversal done by byte -10: Bit reversal done by half-word -11: Bit reversal done by word.

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data. -0: Bit order not affected -1: Bit-reversed output format.

INIT

CRC_INIT register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INIT rw

Toggle fields

INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

POL

CRC_POL register

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle fields

POL

Bits 0-31: POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

DAC

0x40006000: DAC address block description

1/15 fields covered.

Toggle register map

Offset	Name	16	15	14	13	12	11	7	5	2	1	0
0x0	CR	VCMON	VCMEN	CMPEN	DMAUDRIE	DMAEN	MAMP	WAVE	TSEL	TEN	BON	EN
0x4	SWTRIGR											SWTRIG
0x10	DHR								DACDHR
0x2c	DOR								DACDOR
0x34	SR				DMAUDR

Toggle registers

CR

CR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															VCMON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VCMEN rw	CMPEN rw	DMAUDRIE rw	DMAEN rw	MAMP rw				WAVE rw		TSEL rw			TEN rw	BON rw	EN rw

Toggle fields

EN

Bit 0: EN: DAC channel enable This bit is set and cleared by software to enable/disable DAC channel. 0: DAC channel disabled 1: DAC channel enabled.

BON

Bit 1: BON: DAC channel output buffer enable. This bit is set and cleared by software to enable/disable DAC channel output buffer. 0: DAC channel output buffer disabled 1: DAC channel output buffer enabled.

TEN

Bit 2: TEN: DAC channel trigger enable This bit is set and cleared by software to enable/disable DAC channel trigger. 0: DAC channel trigger disabled and data written into the DAC_DHR register are transferred one APB0 clock cycle later to the DAC_DOR register 1: DAC channel trigger enabled and data from the DAC_DHR register are transferred three APB0 clock cycles later to the DAC_DOR register Note: When software trigger is selected, the transfer from the DAC_DHR register to the DAC_DOR register takes only one APB0 clock cycle..

TSEL

Bits 3-5: TSEL[2:0]: DAC channel trigger selection These bits select the external event used to trigger DAC channel. 000: Timer 16 TRGO event 001: PA8 pin event from SYSCFG 010 to 011: Reserved 111: Software trigger Only used if bit TEN = 1 (DAC channel trigger enabled)..

WAVE

Bits 6-7: WAVE[1:0]: DAC channel noise/triangle wave generation enable These bits are set and cleared by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN = 1 (DAC channel trigger enabled)..

MAMP

Bits 8-11: MAMP[3:0]: DAC channel mask amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR triangle amplitude equal to 31 greater than or equal to 0101: Unmask bits[5:0] of LFSR triangle amplitude equal to 63.

DMAEN

Bit 12: DMAEN: DAC channel DMA enable This bit is set and cleared by software. 0: DAC channel DMA mode disabled 1: DAC channel DMA mode enabled.

DMAUDRIE

Bit 13: DMAUDRIE: DAC channel DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel DMA Underrun Interrupt disabled 1: DAC channel DMA Underrun Interrupt enabled.

CMPEN

Bit 14: CMPEN: DAC channel output to COMP INMINUS enable. This bit is set and cleared by software. 0: DAC channel output to COMP INMINUS disabled 1: DAC channel output to COMP INMINUS enabled.

VCMEN

Bit 15: VCMEN: DAC channel output to VCM BUFFER enable. This bit is set and cleared by software. 0: DAC channel output to VCM BUFFER disabled 1: DAC channel output to VCM BUFFER enabled.

VCMON

Bit 16: VCMON: VCMBUFF power-up. This bit is set and cleared by software. 0: VCM BUFFER OFF 1: VCM BUFFER ON.

SWTRIGR

SWTRIGR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															SWTRIG w

Toggle fields

SWTRIG

Bit 0: SWTRIG: DAC channel software trigger This bit is set by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB0 clock cycle later) once the DAC_DHR register value has been loaded into the DAC_DOR register..

DHR

DHR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DACDHR rw

Toggle fields

DACDHR

Bits 0-5: DACDHR[5:0]: DAC channel 6-bit data These bits are written by software which specifies 6-bit data for DAC channel..

DOR

DOR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DACDOR r

Toggle fields

DACDOR

Bits 0-5: DACDOR[5:0]: DAC channel data output These bits are read-only, they contain data output for DAC channel..

SR

SR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		DMAUDR rw

Toggle fields

DMAUDR

Bit 13: DMAUDR: DAC channel DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel 1: DMA underrun error condition occurred for DAC channel (the currently selected trigger is driving DAC channel conversion at a frequency higher than the DMA service capability rate).

DBGMCU

0x40008000:

0/8 fields covered.

Toggle register map

Offset	Name	23	21	14	12	1	0
0x0	CR					DBG_STOP	DBG_SLEEP
0x4	DBG_APB0_FZ			DBG_IWDG_STOP	DBG_RTC_STOP	DBG_TIM16_STOP	DBG_TIM2_STOP
0x8	DBG_APB1_FZ	DBG_I2C2_STOP	DBG_I2C1_STOP

Toggle registers

CR

CR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DBG_STOP rw	DBG_SLEEP rw

Toggle fields

DBG_SLEEP

Bit 0: Allow debug of the CPU in SLEEP mode - 0: Normal operation. All clocks will be disabled automatically in SLEEP mode - 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during SLEEP mode, allowing full CPU debug capability. On exit from SLEEP mode, the clock settings will be set to the SLEEP mode exit state..

DBG_STOP

Bit 1: Allow debug of the CPU in DEEPSTOP mode - 0: Normal operation. All clocks will be disabled automatically in STOP mode - 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during STOP mode, allowing full CPU debug capability. On exit from STOP mode, the clock settings will be set to the STOP mode exit state..

DBG_APB0_FZ

DBG_APB0_FZ register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DBG_IWDG_STOP rw		DBG_RTC_STOP rw											DBG_TIM16_STOP rw	DBG_TIM2_STOP rw

Toggle fields

DBG_TIM2_STOP

Bit 0: TIM2 stop in the CPU debug - 0: Normal operation. TIM2 continues to operate while the CPU is in debug mode - 1: Stop in debug. TIM2 is frozen while the CPU is in debug mode..

DBG_TIM16_STOP

Bit 1: TIM16 stop in the CPU debug - 0: Normal operation. TIM16 continues to operate while the CPU is in debug mode - 1: Stop in debug. TIM16 is frozen while the CPU is in debug mode..

DBG_RTC_STOP

Bit 12: RTC stop in CPU debug - 0: Normal operation. RTC continues to operate while the CPU is in debug mode - 1: Stop in debug. RTC is frozen while the CPU is in debug mode..

DBG_IWDG_STOP

Bit 14: IWDG stop in the CPU debug - 0: Normal operation. IWDG continues to operate while the CPU is in debug mode - 1: Stop in debug. IWDG is frozen while the CPU is in debug mode..

DBG_APB1_FZ

DBG_APB1_FZ register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								DBG_I2C2_STOP rw		DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout stop in CPU debug - 0: Normal operation. I2C1 SMBUS timeout continues to operate while the CPU is in debug mode - 1: Stop in debug. I2C1 SMBUS timeou is frozen while the CPU is in debug mode..

DBG_I2C2_STOP

Bit 23: I2C2 SMBUS timeout stop in CPU debug - 0: Normal operation. I2C2 SMBUS timeout continues to operate while the CPU is in debug mode - 1: Stop in debug. I2C2 SMBUS timeou is frozen while the CPU is in debug mode..

DMA

0x48700000: DMA address block description

32/184 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR	TE1F8	HTIF8	TCIF8	GIF8	TE1F7	HTIF7	TCIF7	GIF7	TE1F6	HTIF6	TCIF6	GIF6	TE1F5	HTIF5	TCIF5	GIF5	TE1F4	HTIF4	TCIF4	GIF4	TE1F3	HTIF3	TCIF3	GIF3	TE1F2	HTIF2	TCIF2	GIF2	TE1F1	HTIF1	TCIF1	GIF1
0x4	IFCR	CTEIF8	CHTIF8	CTCIF8	CGIF8	CTEIF7	CHTIF7	CTCIF7	CGIF7	CTEIF6	CHTIF6	CTCIF6	CGIF6	CTEIF5	CHTIF5	CTCIF5	CGIF5	CTEIF4	CHTIF4	CTCIF4	CGIF4	CTEIF3	CHTIF3	CTCIF3	CGIF3	CTEIF2	CHTIF2	CTCIF2	CGIF2	CTEIF1	CHTIF1	CTCIF1	CGIF1
0x8	CCR1																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	CNDTR1																	NDT
0x10	CPAR1	PA																PA
0x14	CMAR1	MA																MA
0x1c	CCR2																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	CNDTR2																	NDT
0x24	CPAR2	PA																PA
0x28	CMAR2	MA																MA
0x30	CCR3																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	CNDTR3																	NDT
0x38	CPAR3	PA																PA
0x3c	CMAR3	MA																MA
0x44	CCR4																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	CNDTR4																	NDT
0x4c	CPAR4	PA																PA
0x50	CMAR4	MA																MA
0x58	CCR5																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	CNDTR5																	NDT
0x60	CPAR5	PA																PA
0x64	CMAR5	MA																MA
0x6c	CCR6																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	CNDTR6																	NDT
0x74	CPAR6	PA																PA
0x78	CMAR6	MA																MA
0x80	CCR7																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	CNDTR7																	NDT
0x88	CPAR7	PA																PA
0x8c	CMAR7	MA																MA
0x94	CCR8																		MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x98	CNDTR8																	NDT
0x9c	CPAR8	PA																PA
0xa0	CMAR8	MA																MA

Toggle registers

ISR

DMA_ISR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TE1F8 r	HTIF8 r	TCIF8 r	GIF8 r	TE1F7 r	HTIF7 r	TCIF7 r	GIF7 r	TE1F6 r	HTIF6 r	TCIF6 r	GIF6 r	TE1F5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TE1F4 r	HTIF4 r	TCIF4 r	GIF4 r	TE1F3 r	HTIF3 r	TCIF3 r	GIF3 r	TE1F2 r	HTIF2 r	TCIF2 r	GIF2 r	TE1F1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle fields

GIF1

Bit 0: GIF1: Channel 1 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 1 1: A TE, HT or TC event occurred on channel 1.

TCIF1

Bit 1: TCIF1: Channel 1 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 1 1: A transfer complete (TC) event occurred on channel 1.

HTIF1

Bit 2: HTIF1: Channel 1 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 1 1: A half transfer (HT) event occurred on channel 1.

TE1F1

Bit 3: TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 1 1: A transfer error (TE) occurred on channel 1.

GIF2

Bit 4: GIF2: Channel 2 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 2 1: A TE, HT or TC event occurred on channel 2.

TCIF2

Bit 5: TCIF2: Channel 2 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 2 1: A transfer complete (TC) event occurred on channel 2.

HTIF2

Bit 6: HTIF2: Channel 2 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 2 1: A half transfer (HT) event occurred on channel 2.

TE1F2

Bit 7: TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 2 1: A transfer error (TE) occurred on channel 2.

GIF3

Bit 8: GIF3: Channel 3 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 3 1: A TE, HT or TC event occurred on channel 3.

TCIF3

Bit 9: TCIF3: Channel 3 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 3 1: A transfer complete (TC) event occurred on channel 3.

HTIF3

Bit 10: HTIF3: Channel 3 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 3 1: A half transfer (HT) event occurred on channel 3.

TE1F3

Bit 11: TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 3 1: A transfer error (TE) occurred on channel 3.

GIF4

Bit 12: GIF4: Channel 4 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 4 1: A TE, HT or TC event occurred on channel 4.

TCIF4

Bit 13: TCIF4: Channel 4 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 4 1: A transfer complete (TC) event occurred on channel 4.

HTIF4

Bit 14: HTIF4: Channel 4 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 4 1: A half transfer (HT) event occurred on channel 4.

TE1F4

Bit 15: TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 4 1: A transfer error (TE) occurred on channel 4.

GIF5

Bit 16: GIF5: Channel 5 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 5 1: A TE, HT or TC event occurred on channel 5.

TCIF5

Bit 17: TCIF5: Channel 5 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 5 1: A transfer complete (TC) event occurred on channel 5.

HTIF5

Bit 18: HTIF5: Channel 5 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 5 1: A half transfer (HT) event occurred on channel 5.

TE1F5

Bit 19: TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 5 1: A transfer error (TE) occurred on channel 5.

GIF6

Bit 20: GIF6: Channel 6 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 6 1: A TE, HT or TC event occurred on channel 6.

TCIF6

Bit 21: TCIF6: Channel 6 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 6 1: A transfer complete (TC) event occurred on channel 6.

HTIF6

Bit 22: HTIF6: Channel 6 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 6 1: A half transfer (HT) event occurred on channel 6.

TE1F6

Bit 23: TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 6 1: A transfer error (TE) occurred on channel 6.

GIF7

Bit 24: GIF7: Channel 7 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 7 1: A TE, HT or TC event occurred on channel 7.

TCIF7

Bit 25: TCIF7: Channel 7 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 7 1: A transfer complete (TC) event occurred on channel 7.

HTIF7

Bit 26: HTIF7: Channel 7 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 7 1: A half transfer (HT) event occurred on channel 7.

TE1F7

Bit 27: TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 7 1: A transfer error (TE) occurred on channel 7.

GIF8

Bit 28: GIF8: Channel 8 global interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel 8 1: A TE, HT or TC event occurred on channel 8.

TCIF8

Bit 29: TCIF8: Channel 8 transfer complete flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel 8 1: A transfer complete (TC) event occurred on channel 8.

HTIF8

Bit 30: HTIF8: Channel 8 half transfer flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel 8 1: A half transfer (HT) event occurred on channel 8.

TE1F8

Bit 31: TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel 8 1: A transfer error (TE) occurred on channel 8.

IFCR

DMA_IFCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTEIF8 w	CHTIF8 w	CTCIF8 w	CGIF8 w	CTEIF7 w	CHTIF7 w	CTCIF7 w	CGIF7 w	CTEIF6 w	CHTIF6 w	CTCIF6 w	CGIF6 w	CTEIF5 w	CHTIF5 w	CTCIF5 w	CGIF5 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF4 w	CTCIF4 w	CGIF4 w	CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle fields

CGIF1

Bit 0: CGIF1: Channel 1 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF1

Bit 1: CTCIF1: Channel 1 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF1

Bit 2: CHTIF1: Channel 1 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF1

Bit 3: CTEIF1: Channel 1 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF2

Bit 4: CGIF2: Channel 2 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF2

Bit 5: CTCIF2: Channel 2 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF2

Bit 6: CHTIF2: Channel 2 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF2

Bit 7: CTEIF2: Channel 2 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF3

Bit 8: CGIF3: Channel 3 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF3

Bit 9: CTCIF3: Channel 3 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF3

Bit 10: CHTIF3: Channel 3 half transfer clear This bit is set and cleared by software. 0: No effect. 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF3

Bit 11: CTEIF3: Channel 3 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF4

Bit 12: CGIF4: Channel 4 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF4

Bit 13: CTCIF4: Channel 4 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF4

Bit 14: CHTIF4: Channel 4 half transfer clear This bit is set and cleared by software. 0: No effect. 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF4

Bit 15: CTEIF4: Channel 4 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF5

Bit 16: CGIF5: Channel 5 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF5

Bit 17: CTCIF5: Channel 5 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF5

Bit 18: CHTIF5: Channel 5 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF5

Bit 19: CTEIF5: Channel 5 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF6

Bit 20: CGIF6: Channel 6 global interrupt clear This bit is set and cleared by software. 0: No effect. 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF6

Bit 21: CTCIF6: Channel 6 transfer complete clear This bit is set and cleared by software. 0: No effect. 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF6

Bit 22: CHTIF6: Channel 6 half transfer clear This bit is set and cleared by software. 0: No effect. 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF6

Bit 23: CTEIF6: Channel 6 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF7

Bit 24: CGIF7: Channel 7 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF7

Bit 25: CTCIF7: Channel 7 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF7

Bit 26: CHTIF7: Channel 7 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF7

Bit 27: CTEIF7: Channel 7 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CGIF8

Bit 28: CGIF8: Channel 8 global interrupt clear This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register.

CTCIF8

Bit 29: CTCIF8: Channel 8 transfer complete clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register.

CHTIF8

Bit 30: CHTIF8: Channel 8 half transfer clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register.

CTEIF8

Bit 31: CTEIF8: Channel 8 transfer error clear This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register.

CCR1

DMA_CCRx register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR1

DMA_CNDTRx register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR1

DMA_CPARx register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR1

DMA_CMARx register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR2

DMA_CCRx register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR2

DMA_CNDTRx register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR2

DMA_CPARx register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR2

DMA_CMARx register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR3

DMA_CCRx register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR3

DMA_CNDTRx register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR3

DMA_CPARx register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR3

DMA_CMARx register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR4

DMA_CCRx register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR4

DMA_CNDTRx register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR4

DMA_CPARx register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR4

DMA_CMARx register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR5

DMA_CCRx register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR5

DMA_CNDTRx register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR5

DMA_CPARx register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR5

DMA_CMARx register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR6

DMA_CCRx register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR6

DMA_CNDTRx register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR6

DMA_CPARx register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR6

DMA_CMARx register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR7

DMA_CCRx register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR7

DMA_CNDTRx register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR7

DMA_CPARx register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR7

DMA_CMARx register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

CCR8

DMA_CCRx register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled.

TCIE

Bit 1: TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled.

HTIE

Bit 2: HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled.

TEIE

Bit 3: TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled.

DIR

Bit 4: DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral. 1: Read from memory.

CIRC

Bit 5: CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled.

PINC

Bit 6: PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled.

MINC

Bit 7: MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled.

PSIZE

Bits 8-9: PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

MSIZE

Bits 10-11: MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits.

PL

Bits 12-13: PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high.

MEM2MEM

Bit 14: MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled.

CNDTR8

DMA_CNDTRx register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

CPAR8

DMA_CPARx register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

CMAR8

DMA_CMARx register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

DMAMUX

0x48800000: DMAMUX address block description

0/8 fields covered.

Toggle register map

Offset	Name	4
0x0	C0CR	DMAREQ_ID
0x4	C1CR	DMAREQ_ID
0x8	C2CR	DMAREQ_ID
0xc	C3CR	DMAREQ_ID
0x10	C4CR	DMAREQ_ID
0x14	C5CR	DMAREQ_ID
0x18	C6CR	DMAREQ_ID
0x1c	C7CR	DMAREQ_ID

Toggle registers

C0CR

CxCR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C1CR

CxCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C2CR

CxCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C3CR

CxCR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C4CR

CxCR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C5CR

CxCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C6CR

CxCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

C7CR

CxCR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-4: DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources..

DYNAMIC_REG

0x49000500:

1/60 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	9	8	7	4	3	2	1	0
0x0	PCKTLEN_CONFIG																	PCKTLEN
0x4	MOD0_CONFIG	PA_CLKON_LOCKONTX					BT_SEL	CONST_MAP			MOD_TYPE			DATARATE_E				DATARATE_M
0x8	MOD1_CONFIG									CHFLT_E				CHFLT_M								FDEV_E			FDEV_M
0xc	SNYTH_FREQ		BS			SYNTH_INT								SYNTH_FRAC				SYNTH_FRAC
0x10	VCO_CAL_CONFIG	VCO_CALIB_REQ								VCO_CALFREQ_EXT_SEL	VCO_CALFREQ_EXT							VCO_CALAMP_EXT_SEL		VCO_CALAMP_EXT
0x14	RX_TIMER	RX_OR_nAND_SELECT	RX_SQI_TIMEOUT_MASK	RX_PQI_TIMEOUT_MASK	RX_CS_TIMEOUT_MASK						RX_TIMEOUT							RX_TIMEOUT
0x18	DATABUFFER_THR	TX_ALMOST_EMPTY_THR																RX_ALMOST_FULL_THR
0x1c	RFSEQ_IRQ_ENABLE	AGC_CALIB_DONE_E	SAFEASK_CALIB_DONE_E		RRM_CMD_END_E	RRM_CMD_START_E	SEQ_E		HW_ANA_FAILURE_E		AHB_ACCESS_ERROR_E	TX_ALMOST_EMPTY_1_E	TX_ALMOST_EMPTY_0_E	RX_ALMOST_FULL_1_E	RX_ALMOST_FULL_0_E	DATABUFFER1_USED_E	DATABUFFER0_USED_E		SYNC_VALID_E	PREAMBLE_VALID_E	CS_E		COMMAND_REJECTED_E	SABORT_DONE_E	RXTIMER_STOP_CDT_E	FAST_RX_TERM_E	RX_CRC_ERROR_E	RX_TIMEOUT_E	RX_OK_E	TX_DONE_E
0x20	ADDITIONAL_CTRL	AS_ENABLE									TIME_CAPTURESEL					PA_FC		CH_SPACING							CH_NUM
0x24	FAST_RX_TIMER																							FAST_CS_TERM_EN	FAST_RX_TIMEOUT
0x28	COMMAND						BACK2LOCKON	BACK2ACTIVE																			COMMAND_ID

Toggle registers

PCKTLEN_CONFIG

PCKTLEN_CONFIG register

Offset: 0x0, size: 32, reset: 0x00000014, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCKTLEN rw

Toggle fields

PCKTLEN

Bits 0-15: This bit field has different meanings/usages:.

MOD0_CONFIG

MOD0_CONFIG register

Offset: 0x4, size: 32, reset: 0x00083A93, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA_CLKON_LOCKONTX rw					BT_SEL rw	CONST_MAP rw			MOD_TYPE rw			DATARATE_E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATARATE_M rw

Toggle fields

DATARATE_M

Bits 0-15: The mantissa of the specified data rate (default: 38..

DATARATE_E

Bits 16-19: The exponent of the specified data rate (default: 38..

MOD_TYPE

Bits 20-22: Select the modulation type.

CONST_MAP

Bits 24-25: Also known as FOUR_GFSK_CONST_MAP.

BT_SEL

Bit 26: Select BT value for GFSK.

PA_CLKON_LOCKONTX

Bit 31: Enable the clock on analog PA in LOCKONTX state.

MOD1_CONFIG

MOD1_CONFIG register

Offset: 0x8, size: 32, reset: 0x00400435, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CHFLT_E rw				CHFLT_M rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				FDEV_E rw				FDEV_M rw

Toggle fields

FDEV_M

Bits 0-7: Mantissa of the frequency deviation (default: 28..

FDEV_E

Bits 8-11: Exponent of the frequency deviation (default: 28..

CHFLT_M

Bits 16-19: Mantissa of the channel filter BW (default: 100 kHz).

CHFLT_E

Bits 20-23: Exponent of the channel filter BW (default: 100 kHz).

SNYTH_FREQ

SNYTH_FREQ register

Offset: 0xc, size: 32, reset: 0x04851615, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	BS rw			SYNTH_INT rw								SYNTH_FRAC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SYNTH_FRAC rw

Toggle fields

SYNTH_FRAC

Bits 0-19: Fractional part of the PLL fractional divide factor (default: 868 MHz, XTAL: 48 MHz).

SYNTH_INT

Bits 20-27: PLL integer divide factor (default: 868 MHz, XTAL: 48 MHz).

BS

Bit 30: Synthesizer band selector, i..

VCO_CAL_CONFIG

VCO_CAL_CONFIG register

Offset: 0x10, size: 32, reset: 0x00400088, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VCO_CALIB_REQ rw								VCO_CALFREQ_EXT_SEL rw	VCO_CALFREQ_EXT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VCO_CALAMP_EXT_SEL rw		VCO_CALAMP_EXT rw

Toggle fields

VCO_CALAMP_EXT

Bits 0-13: VCO magnitude calibration word in thermometric code.

VCO_CALAMP_EXT_SEL

Bit 15: Select the mode to provide an external VCO amplitude calibration value through VCO_CALAMP_EXT bit field.

VCO_CALFREQ_EXT

Bits 16-22: VCO Cbank frequency calibration word..

VCO_CALFREQ_EXT_SEL

Bit 23: Select the mode to provide an external VCO frequency calibration value through VCO_CALFREQ_EXT bit field.

VCO_CALIB_REQ

Bit 31: Define if the Radio FSM must launch a VCO calibration request after VCO start-up.

RX_TIMER

RX_TIMER register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RX_OR_nAND_SELECT rw	RX_SQI_TIMEOUT_MASK rw	RX_PQI_TIMEOUT_MASK rw	RX_CS_TIMEOUT_MASK rw						RX_TIMEOUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_TIMEOUT rw

Toggle fields

RX_TIMEOUT

Bits 0-22: RX timer timeout (relative duration in interpolated absolute time unit).

RX_CS_TIMEOUT_MASK

Bit 28: - 0: CS flag does not contribute to timeout disabling.

RX_PQI_TIMEOUT_MASK

Bit 29: - 0: PREAMBLE valid flag does not contribute to timeout disabling.

RX_SQI_TIMEOUT_MASK

Bit 30: - 0: SYNC valid flag does not contribute to timeout disabling.

RX_OR_nAND_SELECT

Bit 31: Select logical OR or logcial AND to apply on CS/PQI/SQI timeout mask.

DATABUFFER_THR

DATABUFFER_THR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TX_ALMOST_EMPTY_THR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_ALMOST_FULL_THR rw

Toggle fields

RX_ALMOST_FULL_THR

Bits 0-15: Almost Full threshold for RX Data Buffers.

TX_ALMOST_EMPTY_THR

Bits 16-31: Almost Empty threshold for TX Data Buffers..

RFSEQ_IRQ_ENABLE

RFSEQ_IRQ_ENABLE register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AGC_CALIB_DONE_E rw	SAFEASK_CALIB_DONE_E rw		RRM_CMD_END_E rw	RRM_CMD_START_E rw	SEQ_E rw		HW_ANA_FAILURE_E rw		AHB_ACCESS_ERROR_E rw	TX_ALMOST_EMPTY_1_E rw	TX_ALMOST_EMPTY_0_E rw	RX_ALMOST_FULL_1_E rw	RX_ALMOST_FULL_0_E rw	DATABUFFER1_USED_E rw	DATABUFFER0_USED_E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SYNC_VALID_E rw	PREAMBLE_VALID_E rw	CS_E rw			COMMAND_REJECTED_E rw	SABORT_DONE_E rw	RXTIMER_STOP_CDT_E rw			FAST_RX_TERM_E rw	RX_CRC_ERROR_E rw	RX_TIMEOUT_E rw	RX_OK_E rw	TX_DONE_E rw

Toggle fields

TX_DONE_E

Bit 0: Enable interrupt on TX_DONE_F flag.

RX_OK_E

Bit 1: Enable interrupt on RX_OK_F flag.

RX_TIMEOUT_E

Bit 2: Enable interrupt on RX_TIMEOUT_F flag.

RX_CRC_ERROR_E

Bit 3: Enable interrupt on RX_CRC_ERROR_F flag.

FAST_RX_TERM_E

Bit 4: Enable interrupt on FAST_RX_TERM_F flag.

RXTIMER_STOP_CDT_E

Bit 7: Enable interrupt on RXTIMER_STOP_CDT_F flag.

SABORT_DONE_E

Bit 8: Enable interrupt on SABORT command treated and done flag.

COMMAND_REJECTED_E

Bit 9: Enable interrupt on COMMAND_REJECTED flag.

CS_E

Bit 12: Enable interrupt on CS_F flag.

PREAMBLE_VALID_E

Bit 13: Enable interrupt on PREAMBLE_VALID_F flag.

SYNC_VALID_E

Bit 14: Enable interrupt on SYNC_VALID_F flag.

DATABUFFER0_USED_E

Bit 16: Enable interrupt on DATABUFFER0_USED_F flag.

DATABUFFER1_USED_E

Bit 17: Enable interrupt on DATABUFFER1_USED_F flag.

RX_ALMOST_FULL_0_E

Bit 18: Enable interrupt on RX_ALMOST_FULL_0_F flag.

RX_ALMOST_FULL_1_E

Bit 19: Enable interrupt on RX_ALMOST_FULL_1_F flag.

TX_ALMOST_EMPTY_0_E

Bit 20: Enable interrupt on TX_ALMOST_EMPTY_0_F flag.

TX_ALMOST_EMPTY_1_E

Bit 21: Enable interrupt on TX_ALMOST_EMPTY_1_F flag.

AHB_ACCESS_ERROR_E

Bit 22: Enable interrupt on AHB_ACCESS_ERROR_F flag.

HW_ANA_FAILURE_E

Bit 24: Enable interrupt on HW_ANA_FAILURE_F flag.

SEQ_E

Bit 26: Enable interrupt on SEQ_F flag.

RRM_CMD_START_E

Bit 27: Enable interrupt on RRM_CMD_END_F flag.

RRM_CMD_END_E

Bit 28: Enable interrupt on RRM_CMD_END_F flag.

SAFEASK_CALIB_DONE_E

Bit 30: Enable interrupt on SAFEASK_CALIB_DONE_F flag.

AGC_CALIB_DONE_E

Bit 31: Enable interrupt on AGC_CALIB_DONE_F flag.

ADDITIONAL_CTRL

ADDITIONAL_CTRL register

Offset: 0x20, size: 32, reset: 0x00038800, access: read-write

1/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AS_ENABLE rw									TIME_CAPTURESEL rw					PA_FC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CH_SPACING r								CH_NUM rw

Toggle fields

CH_NUM

Bits 0-7: Channel number..

CH_SPACING

Bits 8-15: Channel spacing..

PA_FC

Bits 16-17: Power control bandwidth selection according data rate.

TIME_CAPTURESEL

Bits 20-22: Select the trigger event to capture the interpolated absolute time in the TIME_CAPTURE[31:0] register.

AS_ENABLE

Bit 31: Enable the antenna switching feature..

FAST_RX_TIMER

FAST_RX_TIMER register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FAST_CS_TERM_EN rw	FAST_RX_TIMEOUT rw

Toggle fields

FAST_RX_TIMEOUT

Bits 0-7: Fast RX termination timer value (corresponding to the delay to measure the RSSI and to let the HW check CS flag information).

FAST_CS_TERM_EN

Bit 8: Enable the Fast RX Termination feature.

COMMAND

COMMAND register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					BACK2LOCKON rw	BACK2ACTIVE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												COMMAND_ID rw

Toggle fields

COMMAND_ID

Bits 0-3: Opcode coresponding to a command:.

BACK2ACTIVE

Bit 25: Select the default/return state for the Radio FSM to be ACTIVE2.

BACK2LOCKON

Bit 26: Request to the Radio FSM to stay in LOCKON state when exiting a RX or a TX.

FLASH_CTRL

0x40001000: 4kb addressable space

6/45 fields covered.

Toggle register map

Offset	Name	31	30	22	20	19	17	16	15	14	7	6	5	4	3	2	1	0
0x0	COMMAND										COMMAND
0x4	CONFIG											SLEEP_SM	WAIT_STATE			DIS_GROUP_WRITE	REMAP
0x8	IRQSTAT												FNREADY_MIS	READOK_MIS	ILLCMD_MIS	CMDBUSYERR_MIS	CMDSTART_MIS	CMDDONE_MIS
0xc	IRQMASK												FNREADYM	READOKM	ILLCMDM	CMDBUSYERRM	CMDSTARTM	CMDDONEM
0x10	IRQRAW												CMDSLEEPERR_RIS	READOK_RIS	ILLCMD_RIS	CMDBUSYERR_RIS	CMDSTART_RIS	CMDDONE_RIS
0x14	SIZE			PACKAGE_SIZE	JTAG_DISABLE	FLASH_SECURE	RAM_SIZE	FLASH_SIZE	FLASH_SIZE
0x18	ADDRESS								XADDR				YADDR
0x24	LFSRVAL	LFSRVAL							LFSRVAL
0x34	PAGEPROT0		SEGOFFSET1	SEGSIZE1						SEGOFFSET0		SEGSIZE0
0x38	PAGEPROT1		SEGOFFSET3	SEGSIZE3						SEGOFFSET2		SEGSIZE2
0x40	DATA0	DATA0							DATA0
0x44	DATA1	DATA1							DATA1
0x48	DATA2	DATA2							DATA2
0x4c	DATA3	DATA3							DATA3
0x50	UNLOCK012	UNLOCK012							UNLOCK012
0x54	UNLOCK3	UNLOCK3							UNLOCK3

Toggle registers

COMMAND

COMMAND register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								COMMAND rw

Toggle fields

COMMAND

Bits 0-7: Macro commands for flash operations (may require DATA0...DATA3 to be set): - 0x11 : ERASE - 0x22 : MASSERASE - 0x33 : WRITE - 0x55 : MASSREAD - 0xAA : SLEEP - 0xBB : WAKEUP - 0xCC : BURSTWRITE - 0xEE : OTPWRITE - 0xFF : KEYWRITE.

CONFIG

CONFIG register

Offset: 0x4, size: 32, reset: 0x00000010, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SLEEP_SM rw	WAIT_STATE rw			DIS_GROUP_WRITE rw	REMAP rw

Toggle fields

REMAP

Bit 1: CPU access routing (it supersedes PREMAP configuration): - 0 : FLASH memory addressed - 1 : SRAM0 memory addressed.

DIS_GROUP_WRITE

Bit 2: Burst write Control: - 0 : burst write allowed - 1 : burst write forbidden.

WAIT_STATE

Bits 4-5: Add latency to flash read opeations: - 00 : no latency - 01 : 1 clock cycle latency - 10 : 2 clock cycles latency - 11 : 3 clock cycles latency.

SLEEP_SM

Bit 6: Flash memory power-down mode enable in SLEEP mode This bit allows to have the Flash memory in power-down mode or in idle mode when the device is in Sleep mode. - 0: When the device is in Sleep mode, the NVM is in Idle mode. - 1: When the device is in Sleep mode, the NVM is in power-down mode..

IRQSTAT

IRQSTAT register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FNREADY_MIS rw	READOK_MIS rw	ILLCMD_MIS rw	CMDBUSYERR_MIS rw	CMDSTART_MIS rw	CMDDONE_MIS rw

Toggle fields

CMDDONE_MIS

Bit 0: (1: clear, 0: inactive) CMDDONE_MIS flag.

CMDSTART_MIS

Bit 1: (1: clear, 0: inactive) CMDSTART_MIS flag.

CMDBUSYERR_MIS

Bit 2: (1: clear, 0: inactive) CMDBUSYERR_MIS flag.

ILLCMD_MIS

Bit 3: (1: clear, 0: inactive) ILLCMD_MIS flag.

READOK_MIS

Bit 4: (1: clear, 0: inactive) READOK_MIS flag.

FNREADY_MIS

Bit 5: (1: clear, 0: inactive) FNREADY_MIS flag.

IRQMASK

IRQMASK register

Offset: 0xc, size: 32, reset: 0x0000003F, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FNREADYM rw	READOKM rw	ILLCMDM rw	CMDBUSYERRM rw	CMDSTARTM rw	CMDDONEM rw

Toggle fields

CMDDONEM

Bit 0: (1: mask, 0: inactive) CMDDONE_MIS mask.

CMDSTARTM

Bit 1: (1: mask, 0: inactive) CMDSTART_MIS mask.

CMDBUSYERRM

Bit 2: (1: mask, 0: inactive) CMDBUSYERR_MIS mask.

ILLCMDM

Bit 3: (1: mask, 0: inactive) ILLCMD_MIS mask.

READOKM

Bit 4: (1: mask, 0: inactive) READOK_MIS mask.

FNREADYM

Bit 5: (1: mask, 0: inactive) FNREADY_MIS mask.

IRQRAW

IRQRAW register

Offset: 0x10, size: 32, reset: 0x00000001, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CMDSLEEPERR_RIS rw	READOK_RIS rw	ILLCMD_RIS rw	CMDBUSYERR_RIS rw	CMDSTART_RIS rw	CMDDONE_RIS rw

Toggle fields

CMDDONE_RIS

Bit 0: (1: active, 0: inactive) COMMAND sequence ended.

CMDSTART_RIS

Bit 1: (1: active, 0: inactive) COMMAND sequence started.

CMDBUSYERR_RIS

Bit 2: (1: active, 0: inactive) COMMAND issued while flash busy.

ILLCMD_RIS

Bit 3: (1: active, 0: inactive) Illegal command issued.

READOK_RIS

Bit 4: (1: active, 0: inactive) READ COMMAND completed successfully.

CMDSLEEPERR_RIS

Bit 5: (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1).

SIZE

SIZE register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PACKAGE_SIZE r		JTAG_DISABLE r	FLASH_SECURE r		RAM_SIZE r	FLASH_SIZE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLASH_SIZE r

Toggle fields

FLASH_SIZE

Bits 0-16: Maximum valid address for flash memory: - 00 : 0x03FFF (64kb) - 01 : 0x07FFF (128kb) - 10 : 0x0BFFF (192kb) - 11 : 0x0FFFF (256kb).

RAM_SIZE

Bit 17: RAM memory size selection: - 0 : 16kb - 1 : 32kb.

FLASH_SECURE

Bit 19: Flash memory protection (0: no key present, 1: key present).

JTAG_DISABLE

Bit 20: Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE, 1: Flash and JTAG protected).

PACKAGE_SIZE

Bits 21-22: Package selection: - 0- : CSP - 10 : 32pins - 11 : 48pins.

ADDRESS

ADDRESS register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XADDR rw										YADDR rw

Toggle fields

YADDR

Bits 0-5: Flash column address offset to be used with some COMMAND.

XADDR

Bits 6-15: Flash row address offset to be used with some COMMAND.

LFSRVAL

LFSRVAL register

Offset: 0x24, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LFSRVAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LFSRVAL r

Toggle fields

LFSRVAL

Bits 0-31: Flash read data CRC signature.

PAGEPROT0

PAGEPROT0 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SEGOFFSET1 rw								SEGSIZE1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SEGOFFSET0 rw								SEGSIZE0 rw

Toggle fields

SEGSIZE0

Bits 0-6: First segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET0

Bits 8-14: First segment, 7-bit page protection offset (first page number in protected segment).

SEGSIZE1

Bits 16-22: Second segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET1

Bits 24-30: Second segment, 7-bit page protection offset (first page number in protected segment).

PAGEPROT1

PAGEPROT1 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SEGOFFSET3 rw								SEGSIZE3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SEGOFFSET2 rw								SEGSIZE2 rw

Toggle fields

SEGSIZE2

Bits 0-6: Third segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET2

Bits 8-14: Third segment, 7-bit page protection offset (first page number in protected segment).

SEGSIZE3

Bits 16-22: Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included).

SEGOFFSET3

Bits 24-30: Fourth segment, 7-bit page protection offset (first page number in protected segment).

DATA0

DATA0 register

Offset: 0x40, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA0 rw

Toggle fields

DATA0

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD.

DATA1

DATA1 register

Offset: 0x44, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA1 rw

Toggle fields

DATA1

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

DATA2

DATA2 register

Offset: 0x48, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA2 rw

Toggle fields

DATA2

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

DATA3

DATA3 register

Offset: 0x4c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA3 rw

Toggle fields

DATA3

Bits 0-31: Value to be used as DATA for any COMMAND of type WRITE.

UNLOCK012

UNLOCK012 register

Offset: 0x50, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UNLOCK012 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UNLOCK012 rw

Toggle fields

UNLOCK012

Bits 0-31: (NOT TO BE DOCUMENTED) Remove read-write protection from IFR0, IFR1, IFR2 sectors.

UNLOCK3

UNLOCK3 register

Offset: 0x54, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UNLOCK3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UNLOCK3 rw

Toggle fields

UNLOCK3

Bits 0-31: (NOT TO BE DOCUMENTED) Remove read-write protection from IFR3 sector.

GPIOA

0x48000000:

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

MODER register

Offset: 0x0, size: 32, reset: 0x000000A0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE1

Bits 2-3: MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE2

Bits 4-5: MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE3

Bits 6-7: MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE4

Bits 8-9: MODE4[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE5

Bits 10-11: MODE5[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE6

Bits 12-13: MODE6[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE7

Bits 14-15: MODE7[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE8

Bits 16-17: MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE9

Bits 18-19: MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE10

Bits 20-21: MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE11

Bits 22-23: MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE12

Bits 24-25: MODE12[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE13

Bits 26-27: MODE13[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE14

Bits 28-29: MODE14[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE15

Bits 30-31: MODE15[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

OTYPER

OTYPER register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: OT0: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT1

Bit 1: OT1: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT2

Bit 2: OT2: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT3

Bit 3: OT3: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT4

Bit 4: OT4: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT5

Bit 5: OT5: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT6

Bit 6: OT6: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT7

Bit 7: OT7: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT8

Bit 8: OT8: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT9

Bit 9: OT9: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT10

Bit 10: OT10: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT11

Bit 11: OT11: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT12

Bit 12: OT12: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT13

Bit 13: OT13: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT14

Bit 14: OT14: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT15

Bit 15: OT15: Port A configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OSPEEDR

OSPEEDR register

Offset: 0x8, size: 32, reset: 0x00000030, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: OSPEED0[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED1

Bits 2-3: OSPEED1[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED2

Bits 4-5: OSPEED2[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED3

Bits 6-7: OSPEED3[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED4

Bits 8-9: OSPEED4[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED5

Bits 10-11: OSPEED5[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED6

Bits 12-13: OSPEED6[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED7

Bits 14-15: OSPEED7[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED8

Bits 16-17: OSPEED8[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED9

Bits 18-19: OSPEED9[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED10

Bits 20-21: OSPEED10[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED11

Bits 22-23: OSPEED11[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED12

Bits 24-25: OSPEED12[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED13

Bits 26-27: OSPEED13[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED14

Bits 28-29: OSPEED14[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

OSPEED15

Bits 30-31: OSPEED15[1:0]: Port A configuration bits These bits are written by software to configure the I/O output speed..

PUPDR

PUPDR register

Offset: 0xc, size: 32, reset: 0x55555595, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: PUPD0: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD1

Bits 2-3: PUPD1: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD2

Bits 4-5: PUPD2: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD3

Bits 6-7: PUPD3: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD4

Bits 8-9: PUPD4: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD5

Bits 10-11: PUPD5: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD6

Bits 12-13: PUPD6: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD7

Bits 14-15: PUPD7: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD8

Bits 16-17: PUPD8: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD9

Bits 18-19: PUPD9: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD10

Bits 20-21: PUPD10: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD11

Bits 22-23: PUPD11: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD12

Bits 24-25: PUPD12: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD13

Bits 26-27: PUPD13: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD14

Bits 28-29: PUPD14: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD15

Bits 30-31: PUPD15: Port A configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

IDR

IDR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID1

Bit 1: ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID2

Bit 2: ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID3

Bit 3: ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID4

Bit 4: ID4: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID5

Bit 5: ID5: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID6

Bit 6: ID6: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID7

Bit 7: ID7: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID8

Bit 8: ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID9

Bit 9: ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID10

Bit 10: ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID11

Bit 11: ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID12

Bit 12: ID12: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID13

Bit 13: ID13: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID14

Bit 14: ID14: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID15

Bit 15: ID15: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ODR

ODR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: OD0: Port A output data bit These bits can be read and written by software.

OD1

Bit 1: OD1: Port A output data bit These bits can be read and written by software.

OD2

Bit 2: OD2: Port A output data bit These bits can be read and written by software.

OD3

Bit 3: OD3: Port A output data bit These bits can be read and written by software.

OD4

Bit 4: OD4: Port A output data bit These bits can be read and written by software.

OD5

Bit 5: OD5: Port A output data bit These bits can be read and written by software.

OD6

Bit 6: OD6: Port A output data bit These bits can be read and written by software.

OD7

Bit 7: OD7: Port A output data bit These bits can be read and written by software.

OD8

Bit 8: OD8: Port A output data bit These bits can be read and written by software.

OD9

Bit 9: OD9: Port A output data bit These bits can be read and written by software.

OD10

Bit 10: OD10: Port A output data bit These bits can be read and written by software.

OD11

Bit 11: OD11: Port A output data bit These bits can be read and written by software.

OD12

Bit 12: OD12: Port A output data bit These bits can be read and written by software.

OD13

Bit 13: OD13: Port A output data bit These bits can be read and written by software.

OD14

Bit 14: OD14: Port A output data bit These bits can be read and written by software.

OD15

Bit 15: OD15: Port A output data bit These bits can be read and written by software.

BSRR

BSRR register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: BS0: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Sets the corresponding ODx bit.

BS1

Bit 1: BS1: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Sets the corresponding ODx bit.

BS2

Bit 2: BS2: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Sets the corresponding ODx bit.

BS3

Bit 3: BS3: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS4

Bit 4: BS4: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS5

Bit 5: BS5: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000.

BS6

Bit 6: BS6: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS7

Bit 7: BS7: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000.

BS8

Bit 8: BS8: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS9

Bit 9: BS9: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS10

Bit 10: BS10: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS11

Bit 11: BS11: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS12

Bit 12: BS12: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS13

Bit 13: BS13: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS14

Bit 14: BS14: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS15

Bit 15: BS15: Port A set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BR0

Bit 16: BR0: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: BR1: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: BR2: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: BR3: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: BR4: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: BR5: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: BR6: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: BR7: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: BR8: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: BR9: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: BR10: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: BR11: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: BR12: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: BR13: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: BR14: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: BR15: Port A reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

LCKR

LCKR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: LCK0: Port A lock bit 0 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK1

Bit 1: LCK1: Port A lock bit 1 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK2

Bit 2: LCK2: Port A lock bit 2 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK3

Bit 3: LCK3: Port A lock bit 3 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK4

Bit 4: LCK4: Port A lock bit 4 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK5

Bit 5: LCK5: Port A lock bit 5 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK6

Bit 6: LCK6: Port A lock bit 6 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK7

Bit 7: LCK7: Port A lock bit 7 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK8

Bit 8: LCK8: Port A lock bit 8 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK9

Bit 9: LCK9: Port A lock bit 9 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK10

Bit 10: LCK10: Port A lock bit 10 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK11

Bit 11: LCK11: Port A lock bit 11 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK12

Bit 12: LCK12: Port A lock bit 12 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK13

Bit 13: LCK13: Port A lock bit 13 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK14

Bit 14: LCK14: Port A lock bit 14 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK15

Bit 15: LCK15: Port A lock bit 15 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCKK

Bit 16: LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. -0: Port configuration lock key not active -1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset.

AFRL

AFRL register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL1

Bits 4-7: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL2

Bits 8-11: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL3

Bits 12-15: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL4

Bits 16-19: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL5

Bits 20-23: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL6

Bits 24-27: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL7

Bits 28-31: y[3:0]: Alternate function selection for port A pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFRH

AFRH register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL9

Bits 4-7: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL10

Bits 8-11: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL11

Bits 12-15: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL12

Bits 16-19: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL13

Bits 20-23: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL14

Bits 24-27: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL15

Bits 28-31: y[3:0]: Alternate function selection for port A pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

BRR

BRR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: BR0: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR1

Bit 1: BR1: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR2

Bit 2: BR2: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR3

Bit 3: BR3: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR4

Bit 4: BR4: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR5

Bit 5: BR5: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR6

Bit 6: BR6: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR7

Bit 7: BR7: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR8

Bit 8: BR8: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR9

Bit 9: BR9: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR10

Bit 10: BR10: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR11

Bit 11: BR11: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR12

Bit 12: BR12: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR13

Bit 13: BR13: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR14

Bit 14: BR14: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR15

Bit 15: BR15: Port A reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

GPIOB

0x48100000:

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

MODER register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE1

Bits 2-3: MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE2

Bits 4-5: MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE3

Bits 6-7: MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE4

Bits 8-9: MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE5

Bits 10-11: MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE6

Bits 12-13: MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE7

Bits 14-15: MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE8

Bits 16-17: MODE8[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE9

Bits 18-19: MODE9[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE10

Bits 20-21: MODE10[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE11

Bits 22-23: MODE11[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE12

Bits 24-25: MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE13

Bits 26-27: MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE14

Bits 28-29: MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

MODE15

Bits 30-31: MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. -00: Input mode -01: output mode -10: Alternate function mode -11: Analog mode.

OTYPER

OTYPER register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: OT0: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT1

Bit 1: OT1: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT2

Bit 2: OT2: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT3

Bit 3: OT3: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT4

Bit 4: OT4: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT5

Bit 5: OT5: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT6

Bit 6: OT6: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT7

Bit 7: OT7: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT8

Bit 8: OT8: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT9

Bit 9: OT9: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT10

Bit 10: OT10: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT11

Bit 11: OT11: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT12

Bit 12: OT12: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT13

Bit 13: OT13: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT14

Bit 14: OT14: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OT15

Bit 15: OT15: Port B configuration bits These bits are written by software to configure the I/O output type. -0: Output push-pull (reset state) -1: Output open-drain.

OSPEEDR

OSPEEDR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: OSPEED0[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED1

Bits 2-3: OSPEED1[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED2

Bits 4-5: OSPEED2[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED3

Bits 6-7: OSPEED3[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED4

Bits 8-9: OSPEED4[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED5

Bits 10-11: OSPEED5[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED6

Bits 12-13: OSPEED6[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED7

Bits 14-15: OSPEED7[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED8

Bits 16-17: OSPEED8[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED9

Bits 18-19: OSPEED9[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED10

Bits 20-21: OSPEED10[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED11

Bits 22-23: OSPEED11[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED12

Bits 24-25: OSPEED12[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED13

Bits 26-27: OSPEED13[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED14

Bits 28-29: OSPEED14[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

OSPEED15

Bits 30-31: OSPEED15[1:0]: Port B configuration bits These bits are written by software to configure the I/O output speed..

PUPDR

PUPDR register

Offset: 0xc, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: PUPD0: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD1

Bits 2-3: PUPD1: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD2

Bits 4-5: PUPD2: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD3

Bits 6-7: PUPD3: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD4

Bits 8-9: PUPD4: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD5

Bits 10-11: PUPD5: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD6

Bits 12-13: PUPD6: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD7

Bits 14-15: PUPD7: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD8

Bits 16-17: PUPD8: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD9

Bits 18-19: PUPD9: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD10

Bits 20-21: PUPD10: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD11

Bits 22-23: PUPD11: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD12

Bits 24-25: PUPD12: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD13

Bits 26-27: PUPD13: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD14

Bits 28-29: PUPD14: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

PUPD15

Bits 30-31: PUPD15: Port B configuration bits These bits are written by software to configure the I/O pull-up or pull-down -00: No pull-up, pull-down -01: Pull-up -10: Pull-down -11: Reserved.

IDR

IDR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID1

Bit 1: ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID2

Bit 2: ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID3

Bit 3: ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID4

Bit 4: ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID5

Bit 5: ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID6

Bit 6: ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID7

Bit 7: ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID8

Bit 8: ID8: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID9

Bit 9: ID9: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID10

Bit 10: ID10: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID11

Bit 11: ID11: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID12

Bit 12: ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID13

Bit 13: ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID14

Bit 14: ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ID15

Bit 15: ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port.

ODR

ODR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: OD0: Port B output data bit These bits can be read and written by software.

OD1

Bit 1: OD1: Port B output data bit These bits can be read and written by software.

OD2

Bit 2: OD2: Port B output data bit These bits can be read and written by software.

OD3

Bit 3: OD3: Port B output data bit These bits can be read and written by software.

OD4

Bit 4: OD4: Port B output data bit These bits can be read and written by software.

OD5

Bit 5: OD5: Port B output data bit These bits can be read and written by software.

OD6

Bit 6: OD6: Port B output data bit These bits can be read and written by software.

OD7

Bit 7: OD7: Port B output data bit These bits can be read and written by software.

OD8

Bit 8: OD8: Port B output data bit These bits can be read and written by software.

OD9

Bit 9: OD9: Port B output data bit These bits can be read and written by software.

OD10

Bit 10: OD10: Port B output data bit These bits can be read and written by software.

OD11

Bit 11: OD11: Port B output data bit These bits can be read and written by software.

OD12

Bit 12: OD12: Port B output data bit These bits can be read and written by software.

OD13

Bit 13: OD13: Port B output data bit These bits can be read and written by software.

OD14

Bit 14: OD14: Port B output data bit These bits can be read and written by software.

OD15

Bit 15: OD15: Port B output data bit These bits can be read and written by software.

BSRR

BSRR register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: BS0: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS1

Bit 1: BS1: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS2

Bit 2: BS2: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS3

Bit 3: BS3: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS4

Bit 4: BS4: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS5

Bit 5: BS5: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS6

Bit 6: BS6: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS7

Bit 7: BS7: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS8

Bit 8: BS8: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS9

Bit 9: BS9: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS10

Bit 10: BS10: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS11

Bit 11: BS11: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS12

Bit 12: BS12: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS13

Bit 13: BS13: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS14

Bit 14: BS14: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BS15

Bit 15: BS15: Port B set bit y These bits are write-only. A read to these bits returns the value 0x0000..

BR0

Bit 16: BR0: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: BR1: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: BR2: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: BR3: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: BR4: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: BR5: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: BR6: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: BR7: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: BR8: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: BR9: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: BR10: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: BR11: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: BR12: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: BR13: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: BR14: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: BR15: Port B reset bit y These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority..

LCKR

LCKR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: LCK0: Port B lock bit 0 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK1

Bit 1: LCK1: Port B lock bit 1 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK2

Bit 2: LCK2: Port B lock bit 2 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK3

Bit 3: LCK3: Port B lock bit 3 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK4

Bit 4: LCK4: Port B lock bit 4 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK5

Bit 5: LCK5: Port B lock bit 5 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK6

Bit 6: LCK6: Port B lock bit 6 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK7

Bit 7: LCK7: Port B lock bit 7 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK8

Bit 8: LCK8: Port B lock bit 8 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK9

Bit 9: LCK9: Port B lock bit 9 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK10

Bit 10: LCK10: Port B lock bit 10 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK11

Bit 11: LCK11: Port B lock bit 11 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK12

Bit 12: LCK12: Port B lock bit 12 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK13

Bit 13: LCK13: Port B lock bit 13 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK14

Bit 14: LCK14: Port B lock bit 14 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCK15

Bit 15: LCK15: Port B lock bit 15 These bits are read/write but can only be written when the LCKK bit is 0, using the specific sequence described in LCKK bit description. -0: Port configuration not locked -1: Port configuration locked.

LCKK

Bit 16: LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. -0: Port configuration lock key not active -1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset.

AFRL

AFRL register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL1

Bits 4-7: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL2

Bits 8-11: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL3

Bits 12-15: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL4

Bits 16-19: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL5

Bits 20-23: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL6

Bits 24-27: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL7

Bits 28-31: y[3:0]: Alternate function selection for Port B pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFRH

AFRH register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL9

Bits 4-7: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL10

Bits 8-11: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL11

Bits 12-15: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL12

Bits 16-19: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL13

Bits 20-23: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL14

Bits 24-27: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

AFSEL15

Bits 28-31: y[3:0]: Alternate function selection for Port B pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved.

BRR

BRR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: BR0: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR1

Bit 1: BR1: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR2

Bit 2: BR2: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR3

Bit 3: BR3: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR4

Bit 4: BR4: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR5

Bit 5: BR5: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR6

Bit 6: BR6: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR7

Bit 7: BR7: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR8

Bit 8: BR8: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR9

Bit 9: BR9: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR10

Bit 10: BR10: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR11

Bit 11: BR11: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR12

Bit 12: BR12: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR13

Bit 13: BR13: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR14

Bit 14: BR14: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

BR15

Bit 15: BR15: Port B reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. -0: No action on the corresponding ODx bit -1: Resets the corresponding ODx bit.

I2C1

0x41000000:

18/75 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	I2C_CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	I2C_CR2			PECBYTE	AUTOEND	RELOAD	NBYTES							NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	I2C_OAR1													OA1EN					OA1MODE	OA1
0xc	I2C_OAR2													OA2EN					OA2MSK			OA2
0x10	I2C_TIMING	PRESC					SCLDEL				SDADEL			SCLH								SCLL
0x14	I2C_TIMEOUT	TEXTEN	TIMEOUTB											TIMEOUTEN			TIDLE	TIMEOUTA
0x18	I2C_ISR						ADDCODE						DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	I2C_ICR															ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	I2C_PEC																					PEC
0x24	I2C_RXDR																					RXDATA
0x28	I2C_TXDR																					TXDATA

Toggle registers

I2C_CR1

I2C_CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw		NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN r	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable - 0: Peripheral disable - 1: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable - 0: Transmit (TXIS) interrupt disabled - 1: Transmit (TXIS) interrupt enabled.

RXIE

Bit 2: RX Interrupt enable - 0: Receive (RXNE) interrupt disabled - 1: Receive (RXNE) interrupt enabled.

ADDRIE

Bit 3: Address match Interrupt enable (slave only) - 0: Address match (ADDR) interrupts disabled - 1: Address match (ADDR) interrupts enabled.

NACKIE

Bit 4: Not acknowledge received Interrupt enable - 0: Not acknowledge (NACKF) received interrupts disabled - 1: Not acknowledge (NACKF) received interrupts enabled.

STOPIE

Bit 5: STOP detection Interrupt enable - 0: Stop detection (STOPF) interrupt disabled - 1: Stop detection (STOPF) interrupt enabled.

TCIE

Bit 6: Transfer Complete interrupt enable - 0: Transfer Complete interrupt disabled - 1: Transfer Complete interrupt enabled.

ERRIE

Bit 7: Error interrupts enable - 0: Error detection interrupts disabled - 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK - 0000: Digital filter disabled - 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK - 1111: digital filter enabled and filtering capability up to15 tI2CCLK.

ANFOFF

Bit 12: Analog noise filter OFF - 0: Analog noise filter enabled - 1: Analog noise filter disabled.

TXDMAEN

Bit 14: DMA transmission requests enable - 0: DMA mode disabled for transmission - 1: DMA mode enabled for transmission.

RXDMAEN

Bit 15: DMA reception requests enable - 0: DMA mode disabled for reception - 1: DMA mode enabled for reception.

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode. - 0: Slave byte control disabled - 1: Slave byte control enabled.

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. - 0: Clock stretching enabled - 1: Clock stretching disabled Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable - 0: Host address disabled. Address 0b0001000x is NACKed. - 1: Host address enabled. Address 0b0001000x is ACKed..

SMBDEN

Bit 21: SMBus Device Default address enable - 0: Device default address disabled. Address 0b1100001x is NACKed. - 1: Device default address enabled. Address 0b1100001x is ACKed..

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): - 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. - 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. Host mode (SMBHEN=1): - 0: SMBus Alert pin (SMBA) not supported. - 1: SMBus Alert pin (SMBA) supported..

PECEN

Bit 23: PEC enable - 0: PEC calculation disabled - 1: PEC calculation enabled.

I2C_CR2

I2C_CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address.

RD_WRN

Bit 10: Transfer direction (master mode) - 0: Master requests a write transfer. - 1: Master requests a read transfer..

ADD10

Bit 11: Ten-bit addressing mode (master mode) - 0: The master operates in 7-bit addressing mode, - 1: The master operates in 10-bit addressing mode.

HEAD10R

Bit 12: Ten bit (10-bit) address header only read direction (master receiver mode) - 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. - 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction..

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. - 0: No Start generation. - 1: Restart/Start generation: If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free..

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: - 0: No Stop generation. - 1: Stop generation after current byte transfer..

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. - 0: an ACK is sent after current received byte. - 1: a NACK is sent after current received byte..

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software. - 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). - 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low..

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. - 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. - 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred..

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. - 0: No PEC transfer. - 1: PEC transmission/reception is requested.

I2C_OAR1

I2C_OAR1 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode - 0: Own address 1 is a 7-bit address. - 1: Own address 1 is a 10-bit address..

OA1EN

Bit 15: Own Address 1 enable - 0: Own address 1 disabled. The received slave address OA1 is NACKed. - 1: Own address 1 enabled. The received slave address OA1 is ACKed..

I2C_OAR2

I2C_OAR2 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own Address 2 masks - 000: No mask - 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. - 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. - 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. - 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. - 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. - 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. - 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged..

OA2EN

Bit 15: Own Address 2 enable.

I2C_TIMING

I2C_TIMING register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in transmission mode. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in transmission mode. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters and for SCL high and low level counters tPRESC = (PRESC+1) x tI2CCLK.

I2C_TIMEOUT

I2C_TIMEOUT register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection - 0: TIMEOUTA is used to detect SCL low timeout - 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) Note: This bit can be written only when TIMOUTEN=0..

TIMEOUTEN

Bit 15: Clock timeout enable - 0: SCL timeout detection is disabled - 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1)..

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable - 0: Extended clock timeout detection is disabled - 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1)..

I2C_ISR

I2C_ISR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). - 0: Write transfer, slave enters receiver mode. - 1: Read transfer, slave enters transmitter mode..

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

I2C_ICR

I2C_ICR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

I2C_PEC

I2C_PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

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PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

I2C_RXDR

I2C_RXDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

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RXDATA

Bits 0-7: Eight bit (8-bit) receive data Data byte received from the I2C bus..

I2C_TXDR

I2C_TXDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

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TXDATA

Bits 0-7: Eight bits (8-bit) transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

I2C2

0x41001000:

18/75 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	I2C_CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	I2C_CR2			PECBYTE	AUTOEND	RELOAD	NBYTES							NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	I2C_OAR1													OA1EN					OA1MODE	OA1
0xc	I2C_OAR2													OA2EN					OA2MSK			OA2
0x10	I2C_TIMING	PRESC					SCLDEL				SDADEL			SCLH								SCLL
0x14	I2C_TIMEOUT	TEXTEN	TIMEOUTB											TIMEOUTEN			TIDLE	TIMEOUTA
0x18	I2C_ISR						ADDCODE						DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	I2C_ICR															ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	I2C_PEC																					PEC
0x24	I2C_RXDR																					RXDATA
0x28	I2C_TXDR																					TXDATA

Toggle registers

I2C_CR1

I2C_CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw		NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN r	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable - 0: Peripheral disable - 1: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable - 0: Transmit (TXIS) interrupt disabled - 1: Transmit (TXIS) interrupt enabled.

RXIE

Bit 2: RX Interrupt enable - 0: Receive (RXNE) interrupt disabled - 1: Receive (RXNE) interrupt enabled.

ADDRIE

Bit 3: Address match Interrupt enable (slave only) - 0: Address match (ADDR) interrupts disabled - 1: Address match (ADDR) interrupts enabled.

NACKIE

Bit 4: Not acknowledge received Interrupt enable - 0: Not acknowledge (NACKF) received interrupts disabled - 1: Not acknowledge (NACKF) received interrupts enabled.

STOPIE

Bit 5: STOP detection Interrupt enable - 0: Stop detection (STOPF) interrupt disabled - 1: Stop detection (STOPF) interrupt enabled.

TCIE

Bit 6: Transfer Complete interrupt enable - 0: Transfer Complete interrupt disabled - 1: Transfer Complete interrupt enabled.

ERRIE

Bit 7: Error interrupts enable - 0: Error detection interrupts disabled - 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK - 0000: Digital filter disabled - 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK - 1111: digital filter enabled and filtering capability up to15 tI2CCLK.

ANFOFF

Bit 12: Analog noise filter OFF - 0: Analog noise filter enabled - 1: Analog noise filter disabled.

TXDMAEN

Bit 14: DMA transmission requests enable - 0: DMA mode disabled for transmission - 1: DMA mode enabled for transmission.

RXDMAEN

Bit 15: DMA reception requests enable - 0: DMA mode disabled for reception - 1: DMA mode enabled for reception.

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode. - 0: Slave byte control disabled - 1: Slave byte control enabled.

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. - 0: Clock stretching enabled - 1: Clock stretching disabled Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

GCEN

Bit 19: General call enable - 0: General call disabled. Address 0b00000000 is NACKed. - 1: General call enabled. Address 0b00000000 is ACKed..

SMBHEN

Bit 20: SMBus Host address enable - 0: Host address disabled. Address 0b0001000x is NACKed. - 1: Host address enabled. Address 0b0001000x is ACKed..

SMBDEN

Bit 21: SMBus Device Default address enable - 0: Device default address disabled. Address 0b1100001x is NACKed. - 1: Device default address enabled. Address 0b1100001x is ACKed..

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): - 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. - 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. Host mode (SMBHEN=1): - 0: SMBus Alert pin (SMBA) not supported. - 1: SMBus Alert pin (SMBA) supported..

PECEN

Bit 23: PEC enable - 0: PEC calculation disabled - 1: PEC calculation enabled.

I2C_CR2

I2C_CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address.

RD_WRN

Bit 10: Transfer direction (master mode) - 0: Master requests a write transfer. - 1: Master requests a read transfer..

ADD10

Bit 11: Ten-bit addressing mode (master mode) - 0: The master operates in 7-bit addressing mode, - 1: The master operates in 10-bit addressing mode.

HEAD10R

Bit 12: Ten bit (10-bit) address header only read direction (master receiver mode) - 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. - 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction..

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. - 0: No Start generation. - 1: Restart/Start generation: If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free..

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: - 0: No Stop generation. - 1: Stop generation after current byte transfer..

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. - 0: an ACK is sent after current received byte. - 1: a NACK is sent after current received byte..

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software. - 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). - 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low..

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. - 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. - 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred..

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. - 0: No PEC transfer. - 1: PEC transmission/reception is requested.

I2C_OAR1

I2C_OAR1 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

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OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode - 0: Own address 1 is a 7-bit address. - 1: Own address 1 is a 10-bit address..

OA1EN

Bit 15: Own Address 1 enable - 0: Own address 1 disabled. The received slave address OA1 is NACKed. - 1: Own address 1 enabled. The received slave address OA1 is ACKed..

I2C_OAR2

I2C_OAR2 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own Address 2 masks - 000: No mask - 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. - 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. - 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. - 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. - 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. - 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. - 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged..

OA2EN

Bit 15: Own Address 2 enable - 0: Own address 2 disabled. The received slave address OA2 is NACKed. - 1: Own address 2 enabled. The received slave address OA2 is ACKed..

I2C_TIMING

I2C_TIMING register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in transmission mode. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in transmission mode. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters and for SCL high and low level counters tPRESC = (PRESC+1) x tI2CCLK.

I2C_TIMEOUT

I2C_TIMEOUT register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection - 0: TIMEOUTA is used to detect SCL low timeout - 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) Note: This bit can be written only when TIMOUTEN=0..

TIMEOUTEN

Bit 15: Clock timeout enable - 0: SCL timeout detection is disabled - 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1)..

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable - 0: Extended clock timeout detection is disabled - 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1)..

I2C_ISR

I2C_ISR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). - 0: Write transfer, slave enters receiver mode. - 1: Read transfer, slave enters transmitter mode..

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

I2C_ICR

I2C_ICR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation..

I2C_PEC

I2C_PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

I2C_RXDR

I2C_RXDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

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RXDATA

Bits 0-7: Eight bit (8-bit) receive data Data byte received from the I2C bus..

I2C_TXDR

I2C_TXDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: Eight bits (8-bit) transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

IWDG

0x40003000:

3/7 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0	KR	KEY
0x4	PR			PR
0x8	RLR		RL
0xc	SR			WVU	RVU	PVU
0x10	WINR		WIN

Toggle registers

KR

IWDG_KR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value. Software can only write these bits. Reading returns the reset value. These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. Writing the key value CCCCh starts the watchdog.

PR

IWDG_PR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle fields

PR

Bits 0-2: Prescaler divider. Set and reset by software. These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider/4 001: divider/8 010: divider/16 011: divider/32 100: divider/64 101: divider/128 110: divider/256 111: divider/256.

RLR

IWDG_RLR register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

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RL

Bits 0-11: Watchdog counter reload value. Set and reset by software. These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value..

SR

IWDG_SR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

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PVU

Bit 0: Watchdog prescaler value update. Read only bit. This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset.

RVU

Bit 1: Watchdog counter reload value update. Read only bit. This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset.

WVU

Bit 2: Watchdog counter window value update. Read only bit. This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic 'window' = 1.

WINR

IWDG_WINR register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle fields

WIN

Bits 0-11: Watchdog counter window value. Set and reset by software. These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value..

LCD

0x40007000:

6/31 fields covered.

Toggle register map

Offset	Name	25	21	17	15	12	9	8	6	5	4	3	2	1	0
0x0	CR							BUFEN	BIAS		DUTY			VSEL	LCDEN
0x4	FCR	PS	DIV	BLINK	BLINKF	CC	DEAD		PON			UDDIE		SOFIE	HD
0x8	SR									FCRSF	RDY	UDD	UDR	SOF	ENS
0xc	CLR											UDDC		SOFC
0x14	RAM_COM0				SEGMENT_DATA
0x1c	RAM_COM1				SEGMENT_DATA
0x24	RAM_COM2				SEGMENT_DATA
0x2c	RAM_COM3				SEGMENT_DATA
0x34	RAM_COM4				SEGMENT_DATA
0x3c	RAM_COM5				SEGMENT_DATA
0x44	RAM_COM6				SEGMENT_DATA
0x4c	RAM_COM7				SEGMENT_DATA

Toggle registers

CR

LCD_CR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							BUFEN rw		BIAS rw		DUTY rw			VSEL rw	LCDEN rw

Toggle fields

LCDEN

Bit 0: LCD controller enable.

VSEL

Bit 1: Voltage source selection.

DUTY

Bits 2-4: Duty selection.

BIAS

Bits 5-6: Bias selector.

BUFEN

Bit 8: Voltage output buffer enable.

FCR

LCD_FCR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PS rw				DIV rw				BLINK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BLINKF rw			CC rw			DEAD rw			PON rw			UDDIE rw		SOFIE rw	HD rw

Toggle fields

HD

Bit 0: High drive enable.

SOFIE

Bit 1: Start of frame interrupt enable.

UDDIE

Bit 3: Update display done interrupt enable.

PON

Bits 4-6: Pulse ON duration.

DEAD

Bits 7-9: Dead time duration.

CC

Bits 10-12: Contrast control.

BLINKF

Bits 13-15: Blink frequency selection.

BLINK

Bits 16-17: Blink mode selection.

DIV

Bits 18-21: DIV clock divider.

PS

Bits 22-25: PS 16-bit prescaler.

SR

LCD_SR register

Offset: 0x8, size: 32, reset: 0x00000020, access: read-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FCRSF r	RDY r	UDD r	UDR r	SOF r	ENS r

Toggle fields

ENS

Bit 0: LCD enabled status.

SOF

Bit 1: Start of frame flag.

UDR

Bit 2: Update display request.

UDD

Bit 3: Update Display Done.

RDY

Bit 4: Ready flag.

FCRSF

Bit 5: LCD Frame Control Register Synchronization flag.

CLR

LCD_CLR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												UDDC w		SOFC w

Toggle fields

SOFC

Bit 1: Start of frame flag clear.

UDDC

Bit 3: Update display done clear.

RAM_COM0

LCD_RAM_COMx register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM1

LCD_RAM_COMx register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM2

LCD_RAM_COMx register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM3

LCD_RAM_COMx register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM4

LCD_RAM_COMx register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM5

LCD_RAM_COMx register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM6

LCD_RAM_COMx register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

RAM_COM7

LCD_RAM_COMx register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEGMENT_DATA rw

Toggle fields

SEGMENT_DATA

Bits 0-15: Each bit corresponds to one pixel of the LCD display..

LCSC

0x4000a000:

13/46 fields covered.

Toggle register map

Offset	Name	31	30	27	26	23	21	18	17	15	13	11	7	6	5	4	3	2	1	0
0x0	CR0				TICAP		TCAP				TMEAS
0x4	CR1		TSTART_VCM					TREC_VCM		TREC_VCM			LCAB_DAMP_THRES
0x8	CR2									LCT_DAMP_THRES			TAMP_PSC
0xc	PULSE_CR											LCT_PULSE_WIDTH					LCAB_PULSE_WIDTH
0x10	ENR	LCSC_EN															CNT_OFB_WKP_IE	TAMP_IE	ACLKWISE_IE	CLKWISE_IE
0x14	WHEEL_SR	ACLKWISE								CLKWISE
0x18	CONFR	ACLKWISE_THRES								CLKWISE_THRES
0x1c	COMP_CTN			CMP_LCT_CNT					CMP_LCB_CNT	CMP_LCB_CNT			CMP_LCA_CNT
0x20	SR														LAST_DIR		ACLKWISE_STATE		CLKWISE_STATE
0x24	STAT	MAX_LCAB_CNT_BOUND				MIN_LCAB_CNT_BOUND				MAX_LCAB_CNT			MIN_LCAB_CNT
0x28	TST_CFG																TST_CFG			TST_EN
0x2c	ANATST_CFG												DAC_PWDN	DAC_PWDN_SEL	COMP_PWDN	COMP_PWDN_SEL	VCMBUFF_PWDN	VCMBUFF_PWDN_SEL	VCMBUFF_ENOUT	VCMBUFF_ENOUT_SEL
0x40	VER									PROD		VER	REV
0x44	ISR																CNT_OFB_F	TAMP_F	ACLKWISE_F	CLKWISE_F

Toggle registers

CR0

LCSC_CR0 register

Offset: 0x0, size: 32, reset: 0x000B005C, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					TICAP rw					TCAP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		TMEAS rw

Toggle fields

TMEAS

Bits 0-13: Measurement Time.

TCAP

Bits 16-21: Capture Time.

TICAP

Bits 24-26: Inter Capture Time.

CR1

LCSC_CR1 register

Offset: 0x4, size: 32, reset: 0x3C010C80, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	TSTART_VCM rw												TREC_VCM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TREC_VCM rw								LCAB_DAMP_THRES rw

Toggle fields

LCAB_DAMP_THRES

Bits 0-7: LCAB_DAMP_THRES[7:0]: Damping threshold for LCA and LCB.

TREC_VCM

Bits 10-18: VCMBUFF Recovery Time.

TSTART_VCM

Bits 20-30: VCMBUFF Starting Time.

CR2

LCSC_CR2 register

Offset: 0x8, size: 32, reset: 0x00008000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCT_DAMP_THRES rw								TAMP_PSC rw

Toggle fields

TAMP_PSC

Bits 0-7: Tamper measurement interval..

LCT_DAMP_THRES

Bits 8-15: Damping threshold for LCT.

PULSE_CR

LCSC_PULSE_CR register

Offset: 0xc, size: 32, reset: 0x00000070, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LCT_PULSE_WIDTH rw								LCAB_PULSE_WIDTH rw

Toggle fields

LCAB_PULSE_WIDTH

Bits 0-3: Low Pulse Width for LCA and LCB.

LCT_PULSE_WIDTH

Bits 8-11: Low Pulse Width for LCT.

ENR

LCSC_ENR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LCSC_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CNT_OFB_WKP_IE rw	TAMP_IE rw	ACLKWISE_IE rw	CLKWISE_IE rw

Toggle fields

CLKWISE_IE

Bit 0: Clock Wise Interrupt and Wakeup Enable.

ACLKWISE_IE

Bit 1: Anti Clock Wise Interrupt and Wakeup Enable.

TAMP_IE

Bit 2: Tamper Interrupt and Wakeup Enable.

CNT_OFB_WKP_IE

Bit 3: LCAB Counter Out Of Bound wakeup enable.

LCSC_EN

Bit 31: LCSC Enable.

WHEEL_SR

LCSC_WHEEL_SR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACLKWISE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKWISE r

Toggle fields

CLKWISE

Bits 0-15: Number of Clock Wise revolutions.

ACLKWISE

Bits 16-31: Number of Anti Clock Wise revolutions.

CONFR

LCSC_CONFR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACLKWISE_THRES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKWISE_THRES rw

Toggle fields

CLKWISE_THRES

Bits 0-15: Number of Clock Wise revolutions target.

ACLKWISE_THRES

Bits 16-31: Number of Anti Clock Wise revolutions target.

COMP_CTN

LCSC_COMP_CTN register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CMP_LCT_CNT r										CMP_LCB_CNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP_LCB_CNT r								CMP_LCA_CNT r

Toggle fields

CMP_LCA_CNT

Bits 0-7: LCA Comparator last damping count.

CMP_LCB_CNT

Bits 10-17: LCB Comparator last damping count.

CMP_LCT_CNT

Bits 20-27: LCT Comparator last damping count.

SR

LCSC_SR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LAST_DIR r		ACLKWISE_STATE r		CLKWISE_STATE r

Toggle fields

CLKWISE_STATE

Bits 0-1: The current state of the LCSC clockwise FSM:.

ACLKWISE_STATE

Bits 2-3: The current state of the LCSC anti clockwise FSM:.

LAST_DIR

Bits 4-5: The last direction detected:.

STAT

LCSC_STAT register

Offset: 0x24, size: 32, reset: 0xFF0000FF, access: read-write

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MAX_LCAB_CNT_BOUND rw								MIN_LCAB_CNT_BOUND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MAX_LCAB_CNT r								MIN_LCAB_CNT r

Toggle fields

MIN_LCAB_CNT

Bits 0-7: The Minimum of CMP_LCA_CNT, CMP_LCB_CNT reached during the.

MAX_LCAB_CNT

Bits 8-15: The Maximum of CMP_LCA_CNT, CMP_LCB_CNT reached during.

MIN_LCAB_CNT_BOUND

Bits 16-23: The Minimum bound of CMP_LCA_COUNT,.

MAX_LCAB_CNT_BOUND

Bits 24-31: The Maximum bound of CMP_LCA_COUNT,.

TST_CFG

LCSC Test Configuration Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TST_CFG rw			TST_EN rw

Toggle fields

TST_EN

Bit 0: Test Enable.

TST_CFG

Bits 1-3: DTB output selection.

ANATST_CFG

LCSC ANA Test Configuration Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DAC_PWDN rw	DAC_PWDN_SEL rw	COMP_PWDN rw	COMP_PWDN_SEL rw	VCMBUFF_PWDN rw	VCMBUFF_PWDN_SEL rw	VCMBUFF_ENOUT rw	VCMBUFF_ENOUT_SEL rw

Toggle fields

VCMBUFF_ENOUT_SEL

Bit 0: Selection of the signal to be used to supply the DAC in the LCSC.

VCMBUFF_ENOUT

Bit 1: VCMBUFFER output buffer enable pin.

VCMBUFF_PWDN_SEL

Bit 2: Selection of the signal to be used to supply the DAC in the LCSC.

VCMBUFF_PWDN

Bit 3: VCMBUFF power-down pin.

COMP_PWDN_SEL

Bit 4: Selection of the signal to be used to supply the COMP in the LCSC Analog part.

COMP_PWDN

Bit 5: COMP power-down pin.

DAC_PWDN_SEL

Bit 6: Selection of the signal to be used to supply the DAC in the LCSC Analog part.

DAC_PWDN

Bit 7: DAC power-down pin.

VER

LCSC_VER register

Offset: 0x40, size: 32, reset: 0x00001000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROD r				VER r				REV r

Toggle fields

REV

Bits 4-7: Revision of the RFIP to be used for metal fixes).

VER

Bits 8-11: Version of the RFIP (to be used for cut upgrades).

PROD

Bits 12-15: Used for major upgrades (new protocols support / new features).

ISR

LCSC_ISR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CNT_OFB_F rw	TAMP_F rw	ACLKWISE_F rw	CLKWISE_F rw

Toggle fields

CLKWISE_F

Bit 0: Clock Wise Flag:.

ACLKWISE_F

Bit 1: Anti Clock Wise Flag:.

TAMP_F

Bit 2: Tamper Flag.

CNT_OFB_F

Bit 3: Out of Bound Counter Flag.

LPAWUR

0x49001000:

2/26 fields covered.

Toggle register map

Offset	Name	31	25	21	20	19	18	17	15	13	12	8	7	4	3	2	1	0
0x0	FRAME_CONFIG0		SLOW_CLK_CYCLE_PER_BIT_CNT			PAYLOAD_LENGTH			SYNC_THRESHOLD_COUNT			SYNC_LENGTH	PREAMBLE_THRESHOLD_COUNT
0x4	FRAME_CONFIG1						TREC_LOOP_ALGO_SEL	PREAMBLE_ENABLE	FRAME_SYNC_COUNTER_TIMEOUT				KP		KI
0x8	FRAME_SYNC_CONFIG	FRAME_SYNC_PATTERN_H							FRAME_SYNC_PATTERN_L
0xc	RFIP_CONFIG															WAKEUP_LEVEL		LPAWUR_ENABLE
0x10	RF_CONFIG			LPF3_CAL	ED_ICAL			AGC_HIGH_LVL	AGC_HIGH_LVL	ED_DC_CTRL	AGC_LOW_LVL			CLKDIV				ED_SWITCH
0x14	AGC_CONFIG														AGC_RESET_MODE	AGC_HOLD_MODE	AGC_MODE
0x1c	PAYLOAD_0	PAYLOAD_0							PAYLOAD_0
0x20	PAYLOAD_1	PAYLOAD_1							PAYLOAD_1

Toggle registers

FRAME_CONFIG0

FRAME_CONFIG0 register

Offset: 0x0, size: 32, reset: 0x02074012, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						SLOW_CLK_CYCLE_PER_BIT_CNT rw						PAYLOAD_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SYNC_THRESHOLD_COUNT rw							SYNC_LENGTH rw	PREAMBLE_THRESHOLD_COUNT rw

Toggle fields

PREAMBLE_THRESHOLD_COUNT

Bits 0-7: The number of transitions for preamble detection when receiving the manchester encoded preamble..

SYNC_LENGTH

Bit 8: Frame sync pattern length ( Manchester encoded )..

SYNC_THRESHOLD_COUNT

Bits 10-15: detection threshold when receivng the Frame sync ( Manchester encoded)..

PAYLOAD_LENGTH

Bits 16-19: The number of data Bytes in the payload ( decoded )..

SLOW_CLK_CYCLE_PER_BIT_CNT

Bits 21-25: The number of expected slow clock cycle per each manchester coded bit..

FRAME_CONFIG1

FRAME_CONFIG1 register

Offset: 0x4, size: 32, reset: 0x00024669, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													TREC_LOOP_ALGO_SEL rw	PREAMBLE_ENABLE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FRAME_SYNC_COUNTER_TIMEOUT rw								KP rw				KI rw

Toggle fields

KI

Bits 0-3: ki gain value for the timing recovery loop..

KP

Bits 4-7: kp gain value for the timing recovery loop..

FRAME_SYNC_COUNTER_TIMEOUT

Bits 8-15: The timeout in manchester encoded bits for the Frame Sync,it represents the number of samples after which in case the frame sync is not detected a sync_error is raised..

PREAMBLE_ENABLE

Bit 17: Preamble detection enable.

TREC_LOOP_ALGO_SEL

Bit 18: Timing recovery loop algorithm selection:.

FRAME_SYNC_CONFIG

FRAME_SYNC_CONFIG register

Offset: 0x8, size: 32, reset: 0x00009696, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FRAME_SYNC_PATTERN_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FRAME_SYNC_PATTERN_L rw

Toggle fields

FRAME_SYNC_PATTERN_L

Bits 0-15: The value of the frame sync pattern, Low word, manchester encoded, used when the frame sync length is 16 bit (default 0x9696 which represent a frame sync value of 0x99).

FRAME_SYNC_PATTERN_H

Bits 16-31: The value of the frame sync pattern, High word, manchester encoded, used only when the frame sync length is 32 bits (default 0x0000 ).

RFIP_CONFIG

RFIP_CONFIG register

Offset: 0xc, size: 32, reset: 0x00000006, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WAKEUP_LEVEL rw		LPAWUR_ENABLE rw

Toggle fields

LPAWUR_ENABLE

Bit 0: Enable (start) or Disable (stop) the LPAWUR feature (0: disabled by default).

WAKEUP_LEVEL

Bits 1-2: - 00: the bit Sync has been detected.

RF_CONFIG

RF_CONFIG register

Offset: 0x10, size: 32, reset: 0x000133EE, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										LPF3_CAL rw	ED_ICAL rw			AGC_HIGH_LVL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AGC_HIGH_LVL rw		ED_DC_CTRL rw	AGC_LOW_LVL rw								CLKDIV rw				ED_SWITCH rw

Toggle fields

ED_SWITCH

Bit 0: - 0 : Normal operation (default).

CLKDIV

Bits 1-4: Calibrate 4kHz clock (programmable divider).

AGC_LOW_LVL

Bits 11-12: AGC level (Low) (default value: 0x2).

ED_DC_CTRL

Bit 13: DC current subtraction enabling signal (default value: 0x1).

AGC_HIGH_LVL

Bits 14-17: AGC level (High) (default value: 0x4).

ED_ICAL

Bits 18-20: Current versus VBAT calibration for ED.

LPF3_CAL

Bit 21: .

AGC_CONFIG

AGC_CONFIG register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_RESET_MODE rw	AGC_HOLD_MODE rw	AGC_MODE rw

Toggle fields

AGC_MODE

Bits 0-1: Define the working mode of the AGC:.

AGC_HOLD_MODE

Bit 2: The behavior when the AGC is ON and is working in HOLD mode.

AGC_RESET_MODE

Bit 3: The AGC reset behavior when the AGC is working in ON or HOLD mode.

PAYLOAD_0

PAYLOAD_0 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PAYLOAD_0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PAYLOAD_0 r

Toggle fields

PAYLOAD_0

Bits 0-31: First part of the payload (Least significant Byte First).

PAYLOAD_1

PAYLOAD_1 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PAYLOAD_1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PAYLOAD_1 r

Toggle fields

PAYLOAD_1

Bits 0-31: Second part of the payload (Least significant Byte First).

LPUART

0x41005000:

22/84 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M_1			DEAT					DEDT						CMIE	MME	M_0	WAKE	PCE	PS	PEIE	TXEIE_TXFNFIE	TCIE	RXNEIE_RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD												MSBFIRST	DATAINV	TXINV	RXINV	SWAP		STOP									ADDM7
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG				TXFTIE	WUFIE	WUS						DEP	DEM	DDRE	OVRDIS		CTSIE	CTSE	RTSE	DMAT	DMAR			HDSEL			EIE
0xc	BRR													BRR				BRR
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ
0x1c	ISR					TXFT	RXFT		RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY						CTS	CTSIF		TXE_TXFNF	TC	RXNE_RXFNE	IDLE	ORE	NF	FE	PE
0x20	ICR												WUCF			CMCF								CTSCF			TCCF		IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M_1 rw			DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CMIE rw	MME rw	M_0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE_TXFNFIE rw	TCIE rw	RXNEIE_RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled.

UESM

Bit 1: UESM: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that the LPUART clock selection is LSE in the RCC. This bit is set and cleared by software. -0: LPUART not able to wake up the MCU from Stop mode. -1: LPUART able to wake up the MCU from Stop mode. When this function is active, the clock source for the LPUART must be LSE (see RCC chapter).

RE

Bit 2: RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit.

TE

Bit 3: TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled.

IDLEIE

Bit 4: IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register.

RXNEIE_RXFNEIE

Bit 5: RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register.

TCIE

Bit 6: TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register.

TXEIE_TXFNFIE

Bit 7: TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register.

PEIE

Bit 8: PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register.

PS

Bit 9: PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0)..

PCE

Bit 10: PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0)..

WAKE

Bit 11: WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0)..

M_0

Bit 12: M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0)..

MME

Bit 13: MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode.

CMIE

Bit 14: CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register..

DEDT

Bits 16-20: DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0)..

DEAT

Bits 21-25: DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0)..

M_1

Bit 28: Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s.

FIFOEN

Bit 29: FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled..

TXFEIE

Bit 30: TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register.

RXFFIE

Bit 31: RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register.

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw												MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw		STOP rw									ADDM7 rw

Toggle fields

ADDM7

Bit 4: ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0).

STOP

Bits 12-13: STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0)..

SWAP

Bit 15: SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0)..

RXINV

Bit 16: RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0)..

TXINV

Bit 17: TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0)..

DATAINV

Bit 18: DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0)..

MSBFIRST

Bit 19: MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0)..

ADD

Bits 24-31: ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw				TXFTIE rw	WUFIE rw	WUS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw		CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw			HDSEL rw			EIE rw

Toggle fields

EIE

Bit 0: EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register..

HDSEL

Bit 3: HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0)..

DMAR

Bit 6: DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception.

DMAT

Bit 7: DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission.

RTSE

Bit 8: RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0)..

CTSE

Bit 9: CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0).

CTSIE

Bit 10: CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register.

OVRDIS

Bit 12: OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0)..

DDRE

Bit 13: DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0)..

DEM

Bit 14: DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0)..

DEP

Bit 15: DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0)..

WUS

Bits 20-21: WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). -00: WUF active on address match (as defined by ADD[7:0] and ADDM7) -01:Reserved. -10: WUF active on Start bit detection -11: WUF active on RXNE. This bit field can only be written when the LPUART is disabled (UE=0)..

WUFIE

Bit 22: WUFIE: Wakeup from Stop mode interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register.

TXFTIE

Bit 23: TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG..

RXFTCFG

Bits 25-27: RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved..

RXFTIE

Bit 28: RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG..

TXFTCFG

Bits 29-31: TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved..

BRR

BRR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BRR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle fields

BRR

Bits 0-19: BRR[19:0].

RQR

RQR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w

Toggle fields

SBKRQ

Bit 1: SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available..

MMRQ

Bit 2: MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag..

RXFRQ

Bit 3: RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0 When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes..

ISR

ISR register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r		RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTS r	CTSIF r		TXE_TXFNF r	TC r	RXNE_RXFNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error.

FE

Bit 1: FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected.

NF

Bit 2: NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected.

ORE

Bit 3: ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected.

IDLE

Bit 4: IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected.

RXNE_RXFNE

Bit 5: RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read..

TC

Bit 6: TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete.

TXE_TXFNF

Bit 7: TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full.

CTSIF

Bit 9: CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line.

CTS

Bit 10: CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset.

BUSY

Bit 16: BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going.

CMF

Bit 17: CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected.

SBKF

Bit 18: SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted.

RWU

Bit 19: RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode.

WUF

Bit 20: WUF: Wakeup from Stop mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=1 in the LPUART_CR3 register.

TEACK

Bit 21: TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode..

TXFE

Bit 23: TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty..

RXFF

Bit 24: RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full..

RXFT

Bit 26: RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesnt reach the programmed threshold. -1: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesnt reach the programmed threshold. -1: TXFIFO reached the programmed threshold.

ICR

ICR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTSCF w			TCCF w		IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.

NECF

Bit 2: NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register..

ORECF

Bit 3: ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TCCF

Bit 6: TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.

CTSCF

Bit 9: CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

CMCF

Bit 17: CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.

WUCF

Bit 20: WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register..

RDR

RDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

TDR

TDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1..

PRESC

PRESC register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be '1011' i.e. input clock divided by 256.

MISC

0x49000700:

7/13 fields covered.

Toggle register map

Offset	Name	31	30	15	14	11	7	1	0
0x0	RFIP_VERSION			PRODUCT		VERSION	REVISION
0x4	RRM_UDRA_CTRL								RRM_CMD_REQ
0x8	SEQUENCER_CTRL							DISABLE_SEQ	GEN_SEQ_TRIGGER
0xc	ABSOLUTE_TIME	ABSOLUTE_TIME		ABSOLUTE_TIME
0x10	SCM_COUNTER_VAL				SCM_COUNTER_CURRVAL
0x14	SCM_MIN_MAX	CLEAR_MIN_MAX	SCM_COUNTER_MAXVAL		SCM_COUNTER_MINVAL
0x18	WAKEUP_IRQ_STATUS							RFIP_WAKEUP_F	CPU_WAKEUP_F

Toggle registers

RFIP_VERSION

RFIP_VERSION register

Offset: 0x0, size: 32, reset: 0x00001200, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRODUCT r				VERSION r				REVISION r

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REVISION

Bits 4-7: Revision of the MR_SubG (to be used for metal fixes).

VERSION

Bits 8-11: Version of the MR_SubG (to be used for cut upgrades).

PRODUCT

Bits 12-15: Used for major upgrades (new protocols support / new features).

RRM_UDRA_CTRL

RRM_UDRA_CTRL register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RRM_CMD_REQ w

Toggle fields

RRM_CMD_REQ

Bit 0: Action bit: write 1 to request a RRM-UDRA command..

SEQUENCER_CTRL

SEQUENCER_CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DISABLE_SEQ rw	GEN_SEQ_TRIGGER w

Toggle fields

GEN_SEQ_TRIGGER

Bit 0: Action bit: write 1 to generate a trigger event on Sequencer..

DISABLE_SEQ

Bit 1: Enable/disable the Sequencer.

ABSOLUTE_TIME

ABSOLUTE_TIME register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ABSOLUTE_TIME r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABSOLUTE_TIME r

Toggle fields

ABSOLUTE_TIME

Bits 0-31: Indicate the interpolated absolute..

SCM_COUNTER_VAL

SCM_COUNTER_VAL register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SCM_COUNTER_CURRVAL r

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SCM_COUNTER_CURRVAL

Bits 0-14: Slow Clock Measurement: number of 16 MHz clock cycles contained in 32 slow clock periods..

SCM_MIN_MAX

SCM_MIN_MAX register

Offset: 0x14, size: 32, reset: 0x00007FFF, access: read-write

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLEAR_MIN_MAX w	SCM_COUNTER_MAXVAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SCM_COUNTER_MINVAL r

Toggle fields

SCM_COUNTER_MINVAL

Bits 0-14: Slow Clock Measurement: minimum SCM_COUNTER value seen since the counter is ON and since last clear request..

SCM_COUNTER_MAXVAL

Bits 16-30: Slow Clock Measurement: maximum SCM_COUNTER value seen since the counter is ON and since last clear request..

CLEAR_MIN_MAX

Bit 31: Write 1' to clear the SCM_COUNTER_MINVAL and SCM_COUNTER_MAXVAL bit fields..

WAKEUP_IRQ_STATUS

WAKEUP_IRQ_STATUS register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RFIP_WAKEUP_F rw	CPU_WAKEUP_F rw

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CPU_WAKEUP_F

Bit 0: Set when the interpolated absolute time matches the CPU_WAKEUPTIME while WAKEUP_CTRL..

RFIP_WAKEUP_F

Bit 1: Set when the interpolated absolute time matches the RFIP_WAKEUPTIME while WAKEUP_CTRL..

MR_SUBG

0x49000000:

7/71 fields covered.

Toggle register map

Offset	Name	7	6	5	4	3	2	1	0
0x0	RF_FSM0_TIMEOUT	ENA_RFREG_TIMER
0x4	RF_FSM1_TIMEOUT	SYNTH_SETUP_TIMER
0x8	RF_FSM2_TIMEOUT	VCO_CALIB_LOCK_TIMER
0xc	RF_FSM3_TIMEOUT	VCO_LOCK_TIMER
0x10	RF_FSM4_TIMEOUT	EN_RX_TIMER
0x14	RF_FSM5_TIMEOUT	EN_PA_TIMER
0x18	RF_FSM6_TIMEOUT	PA_DWN_ANA_TIMER
0x1c	RF_FSM7_TIMEOUT	EN_LNA_TIMER
0x20	AFC0_CONFIG	AFC_FAST_GAIN_LOG2				AFC_SLOW_GAIN_LOG2
0x24	AFC1_CONFIG	AFC_FAST_PERIOD
0x28	AFC2_CONFIG	AFC_FREEZE_ON_SYNC	AFC_EN	AFC_MODE	AFC_PD_LEAKAGE
0x2c	AFC3_CONFIG	AFC_REINIT_OPTION		AFC_TH_SIGN_PERM				AFC_SIGN_PERM_CHECK	AFC_INIT_MODE
0x30	CLKREC_CTRL0	PSTFLT_LEN	CLKREC_P_GAIN_FAST			CLKREC_I_GAIN_FAST
0x34	CLKREC_CTRL1	CLKREC_ALGO_SEL	CLKREC_P_GAIN_SLOW			CLKREC_I_GAIN_SLOW
0x38	DCREM_CTRL0	TRACK_GAIN			START_GAIN
0x40	IQC_CTRL0	SLOW_GAIN				FAST_GAIN
0x44	IQC_CTRL1	QPD_ATTACK
0x48	IQC_CTRL2	QPD_DECAY
0x4c	IQC_CTRL3					FAST_TIME
0x50	AGC_ANA_ENG	RFD_RX_PGA_AGCGAIN			RFD_RX_ATTEN_AGCGAIN				FORCE_AGC_GAINS
0x54	AGC0_CTRL	AGC_EN	AGC_START_ONHOLD	AGC_HOLD_TIME
0x58	AGC1_CTRL	AGC_MAX_THR				AGC_MIN_THR
0x5c	AGC2_CTRL	AGC_HIGH_ATTEN_MODE	AGC_FREEZE_ON_STEADY	AGC_FREEZE_ON_SYNC	AGC_START_MAX_ATTEN	AGC_MEAS_TIME
0x60	AGC3_CTRL	AGC_MAX_ATTEN				AGC_MIN_ATTEN
0x64	AGC4_CTRL					AGC_FREEZE_THR
0xa0	AGC_PGA_HWTRIM_OUT					AGC_HW_PGA_TRIM
0xa8	PA_REG					PA_DEGEN_ON		CFG_FILT
0xac	PA_HWTRIM_OUT	PA_HW_DEGEN_TRIM
0xbc	RSSI_FLT	RSSI_FLT				OOK_PEAK_DECAY
0xc8	SYNTH2_ANA_ENG					RFD_PLL_LD_WIN_ACC	RFD_PLL_VCO_ALC_AMP
0xe8	RXADC_HWDELAYTRIM_OUT			RXADC_HW_DELAYTRIM_Q			RXADC_HW_DELAYTRIM_I
0xf4	RX_AAF_HWTRIM_OUT					AAF_HW_FCTRIM
0x100	SINGEN_ANA_ENG						RFD_SINGEN_LBE	RFD_SINGEN_DIV2_PUP	RFD_SINGEN_ENA
0x108	RF_INFO_OUT	RFSUBG_ID				FQCY_BAND_ID
0x124	RF_FSM8_TIMEOUT	SYNTH_PDWN_TIMER
0x128	RF_FSM9_TIMEOUT	END_RX_TIMER
0x12c	RF_FSM10_TIMEOUT	END_TX_TIMER
0x144	SUBG_DIG_CTRL0								FORCE_GPIO_OUTPUT
0x148	RX_CHAIN_ENG							PGA_PRECH_ENA	LNA_ISOL_ENA
0x14c	DEMOD_DIG_ENG						RX_BLANKING_LENGTH

Toggle registers

RF_FSM0_TIMEOUT

RF_FSM0_TIMEOUT register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ENA_RFREG_TIMER rw

Toggle fields

ENA_RFREG_TIMER

Bits 0-7: Timeout for the RF regulator startup (duration in ENA_RF_REG state).

RF_FSM1_TIMEOUT

RF_FSM1_TIMEOUT register

Offset: 0x4, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTH_SETUP_TIMER rw

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SYNTH_SETUP_TIMER

Bits 0-7: Timeout management for the RF regulator to stabilize after RF PLL power on.

RF_FSM2_TIMEOUT

RF_FSM2_TIMEOUT register

Offset: 0x8, size: 32, reset: 0x00000050, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								VCO_CALIB_LOCK_TIMER rw

Toggle fields

VCO_CALIB_LOCK_TIMER

Bits 0-7: Timeout for the RF PLL calibration + RF PLL lock (duration in CALIB_VCO+LOCKRXTX state).

RF_FSM3_TIMEOUT

RF_FSM3_TIMEOUT register

Offset: 0xc, size: 32, reset: 0x00000028, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								VCO_LOCK_TIMER rw

Toggle fields

VCO_LOCK_TIMER

Bits 0-7: Timeout for the RF PLL lock event when no calibration is requested (duration in LOCKRXTX state).

RF_FSM4_TIMEOUT

RF_FSM4_TIMEOUT register

Offset: 0x10, size: 32, reset: 0x0000000F, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EN_RX_TIMER rw

Toggle fields

EN_RX_TIMER

Bits 0-7: Timeout for the analog RX chain setup (duration in EN_RX state).

RF_FSM5_TIMEOUT

RF_FSM5_TIMEOUT register

Offset: 0x14, size: 32, reset: 0x00000019, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EN_PA_TIMER rw

Toggle fields

EN_PA_TIMER

Bits 0-7: Timeout for the analog PA (DAC) setup (duration in EN_PA state).

RF_FSM6_TIMEOUT

RF_FSM6_TIMEOUT register

Offset: 0x18, size: 32, reset: 0x00000019, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PA_DWN_ANA_TIMER rw

Toggle fields

PA_DWN_ANA_TIMER

Bits 0-7: Timeout for the analog PA (DAC) ramp down (duration in PA_DWN_ANA state).

RF_FSM7_TIMEOUT

RF_FSM7_TIMEOUT register

Offset: 0x1c, size: 32, reset: 0x00000005, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EN_LNA_TIMER rw

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EN_LNA_TIMER

Bits 0-7: Timeout for the analog RX chain signals settlement once PGA precharge is shut down (duration in EN_LNA state).

AFC0_CONFIG

AFC0_CONFIG register

Offset: 0x20, size: 32, reset: 0x00000025, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AFC_FAST_GAIN_LOG2 rw				AFC_SLOW_GAIN_LOG2 rw

Toggle fields

AFC_SLOW_GAIN_LOG2

Bits 0-3: AFC loop gain in slow mode (2's log).

AFC_FAST_GAIN_LOG2

Bits 4-7: AFC loop gain in fast mode (2's log).

AFC1_CONFIG

AFC1_CONFIG register

Offset: 0x24, size: 32, reset: 0x00000018, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AFC_FAST_PERIOD rw

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AFC_FAST_PERIOD

Bits 0-7: Length of the AFC fast period (in number of samples unit).

AFC2_CONFIG

AFC2_CONFIG register

Offset: 0x28, size: 32, reset: 0x000000C8, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AFC_FREEZE_ON_SYNC rw	AFC_EN rw	AFC_MODE rw	AFC_PD_LEAKAGE rw

Toggle fields

AFC_PD_LEAKAGE

Bits 0-4: AFC Peak Detection leakage..

AFC_MODE

Bit 5: Select AFC mode:.

AFC_EN

Bit 6: Enable AFC..

AFC_FREEZE_ON_SYNC

Bit 7: Freeze AFC correction upon SYNC word detection.

AFC3_CONFIG

AFC3_CONFIG register

Offset: 0x2c, size: 32, reset: 0x000000E8, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AFC_REINIT_OPTION rw		AFC_TH_SIGN_PERM rw				AFC_SIGN_PERM_CHECK rw	AFC_INIT_MODE rw

Toggle fields

AFC_INIT_MODE

Bit 0: Control the initialization phase of the AFC and clock recovery algorithms:.

AFC_SIGN_PERM_CHECK

Bit 1: Enable the check of sign permanence of AFC corrected signal..

AFC_TH_SIGN_PERM

Bits 2-5: Threshold of chech sign permanence mechanism..

AFC_REINIT_OPTION

Bits 6-7: Select the AFC reinitialization option:.

CLKREC_CTRL0

CLKREC_CTRL0 register

Offset: 0x30, size: 32, reset: 0x000000B8, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PSTFLT_LEN rw	CLKREC_P_GAIN_FAST rw			CLKREC_I_GAIN_FAST rw

Toggle fields

CLKREC_I_GAIN_FAST

Bits 0-3: Integral fast gain for the clock recovery loop (PLL mode only).

CLKREC_P_GAIN_FAST

Bits 4-6: Clock recovery fast loop gain (log2).

PSTFLT_LEN

Bit 7: Control the length of the demodulator post-filter.

CLKREC_CTRL1

CLKREC_CTRL1 register

Offset: 0x34, size: 32, reset: 0x0000005C, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CLKREC_ALGO_SEL rw	CLKREC_P_GAIN_SLOW rw			CLKREC_I_GAIN_SLOW rw

Toggle fields

CLKREC_I_GAIN_SLOW

Bits 0-3: Integral slow gain for the clock recovery loop (PLL mode only).

CLKREC_P_GAIN_SLOW

Bits 4-6: Clock recovery slow loop gain (log2).

CLKREC_ALGO_SEL

Bit 7: Symbol timing recovery algorithm selection.

DCREM_CTRL0

DCREM_CTRL0 register

Offset: 0x38, size: 32, reset: 0x000000E8, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TRACK_GAIN rw			START_GAIN rw

Toggle fields

START_GAIN

Bits 0-4: Filter gain in start mode for the DC removal block..

TRACK_GAIN

Bit 7: Filter gain in track mode for the DC removal block..

IQC_CTRL0

IQC_CTRL0 register

Offset: 0x40, size: 32, reset: 0x000000E3, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SLOW_GAIN rw				FAST_GAIN rw

Toggle fields

FAST_GAIN

Bits 0-3: Gain of the correction loop in fast mode..

SLOW_GAIN

Bits 4-7: Gain of the correction loop in slow mode..

IQC_CTRL1

IQC_CTRL1 register

Offset: 0x44, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								QPD_ATTACK rw

Toggle fields

QPD_ATTACK

Bits 0-7: Attack coefficient for QPD:.

IQC_CTRL2

IQC_CTRL2 register

Offset: 0x48, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								QPD_DECAY rw

Toggle fields

QPD_DECAY

Bits 0-7: Decay coefficient for QPD:.

IQC_CTRL3

IQC_CTRL3 register

Offset: 0x4c, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												FAST_TIME rw

Toggle fields

FAST_TIME

Bits 0-3: Duration of the fast mode..

AGC_ANA_ENG

AGC_ANA_ENG register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RFD_RX_PGA_AGCGAIN rw			RFD_RX_ATTEN_AGCGAIN rw				FORCE_AGC_GAINS rw

Toggle fields

FORCE_AGC_GAINS

Bit 0: Select the mode for AGC analog part:.

RFD_RX_ATTEN_AGCGAIN

Bits 1-4: Attenuation at LNA level by step of 6dB with thermometric code:.

RFD_RX_PGA_AGCGAIN

Bits 5-7: Attenuation at PGA level by step of 6dB with binary code:.

AGC0_CTRL

AGC0_CTRL register

Offset: 0x54, size: 32, reset: 0x00000099, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AGC_EN rw	AGC_START_ONHOLD rw	AGC_HOLD_TIME rw

Toggle fields

AGC_HOLD_TIME

Bits 0-5: AGC hold time..

AGC_START_ONHOLD

Bit 6: Start the AGC with a hold phase..

AGC_EN

Bit 7: Enable the AGC.

AGC1_CTRL

AGC1_CTRL register

Offset: 0x58, size: 32, reset: 0x00000062, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AGC_MAX_THR rw				AGC_MIN_THR rw

Toggle fields

AGC_MIN_THR

Bits 0-3: Minimum signal threshold..

AGC_MAX_THR

Bits 4-7: Maximum signal threshold..

AGC2_CTRL

AGC2_CTRL register

Offset: 0x5c, size: 32, reset: 0x000000AF, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AGC_HIGH_ATTEN_MODE rw	AGC_FREEZE_ON_STEADY rw	AGC_FREEZE_ON_SYNC rw	AGC_START_MAX_ATTEN rw	AGC_MEAS_TIME rw

Toggle fields

AGC_MEAS_TIME

Bits 0-3: Measure time..

AGC_START_MAX_ATTEN

Bit 4: Start the AGC with maximum attenuation..

AGC_FREEZE_ON_SYNC

Bit 5: Enable the freeze on SYNC detection feature.

AGC_FREEZE_ON_STEADY

Bit 6: Enable the autofreeze feature.

AGC_HIGH_ATTEN_MODE

Bit 7: Enable the high attenuation mode..

AGC3_CTRL

AGC3_CTRL register

Offset: 0x60, size: 32, reset: 0x00000090, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								AGC_MAX_ATTEN rw				AGC_MIN_ATTEN rw

Toggle fields

AGC_MIN_ATTEN

Bits 0-3: Minimum AGC attenuation..

AGC_MAX_ATTEN

Bits 4-7: Maximum AGC attenuation..

AGC4_CTRL

AGC4_CTRL register

Offset: 0x64, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_FREEZE_THR rw

Toggle fields

AGC_FREEZE_THR

Bits 0-3: Signal threshold for the autofreeze feature..

AGC_PGA_HWTRIM_OUT

AGC_PGA_HWTRIM_OUT register

Offset: 0xa0, size: 32, reset: 0x00000008, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AGC_HW_PGA_TRIM r

Toggle fields

AGC_HW_PGA_TRIM

Bits 0-3: AGC PGA calibration information loaded by HW from the SoC flash..

PA_REG

PA_REG register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PA_DEGEN_ON rw		CFG_FILT rw

Toggle fields

CFG_FILT

Bits 0-1: FIR configuration:.

PA_DEGEN_ON

Bit 3: Enable a 'degeneration' mode, which introduces a pre-distortion to linearize the power control curve..

PA_HWTRIM_OUT

PA_HWTRIM_OUT register

Offset: 0xac, size: 32, reset: 0x00000088, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PA_HW_DEGEN_TRIM r

Toggle fields

PA_HW_DEGEN_TRIM

Bits 4-7: MSB part meaning:.

RSSI_FLT

RSSI_FLT register

Offset: 0xbc, size: 32, reset: 0x000000E0, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RSSI_FLT rw				OOK_PEAK_DECAY rw

Toggle fields

OOK_PEAK_DECAY

Bits 0-3: Peak decay control for OOK: 3 slow decay; 0 fast decay.

RSSI_FLT

Bits 4-7: Gain of the RSSI filter.

SYNTH2_ANA_ENG

SYNTH2_ANA_ENG register

Offset: 0xc8, size: 32, reset: 0x0000004C, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												RFD_PLL_LD_WIN_ACC rw	RFD_PLL_VCO_ALC_AMP rw

Toggle fields

RFD_PLL_VCO_ALC_AMP

Bits 0-2: Select the level of max VCO amplitude in amplitude level control loop..

RFD_PLL_LD_WIN_ACC

Bit 3: Select the PLL lock detector window selection:.

RXADC_HWDELAYTRIM_OUT

RXADC_HWDELAYTRIM_OUT register

Offset: 0xe8, size: 32, reset: 0x0000001B, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RXADC_HW_DELAYTRIM_Q r			RXADC_HW_DELAYTRIM_I r

Toggle fields

RXADC_HW_DELAYTRIM_I

Bits 0-2: Control bits of the RX ADC loop delay for I channel (from SoC Flash)..

RXADC_HW_DELAYTRIM_Q

Bits 3-5: Control bits of the RX ADC loop delay for Q channel (from SoC Flash)..

RX_AAF_HWTRIM_OUT

RX_AAF_HWTRIM_OUT register

Offset: 0xf4, size: 32, reset: 0x00000006, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												AAF_HW_FCTRIM r

Toggle fields

AAF_HW_FCTRIM

Bits 0-3: AAF calibration information loaded by HW..

SINGEN_ANA_ENG

SINGEN_ANA_ENG register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													RFD_SINGEN_LBE rw	RFD_SINGEN_DIV2_PUP rw	RFD_SINGEN_ENA rw

Toggle fields

RFD_SINGEN_ENA

Bit 0: Enable SINGEN signal for the RFSUBGanalog IP..

RFD_SINGEN_DIV2_PUP

Bit 1: This bit value is directly connected to the RFSUBG analog IP pin..

RFD_SINGEN_LBE

Bit 2: This bit value is directly connected to the RFSUBG analog IP pin..

RF_INFO_OUT

RF_INFO_OUT register

Offset: 0x108, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RFSUBG_ID r				FQCY_BAND_ID r

Toggle fields

FQCY_BAND_ID

Bits 0-3: FQCY_BAND_ID[3:0]: Indicates the version of the RFSUBG IP embedded in the device.

RFSUBG_ID

Bits 4-7: Indicate the version of the analog RFSUBG IP embedded in the device.

RF_FSM8_TIMEOUT

RF_FSM8_TIMEOUT register

Offset: 0x124, size: 32, reset: 0x0000000A, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SYNTH_PDWN_TIMER rw

Toggle fields

SYNTH_PDWN_TIMER

Bits 0-7: Timeout management for the RF regulator to stabilize after PLL shut down.

RF_FSM9_TIMEOUT

RF_FSM9_TIMEOUT register

Offset: 0x128, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								END_RX_TIMER rw

Toggle fields

END_RX_TIMER

Bits 0-7: Timeout management for the RF regulator to stabilize after analog RX chain shut down.

RF_FSM10_TIMEOUT

RF_FSM10_TIMEOUT register

Offset: 0x12c, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								END_TX_TIMER rw

Toggle fields

END_TX_TIMER

Bits 0-7: Timeout management for the RF regulator to stabilize after clock stops on the analog PA block.

SUBG_DIG_CTRL0

SUBG_DIG_CTRL0 register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															FORCE_GPIO_OUTPUT rw

Toggle fields

FORCE_GPIO_OUTPUT

Bit 0: Option for the direct GPIO signal output.

RX_CHAIN_ENG

RX_CHAIN_ENG register

Offset: 0x148, size: 32, reset: 0x00000003, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														PGA_PRECH_ENA rw	LNA_ISOL_ENA rw

Toggle fields

LNA_ISOL_ENA

Bit 0: Option for LNA during the EN_RX state of the Radio FSM:.

PGA_PRECH_ENA

Bit 1: Option for PGA precharge during the EN_RX state of the Radio FSM:.

DEMOD_DIG_ENG

DEMOD_DIG_ENG register

Offset: 0x14c, size: 32, reset: 0x00000003, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													RX_BLANKING_LENGTH rw

Toggle fields

RX_BLANKING_LENGTH

Bits 0-2: Number of data samples at RX start for which the signal at the output of the channel filter is kept forced to zero:.

PWRC

0x48500000:

20/113 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1								ENBORL	SELBORH		ENBORH	APC	IBIAS_RUN_STATE	IBIAS_RUN_AUTO	ENSDNBOR	LPMS
0x4	CR2		RFREGON_STATUS	RFREGRDY	RFREGBYP	RFREGCEXT	RFREGEN	ENTS	GPIORET	LPREG_VH_STATUS	LPREG_FORCE_VH	RAMRET1	DBGRET	PVDLS			PVDE
0x8	IEWU						EWLPAWUR	EWMRSUBGHCPU	EWMRSUBG				EIWL4	EIWL3	EIWL2	EIWL1	EIWL0
0xc	IWUP						WLPAWURP	WMRSUBGHCPUP	WMRSUBGHP				IWUP4	IWUP3	IWUP2	IWUP1	IWUP0
0x10	IWUF						WLPAWURF	WMRSUBGHCPUF	WMRSUBGF				IWUF4	IWUF3	IWUF2	IWUF1	IWUF0
0x14	SR2	IOBOOTVAL				PVDO		REGMS	REGLPS	IOBOOTVAL2					SMPSRDY	SMPSENR	SMPSBYPR
0x1c	CR5	SMPS_BOF_DYN	SMPS_PRECH_CUR_SEL		CLKDETR_DISABLE	SMPS_ENA_DCM	NOSMPS	SMPSFBYP	SMPSLPOPEN	NOSMPS_BOF	SMPS_BOF_STATIC	SMPSBOMSEL		SMPSLVL
0x20	PUCRA	PUA
0x24	PDCRA	PDA
0x28	PUCRB	PUB
0x2c	PDCRB	PDB
0x30	EWUA	EWUA
0x34	WUPA	WUPA
0x38	WUFA	WUFA
0x40	EWUB	EWUB
0x44	WUPB	WUPB
0x48	WUFB	WUFB
0x4c	SDWN_WUEN																WUEN
0x50	SDWN_WUPOL																WUPOL
0x54	SDWN_WUF																WUF
0x58	BOF_TUNE													BOF_TUNE
0x84	DBGR	DIS_PRECH					KELVIN_TEST			SMPSFRDY							DEEPSTOP2
0x88	EXTSRR						RFPHASEF	DEEPSTOPF
0x8c	DBGSMPS	BOF_CUR_SEL		ILIM_BOOST	DIS_ILIM	TEST_OL	DIS_BIG_MOS	CTLRES_RAMP	TESTILIM	NO_STUP	HOT_STUP	TESTKEL		TESTDIG
0x90	TRIMR			BOF_TRIM			SMPS_TRIM			TRIM_MR				SPARE	RFD_REG_TRIM
0x94	ENGTRIM			SMPS_TRIM			SMPSTRIMEN	TRIM_MR				TRIMMREN	SPARE	TRIM_RFDREG			TRIMRFDREGEN
0x98	DBG_STATUS_REG1						FLASH_FSM_STATE								SMPS_FSM_STATE
0x9c	DBG_STATUS_REG2							RAM_FSM_STATE						PMU_FSM_STATE
0xa0	ENGTRIM2													BOF_TRIM			BOFTRIMEN

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000114, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							ENBORL rw	SELBORH rw		ENBORH rw	APC rw	IBIAS_RUN_STATE rw	IBIAS_RUN_AUTO rw	ENSDNBOR rw	LPMS rw

Toggle fields

LPMS

Bit 0: LPMS Low Power Mode Selection Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. - 0: Deep Stop mode (default) - 1: Shutdown mode.

ENSDNBOR

Bit 1: ENSDNBOR: Enable BOR supply monitoring during shutdown mode. - 1: the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode - 0: the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode..

IBIAS_RUN_AUTO

Bit 2: IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. - 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) - 1: IBIAS control is automatic (default)..

IBIAS_RUN_STATE

Bit 3: IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is disabled. - 0: IBIAS control is disabled (default). - 1: IBIAS control is enabled..

APC

Bit 4: APC Apply Pull-up and pull-down configuration from CPU - 1: the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. - 0: the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os..

ENBORH

Bit 5: ENBORH: enable BORH configuration - 1: BORH is enabled, threshold level depends on SELBOR[1:0] - 0: BORH off (VBOR0): threshold level for above 1.60V voltage operation..

SELBORH

Bits 6-7: SELBORH[1:0]: BORH selection of Vbor threshold - 11: BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation. - 10: BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation - 01: BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation - 00: BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation..

ENBORL

Bit 8: ENBORL: Enable BORL reset supervising during RUN mode. - 0: No BORL is monitored during RUN mode. - 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/13 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	RFREGON_STATUS r	RFREGRDY r	RFREGBYP rw	RFREGCEXT rw	RFREGEN rw	ENTS rw	GPIORET rw	LPREG_VH_STATUS r	LPREG_FORCE_VH rw	RAMRET1 rw	DBGRET rw	PVDLS rw			PVDE rw

Toggle fields

PVDE

Bit 0: PVDE Programmable Voltage Detector Enable When this bit is set the Power Voltage Detector is enabled.

PVDLS

Bits 1-3: PVDLS[2:0] Programmable Voltage Detector Level selection - 000: 2.05 V - Lowest level - 001: 2.20 V - 010: 2.36 V - 011: 2.52 V - 100: 2.64 V - 101: 2.81 V - 110: 2.91 V - Highest level - 111: External input analog voltage (compare internally to VBGP; When external input VBGP then PVDO=1).

DBGRET

Bit 4: DBGRET: PA2 and PA3 retention enable after DEEPSTOP - 0: PA2, PA3 don't retain their status exiting from DEEPSTOP (default). - 1: PA2, PA3 retain their status exiting from DEEPSTOP..

RAMRET1

Bit 5: RAMRET1: RAM1 retention during low power mode - 1: RAM1 bank is powered during low power mode - 0: RAM1 bank is disabled during low power mode (by default).

LPREG_FORCE_VH

Bit 6: force LPREG=1.2V during DEEPSTOP - 1: Force LPREG=1.2V during DEEPSTOP - 0: No Force (Default) Note LPREG= 1.2v can still apply when LCDEN or COMP.SCALEREN request it.

LPREG_VH_STATUS

Bit 7: status LPREG VH (1.2v) during DEEPSTOP - 1: LPREG=1.2V during DEEPSTOP - 0: LPREG=1V during DEEPSTOP.

GPIORET

Bit 8: GPIORET: GPIO retention enable. - 0: Release GPIO retention after deepstop (Should be reset after restore Context) - 1: Enable GPIO Retention during deepstop (Must be set before deepstop).

ENTS

Bit 9: ENTS: Enable Temperature Sensor - 1: Temperature sensor is enabled - 0: Temperature sensor is disabled.

RFREGEN

Bit 10: RFREGEN: RF Regulator Enable - 1: Enable RF Regulator - 0: Disable RF Regulator (Note: RF Regulator can still be enabled by the RFSUGB or RCC_CR.HSEON).

RFREGCEXT

Bit 11: RFREGCEXT: RF Regulator External Supply Bypass - 1: External supply bypass capability - 0: Internal supply only.

RFREGBYP

Bit 12: RFREGBYP: RF Regulator Bypass Enable - 1: LDO output connected to VSMPS. - 0: internally generated 1.2V.

RFREGRDY

Bit 13: RFDREGRDY: RF Regulator Ready flag - 1: RF Regulator is ready - 0: RF Regulator is not ready.

RFREGON_STATUS

Bit 14: RFREGON_STATUS: RF Regulator On Status - 1: RF Regulator is enabled - 0: RF Regulator is disabled.

IEWU

IEWU register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					EWLPAWUR rw	EWMRSUBGHCPU rw	EWMRSUBG rw				EIWL4 rw	EIWL3 rw	EIWL2 rw	EIWL1 rw	EIWL0 rw

Toggle fields

EIWL0

Bit 0: EWL0 Enable Internal WakeUp line LPUART When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. - 0: wakeup disabled. - 1: wakeup enabled..

EIWL1

Bit 1: EIWL1 Enable Internal WakeUp line RTC When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. - 0: wakeup disabled. - 1: wakeup enabled..

EIWL2

Bit 2: EIWL2 Enable Internal WakeUp line LCD When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. - 0: wakeup disabled. - 1: wakeup enabled..

EIWL3

Bit 3: EIWL3 Enable Internal Wakeup line COMP When this bit is set the COMP wakeup is enabled and an edge will trigger a COMP wakeup event - 0: wakeup disabled. - 1: wakeup enabled..

EIWL4

Bit 4: EIWL4 Enable Internal Wakeup line LCSC When this bit is set the LCSC wakeup is enabled and an edge will trigger a LCSC wakeup event - 0: wakeup disabled. - 1: wakeup enabled..

EWMRSUBG

Bit 8: EWMRSUB Wakeup MRSUBG Enable When this bit is set the MRSUBG wakeup is enabled and a rising edge will trigger a MRSUBG wakeup event - 0: MRSUBG wakeup disabled. - 1: MRSUBG wakeup enabled..

EWMRSUBGHCPU

Bit 9: EWMRSUBGHCPU Wakeup MRSUBG Host CPU Enable When this bit is set the MRSUBG HOST CPU wakeup is enabled and a rising edge will trigger a MRSUBG Host CPU wakeup event - 0: MRSUBG Host CPU wakeup disabled. - 1: MRSUBG Host CPU wakeup enabled..

EWLPAWUR

Bit 10: EWLPAWUR: Wakeup Bubble Enable When this bit is set the Bubble wakeup is enabled and a rising edge will trigger a LPAWUR wakeup event - 0: LPAWUR wakeup disabled. - 1: LPAWUR wakeup enabled..

IWUP

IWUP register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					WLPAWURP rw	WMRSUBGHCPUP rw	WMRSUBGHP rw				IWUP4 rw	IWUP3 rw	IWUP2 rw	IWUP1 rw	IWUP0 rw

Toggle fields

IWUP0

Bit 0: IWUP0: Wakeup polarity for internal wakeup line 0 event (LPUART). - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

IWUP1

Bit 1: IWUP1: Wakeup polarity for internal wakeup line 1 event (RTC). - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

IWUP2

Bit 2: IWUP2: Wakeup polarity for internal wakeup line 2 event (LCD). - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

IWUP3

Bit 3: IWUP3: Wakeup polarity for internal wakeup line 3 event (COMP). - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

IWUP4

Bit 4: IWUP4: Wakeup polarity for internal wakeup line 4 event (LCSC). - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

WMRSUBGHP

Bit 8: WMRSUBGHP: Wakeup polarity for internal wakeup MRSUBG event - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

WMRSUBGHCPUP

Bit 9: WMRSUBGHCPUP: Wakeup polarity for internal wakeup MRSUBG Host CPU event - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

WLPAWURP

Bit 10: WLPAWURP: Wakeup polarity for wakeup LPAWUR event. - 0: Detection of wakeup event on rising edge (default). - 1: Detection of wakeup event on falling edge..

IWUF

IWUF register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					WLPAWURF rw	WMRSUBGHCPUF rw	WMRSUBGF rw				IWUF4 rw	IWUF3 rw	IWUF2 rw	IWUF1 rw	IWUF0 rw

Toggle fields

IWUF0

Bit 0: IWUF0: Internal wakeup flag (LPUART). - 0: no wakeup from LPUART occurred since last clear. - 1: a wakeup from LPUART occurred since last clear. Cleared by writing 1 in this bit..

IWUF1

Bit 1: IWUF1: Internal wakeup flag (RTC). - 0: no wakeup from RTC occurred since last clear. - 1: a wakeup from RTC occurred.

IWUF2

Bit 2: IWUF2: Internal wakeup flag (LCD). - 0: no wakeup from LCD occurred since last clear. - 1: a wakeup from LCD occurred since last clear. Cleared by writing 1 in this bit..

IWUF3

Bit 3: IWUF3: Internal wakeup flag (COMP). - 0: no wakeup from COMP occurred since last clear. - 1: a wakeup from COMP occurred since last clear. Cleared by writing 1 in this bit..

IWUF4

Bit 4: IWUF4: Internal wakeup flag (LCSC). - 0: no wakeup from LCSC occurred since last clear. - 1: a wakeup from LCSC occurred since last clear. Cleared by writing 1 in this bit..

WMRSUBGF

Bit 8: WMRSUBGF Wakeup MRSUBG Flag This bit is set by hardware when a MRSUBG wakeup is detected It is cleared by a reset pad or by software writing 1 in this bit field. - 0: No MRSUBG Wakeup detected - 1: MRSUBG Wakeup detected writting 1 in this bit, clears the interrupt.

WMRSUBGHCPUF

Bit 9: WMRSUBGHCPUF Wakeup MRSUBG HOST CPU Flag (cf. user manual) This bit is set by hardware when a MRSUBG HOST CPU wakeup is detected It is cleared by a reset pad or by software writing 1 in this bit field. - 0: No MRSUBG Host CPU wakeup detected - 1: MRSUBG Host CPU wakeup detected writting 1 in this bit, clears the interrupt.

WLPAWURF

Bit 10: WLPAWURF Wakeup LPAWUR Flag (cf. user manual) This bit is set by hardware when a LPAWUR wakeup is detected It is cleared by a reset pad or by software writing 1 in this bit field. - 0: No LPAWUR wakeup detected - 1: LPAWUR wakeup detected writting 1 in this bit, clears the interrupt.

SR2

SR2 register

Offset: 0x14, size: 32, reset: 0x0000F3F6, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOBOOTVAL r				PVDO r		REGMS r	REGLPS r	IOBOOTVAL2 r					SMPSRDY r	SMPSENR r	SMPSBYPR r

Toggle fields

SMPSBYPR

Bit 0: SMPSBYPR: SMPS Force Bypass Control Replica This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state..

SMPSENR

Bit 1: SMPSENR: SMPS Enable Control Replica This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state..

SMPSRDY

Bit 2: SMPSRDY: SMPS Ready Status This bit provides the information whether SMPS is ready. - 0: SMPS regulator is not ready - 1: SMPS regulator is ready..

IOBOOTVAL2

Bits 4-7: Bit3: PB15 input value on VDD33 latched at POR Bit2: PB14 input value on VDD33 latched at POR Bit1: PB13 input value on VDD33 latched at POR Bit0: PB12 input value on VDD33 latched at POR.

REGLPS

Bit 8: REGLPS: Regulator Low Power Started This bit provides the information whether low power regulator is ready. - 0: LP regulator is not ready. - 1: LP regulator is ready..

REGMS

Bit 9: REGMS: Main regulator ready status. - 0: The Main regulator is not ready. - 1: The Main regulator is ready..

PVDO

Bit 11: PVDO: Power Voltage Detector Output When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is lower than the selected PVD threshold (CR2.PVDLS).

IOBOOTVAL

Bits 12-15: Bit3: PA11 input value on VDD33 latched at POR Bit2: PA10 input value on VDD33 latched at POR Bit1: PA9 input value on VDD33 latched at POR Bit0: PA8 input value on VDD33 latched at POR.

CR5

CR5 register

Offset: 0x1c, size: 32, reset: 0x00006014, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPS_BOF_DYN rw	SMPS_PRECH_CUR_SEL rw		CLKDETR_DISABLE rw	SMPS_ENA_DCM rw	NOSMPS rw	SMPSFBYP rw	SMPSLPOPEN rw	NOSMPS_BOF rw	SMPS_BOF_STATIC rw	SMPSBOMSEL rw		SMPSLVL rw

Toggle fields

SMPSLVL

Bits 0-3: SMPSLVL[3:0] SMPS Output Level Voltage Selection Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) Vout = 1.2 + 0.05*SMPSOUT (V).

SMPSBOMSEL

Bits 4-5: SMPSBOMSEL: SMPS BOM Selection: - 00: BOM1 - 01: BOM2 (default) - 10: BOM3 - 11: n/a.

SMPS_BOF_STATIC

Bit 6: SMPS_BOF_STATIC: SMPS Bypass on the Fly static - 0 : disabled (by default) - 1 : SMPS Bypass on the fly static is enabled (EN_SW=1).

NOSMPS_BOF

Bit 7: NOSMPS_BOF: No SMPS Mode to be used in accordance to SMPS_BOF_STATIC =1 When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only SMPS_BOF_STATIC=1. - 0 : No effect, SMPS is enabled. (default) - 1 : SMPS is disabled;.

SMPSLPOPEN

Bit 8: SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. - 0 : in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. (default) - 1 : in Low Power mode, SMPS is disabled, output is floating.

SMPSFBYP

Bit 9: SMPSFB Force SMPS Regulator in bypass mode When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. - 0 : no effect (by default) - 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1).

NOSMPS

Bit 10: NOSMPS: No SMPS Mode When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. - 0 : No effect, SMPS is enabled. (Default) - 1 : SMPS is disabled;.

SMPS_ENA_DCM

Bit 11: SMPS_ENA_DCM: enable discontinuous conduction mode - 0 : disable (Default) - 1 : enable.

CLKDETR_DISABLE

Bit 12: CLKDETR_DISABLE: disable SMPS clock detection The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. - 0 : SMPS clock detection enabled (default) - 1 : SMPS clock detection disabled.

SMPS_PRECH_CUR_SEL

Bits 13-14: SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current - 00: 2.5mA - 01: 5mA - 10: 10mA - 11: 20mA (default).

SMPS_BOF_DYN

Bit 15: SMPS_BOF_DYN: SMPS Bypass on the Fly dynamic - 0 : disabled (by default) - 1 : SMPS Bypass on the fly dynamic is enabled (EN_LDO=1).

PUCRA

PUCRA register

Offset: 0x20, size: 32, reset: 0x0000FFF7, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUA rw

Toggle fields

PUA

Bits 0-15: PUA[x] : Pull Up Port A Pull up activation on port A[i] pad when APC bit of PWRC CR1 is set - 1: Pull-Up activated on port A[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRA[x] is reset - 0: Pull-Up not activated on port A[i].

PDCRA

PDCRA register

Offset: 0x24, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PDA rw

Toggle fields

PDA

Bits 0-15: PDA[x]: Pull Down Port A Pull Down activation on port A[i] pad when APC bit of PWRC CR1 is set - 1: Pull-Down activated on Port A[i] when APC bit of PWRC CR1 bit is set - 0: Pull-Down not activated on Port A[i].

PUCRB

PUCRB register

Offset: 0x28, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUB rw

Toggle fields

PUB

Bits 0-15: PUB[x] : Pull Up Port B Pull up activation on port B[i] pad when APC bit of PWRC CR1 is set - 1: Pull-Up activated on port B[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRB[x] is reset - 0: Pull-Up not activated on port B[i].

PDCRB

PDCRB register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PDB rw

Toggle fields

PDB

Bits 0-15: PDB[x]: Pull Down Port B Pull Down activation on port B[i] pad when APC bit of PWRC CR1 is set - 1: Pull-Down activated on Port B[i] when APC bit of PWRC CR1 bit is set - 0: Pull-Down not activated on Port B[i].

EWUA

EWUA register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EWUA rw

Toggle fields

EWUA

Bits 0-15: EWUA[x] Enable WakeUp line PA[x] When this bit is set the PA[x] wakeup line is enabled and a rising or falling edge on wakeup line PA[x] will trigger a CPU wakeup event depending on CR7.WUPA[x] bit..

WUPA

WUPA register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUPA rw

Toggle fields

WUPA

Bits 0-15: WUPA[x] Wake-up Line PA[x] Polarity This bit defines the polarity used for event detection on external wake-up line PA[x] - 0: Detection on high level (rising edge) - 1: Detection on low level (falling edge).

WUFA

WUFA register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUFA rw

Toggle fields

WUFA

Bits 0-15: WUFA[x] WakeUp Flag PA[x] This bit is set when a wakeup is detected on wakeup line PA[x]. It is cleared by a reset pad or by writing 1 in this bit field. Writing 1 this bit, clears the interrupt:.

EWUB

EWUB register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EWUB rw

Toggle fields

EWUB

Bits 0-15: EWUB[x] Enable WakeUp line PB[x] When this bit is set the PB[x] wakeup line is enabled and a rising or falling edge on wakeup line PB[x] will trigger a CPU wakeup event depending on CR9.WUPB[x] bit..

WUPB

WUPB register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUPB rw

Toggle fields

WUPB

Bits 0-15: WUPB[x] Wake-up Line PB[x] Polarity This bit defines the polarity used for event detection on external wake-up line PB[x] - 0: Detection on high level (rising edge) - 1: Detection on low level (falling edge).

WUFB

WUFB register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUFB rw

Toggle fields

WUFB

Bits 0-15: WUFB[x] WakeUp Flag PB[x] This bit is set when a wakeup is detected on wakeup line PB[x]. It is cleared by a reset pad or by writing 1 in this bit field. Writing 1 this bit, clears the interrupt:.

SDWN_WUEN

SDWN_WUEN register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WUEN rw

Toggle fields

WUEN

Bit 0: WUEN PB0 I/O WakeUp from shutdown Enable When this bit is set the PB0 wakeup from shutdown is enabled so that a rising or falling edge on PB0 (depending on SDWN_WUPOL..WUPOL bit) will trigger a CPU wakeup. It is cleared by a PORESETn. - 0: PB0 wakeup from shutdown disabled - 1: PB0 wakeup from shutdown enabled.

SDWN_WUPOL

SDWN_WUPOL register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WUPOL rw

Toggle fields

WUPOL

Bit 0: WUPOL PB0 I/O WakeUp from shutdown Polarity This bit defines the polarity used for wakeup from shutdown detection on PB0 pin. It is cleared by a PORESETn. - 0: Detection on high level (rising edge) - 1: Detection on low level (falling edge).

SDWN_WUF

SDWN_WUF register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															WUF rw

Toggle fields

WUF

Bit 0: WUF PB0 I/O WakeUp from shutdown Flag This bit is set when a wakeup from shutdown is detected on PB0 pin. It is cleared by a PORESETn or by writing 0 in this bit field. - 0: Shutdown wakeup from PB0 not occurred - 1: Shutdown wakeup from PB0 occurred.

BOF_TUNE

BOF_TUNE register

Offset: 0x58, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BOF_TUNE rw

Toggle fields

BOF_TUNE

Bits 0-3: BOF_TUNE: selection of the Bypass on the Fly LDO output voltage. - 0: 1.2V - 1: 1.2V - 2: 1.2V - 3: 1.3V - 4: 1.4V (Default) - 5: 1.5V - 6: 1.6V - 7: 1.7V - 8: 1.8V - 9: 1.9V - 10: 2V - 11: 2.1V - 12: 2.2V - 13: 2.3V - 14: 2.4V - 15: 2.4V.

DBGR

DBGR register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIS_PRECH rw					KELVIN_TEST rw			SMPSFRDY rw							DEEPSTOP2 rw

Toggle fields

DEEPSTOP2

Bit 0: DEEPSTOP2 low power saving mode emulation enable this bit enable an emulated debug DEEPSTOP low power mode. If emulation is enabled, entering in DEEPSTOP mode, the v12i power domain still enters power saving mode, but its clock and power are maintained..

SMPSFRDY

Bit 7: SMPSFB Force ready check When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. - 0 : no effect (by default) - 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1).

KELVIN_TEST

Bits 8-10: KELVIN_TEST[2:0]: Enable TEST mode Kelvin for LDO_RF (Write protected by IFR3 key) - 000: 0mA (open) (default 0x0) - 001 for 1mA - 010 for 3mA - 011 for 5mA - 100 for 8mA - 101 for 10mA else: 0mA (open) for other combinations..

DIS_PRECH

Bits 13-15: DIS_PRECH[2:0]: disable precharge during deepstop (debug) allowed combination are: - 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) - 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) else: No effect (default 0x0).

EXTSRR

EXTSRR register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					RFPHASEF rw	DEEPSTOPF rw

Toggle fields

DEEPSTOPF

Bit 9: DEEPSTOPF System DeepStop Flag This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field - 0: System has not been in DEEPSTOP mode - 1: System has been in DEEPSTOP mode.

RFPHASEF

Bit 10: RFPHASEF RFPHASE Flag This bit is set by hardware after a S3LP wake-up event (S3LP activation); it is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. - 0: RF IP does not require attention - 1: RF IP awake and requesting system attention.

DBGSMPS

DBGSMPS register

Offset: 0x8c, size: 32, reset: 0x00008000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BOF_CUR_SEL rw		ILIM_BOOST rw	DIS_ILIM rw	TEST_OL rw	DIS_BIG_MOS rw	CTLRES_RAMP rw	TESTILIM rw	NO_STUP rw	HOT_STUP rw	TESTKEL rw		TESTDIG rw

Toggle fields

TESTDIG

Bits 0-3: TESTDIG: SMPS TEST_DIG_3V3[3:0] SMPS control signal.

TESTKEL

Bits 4-5: TESTKEL: SMPS TEST_KEL_3V3[1:0] SMPS control signal.

HOT_STUP

Bit 6: HOT_STUP_3V3 SMPS control signal.

NO_STUP

Bit 7: NO_STUP_3V3 SMPS control signal.

TESTILIM

Bit 8: TESTILIM: SMPS TEST_ILIM_3V3 SMPS control signal.

CTLRES_RAMP

Bit 9: CTLRES_RAM_3V3 SMPS control signal.

DIS_BIG_MOS

Bit 10: DIS_BIG_MOS_3V3 SMPS control signal.

TEST_OL

Bit 11: TEST_OL_3V3 SMPS control signal.

DIS_ILIM

Bit 12: DIS_ILIM_3V3 SMPS control signal.

ILIM_BOOST

Bit 13: ILIM_BOOST_3V3 SMPS current limitation Boost - 0: Max current = 110mA (Default) - 1: Max current = 130mA.

BOF_CUR_SEL

Bits 14-15: BOF_CUR_SEL Bypass On the Fly current limitation - 00 : 20mA - 01 : 40mA - 10 : 60mA (default) - 11 : no limit.

TRIMR

TRIMR register

Offset: 0x90, size: 32, reset: 0x00002304, access: read-only

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		BOF_TRIM r			SMPS_TRIM r			TRIM_MR r				SPARE r	RFD_REG_TRIM r

Toggle fields

RFD_REG_TRIM

Bits 0-2: RFD_REG_TRIM[2:0]: RF LDO Trimming By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. if associated ENGTRIM is enabled the RF LDO trimming can be controlled by the dedicated ENGTRIM register. Default= '100'..

SPARE

Bit 3: .

TRIM_MR

Bits 4-7: TRIM_MR[3:0]: Main Regulator Voltage Trimming By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. if associated ENGTRIM.TRIMMREN is enabled the Main Regulator Voltage can be controlled by the dedicated ENGTRIM.TRIM_MR register. Default= '0000'..

SMPS_TRIM

Bits 8-10: SMPS_TRIM[2:0]: SMPS Output Voltage Trimming By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '011'..

BOF_TRIM

Bits 11-13: BOF_TRIM[2:0]: Bypass On the Fly Output Voltage Trimming By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '100'..

ENGTRIM

ENGTRIM register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SMPS_TRIM rw			SMPSTRIMEN rw	TRIM_MR rw				TRIMMREN rw	SPARE rw	TRIM_RFDREG rw			TRIMRFDREGEN rw

Toggle fields

TRIMRFDREGEN

Bit 0: TRIMRFDREGEN: trimming RFREG enabled - 1: trimming bit applied from ENGTRIM register - 0: trimming bit applied from OBL (can be read on TRIMR register).

TRIM_RFDREG

Bits 1-3: TRIM_RFDREG: RF Regulator Trimming By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMRFDREGEN=1, the startup current can be controlled by this register..

SPARE

Bit 4: .

TRIMMREN

Bit 5: TRIMMREN: trimming MR enabled - 1: trimming bit applied from ENGTRIM register - 0: trimming bit applied from OBL (can be read on TRIMR register).

TRIM_MR

Bits 6-9: TRIM_MR: Main Regulator Output Voltage Trimming By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMMREN=1, the startup current can be controlled by this register..

SMPSTRIMEN

Bit 10: SMPSTRIMEN: trimming SMPS enabled - 1: trimming bit applied from ENGTRIM register - 0: trimming bit applied from OBL (can be read on TRIMR register).

SMPS_TRIM

Bits 11-13: SMPS_TRIM: SMPS Output Voltage Trimming By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.SMPSTRIMEN=1, the SMPS output voltage can be controlled by this register..

DBG_STATUS_REG1

DBG_STATUS_REG1 register

Offset: 0x98, size: 32, reset: 0x00000202, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					FLASH_FSM_STATE r								SMPS_FSM_STATE r

Toggle fields

SMPS_FSM_STATE

Bits 0-2: SMPS_FSM_STATE[2:0]: Indicates the current state of the SMPS FSM inside the PWRC.: - 000: STARTUP - 001: SMPS_REQ - 010: SMPS_RUN - 011: STOP - 100: NOSMPS - 101: PRECHARGE - 110: NOSMPS_BOF.

FLASH_FSM_STATE

Bits 8-10: FLASH_FSM_STATE[2:0]: Indicates the current state of the FLASH FSM inside the PWRC: - 000: STATE1: FLASH POR - 001: STATE2: FLASH PWRUP - 010: STATE3: FLASH READY - 101: STATE4: FLASH SWITCH OFF - 110: STATE5: FLASH PWR DOWN.

DBG_STATUS_REG2

DBG_STATUS_REG2 register

Offset: 0x9c, size: 32, reset: 0x00000201, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						RAM_FSM_STATE r						PMU_FSM_STATE r

Toggle fields

PMU_FSM_STATE

Bits 0-3: PMU_FSM_STATE[3:0]: Indicates the current state of the PMU FSM inside the PWRC. - 0000: POR - 0001: RUN - 0010: DS ENTRY - 0011: WAIT1 - 0100: WAIT2 - 0101: WAIT - 0110: WAIT3 - 0111: WAIT4 - 1000: ISOLATION - 1001: DEEPSTOP - 1010: SHUTDOWN - 1011: DEEPSTOP EXIT.

RAM_FSM_STATE

Bits 8-9: RAM_FSM_STATE[1:0]: Indicates the current state of the RAM FSM inside the PWRC: - 00: POR - 01: POWER UP - 10: READY - 11: OFF.

ENGTRIM2

ENGTRIM2 register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BOF_TRIM rw			BOFTRIMEN rw

Toggle fields

BOFTRIMEN

Bit 0: BOFTRIMEN: trimming BOF enabled - 1: trimming bit applied from ENGTRIM2 register - 0: trimming bit applied from OBL (can be read on TRIMR register).

BOF_TRIM

Bits 1-3: SMPS_TRIM: SMPS Output Voltage Trimming By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.BOFTRIMEN=1, the SMPS output voltage can be controlled by this register..

RCC

0x48400000:

18/160 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR														HSERDY	HSEON	FMRAT	HSIPLLRDY	HSIPLLON	HSEPLLBUFON		HSIRDY	LOCKDET_NSTOP			LSEBYP	LSERDY	LSEON	LSIRDY	LSION
0x4	ICSCR			HSITRIM										HSITRIMOFFSET													LSIBW				LSITRIMOK	LSITRIMEN
0x8	CFGR	CCOPRE			MCOSEL			LCOSEL	SPI3I2SCLKSEL				LCOEN		IOBOOSTEN	CLKSLOWSEL	CLKSLOWSEL		LPUCLKSEL	SMPSDIV		CLKSYSDIV_STATUS			CLKSYSDIV				HSESEL_STATUS	STOPHSI	HSESEL
0xc	CSSWCR			HSITRIMSW					HSISWTRIMEN																	LSEDRV		LSISWBW				LSISWTRIMEN
0x10	KRMR																										KRM					KRM_EN
0x18	CIER																		LCSCRSTIE			LCDRSTIE	LPURSTIE	WDGRSTIE	RTCRSTIE	HSIPLLUNLOCKDETIE	HSIPLLRDYIE	HSERDYIE	HSIRDYIE		LSERDYIE	LSIRDYIE
0x1c	CIFR																		LCSCRSTIF			LCDRSTIF	LPURSTIF	WDGRSTIF	RTCRSTIF	HSIPLLUNLOCKDETIF	HSIPLLRDYIF	HSERDYIF	HSIRDYIF		LSERDYIF	LSIRDYIF
0x20	CSCMDR																								EOFSEQ_IRQ	EOFSEQ_IE	STATUS		CLKSYSDIV_REQ			REQUEST
0x30	AHBRSTR											AESRST		RNGRST						CRCRST									GPIOBRST	GPIOARST		DMARST
0x34	APB0RSTR																DBGMCURST	WDGRST	LCSCRST	RTCRST	DACRST	COMPRST	LCDCRST	SYSCFGRST							TIM16RST	TIM2RST
0x38	APB1RSTR								I2C2RST		I2C1RST							SPI3RST				USARTRST		LPUARTRST				ADCRST				SPI1RST
0x40	APB2RSTR																												LPAWURRST			MRSUBGRST
0x50	AHBENR											AESEN		RNGEN						CRCEN									GPIOBEN	GPIOAEN		DMAEN
0x54	APB0ENR																DBGMCUEN	WDGEN	LCSCEN	RTCEN	DACEN	COMPEN	LCDEN	SYSCFGEN							TIM16EN	TIM2EN
0x58	APB1ENR								I2C2EN		I2C1EN							SPI3EN				USARTEN		LPUARTEN			ADCANAEN	ADCDIGEN				SPI1EN
0x60	APB2ENR																												LPAWUREN			MRSUBGEN
0x80	DBGR									FORCEXO48MREADY	DBGXOEXT	DBGBYPHSI	DBGHSIOFF
0x94	CSR		LOCKUPRSTF	WDGRSTF	SFTRSTF	PORRSTF	PADRSTF		RMVF
0x98	RFSWHSECR													AMPLTHRESH			ISTARTUP		SWXOTUNE						SWXOTUNEEN	GMC
0x9c	RFHSECR																									AMPLREADY	XOTUNE
0xa0	AHBSMENR											AESSMEN		RNGSMEN						CRCSMEN		SRAM1SMEN	SRAM0SMEN						GPIOBSMEN	GPIOASMEN	FLASHSMEN	DMASMEN
0xa4	APB0SMENR																DBGMCUSMEN	WDGSMEN	LCSCSMEN	RTCSMEN	DACSMEN	COMPSMEN	LCDCSMEN	SYSCFGSMEN							TIM16SMEN	TIM2SMEN
0xa8	APB1SMENR								I2C2SMEN		I2C1SMEN							SPI3SMEN				USARTSMEN		LPUARTSMEN				ADCDIGSMEN				SPI1SMEN

Toggle registers

CR

CR register

Offset: 0x0, size: 32, reset: 0x00001400, access: read-write

5/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FMRAT rw	HSIPLLRDY r	HSIPLLON rw	HSEPLLBUFON rw		HSIRDY r	LOCKDET_NSTOP rw			LSEBYP rw	LSERDY r	LSEON rw	LSIRDY r	LSION rw

Toggle fields

LSION

Bit 2: Internal Low Speed oscillator enable Set and reset by software. Reset source only for this field: PORESETn 0: LSI RC oscillator OFF 1: LSI RC oscillator ON.

LSIRDY

Bit 3: Internal Low Speed oscillator Ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. Reset source only for this field: PORESETn 0: LSI RC oscillator not ready 1: LSI RC oscillator ready.

LSEON

Bit 4: External Low Speed Clock enable. Set and reset by software. Reset source only for this field: PORESETn 0: LSE oscillator OFF 1: LSE oscillator ON Note that enablng this bit, the configuration of PB12 and PB13 will be bypassed (whatever DFTMUX or AF selection).

LSERDY

Bit 5: External Low Speed Clock ready flag. Set by hardware to indicate that LSE oscillator is stable. 0: LSE oscillator not ready 1: LSE oscillator ready.

LSEBYP

Bit 6: External Low Speed Clock bypass. Set and reset by software. Reset source only for this field: PORESETn 0: LSE oscillator bypass OFF 1: LSE oscillator bypass ON Note that enablng this bit, the configuration of PB13 will be bypassed (whatever DFTMUX or AF selection).

LOCKDET_NSTOP

Bits 7-9: Lock detector Nstop value When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0..

HSIRDY

Bit 10: Internal High Speed clock ready flag. Set by hardware to indicate that internal RC 64MHz oscillator is stable. This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). 0: internal RC 64 MHz oscillator not ready 1: internal RC 64 MHz oscillator ready.

HSEPLLBUFON

Bit 12: External High Speed Clock Buffer for PLL RF enable. Set and reset by software. 0: HSE PLL Buffer OFF 1: HSE PLL Buffer ON (default).

HSIPLLON

Bit 13: Internal High Speed Clock PLL enable 0: PLL is OFF 1: PLL is ON.

HSIPLLRDY

Bit 14: Internal High Speed Clock PLL ready flag. 0: PLL is unlocked 1: PLL is locked.

FMRAT

Bit 15: Force MRSUBG accurate clock ready status (for debug purpose) 0: no effect 1: active_transmission is force to '1' whatever the HSIPLLRDY/HSE status.

HSEON

Bit 16: External High Speed Clock enable. Set and reset by software. in low power mode, HSE is turned off. HSE is turned ON only when RFSUBG LDO is Ready 0: HSE oscillator OFF 1: HSE oscillator ON.

HSERDY

Bit 17: External High Speed Clock ready flag. Set by hardware to indicate that HSE oscillator is stable. 0: HSE oscillator not ready 1: HSE oscillator ready.

ICSCR

ICSCR register

Offset: 0x4, size: 32, reset: 0x3F000000, access: read-write

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		HSITRIM r											HSITRIMOFFSET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LSIBW r				LSITRIMOK r	LSITRIMEN rw

Toggle fields

LSITRIMEN

Bit 0: Low Speed oscillator trimming enable Set and reset by software. Reset source only for this field: PORESETn 0: LSI oscillator Bias trimming disabled 1: LSI oscillator Bias trimming enabled.

LSITRIMOK

Bit 1: LSITRIMOK: Low Speed oscillator trimming OK Set and reset by hardware to indicate when the Low Speed Internal RC oscillator has reached an optimal trimming of its bias current; this bit is only valid when LSITRIMEN is active. 0: LSI Bias trimming (LSIBW) is not good 1: LSI Bias trimming (LSIBW) value is OK.

LSIBW

Bits 2-5: Trimming in test mode The value stored is the correspondent Engi Byte and represents the actual value driving the input of the hardware macro. This value is loaded soon after the completion of the Option Byte Loading procedure. This field is directly writeable only in Test Mode..

HSITRIMOFFSET

Bits 16-18: ICSCR[18:16] = HSITRIMOFFSET[2:0]: High Speed oscillator signed trimming offset 000: 0 (+ 0 MHz / default) 001: 1 (-0.5 MHz) 010: 2 (-1MHz) 011: 3 (-1.5 MHz) 100: -1 (+2 MHz) 101: -2 (+1.5MHz) 110: -3 (+1 MHz) 111: -4 (+0.5 MHz).

HSITRIM

Bits 24-29: High Speed Internal clock trimming. This value is loaded soon after the completion of the Option Byte Loading procedure. When max value 0x3f is set, HSI is less than 64MHz.

CFGR

CFGR register

Offset: 0x8, size: 32, reset: 0x00000240, access: read-write

2/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCOPRE rw			MCOSEL rw			LCOSEL rw		SPI3I2SCLKSEL rw				LCOEN rw		IOBOOSTEN rw	CLKSLOWSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLKSLOWSEL rw		LPUCLKSEL rw	SMPSDIV rw		CLKSYSDIV_STATUS r			CLKSYSDIV rw				HSESEL_STATUS r	STOPHSI rw	HSESEL rw

Toggle fields

HSESEL

Bit 1: Clock source selection request: 0: HSI clock source is requested (default) 1: HSE clock source is requested.

STOPHSI

Bit 2: Stop HSI clock source request 0: HSI is enabled (default) 1: disable HSI is requested.

HSESEL_STATUS

Bit 3: Clock source selection Status 0: HSI clock source is selected 1: HSE clock source is selected Mirror the actual system clock source, depending on clock switching mechanism and limitations.

CLKSYSDIV

Bits 5-7: system clock frequency selection request 000: div1 (HSI 64M / HSE 48M) 001: div2 (HSI 32M / HSE 24M) 010: div4/div3 (HSI/HSE) (16M) 011: div8/div6 (HSI/HSE) (8M) * 100: div16/div12 (HSI/HSE) (4M) * 101: div32/div24 (HSI/HSE) (2M) * 110: div64/div48 (HSI/HSE) (1M) * Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN register.

CLKSYSDIV_STATUS

Bits 8-10: system clock frequency selection status 000: div1 (HSI 64M / HSE 48M) 001: div2 (HSI 32M / HSE 24M) 010: div4/div3 (HSI/HSE) (16M) 011: div8/div6 (HSI/HSE) (8M) 100: div16/div12 (HSI/HSE) (4M) 101: div32/div24 (HSI/HSE) (2M) 110: div64/div48 (HSI/HSE) (1M) Note: behavior depends on depending on CFGR.HSESEL and APB2ENR.MRSUBGEN register.

SMPSDIV

Bit 12: SMPS clock prescaling factor to generate 4MHz or 8MHz 0: SMPS clock 8MHz (default ) 1: SMPS clock 4MHz.

LPUCLKSEL

Bit 13: LPUCLKSEL: Selection of LPUART clock 0: 16 MHz peripheral clock (default) 1: LSE clock (Mandatory in LPUART deepstop mode).

CLKSLOWSEL

Bits 15-16: slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn 00: '0' (default) 01: LSE oscillator clock used as slow clock 10: LSI oscillator clock used as slow clock 11:HSI_64M divided by 2048 used as slow clock.

IOBOOSTEN

Bit 17: IOBOOSTEN: IO BOOSTER enable 0: IO BOOSTER block is disabled 1: IO BOOSTER block is enabled..

LCOEN

Bit 19: LCOEN: LCO enable on PA10 also in deepstop. 0: LCO output on PA10 is disabled 1: LCO output on PA10 is enabled..

SPI3I2SCLKSEL

Bits 22-23: SPI3I2SCLKSEL: Selection of I2S clock for SPI3 IP. 00: 32 MHz peripheral clock (default) 01: 16 MHz peripheral clock 10: CLK_SYS 11: CLK_SYS Note: the I2S clock frequency must be higher or equal to the system clock (configured through RCC_CFGR.CLKSYSDIV[2:0] bit field)..

LCOSEL

Bits 24-25: Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn 00: LCO output disabled, no clock on LCO 01: not used 10: internal 32 KHz (LSI) oscillator clock selected 11: external 32 KHz (LSE) oscillator clock selected.

MCOSEL

Bits 26-28: Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. 000: MCO output disabled, no clock on MCO 001: system clock selected 010: na 011: internal RC 64 MHz (HSI) oscillator clock selected 100: external oscillator (HSE) clock selected 101: internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected 110: SMPS clock selected 111: AUX ADC ANA clock selected.

CCOPRE

Bits 29-31: Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. 000: CCO clock is divided by 1 001: CCO clock is divided by 2 010: CCO clock is divided by 4 011: CCO clock is divided by 8 100: CCO clock is divided by 16 101: CCO clock is divided by 32 Others: not used.

CSSWCR

CSSWCR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		HSITRIMSW rw						HSISWTRIMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LSEDRV rw		LSISWBW rw				LSISWTRIMEN rw

Toggle fields

LSISWTRIMEN

Bit 0: Low Speed oscillator trimming by SW enable Set and reset by software. Reset source only for this field: PORESETn 0: LSI oscillator Bias trimming by SW disabled 1: LSI oscillator Bias trimming by SW enabled.

LSISWBW

Bits 1-4: Low Speed Internal clock trimming value to set by SW Reset source only for this field: PORESETn.

LSEDRV

Bits 5-6: Maximum Crystal gm for Low Speed External XO (to connect to XTDRV of 32kHz LSE XO => into IO V33?) to amplify drinving capacity modulation Set by software. Reset source only for this field: PORESETn 00: 0.0, low drive capability 01: 0.1, medium low drive capability 10: 1.0, medium high drive capability 11: 1.1, highdrive capability.

HSISWTRIMEN

Bit 23: High Speed oscillator trimming by SW enable Set and reset by software. 0: HSI oscillator Bias trimming by SW disabled 1: HSI oscillator Bias trimming by SW enabled.

HSITRIMSW

Bits 24-29: High Speed Internal clock trimming value to set by SW..

KRMR

KRMR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										KRM rw					KRM_EN rw

Toggle fields

KRM_EN

Bit 0: KRM_EN: Variable rate multiplier Enable Reset source only for this field: PORESETn 0: KRM is disabled (default) 1: KRM is enabled..

KRM

Bits 1-5: KRM[4:0] :SMPS clock dividing Ratio (CLK_SPMS_KRM frequency= CLK_ROOT frequency (depending on RCC_CFGR.HSESEL) divided by KRM when KRMEN=1) Reset source only for this field: PORESETn - 0x00 to 0x08: SMPS clock frequency equals CLK_ROOT/8 (8.00 MHz / 6.00 MHz) - 0x09: SMPS clock frequency equals CLK_ROOT/9 (7.11 MHz / 5.33 MHz) - 0x0A: SMPS clock frequency equals CLK_ROOT/10 (6.40 MHz / 4.80 MHz) - 0x0B: SMPS clock frequency equals CLK_ROOT/11 (5.82 MHz / 4.36 MHz) - 0x0C: SMPS clock frequency equals CLK_ROOT/12 (5.33 MHz / 4.00 MHz) - 0x0D: SMPS clock frequency equals CLK_ROOT/13 (4.92 MHz / 3.69 MHz) - 0x0E: SMPS clock frequency equals CLK_ROOT/14 (4.57 MHz / 3.43 MHz) - 0x0F: SMPS clock frequency equals CLK_ROOT/15 (4.27 MHz / 3.20 MHz) - 0x10: SMPS clock frequency equals CLK_ROOT/16 (4.00 MHz / 3.00 MHz) - 0x1x: Reserved Note: SMPS clock frequency must be selected in a range [4-8] MHz (depending on RCC_KRMR.KRM and RCC_CFGR.HSESEL)..

CIER

CIER register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LCSCRSTIE rw			LCDRSTIE rw	LPURSTIE rw	WDGRSTIE rw	RTCRSTIE rw	HSIPLLUNLOCKDETIE rw	HSIPLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw		LSERDYIE rw	LSIRDYIE rw

Toggle fields

LSIRDYIE

Bit 0: LSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled.

LSERDYIE

Bit 1: LSE Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled.

HSIRDYIE

Bit 3: HSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled.

HSERDYIE

Bit 4: HSE Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled.

HSIPLLRDYIE

Bit 5: HSI PLL Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. 0: HSI PLL ready interrupt disabled 1: HSI PLL ready interrupt enabled.

HSIPLLUNLOCKDETIE

Bit 6: HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. 0: HSI PLL unlock detection interrupt disabled 1: HSI PLL unlock detection interrupt enabled.

RTCRSTIE

Bit 7: RTCRSTIE: RTC reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the RTC reset end. 0: HSI PLL unlock detection interrupt disabled 1: HSI PLL unlock detection interrupt enabled.

WDGRSTIE

Bit 8: WDGRSTIE: Watchdog reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the watchdog reset end. 0: interrupt disabled 1: interrupt enabled.

LPURSTIE

Bit 9: LPURSTIE: LPUART reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the LPUART reset end. 0: interrupt disabled 1: interrupt enabled.

LCDRSTIE

Bit 10: LCDRSTIE: LCD reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the LCD reset end. 0: interrupt disabled 1: interrupt enabled.

LCSCRSTIE

Bit 13: LCSCRSTIE: LCSC reset release interrupt enable. 0: LCSC reset release interrupt is disabled. 1: LCSC reset release interrupt is enabled..

CIFR

CIFR register

Offset: 0x1c, size: 32, reset: 0x00000008, access: read-write

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		LCSCRSTIF rw			LCDRSTIF rw	LPURSTIF rw	WDGRSTIF rw	RTCRSTIF rw	HSIPLLUNLOCKDETIF rw	HSIPLLRDYIF rw	HSERDYIF rw	HSIRDYIF rw		LSERDYIF rw	LSIRDYIF rw

Toggle fields

LSIRDYIF

Bit 0: LSI Ready Interrupt flag Set by hardware when LSI clock becomes stable. 0: No clock ready interrupt caused by the internal RC 32 KHz oscillator 1: Clock ready interrupt caused by the internal RC 32 kHz oscillator.

LSERDYIF

Bit 1: LSE Ready Interrupt Flag. Set by hardware when LSE clock becomes stable. 0: No clock ready interrupt caused by the LSE oscillator 1: Clock ready interrupt caused by the LSE oscillator.

HSIRDYIF

Bit 3: HSI Ready Interrupt Flag. Set by hardware when HSI becomes stable. 0: No clock ready interrupt caused by the HSI oscillator 1: Clock ready interrupt caused by the HSI oscillator.

HSERDYIF

Bit 4: HSE Ready Interrupt Flag. Set by hardware when HSE becomes stable. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator.

HSIPLLRDYIF

Bit 5: HSI PLL Ready Interrupt Flag. Set by hardware when HSI PLL 64MHz becomes stable. 0: No clock ready interrupt caused by the HSI PLL64 MHz oscillator 1: Clock ready interrupt caused by the HSI PLL64 MHz oscillator.

HSIPLLUNLOCKDETIF

Bit 6: HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag..

RTCRSTIF

Bit 7: RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

WDGRSTIF

Bit 8: WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

LPURSTIF

Bit 9: LPUART reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

LCDRSTIF

Bit 10: LCD reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

LCSCRSTIF

Bit 13: LCSC reset end Interrupt Flag. Raised when reset is released on 32kHz clock.

CSCMDR

CSCMDR register

Offset: 0x20, size: 32, reset: 0x00000080, access: read-write

1/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EOFSEQ_IRQ rw	EOFSEQ_IE rw	STATUS r		CLKSYSDIV_REQ rw			REQUEST rw

Toggle fields

REQUEST

Bit 0: Request for system clock switching Cleared by hardware when system clock frequency switch is done 0: To cancel an ongiong request - still possible until IRQ assertion 1: To update the system clock frequency.

CLKSYSDIV_REQ

Bits 1-3: system clock frequency selection request 000: div1 (HSI 64M / HSE) (48M) 001: div2 (HSI 32M / HSE (24M*) 010: div4/div3 (HSI/HSE) (16M) 011: div8/div6 (HSI/HSE) (8M) * 100: div16/div12 (HSI/HSE) (4M) * 101: div32/div24 (HSI/HSE) (2M) * 110: div64/div48 (HSI/HSE) (1M) * Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN.

STATUS

Bits 4-5: Status of clock switch sequence 00: IDLE no switch requested 01: ONGOING clock frequency switch is ongoing 10: DONE clock frequency switch done 11: Reserved.

EOFSEQ_IE

Bit 6: End of sequence Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the clock system switch. 0: End of sequence interrupt disabled 1: End of sequence interrupt enabled.

EOFSEQ_IRQ

Bit 7: End of Sequence flag Set by hardware when clock system swtich is ended 0: No end of sequence event occured 1: End of sequece event occured.

AHBRSTR

AHBRSTR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											AESRST rw		RNGRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw									GPIOBRST rw	GPIOARST rw		DMARST rw

Toggle fields

DMARST

Bit 0: DMA and DMAMUX reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

GPIOARST

Bit 2: GPIOA reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

GPIOBRST

Bit 3: GPIOB reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

CRCRST

Bit 12: CRC reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

RNGRST

Bit 18: RNG reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

AESRST

Bit 20: AES reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

APB0RSTR

APB0RSTR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBGMCURST rw	WDGRST rw	LCSCRST rw	RTCRST rw	DACRST rw	COMPRST rw	LCDCRST rw	SYSCFGRST rw							TIM16RST rw	TIM2RST rw

Toggle fields

TIM2RST

Bit 0: TIM2RST: TIM2 reset. 0: TIM2 IP is not under reset. 1: TIM2 IP is under reset..

TIM16RST

Bit 1: TIM16RST: TIM16 reset. 0: TIM16 IP is not under reset. 1: TIM16 IP is under reset..

SYSCFGRST

Bit 8: SYSCFGRST: system controller reset. 0: system controller IP is not under reset. 1: system controller IP is under reset..

LCDCRST

Bit 9: LCDCRST: LCD controller reset. 0: LCD controller IP is not under reset. 1: LCD controller IP is under reset..

COMPRST

Bit 10: COMPRST: COMP reset. 0: COMP IP is not under reset. 1: COMP IP is under reset..

DACRST

Bit 11: DACRST: DAC reset. 0: DAC IP is not under reset. 1: DAC IP is under reset..

RTCRST

Bit 12: RTCRST: RTC reset. 0: RTC IP is not under reset. 1: RTC IP is under reset..

LCSCRST

Bit 13: LCSCRST: LCSC reset. 0: LCSC IP is not under reset. 1: LCSC IP is under reset..

WDGRST

Bit 14: WDGRST: Watchdog reset. 0: Watchdog IP is not under reset. 1: Watchdog IP is under reset..

DBGMCURST

Bit 15: DBGMCURST: DBGMCU reset. 0: DBGMCU IP is not under reset. 1: DBGMCU IP is under reset..

APB1RSTR

APB1RSTR register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								I2C2RST rw		I2C1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3RST rw				USARTRST rw		LPUARTRST rw				ADCRST rw				SPI1RST rw

Toggle fields

SPI1RST

Bit 0: SPI1 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

ADCRST

Bit 4: ADC reset for Aux-ADC IP Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

LPUARTRST

Bit 8: LPUART reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

USARTRST

Bit 10: USART reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

SPI3RST

Bit 14: SPI3 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

I2C1RST

Bit 21: I2C1 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

I2C2RST

Bit 23: I2C2 reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

APB2RSTR

APB2RSTR register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												LPAWURRST rw			MRSUBGRST rw

Toggle fields

MRSUBGRST

Bit 0: Radio MRSUBG reset. Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

LPAWURRST

Bit 3: Bubble reset Set and reset by software. 0: IP is not under reset. 1: IP is under reset..

AHBENR

AHBENR register

Offset: 0x50, size: 32, reset: 0x0000000C, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											AESEN rw		RNGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw									GPIOBEN rw	GPIOAEN rw		DMAEN rw

Toggle fields

DMAEN

Bit 0: DMA and DMAMUX enable Set and enable by software. 0: does not enable 1: enable.

GPIOAEN

Bit 2: GPIOA enable. It must be enabled by default.

GPIOBEN

Bit 3: GPIOB enable. It must be enabled by default.

CRCEN

Bit 12: CRC enable Set and enable by software. 0: does not enable 1: enable.

RNGEN

Bit 18: RNG clock enable Set and enable by software. 0: does not enable 1: enable.

AESEN

Bit 20: AESEN: AES clock enable. 0: AES IP is clock gated. 1: AES IP is clocked..

APB0ENR

APB0ENR register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBGMCUEN rw	WDGEN rw	LCSCEN rw	RTCEN rw	DACEN rw	COMPEN rw	LCDEN rw	SYSCFGEN rw							TIM16EN rw	TIM2EN rw

Toggle fields

TIM2EN

Bit 0: TIM2: Advanced Timer clock enable Set and enable by software. 0: clock disable 1: clock enable.

TIM16EN

Bit 1: TIM16: Advanced Timer clock enable Set and enable by software. 0: clock disable 1: clock enable.

SYSCFGEN

Bit 8: SYSTEM CONFIG clock enable Set and enable by software. 0: clock disable 1: clock enable.

LCDEN

Bit 9: LCD clock enable Set and enable by software. 0: clock disable 1: clock enable.

COMPEN

Bit 10: COMP clock enable Set and enable by software. 0: clock disable 1: clock enable.

DACEN

Bit 11: DAC clock enable Set and enable by software. 0: clock disable 1: clock enable.

RTCEN

Bit 12: RTC clock enable Set and enable by software. Reset source only for this field: PORESETn 0: clock disable 1: clock enable.

LCSCEN

Bit 13: LCSC clock enable. Set and enable by software. 0: clock disable 1: clock enable.

WDGEN

Bit 14: Watchdog clock enable. Set and enable by software. 0: clock disable 1: clock enable.

DBGMCUEN

Bit 15: DBG MCU clock enable. Set and enable by software. 0: clock disable 1: clock enable.

APB1ENR

APB1ENR register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								I2C2EN rw		I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3EN rw				USARTEN rw		LPUARTEN rw			ADCANAEN rw	ADCDIGEN rw				SPI1EN rw

Toggle fields

SPI1EN

Bit 0: SPI1 clock enable Set and enable by software. 0: clock disable 1: clock enable.

ADCDIGEN

Bit 4: AUXADC clock enable for Aux-ADC digital clock Set and enable by software. 0: clock disable 1: clock enable.

ADCANAEN

Bit 5: ADC clock enable for Aux-ADC analog clock Set and enable by software. 0: clock disable 1: clock enable.

LPUARTEN

Bit 8: LPUART clock enable Set and enable by software. 0: clock disable 1: clock enable.

USARTEN

Bit 10: USART clock enable Set and enable by software. 0: clock disable 1: clock enable.

SPI3EN

Bit 14: SPI3 clock enable Set and enable by software. 0: clock disable 1: clock enable.

I2C1EN

Bit 21: I2C1 clock enable Set and enable by software. 0: clock disable 1: clock enable.

I2C2EN

Bit 23: I2C2 clock enable Set and enable by software. 0: clock disable 1: clock enable.

APB2ENR

APB2ENR register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												LPAWUREN rw			MRSUBGEN rw

Toggle fields

MRSUBGEN

Bit 0: MRSUBG clock enable. Note: when this bit is '1', it must prevent clk_sys different from 16, 32, 64. If the configured clock is lower than 16MHz (1, 2, 4 or 8 MHz) or equal to 24MHz, clk_sys must be 16MHz 0: clock disable 1: clock enable.

LPAWUREN

Bit 3: Bubble clock enable Set and enable by software. 0: clock disable 1: clock enable.

DBGR

DBGR register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									FORCEXO48MREADY rw	DBGXOEXT rw	DBGBYPHSI rw	DBGHSIOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

DBGHSIOFF

Bit 19: used for debug or test 0: No effect (default) 1: HSI forced off..

DBGBYPHSI

Bit 20: used for debug mode with HSI bypassed by HSE 0: No effect (default) 1: HSI bypassed HSE..

DBGXOEXT

Bit 21: used for debug mode with HSE bypassed by FXTAL_IN clock and ZIV12 output used. 0: No effect (default) 1: HSE bypassed by FXTAL_IN clock and ZIV12 output used..

FORCEXO48MREADY

Bit 22: FORCEXO48MREADY Force XO48M Ready input signal This bit is for debug and force the XO48M ready input, in order to bypass XO48M comparators. 0: No effect (default) 1: Force XOREADY=1.

CSR

CSR register

Offset: 0x94, size: 32, reset: 0x0C000000, access: read-write

5/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	LOCKUPRSTF r	WDGRSTF r	SFTRSTF r	PORRSTF r	PADRSTF r			RMVF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

RMVF

Bit 23: Remove reset flag Set by software to clear the value of the reset flags. It auto clears by HW after clearing reason flags 0: Nothing done 1: Reset the value of the reset flags.

PADRSTF

Bit 26: SYSTEM reset flag Reset by software by writing the RMVF bit. Set by hardware when a reset from pad occurs. 0: No reset from pad occurred 1: Reset from pad occurred.

PORRSTF

Bit 27: POWER reset flag Reset by software by writing the RMVF bit. Set by hardware when a power reset occurs from LPMURESET block. 0: No POWER reset occurred 1: POWER reset occurred.

SFTRSTF

Bit 28: Software reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs. 0: No software reset occurred 1: Software reset occurred.

WDGRSTF

Bit 29: Watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a watchdog reset from V33 domain occurs. 0: No watchdog reset occurred 1: Watchdog reset occurred.

LOCKUPRSTF

Bit 30: LOCK UP reset flag from CM0 Reset by software by writing the RMVF bit. Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. 0: No lockup reset occurred 1: lockup reset occurred.

RFSWHSECR

RFSWHSECR register

Offset: 0x98, size: 32, reset: 0x0000803F, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AMPLTHRESH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISTARTUP rw		SWXOTUNE rw						SWXOTUNEEN rw	GMC rw

Toggle fields

GMC

Bits 0-6: GMC[6:5]: High speed external XO current control reference 00: 10 uA 01: 20 uA 1x: 40 uA GMC[4:0]: High speed external XO current control multiplying factor IcoreHSE= GMC[4:0] * GMC[6:5] Example: GMC[6:0]=0x1111001 -> IcoreHSE=25*40uA / Default 3F: IcoreHSE= 10uA x 31 = 310uA Note: this value is set only by software..

SWXOTUNEEN

Bit 7: RF-HSE capacitor bank tuning by SW enable Set by software.

SWXOTUNE

Bits 8-13: RF-HSE capacitor bank tuning value by SW Set by software.

ISTARTUP

Bits 14-15: RF-HSE Startup current Set by software Default value 2.

AMPLTHRESH

Bits 16-18: RF-HSE Amplitude Control threshold Set by software Default value 0.

RFHSECR

RFHSECR register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									AMPLREADY r	XOTUNE r

Toggle fields

XOTUNE

Bits 0-5: RF-HSE capacitor bank tuning Set by option byte loading soon after Power On Reset..

AMPLREADY

Bit 6: RF-HSE Amplitude Control Ready output.

AHBSMENR

AHBSMENR register

Offset: 0xa0, size: 32, reset: 0x0014160F, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											AESSMEN rw		RNGSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw		SRAM1SMEN rw	SRAM0SMEN rw						GPIOBSMEN rw	GPIOASMEN rw	FLASHSMEN rw	DMASMEN rw

Toggle fields

DMASMEN

Bit 0: DMA clock enable during Sleep mode bit This bit is set and reset by software. - 0: DMA clock disabled in Sleep mode - 1: DMA clock enabled in Sleep mode (if enabled in DMAEN).

FLASHSMEN

Bit 1: Flash clocks enable during Flash Sleep PD and CPU Sleep mode bit This bit is set and reset by software. - 0: Flash clocks are disabled in Flash Sleep PD* and CPU Sleep mode - 1: Flash clocks are enabled in Sleep mode Note: Flash Sleep PD is enabled through nvm_control register CONFIG.SLEEP_PD.

GPIOASMEN

Bit 2: GPIOA clock enable during Sleep mode bit This bit is set and reset by software. - 0: GPIOA clock disabled in Sleep mode - 1: GPIOA clock enabled in Sleep mode (if enabled by GPIOAEN).

GPIOBSMEN

Bit 3: GPIOB clock enable during Sleep mode bit This bit is set and reset by software. - 0: GPIOB clock disabled in Sleep mode - 1: GPIOB clock enabled in Sleep mode (if enabled in GPIOBEN).

SRAM0SMEN

Bit 9: SRAM0 clock enable during Sleep mode bit This bit is set and reset by software. - 0: SRAM0 clock disabled in Sleep mode - 1: SRAM0 clock enabled in Sleep mode.

SRAM1SMEN

Bit 10: SRAM1 clock enable during Sleep mode bit This bit is set and reset by software. - 0: SRAM1 clock disabled in Sleep mode - 1: SRAM1 clock enabled in Sleep mode.

CRCSMEN

Bit 12: CRC clock enable during Sleep mode bit This bit is set and reset by software. - 0: CRC clock disabled in Sleep mode - 1: CRC clock enabled in Sleep mode (if enabled in CRCEN).

RNGSMEN

Bit 18: RNG bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: RNG bus clock disabled in Sleep mode - 1: RNG bus clock enabled in Sleep mode (if enabled in RNGEN).

AESSMEN

Bit 20: AES bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: AES bus clock disabled in Sleep mode - 1: AES bus clock enabled in Sleep mode (if enabled in AESEN).

APB0SMENR

APB0SMENR register

Offset: 0xa4, size: 32, reset: 0x0000FF03, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBGMCUSMEN rw	WDGSMEN rw	LCSCSMEN rw	RTCSMEN rw	DACSMEN rw	COMPSMEN rw	LCDCSMEN rw	SYSCFGSMEN rw							TIM16SMEN rw	TIM2SMEN rw

Toggle fields

TIM2SMEN

Bit 0: TIM2 bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: TIM2 bus clock disabled in Sleep mode - 1: TIM2 bus clock enabled in Sleep mode (if enabled in TIM2EN).

TIM16SMEN

Bit 1: TIM16 bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: TIM16 bus clock disabled in Sleep mode - 1: TIM16 bus clock enabled in Sleep mode (if enabled in TIM16EN).

SYSCFGSMEN

Bit 8: SYSCFG bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: SYSCFG bus clock disabled in Sleep mode - 1: SYSCFG bus clock enabled in Sleep mode (if enabled in SYSCFGEN).

LCDCSMEN

Bit 9: LCDC bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: LCDC bus clock disabled in Sleep mode - 1: LCDC bus clock enabled in Sleep mode (if enabled in LCDCEN).

COMPSMEN

Bit 10: COMP bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: COMP bus clock disabled in Sleep mode - 1: COMP bus clock enabled in Sleep mode (if enabled in COMPEN).

DACSMEN

Bit 11: DAC bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: DAC bus clock disabled in Sleep mode - 1: DAC bus clock enabled in Sleep mode (if enabled in DACEN).

RTCSMEN

Bit 12: RTC bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: RTC bus clock disabled in Sleep mode - 1: RTC bus clock enabled in Sleep mode (if enabled in RTCEN).

LCSCSMEN

Bit 13: LCSC bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: LCSC bus clock disabled in Sleep mode - 1: LCSC bus clock enabled in Sleep mode (if enabled in LCSCEN).

WDGSMEN

Bit 14: WDG clock enable during Sleep mode bit This bit is set and reset by software. - 0: WDG clock disabled in Sleep mode - 1: WDG clock enabled in Sleep mode (if enabled in WDGEN).

DBGMCUSMEN

Bit 15: DBGMCU clock enable during Sleep mode bit This bit is set and reset by software. - 0: DBGMCU clock disabled in Sleep mode - 1: DBGMCU clock enabled in Sleep mode (if enabled in DBGMCUEN).

APB1SMENR

APB1SMENR register

Offset: 0xa8, size: 32, reset: 0x00A04511, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								I2C2SMEN rw		I2C1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI3SMEN rw				USARTSMEN rw		LPUARTSMEN rw				ADCDIGSMEN rw				SPI1SMEN rw

Toggle fields

SPI1SMEN

Bit 0: SPI1 bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: SPI1 bus clock disabled in Sleep mode - 1: SPI1 bus clock enabled in Sleep mode (if enabled in SPI1EN).

ADCDIGSMEN

Bit 4: ADCDIG bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: ADCDIG bus clock disabled in Sleep mode - 1: ADCDIG bus clock enabled in Sleep mode (if enabled by ADCDIGEN).

LPUARTSMEN

Bit 8: LPUART bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: LPUART bus clock disabled in Sleep mode - 1: LPUART bus clock enabled in Sleep mode (if enabled in LPUARTEN).

USARTSMEN

Bit 10: USART bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: USART bus clock disabled in Sleep mode - 1: USART bus clock enabled in Sleep mode (if enabled in USARTEN).

SPI3SMEN

Bit 14: SPI3 bus clock enable during Sleep mode bit This bit is set and reset by software. - 0: SPI3 bus clock disabled in Sleep mode - 1: SPI3 bus clock enabled in Sleep mode (if enabled in SPI3EN).

I2C1SMEN

Bit 21: I2C1 clock enable during Sleep mode bit This bit is set and reset by software. - 0: I2C1 clock disabled in Sleep mode - 1: I2C1 clock enabled in Sleep mode (if enabled in I2C1EN).

I2C2SMEN

Bit 23: I2C2 clock enable during Sleep mode bit This bit is set and reset by software. - 0: I2C2 clock disabled in Sleep mode - 1: I2C2 clock enabled in Sleep mode (if enabled in I2C2EN).

RETAINED

0x49000780:

2/8 fields covered.

Toggle register map

Offset	Name	31	30	15	7
0x0	RFIP_WAKEUPTIME	RFIP_WAKEUPTIME		RFIP_WAKEUPTIME
0x4	CPU_WAKEUPTIME	CPU_WAKEUPTIME		CPU_WAKEUPTIME
0x8	WAKEUP_CTRL	RFIP_WAKEUP_EN	CPU_WAKEUP_EN		SOC_WAKEUP_OFFSET
0xc	RRM_CMDLIST_PTR	CMDLIST_PTR_VALID		CMDLIST_PTR_OFFSET
0x10	SEQ_GLOBALTABLE_PTR			SEQ_GLOBALTABLE_PTR

Toggle registers

RFIP_WAKEUPTIME

RFIP_WAKEUPTIME register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RFIP_WAKEUPTIME r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RFIP_WAKEUPTIME r

Toggle fields

RFIP_WAKEUPTIME

Bits 0-31: (Absolute) Target time to wakeup the RFIP..

CPU_WAKEUPTIME

CPU_WAKEUPTIME register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPU_WAKEUPTIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPU_WAKEUPTIME rw

Toggle fields

CPU_WAKEUPTIME

Bits 1-31: (Absolute) Target time to wakeup the CPU..

WAKEUP_CTRL

WAKEUP_CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RFIP_WAKEUP_EN r	CPU_WAKEUP_EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SOC_WAKEUP_OFFSET rw

Toggle fields

SOC_WAKEUP_OFFSET

Bits 0-7: Delay to be considered by the Wakeup block to anticipate the wakeup request to the PWRC of the SoC versus the target to wakeup the RFIP (or the CPU)..

CPU_WAKEUP_EN

Bit 30: Indicates if the wakeup timer has to wakeup the SoC (match on CPU_WAKEUPTIME[31:4] bit field only) + set the CPU_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on CPU_WAKEUPTIME[31:0] occurs..

RFIP_WAKEUP_EN

Bit 31: Indicates if the wakeup timer has to wakeup the SoC (match on RFIP_WAKEUPTIME[31:4] bit field only) + trigger an event on the Sequencer and set the RFIP_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on RFIP_WAKEUPTIME[31:0] occurs..

RRM_CMDLIST_PTR

RRM_CMDLIST_PTR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDLIST_PTR_VALID rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDLIST_PTR_OFFSET rw

Toggle fields

CMDLIST_PTR_OFFSET

Bits 0-15: Contain the offset versus the SoC RAM base address where to find the RRM-UDRA command list entry point..

CMDLIST_PTR_VALID

Bit 31: Indicate if a command list has to be executed or not.

SEQ_GLOBALTABLE_PTR

SEQ_GLOBALTABLE_PTR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ_GLOBALTABLE_PTR rw

Toggle fields

SEQ_GLOBALTABLE_PTR

Bits 0-15: Contain the offset versus the SoC RAM base address of the GlobalConfiguration RAM table entry point..

RNG

0x48600000:

13/18 fields covered.

Toggle register map

Offset	Name	15	7	3	2	1	0
0x0	CR			TST_CLK	RNG_DIS
0x4	SR				FAULT	REVCLK	RNGRDY
0x8	VAL	RANDOM_VALUE
0x80	TCR						TCR
0x84	ITIP						ITIP
0xfe0	PeriphID0		PartNumber0
0xfe4	PeriphID1		Designer0	PartNumber1
0xfe8	PeriphID2		Revision	Designer1
0xfec	PeriphID3		Configuration
0xff0	PCellID0		RNGPCellID0
0xff4	PCellID1		RNGPCellID1
0xff8	PCellID2		RNGPCellID2
0xffc	PCellID3		RNGPCellID3

Toggle registers

CR

RNG_CR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TST_CLK rw	RNG_DIS rw

Toggle fields

RNG_DIS

Bit 2: RNG Disable bit..

TST_CLK

Bit 3: RNG Test Clock bit..

SR

RNG_SR register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FAULT rw	REVCLK r	RNGRDY r

Toggle fields

RNGRDY

Bit 0: New Random Value Ready..

REVCLK

Bit 1: RNGCLK Clock Reveal bit..

FAULT

Bit 2: Fault Reveal bit..

VAL

RNG_VAL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RANDOM_VALUE r

Toggle fields

RANDOM_VALUE

Bits 0-15: Random Value.

TCR

RNG_TCR register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TCR rw

Toggle fields

TCR

Bit 0: Test-control register.

ITIP

RNG_ITIP register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															ITIP rw

Toggle fields

ITIP

Bit 0: Integration-test input register.

PeriphID0

RNGPeriphID0 register

Offset: 0xfe0, size: 32, reset: 0x000000E1, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PartNumber0 r

Toggle fields

PartNumber0

Bits 0-7: These bits are read back as 0xE1.

PeriphID1

RNGPeriphID1 register

Offset: 0xfe4, size: 32, reset: 0x00000005, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								Designer0 r				PartNumber1 r

Toggle fields

PartNumber1

Bits 0-3: These bits are read back as 0x05.

Designer0

Bits 4-7: These bits are read back as 0x00.

PeriphID2

RNGPeriphID2 register

Offset: 0xfe8, size: 32, reset: 0x00000028, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								Revision r				Designer1 r

Toggle fields

Designer1

Bits 0-3: These bits are read back as 0x08.

Revision

Bits 4-7: These bits are read back as 0x02.

PeriphID3

RNGPeriphID3 register

Offset: 0xfec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								Configuration r

Toggle fields

Configuration

Bits 0-7: These bits are read back as 0x00.

PCellID0

RNGPCellID0 register

Offset: 0xff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RNGPCellID0 r

Toggle fields

RNGPCellID0

Bits 0-7: These bits are read back as 0x0D.

PCellID1

RNGPCellID1 register

Offset: 0xff4, size: 32, reset: 0x000000F0, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RNGPCellID1 r

Toggle fields

RNGPCellID1

Bits 0-7: These bits are read back as 0xF0.

PCellID2

RNGPCellID2 register

Offset: 0xff8, size: 32, reset: 0x00000005, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RNGPCellID2 r

Toggle fields

RNGPCellID2

Bits 0-7: These bits are read back as 0x05.

PCellID3

RNGPCellID3 register

Offset: 0xffc, size: 32, reset: 0x000000B1, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RNGPCellID3 r

Toggle fields

RNGPCellID3

Bits 0-7: These bits are read back as 0xB1.

RTC

0x40004000:

2/101 fields covered.

Toggle register map

Offset	Name	31	30	29	27	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	8	7	6	5	4	3	2	1	0
0x0	TR							PM	HT		HU					MNT			MNU				ST			SU
0x4	DR						YT				YU				WDU			MT	MU					DT		DU
0x8	CR					ITSE	COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE	WUTIE		ALRAIE	TSE	WUTE	ALRAE		FMT	BYPSHAD		TSEDGE	WUCKSEL
0xc	ISR												ITSF	RECALPF			TAMP1F	TSOVF	TSF	WUTF	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUTWF		ALRAWF
0x10	PRER							PREDIV_A								PREDIV_S
0x14	WUTR														WUT
0x1c	ALRMAR	MSK4	WDSEL	DT	DU		MSK3	PM	HT		HU				MSK2	MNT			MNU			MSK1	ST			SU
0x24	WPR																					KEY
0x28	SSR														SS
0x2c	SHIFTR	ADD1S														SUBFS
0x30	TSTR							PM	HT		HU					MNT			MNU				ST			SU
0x34	TSDR														WDU			MT	MU					DT		DU
0x38	TSSSR														SS
0x3c	CALR														CALP	CALW8	CALW16				CALM
0x40	TAMPCR											TAMP1MF	TAMP1NOERASE	TAMP1IE	TAMPPUDIS	TAMPPRCH		TAMPFLT		TAMPFREQ		TAMPTS					TAMPIE	TAMP1TRG	TAMP1E
0x44	ALRMASSR				MASKSS											SS
0x4c	OR																											RTC_OUT_RMP	ALARMOUTTYPE
0x50	BKP0R	BKP													BKP
0x54	BKP1R	BKP													BKP

Toggle registers

TR

RTC_TR register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation. 0: AM or 24-hour format 1: PM.

DR

RTC_DR register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format..

DT

Bits 4-5: Date tens in BCD format..

MU

Bits 8-11: Month units in BCD format..

MT

Bit 12: Month tens in BCD format..

WDU

Bits 13-15: Week day units 000: forbidden 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Sunday.

YU

Bits 16-19: Year units in BCD format..

YT

Bits 20-23: Year tens in BCD format..

CR

RTC_CR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ITSE rw	COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H w	ADD1H w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw		ALRAIE rw	TSE rw	WUTE rw		ALRAE rw		FMT rw	BYPSHAD rw		TSEDGE rw	WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value.

TSEDGE

Bit 3: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting..

BYPSHAD

Bit 5: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters..

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable 0: Alarm A disabled 1: Alarm A enabled.

WUTE

Bit 10: Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled.

TSE

Bit 11: Timestamp enable 0: Timestamp disable 1: Timestamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled.

WUTIE

Bit 14: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change.

SUB1H

Bit 17: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change..

BKP

Bit 18: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not..

COSEL

Bit 19: Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255)..

POL

Bit 20: Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0])..

OSEL

Bits 21-22: Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Reserved 11: Wakeup output enabled.

COE

Bit 23: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled.

ITSE

Bit 24: Timestamp on internal event enable 0: Internal event timestamp disable 1: Internal event timestamp enable.

ISR

RTC_ISR register

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ITSF rw	RECALPF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		TAMP1F rw	TSOVF rw	TSF rw	WUTF rw		ALRAF rw	INIT rw	INITF rw	RSF rw	INITS rw	SHPF rw	WUTWF rw		ALRAWF rw

Toggle fields

ALRAWF

Bit 0: Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed..

WUTWF

Bit 2: Wakeup timer write flag This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed..

SHPF

Bit 3: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect..

INITS

Bit 4: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). 0: Calendar has not been initialized 1: Calendar has been initialized.

RSF

Bit 5: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized..

INITF

Bit 6: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed..

INIT

Bit 7: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset..

ALRAF

Bit 8: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0..

WUTF

Bit 10: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again..

TSF

Bit 11: This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits..

TSOVF

Bit 12: This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

TAMP1F

Bit 13: RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0.

RECALPF

Bit 16: Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0..

ITSF

Bit 17: Internal time-stamp flag This flag is set by hardware when a time-stamp on the internal event occurs. This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits..

PRER

RTC_PRER register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1).

PREDIV_A

Bits 16-22: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1).

WUTR

RTC_WUTR register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden..

ALRMAR

RTC_ALRMAR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MSK1

Bit 7: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds dont care in Alarm A comparison.

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

MSK2

Bit 15: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes dont care in Alarm A comparison.

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation 0: AM or 24-hour format 1: PM.

MSK3

Bit 23: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours dont care in Alarm A comparison.

DU

Bits 24-27: Date units or day in BCD format..

DT

Bits 28-29: Date tens in BCD format..

WDSEL

Bit 30: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is dont care..

MSK4

Bit 31: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day dont care in Alarm A comparison.

WPR

RTC_WPR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

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KEY

Bits 0-7: Write protection key This byte is written by software. Reading this byte always returns 0x00.

SSR

RTC_SSR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ).

SHIFTR

RTC_SHIFTR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescalers counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) ..

ADD1S

Bit 31: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation..

TSTR

RTC_TSTR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation 0: AM or 24-hour format 1: PM.

TSDR

RTC_TSDR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format..

DT

Bits 4-5: Date tens in BCD format..

MU

Bits 8-11: Month units in BCD format..

MT

Bit 12: Month tens in BCD format..

WDU

Bits 13-15: Week day units.

TSSSR

RTC_TSSSR register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value SS[15:0] is the value of the synchronous prescalers counter when the timestamp event occurred..

CALR

RTC_CALR register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

Toggle fields

CALM

Bits 0-8: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP..

CALW16

Bit 13: Use a 16-second calibration cycle period When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stucked at 0 when CALW16=1..

CALW8

Bit 14: Use an 8-second calibration cycle period When CALW8 is set to 1 , the 8-second calibration cycle period is selected. Note: CALM[1:0] are stucked at '00' when CALW8=1..

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM..

TAMPCR

RTC_TAMPCR register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													TAMP1MF rw	TAMP1NOERASE rw	TAMP1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw			TAMPTS rw					TAMPIE rw	TAMP1TRG rw	TAMP1E rw

Toggle fields

TAMP1E

Bit 0: RTC_TAMP1 input detection enable 0: RTC_TAMP1 detection disabled 1: RTC_TAMP1 detection enabled..

TAMP1TRG

Bit 1: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. 1: RTC_TAMP1 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP1 input rising edge triggers a tamper detection event. 1: RTC_TAMP1 input falling edge triggers a tamper detection event..

TAMPIE

Bit 2: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled..

TAMPTS

Bit 7: Activate timestamp on tamper detection event 0: Tamper detection event does not cause a timestamp to be saved 1: Save timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register..

TAMPFREQ

Bits 8-10: Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled. 0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz).

TAMPFLT

Bits 11-12: RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs. 0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). 0x1: Tamper event is activated after 2 consecutive samples at the active level. 0x2: Tamper event is activated after 4 consecutive samples at the active level. 0x3: Tamper event is activated after 8 consecutive samples at the active level..

TAMPPRCH

Bits 13-14: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles.

TAMPPUDIS

Bit 15: RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample. 0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) 1: Disable precharge of RTC_TAMPx pins..

TAMP1IE

Bit 16: Tamper 1 interrupt enable 0: Tamper 1 interrupt is disabled if TAMPIE = 0. 1: Tamper 1 interrupt enabled..

TAMP1NOERASE

Bit 17: Tamper 1 no erase 0: Tamper 1 event erases the backup registers. 1: Tamper 1 event does not erase the backup registers..

TAMP1MF

Bit 18: Tamper 1 mask flag 0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. 1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased..

ALRMASSR

RTC_ALRMASSR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value This value is compared with the contents of the synchronous prescalers counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared..

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..

OR

RTC_OR register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RTC_OUT_RMP rw	ALARMOUTTYPE rw

Toggle fields

ALARMOUTTYPE

Bit 0: RTC_ALARM on PA8 output type.

RTC_OUT_RMP

Bit 1: RTC_OUT remap Setting this bit allows to remap the RTC outputs on PA9 as follows: 0 : If OSEL/= '00' : RTC_ALARM is ouput on PA8 If OSEL= '00' and COE = 1 : RTC_CALIB is output on PA8 1 : If OSEL /= '00' and COE = 0 : RTC_ALARM is output on PA9 If OSEL = '00' and COE = 1: RTC_CALIB is output on PA9 If OSEL /= '00' and COE = 1: RTC_CALIB is output on PA9 and RTC_ALARM is output on PA8. Note: the RTC outputs are functional in DEEPSTOP mode only on PA8..

BKP0R

RTC_BKPxR register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only..

BKP1R

RTC_BKPxR register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VDD12o so they are retained during DEEPSTOP mode. The application can write or read data to and from these registers. This register is reset on PORESETn only..

SPI

0x41002000:

12/41 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SSPCR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	SSPCR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SSPSR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc	SSPDR	DR
0x10	SSPCRCPR	CRCPOLY
0x14	SSPRXCRCR	RXCRC
0x18	SSPTXCRCR																TXCRC

Toggle registers

SSPCR1

SPI_SSPCR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase - 0: The first clock transition is the first data capture edge - 1: The second clock transition is the first data capture edge.

CPOL

Bit 1: Clock polarity - 0: CK to 0 when idle - 1: CK to 1 when idle.

MSTR

Bit 2: Master selection - 0: Slave configuration - 1: Master configuration.

BR

Bits 3-5: Baud rate control - 000: fPCLK/2 - 001: fPCLK/4 - 010: fPCLK/8 - 011: fPCLK/16 - 100: fPCLK/32 - 101: fPCLK/64 - 110: fPCLK/128 - 111: fPCLK/256.

SPE

Bit 6: SPI enable - 0: Peripheral disabled - 1: Peripheral enabled.

LSBFIRST

Bit 7: Frame format - 0: data is transmitted / received with the MSB first - 1: data is transmitted / received with the LSB first.

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored..

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. - 0: Software slave management disabled - 1: Software slave management enabled.

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. - 0: Full duplex (Transmit and receive) - 1: Output disabled (Receive-only mode).

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. - 0: 8-bit CRC length - 1: 16-bit CRC length.

CRCNEXT

Bit 12: Transmit CRC next - 0: Next transmit value is from Tx buffer - 1: Next transmit value is from Tx CRC register.

CRCEN

Bit 13: Hardware CRC calculation enable - 0: CRC calculation disabled - 1: CRC calculation Enabled.

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode - 0: Output disabled (receive-only mode) - 1: Output enabled (transmit-only mode).

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. - 0: 2-line unidirectional data mode selected - 1: 1-line bidirectional data mode selected.

SSPCR2

SPI_SSPCR2 register

Offset: 0x4, size: 32, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. - 0: Rx buffer DMA disabled - 1: Rx buffer DMA enabled.

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. - 0: Tx buffer DMA disabled - 1: Tx buffer DMA enabled.

SSOE

Bit 2: SS output enable - 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration - 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment..

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. - 0: No NSS pulse - 1: NSS pulse generated.

FRF

Bit 4: Frame format - 0: SPI Motorola mode - 1 SPI TI mode.

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). - 0: Error interrupt is masked - 1: Error interrupt is enabled.

RXNEIE

Bit 6: RX buffer not empty interrupt enable - 0: RXNE interrupt masked - 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set..

TXEIE

Bit 7: Tx buffer empty interrupt enable - 0: TXE interrupt masked - 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set..

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers: - 0000: Not used - 0001: Not used - 0010: Not used - 0011: 4-bit - 0100: 5-bit - 0101: 6-bit - 0110: 7-bit - 0111: 8-bit - 1000: 9-bit - 1001: 10-bit - 1010: 11-bit - 1011: 12-bit - 1100: 13-bit - 1101: 14-bit - 1110: 15-bit - 1111: 16-bit If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit)..

FRXTH

Bit 12: FIFO reception threshold FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. This bit is used to set the threshold of the RXFIFO that triggers an RXNE event - 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit).

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

SSPSR

SPI_SSPSR register

Offset: 0x8, size: 32, reset: 0x00000002, access: read-write

10/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty - 0: Rx buffer empty - 1: Rx buffer not empty.

TXE

Bit 1: Transmit buffer empty - 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). - 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer)..

CHSIDE

Bit 2: Channel side - 0: Channel Left has to be transmitted or has been received - 1: Channel Right has to be transmitted or has been received.

UDR

Bit 3: Underrun flag - 0: No underrun occurred - 1: Underrun occurred.

CRCERR

Bit 4: CRC error flag - 0: CRC value received matches the SPIx_RXCRCR value - 1: CRC value received does not match the SPIx_RXCRCR value This flag is set by hardware and cleared by software writing 0..

MODF

Bit 5: Mode fault - 0: No mode fault occurred - 1: Mode fault occurred.

OVR

Bit 6: Overrun flag - 0: No overrun occurred - 1: Overrun occurred.

BSY

Bit 7: Busy flag - 0: SPI (or I2S) not busy - 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware..

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software. - 0: No frame format error - 1: A frame format error occurred.

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full.

FTLVL

Bits 11-12: FIFO Transmission Level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2).

SSPDR

SPI_SSPDR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 18.5.8: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

SSPCRCPR

SPI_SSPCRCPR register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required..

SSPRXCRCR

SPI_SSPRXCRCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. A read to this register when the BSY Flag is set could return an incorrect value..

SSPTXCRCR

SPI_SSPTXCRCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TXCRC r

Toggle fields

TXCRC

Bit 0: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..

SPI3

0x41007000:

12/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SPI_SSPCR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4	SPI_SSPCR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8	SPI_SSPSR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc	SPI_SSPDR	DR
0x10	SPI_SSPCRCPR	CRCPOLY
0x14	SPI_SSPRXCRCR	RXCRC
0x18	SPI_SSPTXCRCR																TXCRC
0x1c	SPI2S_I2SCFGR				ASTREN	I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20	SPI2S_I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

SPI_SSPCR1

SPI_SSPCR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase - 0: The first clock transition is the first data capture edge - 1: The second clock transition is the first data capture edge.

CPOL

Bit 1: Clock polarity - 0: CK to 0 when idle - 1: CK to 1 when idle.

MSTR

Bit 2: Master selection - 0: Slave configuration - 1: Master configuration.

BR

Bits 3-5: Baud rate control - 000: fPCLK/2 - 001: fPCLK/4 - 010: fPCLK/8 - 011: fPCLK/16 - 100: fPCLK/32 - 101: fPCLK/64 - 110: fPCLK/128 - 111: fPCLK/256.

SPE

Bit 6: SPI enable - 0: Peripheral disabled - 1: Peripheral enabled.

LSBFIRST

Bit 7: Frame format - 0: data is transmitted / received with the MSB first - 1: data is transmitted / received with the LSB first.

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored..

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. - 0: Software slave management disabled - 1: Software slave management enabled.

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. - 0: Full duplex (Transmit and receive) - 1: Output disabled (Receive-only mode).

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. - 0: 8-bit CRC length - 1: 16-bit CRC length.

CRCNEXT

Bit 12: Transmit CRC next - 0: Next transmit value is from Tx buffer - 1: Next transmit value is from Tx CRC register.

CRCEN

Bit 13: Hardware CRC calculation enable - 0: CRC calculation disabled - 1: CRC calculation Enabled.

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode - 0: Output disabled (receive-only mode) - 1: Output enabled (transmit-only mode).

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. - 0: 2-line unidirectional data mode selected - 1: 1-line bidirectional data mode selected.

SPI_SSPCR2

SPI_SSPCR2 register

Offset: 0x4, size: 32, reset: 0x00000700, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. - 0: Rx buffer DMA disabled - 1: Rx buffer DMA enabled.

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. - 0: Tx buffer DMA disabled - 1: Tx buffer DMA enabled.

SSOE

Bit 2: SS output enable - 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration - 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment..

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. - 0: No NSS pulse - 1: NSS pulse generated.

FRF

Bit 4: Frame format - 0: SPI Motorola mode - 1 SPI TI mode.

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). - 0: Error interrupt is masked - 1: Error interrupt is enabled.

RXNEIE

Bit 6: RX buffer not empty interrupt enable - 0: RXNE interrupt masked - 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set..

TXEIE

Bit 7: Tx buffer empty interrupt enable - 0: TXE interrupt masked - 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set..

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers: - 0000: Not used - 0001: Not used - 0010: Not used - 0011: 4-bit - 0100: 5-bit - 0101: 6-bit - 0110: 7-bit - 0111: 8-bit - 1000: 9-bit - 1001: 10-bit - 1010: 11-bit - 1011: 12-bit - 1100: 13-bit - 1101: 14-bit - 1110: 15-bit - 1111: 16-bit If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit)..

FRXTH

Bit 12: FIFO reception threshold FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. This bit is used to set the threshold of the RXFIFO that triggers an RXNE event - 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit).

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). - 0: Number of data to transfer is even - 1: Number of data to transfer is odd.

SPI_SSPSR

SPI_SSPSR register

Offset: 0x8, size: 32, reset: 0x00000002, access: read-write

10/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty - 0: Rx buffer empty - 1: Rx buffer not empty.

TXE

Bit 1: Transmit buffer empty - 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). - 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer)..

CHSIDE

Bit 2: Channel side - 0: Channel Left has to be transmitted or has been received - 1: Channel Right has to be transmitted or has been received.

UDR

Bit 3: Underrun flag - 0: No underrun occurred - 1: Underrun occurred.

CRCERR

Bit 4: CRC error flag - 0: CRC value received matches the SPIx_RXCRCR value - 1: CRC value received does not match the SPIx_RXCRCR value This flag is set by hardware and cleared by software writing 0..

MODF

Bit 5: Mode fault - 0: No mode fault occurred - 1: Mode fault occurred.

OVR

Bit 6: Overrun flag - 0: No overrun occurred - 1: Overrun occurred.

BSY

Bit 7: Busy flag - 0: SPI (or I2S) not busy - 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware..

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software. - 0: No frame format error - 1: A frame format error occurred.

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full.

FTLVL

Bits 11-12: FIFO Transmission Level These bits are set and cleared by hardware. - 00: FIFO empty - 01: 1/4 FIFO - 10: 1/2 FIFO - 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2).

SPI_SSPDR

SPI_SSPDR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 18.5.8: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

SPI_SSPCRCPR

SPI_SSPCRCPR register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required..

SPI_SSPRXCRCR

SPI_SSPRXCRCR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. A read to this register when the BSY Flag is set could return an incorrect value..

SPI_SSPTXCRCR

SPI_SSPTXCRCR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															TXCRC r

Toggle fields

TXCRC

Bit 0: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..

SPI2S_I2SCFGR

SPI2S_I2SCFGR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ASTREN rw	I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel) - 0: 16-bit wide - 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in..

DATLEN

Bits 1-2: Data length to be transferred - 00: 16-bit data length - 01: 24-bit data length - 10: 32-bit data length - 11: Not allowed.

CKPOL

Bit 3: Steady state clock polarity - 0: I2S clock steady state is low level - 1: I2S clock steady state is high level.

I2SSTD

Bits 4-5: I2S standard selection - 00: I2S Philips standard. - 01: MSB justified standard (left justified) - 10: LSB justified standard (right justified) - 11: PCM standard.

PCMSYNC

Bit 7: PCM frame synchronization - 0: Short frame synchronization - 1: Long frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode..

I2SCFG

Bits 8-9: I2S configuration mode - 00: Slave - transmit - 01: Slave - receive - 10: Master - transmit - 11: Master - receive.

I2SE

Bit 10: I2S enable - 0: I2S peripheral is disabled - 1: I2S peripheral is enabled Note: This bit is not used in SPI mode..

I2SMOD

Bit 11: I2S mode selection - 0: SPI mode is selected - 1: I2S mode is selected Note: This bit should be configured when the SPI is disabled..

ASTREN

Bit 12: Asynchronous start enable. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards..

SPI2S_I2SPR

SPI2S_I2SPR register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values..

ODD

Bit 8: Odd factor for the prescaler - 0: Real divider value is = I2SDIV *2 - 1: Real divider value is = (I2SDIV * 2)+1.

MCKOE

Bit 9: Master clock output enable - 0: Master clock output is disabled - 1: Master clock output is enabled.

STATIC

0x49000400:

0/68 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	18	15	14	13	12	11	10	9	8	7	6	4	3	2	1	0
0x0	PCKT_CONFIG	POSTAMBLE_SEQ		POSTAMBLE_LENGTH						PREAMBLE_SEQ		PREAMBLE_LENGTH			PREAMBLE_LENGTH				FIX_VAR_LEN	LEN_WIDTH	SYNC_PRESENT	SYNC_LEN				SECONDARY_SYNC_SEL	CRC_MODE
0x4	SYNC	SYNC													SYNC
0x8	SEC_SYNC	SEC_SYNC													SEC_SYNC
0xc	CRC_INIT	CRC_INIT_VAL													CRC_INIT_VAL
0x10	PCKT_CTRL	FORCE_2FSK_SYNC_MODE		PN_SEL	MOD_INTERP_EN	FCS_TYPE_4G	FEC_TYPE_4G	INT_EN_4G	MANCHESTER_TYPE		CODING_SEL		WHIT_INIT		WHIT_INIT				WHIT_EN	WHIT_BF_FEC		TX_MODE		RX_MODE		FOUR_FSK_SYM_SWAP	BYTE_SWAP		PCKT_FORMAT
0x14	DATABUFFER0_PTR	DATABUFFER0_PTR													DATABUFFER0_PTR
0x18	DATABUFFER1_PTR	DATABUFFER1_PTR													DATABUFFER1_PTR
0x1c	DATABUFFER_SIZE														DATABUFFER_SIZE
0x20	PA_LEVEL_3_0	PA_LEVEL3								PA_LEVEL2					PA_LEVEL1								PA_LEVEL0
0x24	PA_LEVEL_7_4	PA_LEVEL7								PA_LEVEL6					PA_LEVEL5								PA_LEVEL4
0x28	PA_CONFIG															PA_RAMP_ENABLE	LIN_NLOG		PA_MODE		PA_DRV_MODE		ASK_OOK_EN	PA_INTERP_EN	PA_LEVEL_MAX_INDEX			PA_RAMP_STEP_WIDTH
0x2c	IF_CTRL	IF_MODE			IF_OFFSET_ANA													IF_OFFSET_DIG
0x30	AS_QI_CTRL	AS_CS_BLANKING	AS_MEAS_TIME			AS_EQU_CTRL								SQI_THR	SQI_EN	CS_MODE		PQI_THR				RSSI_THR
0x34	IQC_CONFIG	IQC_ENABLE	REUSE_CORRECTION	LOAD_IQC_INIT						IQC_CORRECT_IN					IQC_CORRECT_IN
0x38	DSSS_CTRL														ACQ_THR						ACQ_HITS		DSSS_EN	SPREADING_EXP		ACQ_WINDOW

Toggle registers

PCKT_CONFIG

PCKT_CONFIG register

Offset: 0x0, size: 32, reset: 0x000103F1, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POSTAMBLE_SEQ rw		POSTAMBLE_LENGTH rw						PREAMBLE_SEQ rw		PREAMBLE_LENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PREAMBLE_LENGTH rw				FIX_VAR_LEN rw	LEN_WIDTH rw	SYNC_PRESENT rw	SYNC_LEN rw					SECONDARY_SYNC_SEL rw	CRC_MODE rw

Toggle fields

CRC_MODE

Bits 0-2: CRC type (0, 8, 16, 16 802..

SECONDARY_SYNC_SEL

Bit 3: In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC.

SYNC_LEN

Bits 4-8: Length of the SYNC (and secondary) SYNC word in 1-bit granularity.

SYNC_PRESENT

Bit 9: Indicate if a SYNC word is present on the frame or not (null length).

LEN_WIDTH

Bit 10: Indicates if the LENGTH field is defined on 1 byte or 2 bytes.

FIX_VAR_LEN

Bit 11: Select the length mode.

PREAMBLE_LENGTH

Bits 12-21: Length of the PREAMBLE in pairs of bits (0 to 2046).

PREAMBLE_SEQ

Bits 22-23: Select the PREAMBLE pattern to be applied.

POSTAMBLE_LENGTH

Bits 24-29: Length of the POSTAMBLE in pair of bits (0 to 126 bits).

POSTAMBLE_SEQ

Bits 30-31: Packet postamble control: postamble bit sequence selection.

SYNC

SYNC register

Offset: 0x4, size: 32, reset: 0x23232323, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SYNC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SYNC rw

Toggle fields

SYNC

Bits 0-31: Synchro word..

SEC_SYNC

SEC_SYNC register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEC_SYNC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC_SYNC rw

Toggle fields

SEC_SYNC

Bits 0-31: Secondary Synchro word..

CRC_INIT

CRC_INIT register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT_VAL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT_VAL rw

Toggle fields

CRC_INIT_VAL

Bits 0-31: CRC intialization value.

PCKT_CTRL

PCKT_CTRL register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FORCE_2FSK_SYNC_MODE rw		PN_SEL rw	MOD_INTERP_EN rw	FCS_TYPE_4G rw	FEC_TYPE_4G rw	INT_EN_4G rw	MANCHESTER_TYPE rw		CODING_SEL rw		WHIT_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WHIT_INIT rw				WHIT_EN rw	WHIT_BF_FEC rw		TX_MODE rw		RX_MODE rw			FOUR_FSK_SYM_SWAP rw	BYTE_SWAP rw		PCKT_FORMAT rw

Toggle fields

PCKT_FORMAT

Bit 0: Packet format.

BYTE_SWAP

Bit 2: Invert MSB-LSB transmission order (bitendianess).

FOUR_FSK_SYM_SWAP

Bit 3: Invert bit to symbol mapping for 4-(G)FSK.

RX_MODE

Bits 4-6: RX mode.

TX_MODE

Bits 7-8: TX mode.

WHIT_BF_FEC

Bit 10: Whitening before FEC feature.

WHIT_EN

Bit 11: Whitening enable.

WHIT_INIT

Bits 12-20: Whitening initialization value..

CODING_SEL

Bits 21-22: Coding / decoding selection.

MANCHESTER_TYPE

Bit 24: Select the Manchester encoding polarity.

INT_EN_4G

Bit 25: This field is used as Interleaving enable for 802..

FEC_TYPE_4G

Bit 26: FEC type for 802..

FCS_TYPE_4G

Bit 27: FCS type value in header field for 802..

MOD_INTERP_EN

Bit 28: Enable frequency interpolator (for 2-GFSK and 4-GFSK).

PN_SEL

Bit 29: Select the Pseudo Random Binary Sequence (PRBS) polynomial to apply when the selected transmission mode is PN mode (TX_MODE = '11').

FORCE_2FSK_SYNC_MODE

Bit 31: Force SYNC word to be formatted as a 2-(G)FSK bit steam instead of 4-(G)FSK.

DATABUFFER0_PTR

DATABUFFER0_PTR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATABUFFER0_PTR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATABUFFER0_PTR rw

Toggle fields

DATABUFFER0_PTR

Bits 2-31: Start address to be used by the Data Buffer0.

DATABUFFER1_PTR

DATABUFFER1_PTR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATABUFFER1_PTR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATABUFFER1_PTR rw

Toggle fields

DATABUFFER1_PTR

Bits 2-31: Start address to be used by the Data Buffer1.

DATABUFFER_SIZE

DATABUFFER_SIZE register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATABUFFER_SIZE rw

Toggle fields

DATABUFFER_SIZE

Bits 0-15: Size of the Data Buffers (Data Buffer0 and Data Buffer1) expressed in byte unit..

PA_LEVEL_3_0

PA_LEVEL_3_0 register

Offset: 0x20, size: 32, reset: 0x230B0100, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA_LEVEL3 rw								PA_LEVEL2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA_LEVEL1 rw								PA_LEVEL0 rw

Toggle fields

PA_LEVEL0

Bits 0-7: Output power level for first step.

PA_LEVEL1

Bits 8-15: Output power level for second step.

PA_LEVEL2

Bits 16-23: Output power level for third step.

PA_LEVEL3

Bits 24-31: Output power level for fourth step.

PA_LEVEL_7_4

PA_LEVEL_7_4 register

Offset: 0x24, size: 32, reset: 0x51473B2F, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA_LEVEL7 rw								PA_LEVEL6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA_LEVEL5 rw								PA_LEVEL4 rw

Toggle fields

PA_LEVEL4

Bits 0-7: Output power level for fifth step.

PA_LEVEL5

Bits 8-15: Output power level for sixth step.

PA_LEVEL6

Bits 16-23: Output power level for seventh step.

PA_LEVEL7

Bits 24-31: Output power level for eighth step.

PA_CONFIG

PA_CONFIG register

Offset: 0x28, size: 32, reset: 0x0000015C, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PA_RAMP_ENABLE rw	LIN_NLOG rw		PA_MODE rw		PA_DRV_MODE rw		ASK_OOK_EN rw	PA_INTERP_EN rw		PA_LEVEL_MAX_INDEX rw			PA_RAMP_STEP_WIDTH rw

Toggle fields

PA_RAMP_STEP_WIDTH

Bits 0-1: Step width (unit: 1/8 of bit period)..

PA_LEVEL_MAX_INDEX

Bits 2-4: Final level for power ramping (i..

PA_INTERP_EN

Bit 6: Enable power level interpolator..

ASK_OOK_EN

Bit 7: Enable the generation of the internal TXDATA signal provided to the FIR..

PA_DRV_MODE

Bits 8-9: Select the PA topology.

PA_MODE

Bits 10-11: Configure the Power Amplifier (PA) mode.

LIN_NLOG

Bit 13: Enable/disable the linear-to- log conversion of the PA code output from Safe-ASK calibrator.

PA_RAMP_ENABLE

Bit 14: Enable the power ramping.

IF_CTRL

IF_CTRL register

Offset: 0x2c, size: 32, reset: 0x04CD04CD, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IF_MODE rw			IF_OFFSET_ANA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			IF_OFFSET_DIG rw

Toggle fields

IF_OFFSET_DIG

Bits 0-12: Intermediate frequency setting for the digital shift-to-baseband circuits (default: 300 kHz).

IF_OFFSET_ANA

Bits 16-28: Intermediate frequency setting for the synthesizer configuration (default: 300 kHz)..

IF_MODE

Bit 31: Select the cutoff frequency of the AAF for the analog RFSUBG IP.

AS_QI_CTRL

AS_QI_CTRL register

Offset: 0x30, size: 32, reset: 0x58008028, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AS_CS_BLANKING rw	AS_MEAS_TIME rw			AS_EQU_CTRL rw									SQI_THR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQI_EN rw	CS_MODE rw		PQI_THR rw				RSSI_THR rw

Toggle fields

RSSI_THR

Bits 0-8: Signal detect threshold in 1 dB resolution..

PQI_THR

Bits 9-12: PQI threshold (if 0 then )..

CS_MODE

Bits 13-14: Carrier Sense mode selection.

SQI_EN

Bit 15: SQI enable.

SQI_THR

Bits 16-18: SQI threshold defining the precision requested to detect the SYNC word..

AS_EQU_CTRL

Bits 26-27: ISI cancellation equalizer.

AS_MEAS_TIME

Bits 28-30: Select the RSSI measurement duration during Antenna switching procedure.

AS_CS_BLANKING

Bit 31: Blank received data if signal is below the CS threshold.

IQC_CONFIG

IQC_CONFIG register

Offset: 0x34, size: 32, reset: 0xC0000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IQC_ENABLE rw	REUSE_CORRECTION rw	LOAD_IQC_INIT w						IQC_CORRECT_IN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IQC_CORRECT_IN rw

Toggle fields

IQC_CORRECT_IN

Bits 0-23: Correction value Input for the IQ compensation engine (to be used as starting point or when the engine is disabled)..

LOAD_IQC_INIT

Bit 29: Action bit to load the IQC_CORRECT_IN[23:0] bit field in the recirculation register when this bit is written to 1..

REUSE_CORRECTION

Bit 30: Reuse last correction value.

IQC_ENABLE

Bit 31: Enable IQC.

DSSS_CTRL

DSSS_CTRL register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACQ_THR rw						ACQ_HITS rw		DSSS_EN rw	SPREADING_EXP rw			ACQ_WINDOW rw

Toggle fields

ACQ_WINDOW

Bits 0-3: DSSS acquisition window.

SPREADING_EXP

Bits 4-6: DSSS spreading exponent.

DSSS_EN

Bit 7: DSSS mode enable.

ACQ_HITS

Bits 8-9: DSSS acquisition hits.

ACQ_THR

Bits 10-15: DSSS acquisition threshold.

STATUS

0x49000600:

21/52 fields covered.

Toggle register map

Offset	Name	31	30	28	27	26	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	RFSEQ_IRQ_STATUS	AGC_CALIB_DONE_F	SAFEASK_CALIB_DONE_F	RRM_CMD_END_F	RRM_CMD_START_F	SEQ_F	HW_ANA_FAILURE_F		AHB_ACCESS_ERROR_F	TX_ALMOST_EMPTY_1_F	TX_ALMOST_EMPTY_0_F	RX_ALMOST_FULL_1_F	RX_ALMOST_FULL_0_F	DATABUFFER1_USED_F	DATABUFFER0_USED_F		SYNC_VALID_F	PREAMBLE_VALID_F	CS_F			COMMAND_REJECTED_F	SABORT_DONE_F	RXTIMER_STOP_CDT_F			FAST_RX_TERM_F	RX_CRC_FRROR_F	RX_TIMEOUT_F	RX_OK_F	TX_DONE_F
0x4	RFSEQ_STATUS_DETAIL															SEQ_COMPLETE_F	SEQ_ACTIONTIMEOUT_F			PLL_CALAMP_ERROR_F	PLL_CALFREQ_ERROR_F	PLL_UNLOCK_F	PLL_LOCK_FAIL_F			DBM_FIFO_ERROR_F
0x8	RADIO_FSM_INFO																										RADIO_FSM_STATE
0xc	RX_INDICATOR	ANT_SELECT			AGC_WORD						RSSI_LEVEL_RUN					RSSI_LEVEL_RUN							RSSI_LEVEL_ON_SYNC
0x10	RX_INFO_REG															RX_PCKTLEN_OUT
0x14	RX_CRC_REG	RX_CRC_OUT														RX_CRC_OUT
0x18	QI_INFO							AFC_CORRECTION									SQI_SEC	SQI_INFO						PQI_INFO
0x1c	DATABUFFER_INFO	CURRENT_DATABUFFER	NB_DATABUFFER_USED													CURRENT_DATABUFFER_COUNT
0x20	TIME_CAPTURE	TIME_CAPTURE														TIME_CAPTURE
0x24	IQC_CORRECTION_OUT							IQC_CORRECT_OUT								IQC_CORRECT_OUT
0x28	PA_SAFEASK_OUT																							PA_CODEMAX
0x2c	VCO_CALIB_OUT									VCO_CALAMP_OUT						VCO_CALAMP_OUT									VCO_CALFREQ_OUT
0x30	SEQ_INFO																										SEQ_FSM_STATE
0x34	SEQ_EVENT_STATUS	SEQ_EVENT_STATUS														SEQ_EVENT_STATUS

Toggle registers

RFSEQ_IRQ_STATUS

RFSEQ_IRQ_STATUS register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AGC_CALIB_DONE_F rw	SAFEASK_CALIB_DONE_F rw		RRM_CMD_END_F rw	RRM_CMD_START_F rw	SEQ_F rw		HW_ANA_FAILURE_F rw		AHB_ACCESS_ERROR_F rw	TX_ALMOST_EMPTY_1_F rw	TX_ALMOST_EMPTY_0_F rw	RX_ALMOST_FULL_1_F rw	RX_ALMOST_FULL_0_F rw	DATABUFFER1_USED_F rw	DATABUFFER0_USED_F rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SYNC_VALID_F rw	PREAMBLE_VALID_F rw	CS_F rw			COMMAND_REJECTED_F rw	SABORT_DONE_F rw	RXTIMER_STOP_CDT_F rw			FAST_RX_TERM_F rw	RX_CRC_FRROR_F rw	RX_TIMEOUT_F rw	RX_OK_F rw	TX_DONE_F rw

Toggle fields

TX_DONE_F

Bit 0: Transmission done flag.

RX_OK_F

Bit 1: Reception ended and OK flag.

RX_TIMEOUT_F

Bit 2: Reception timeout flag.

RX_CRC_FRROR_F

Bit 3: Reception with CRC error flag.

FAST_RX_TERM_F

Bit 4: Fast RX Termination flag.

RXTIMER_STOP_CDT_F

Bit 7: Enable interrupt on RXTIMER_STOP_CDT_F flag.

SABORT_DONE_F

Bit 8: SABORT command treated and done flag.

COMMAND_REJECTED_F

Bit 9: Command rejection flag..

CS_F

Bit 12: Carrier Sense (RSSI over threshold) flag.

PREAMBLE_VALID_F

Bit 13: Valid PREAMBLE detection flag..

SYNC_VALID_F

Bit 14: Valid SYNC word detection flag..

DATABUFFER0_USED_F

Bit 16: Data Buffer 0 fully read in TX or fully written in RX flag.

DATABUFFER1_USED_F

Bit 17: Data Buffer 1 fully read in TX or fully written in RX flag.

RX_ALMOST_FULL_0_F

Bit 18: Data Buffer0 used (written during a RX) up to programmed thresold flag.

RX_ALMOST_FULL_1_F

Bit 19: Data Buffer1 used (written during a RX) up to programmed thresold flag.

TX_ALMOST_EMPTY_0_F

Bit 20: Data Buffer0 used (read during a TX) up to programmed thresold flag.

TX_ALMOST_EMPTY_1_F

Bit 21: Data Buffer1 used (read during a TX) up to programmed thresold flag.

AHB_ACCESS_ERROR_F

Bit 22: An AHB transfer issue occurred for one of the AHB masters (RRM, Data Buffer Manager, Sequencer)..

HW_ANA_FAILURE_F

Bit 24: Analog HW failure flag (PLL lock / unlock error, calibration error).

SEQ_F

Bit 26: Sequencer completion flag..

RRM_CMD_START_F

Bit 27: RRM-UDRA command list execution started flag..

RRM_CMD_END_F

Bit 28: RRM-UDRA command list execution ended flag..

SAFEASK_CALIB_DONE_F

Bit 30: End of Safe-ASK PA calibration flag..

AGC_CALIB_DONE_F

Bit 31: Valid RSSI value available in the RSSI_RUNNING bit field flag..

RFSEQ_STATUS_DETAIL

RFSEQ_STATUS_DETAIL register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ_COMPLETE_F rw	SEQ_ACTIONTIMEOUT_F rw			PLL_CALAMP_ERROR_F rw	PLL_CALFREQ_ERROR_F rw	PLL_UNLOCK_F rw	PLL_LOCK_FAIL_F rw			DBM_FIFO_ERROR_F rw

Toggle fields

DBM_FIFO_ERROR_F

Bit 5: Data Buffer Manager internal FIFO overflow/underflow flag..

PLL_LOCK_FAIL_F

Bit 8: PLL lock fail status flag.

PLL_UNLOCK_F

Bit 9: PLL unlock event flag.

PLL_CALFREQ_ERROR_F

Bit 10: VCO frequency calibration error flag.

PLL_CALAMP_ERROR_F

Bit 11: VCO amplitude calibration error flag.

SEQ_ACTIONTIMEOUT_F

Bit 14: The Sequencer has ended because the current SeqAction reached its ActionTimeout..

SEQ_COMPLETE_F

Bit 15: The Sequencer has ended the last defined SeqAction properly( NextAction math or null pointer).

RADIO_FSM_INFO

RADIO_FSM_INFO register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RADIO_FSM_STATE r

Toggle fields

RADIO_FSM_STATE

Bits 0-4: State of the Radio FSM.

RX_INDICATOR

RX_INDICATOR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ANT_SELECT r				AGC_WORD r							RSSI_LEVEL_RUN r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSSI_LEVEL_RUN r							RSSI_LEVEL_ON_SYNC r

Toggle fields

RSSI_LEVEL_ON_SYNC

Bits 0-8: RSSI level captured at the end of the SYNC word detection of the received packet..

RSSI_LEVEL_RUN

Bits 12-20: Continuous level of the output of the measured RSSI value.

AGC_WORD

Bits 24-27: AGC word of the received packet..

ANT_SELECT

Bit 31: Currently selected antenna.

RX_INFO_REG

RX_INFO_REG register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_PCKTLEN_OUT r

Toggle fields

RX_PCKTLEN_OUT

Bits 0-15: Indicates received packet length in bytes:.

RX_CRC_REG

RX_CRC_REG register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RX_CRC_OUT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_CRC_OUT r

Toggle fields

RX_CRC_OUT

Bits 0-31: CRC field of the received packet (read-only info).

QI_INFO

QI_INFO register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								AFC_CORRECTION r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SQI_SEC r	SQI_INFO r						PQI_INFO r

Toggle fields

PQI_INFO

Bits 0-7: Preamble Quality Indicator (PQI) value of the received packet..

SQI_INFO

Bits 8-13: SYNC Quality Indicator (SQI) value of the received packet..

SQI_SEC

Bit 14: Indicate if measured SQI refers to SYNC word or secondary SYNC word.

AFC_CORRECTION

Bits 16-23: AFC value frozen at sync reception..

DATABUFFER_INFO

DATABUFFER_INFO register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CURRENT_DATABUFFER r	NB_DATABUFFER_USED r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CURRENT_DATABUFFER_COUNT r

Toggle fields

CURRENT_DATABUFFER_COUNT

Bits 0-15: Indicates the number of bytes used in the last used DATA BUFFER..

NB_DATABUFFER_USED

Bits 16-30: Provides the number of data buffers which have been fully used.

CURRENT_DATABUFFER

Bit 31: Indicates which Data Buffer is currently used by the HW.

TIME_CAPTURE

TIME_CAPTURE register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TIME_CAPTURE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIME_CAPTURE r

Toggle fields

TIME_CAPTURE

Bits 0-31: Interpolated absolute time value captured on specific programmable event through TIME_CAPTURESEL[2:0] bit field..

IQC_CORRECTION_OUT

IQC_CORRECTION_OUT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								IQC_CORRECT_OUT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IQC_CORRECT_OUT r

Toggle fields

IQC_CORRECT_OUT

Bits 0-23: Final correction value output from IQC (compensation engine)..

PA_SAFEASK_OUT

PA_SAFEASK_OUT register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PA_CODEMAX r

Toggle fields

PA_CODEMAX

Bits 0-7: Safe ASK level (provided after a CALIB_SAFEASK command), indicating the maximum PA Power to program before reaching ohmic saturation..

VCO_CALIB_OUT

VCO_CALIB_OUT register

Offset: 0x2c, size: 32, reset: 0x0000FF40, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										VCO_CALAMP_OUT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VCO_CALAMP_OUT r									VCO_CALFREQ_OUT r

Toggle fields

VCO_CALFREQ_OUT

Bits 0-6: VCO frequency calibration value currently output by the VCO calibration block (and applied on the VCO when ON).

VCO_CALAMP_OUT

Bits 8-21: VCO amplitude calibration value currently output by the VCO calibration block (and applied on the VCO when ON).

SEQ_INFO

SEQ_INFO register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											SEQ_FSM_STATE r

Toggle fields

SEQ_FSM_STATE

Bits 0-4: Current state of the Sequencer.

SEQ_EVENT_STATUS

SEQ_EVENT_STATUS register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SEQ_EVENT_STATUS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEQ_EVENT_STATUS r

Toggle fields

SEQ_EVENT_STATUS

Bits 0-31: Current value of the seq_event_status used by the Sequencer for next action mask comparison..

SWITCHABLE

0x49001040:

3/12 fields covered.

Toggle register map

Offset	Name	31	15	11	7	3	2	1	0
0x0	RFIP_VERSION		PRODUCT	VERSION	REVISION
0x4	IRQ_ENABLE					FRAME_VALID_E	FRAME_COMPLETE_E	FRAME_SYNC_COMPLETE_E	BIT_SYNC_DETECTED_E
0x8	STATUS	ERROR_F				FRAME_VALID_F	FRAME_COMPLETE_F	FRAME_SYNC_COMPLETE_F	BIT_SYNC_DETECTED_F

Toggle registers

RFIP_VERSION

RFIP_VERSION register

Offset: 0x0, size: 32, reset: 0x00001100, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRODUCT r				VERSION r				REVISION r

Toggle fields

REVISION

Bits 4-7: Revision of the RFIP to be used for metal fixes).

VERSION

Bits 8-11: Version of the RFIP (to be used for cut upgrades).

PRODUCT

Bits 12-15: Used for major upgrades (new protocols support / new features).

IRQ_ENABLE

IRQ_ENABLE register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												FRAME_VALID_E rw	FRAME_COMPLETE_E rw	FRAME_SYNC_COMPLETE_E rw	BIT_SYNC_DETECTED_E rw

Toggle fields

BIT_SYNC_DETECTED_E

Bit 0: Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid..

FRAME_SYNC_COMPLETE_E

Bit 1: Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid..

FRAME_COMPLETE_E

Bit 2: Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid..

FRAME_VALID_E

Bit 3: Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC)..

STATUS

STATUS register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ERROR_F rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												FRAME_VALID_F rw	FRAME_COMPLETE_F rw	FRAME_SYNC_COMPLETE_F rw	BIT_SYNC_DETECTED_F rw

Toggle fields

BIT_SYNC_DETECTED_F

Bit 0: Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid..

FRAME_SYNC_COMPLETE_F

Bit 1: Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid..

FRAME_COMPLETE_F

Bit 2: Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid..

FRAME_VALID_F

Bit 3: Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC)..

ERROR_F

Bits 30-31: - 11 : CRC error.

SYSTEM_CTRL

0x40000000:

9/207 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DIE_ID																					PRODUCT				VERSION				REVISION
0x4	JTAG_ID	VERSION_NUMBER				PART_NUMBER												PART_NUMBER				MANUF_ID
0x8	I2C_FMP_CTRL																							I2C2_PA14_FMP	I2C2_PA13_FMP	I2C2_PA7_FMP	I2C2_PA6_FMP	I2C1_PB11_FMP	I2C1_PB10_FMP	I2C1_PB7_FMP	I2C1_PB6_FMP	I2C1_PA1_FMP	I2C1_PA0_FMP
0xc	IO_DTR	PB15_DT	PB14_DT	PB13_DT	PB12_DT	PB11_DT	PB10_DT	PB9_DT	PB8_DT	PB7_DT	PB6_DT	PB5_DT	PB4_DT	PB3_DT	PB2_DT	PB1_DT	PB0_DT	PA15_DT	PA14_DT	PA13_DT	PA12_DT	PA11_DT	PA10_DT	PA9_DT	PA8_DT	PA7_DT	PA6_DT	PA5_DT	PA4_DT	PA3_DT	PA2_DT	PA1_DT	PA0_DT
0x10	IO_IBER	PB15_IBE	PB14_IBE	PB13_IBE	PB12_IBE	PB11_IBE	PB10_IBE	PB9_IBE	PB8_IBE	PB7_IBE	PB6_IBE	PB5_IBE	PB4_IBE	PB3_IBE	PB2_IBE	PB1_IBE	PB0_IBE	PA15_IBE	PA14_IBE	PA13_IBE	PA12_IBE	PA11_IBE	PA10_IBE	PA9_IBE	PA8_IBE	PA7_IBE	PA6_IBE	PA5_IBE	PA4_IBE	PA3_IBE	PA2_IBE	PA1_IBE	PA0_IBE
0x14	IO_IEVR	PB15_IEV	PB14_IEV	PB13_IEV	PB12_IEV	PB11_IEV	PB10_IEV	PB9_IEV	PB8_IEV	PB7_IEV	PB6_IEV	PB5_IEV	PB4_IEV	PB3_IEV	PB2_IEV	PB1_IEV	PB0_IEV	PA15_IEV	PA14_IEV	PA13_IEV	PA12_IEV	PA11_IEV	PA10_IEV	PA9_IEV	PA8_IEV	PA7_IEV	PA6_IEV	PA5_IEV	PA4_IEV	PA3_IEV	PA2_IEV	PA1_IEV	PA0_IEV
0x18	IO_IER	PB15_IE	PB14_IE	PB13_IE	PB12_IE	PB11_IE	PB10_IE	PB9_IE	PB8_IE	PB7_IE	PB6_IE	PB5_IE	PB4_IE	PB3_IE	PB2_IE	PB1_IE	PB0_IE	PA15_IE	PA14_IE	PA13_IE	PA12_IE	PA11_IE	PA10_IE	PA9_IE	PA8_IE	PA7_IE	PA6_IE	PA5_IE	PA4_IE	PA3_IE	PA2_IE	PA1_IE	PA0_IE
0x1c	IO_ISCR	PB15_ISC	PB14_ISC	PB13_ISC	PB12_ISC	PB11_ISC	PB10_ISC	PB9_ISC	PB8_ISC	PB7_ISC	PB6_ISC	PB5_ISC	PB4_ISC	PB3_ISC	PB2_ISC	PB1_ISC	PB0_ISC	PA15_ISC	PA14_ISC	PA13_ISC	PA12_ISC	PA11_ISC	PA10_ISC	PA9_ISC	PA8_ISC	PA7_ISC	PA6_ISC	PA5_ISC	PA4_ISC	PA3_ISC	PA2_ISC	PA1_ISC	PA0_ISC
0x20	PWRC_IER																														WKUP_IE	PVD_IE	BORH_IE
0x24	PWRC_ISCR																														WKUP_ISC	PVD_ISC	BORH_ISC
0x28	GPIO_SWA_CTRL																																ATB1_nPVD
0x2c	INTAI_DTR																											RFIP_BUSY_STATUS_DT	COMP_DT			RX_DT	TX_DT
0x30	INTAI_IBER																											RFIP_BUSY_STATUS_IBE	COMP_IBE			RX_IBE	TX_IBE
0x34	INTAI_IEVR																											RFIP_BUSY_STATUS_IEV	COMP_IEV			RX_IEV	TX_IEV
0x38	INTAI_IER																											RFIP_BUSY_STATUS_IE	COMP_IE			RX_IE	TX_IE
0x3c	INTAI_ISCR																											RFIP_BUSY_STATUS_ISC	COMP_ISC	RX_ISEDGE	TX_ISEDGE	RX_ISC	TX_ISC
0x40	SYSCFG_SR1																											RFIP_BUSY_STATUS
0x44	RF_DTB_CONFIG																															RF_DTB_CONFIG

Toggle registers

DIE_ID

DIE_ID register

Offset: 0x0, size: 32, reset: 0x00000120, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PRODUCT r				VERSION r				REVISION r

Toggle fields

REVISION

Bits 0-3: Cut revision (metal fix).

VERSION

Bits 4-7: Cut version.

PRODUCT

Bits 8-11: Product version. May be used to discriminate several version of a same digital BLE LPH device embedding different analog versions.

JTAG_ID

JTAG_ID register

Offset: 0x4, size: 32, reset: 0x02027041, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VERSION_NUMBER r				PART_NUMBER r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PART_NUMBER r				MANUF_ID r

Toggle fields

MANUF_ID

Bits 1-11: Manufacturer ID.

PART_NUMBER

Bits 12-27: Part number.

VERSION_NUMBER

Bits 28-31: Version.

I2C_FMP_CTRL

I2C_FMP_CTRL register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						I2C2_PA14_FMP rw	I2C2_PA13_FMP rw	I2C2_PA7_FMP rw	I2C2_PA6_FMP rw	I2C1_PB11_FMP rw	I2C1_PB10_FMP rw	I2C1_PB7_FMP rw	I2C1_PB6_FMP rw	I2C1_PA1_FMP rw	I2C1_PA0_FMP rw

Toggle fields

I2C1_PA0_FMP

Bit 0: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. 0: PA0 pin operated in standard mode. 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed.

I2C1_PA1_FMP

Bit 1: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. 0: PA1 pin operated in standard mode. 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed.

I2C1_PB6_FMP

Bit 2: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. 0: PB6 pin operated in standard mode. 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed..

I2C1_PB7_FMP

Bit 3: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. 0: PB7 pin operated in standard mode. 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed.

I2C1_PB10_FMP

Bit 4: I2C1_PB10_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB10 I/O. 0: PB10 pin operated in standard mode. 1: FM+ mode is enabled on PB10 pin, and speed control is bypassed..

I2C1_PB11_FMP

Bit 5: I2C1_PB11_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB11 I/O. 0: PB11 pin operated in standard mode. 1: FM+ mode is enabled on PB11 pin, and speed control is bypassed.

I2C2_PA6_FMP

Bit 6: I2C2_PA6_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA6 I/O. 0: PA6 pin operated in standard mode. 1: FM+ mode is enabled on PA6 pin, and speed control is bypassed..

I2C2_PA7_FMP

Bit 7: I2C2_PA7_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA7 I/O. 0: PA7 pin operated in standard mode. 1: FM+ mode is enabled on PA7 pin, and speed control is bypassed.

I2C2_PA13_FMP

Bit 8: I2C2_PA13_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA13 I/O. 0: PA13 pin operated in standard mode. 1: FM+ mode is enabled on PA13 pin, and speed control is bypassed..

I2C2_PA14_FMP

Bit 9: I2C2_PA14_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA14 I/O. 0: PA14 pin operated in standard mode. 1: FM+ mode is enabled on PA14 pin, and speed control is bypassed..

IO_DTR

IO_DTR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_DT rw	PB14_DT rw	PB13_DT rw	PB12_DT rw	PB11_DT rw	PB10_DT rw	PB9_DT rw	PB8_DT rw	PB7_DT rw	PB6_DT rw	PB5_DT rw	PB4_DT rw	PB3_DT rw	PB2_DT rw	PB1_DT rw	PB0_DT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_DT rw	PA14_DT rw	PA13_DT rw	PA12_DT rw	PA11_DT rw	PA10_DT rw	PA9_DT rw	PA8_DT rw	PA7_DT rw	PA6_DT rw	PA5_DT rw	PA4_DT rw	PA3_DT rw	PA2_DT rw	PA1_DT rw	PA0_DT rw

Toggle fields

PA0_DT

Bit 0: PA0_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA1_DT

Bit 1: PA1_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA2_DT

Bit 2: PA2_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA3_DT

Bit 3: PA3_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA4_DT

Bit 4: PA4_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA5_DT

Bit 5: PA5_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA6_DT

Bit 6: PA6_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA7_DT

Bit 7: PA7_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA8_DT

Bit 8: PA8_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA9_DT

Bit 9: PA9_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA10_DT

Bit 10: PA10_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA11_DT

Bit 11: PA11_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA12_DT

Bit 12: PA12_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA13_DT

Bit 13: PA13_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA14_DT

Bit 14: PA14_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PA15_DT

Bit 15: PA15_DT: Interrupt Detection Type for port A I/Os. 0: edge detection. 1: level detection..

PB0_DT

Bit 16: PB0_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB1_DT

Bit 17: PB1_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB2_DT

Bit 18: PB2_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB3_DT

Bit 19: PB3_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB4_DT

Bit 20: PB4_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB5_DT

Bit 21: PB5_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB6_DT

Bit 22: PB6_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB7_DT

Bit 23: PB7_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB8_DT

Bit 24: PB8_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB9_DT

Bit 25: PB9_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB10_DT

Bit 26: PB10_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB11_DT

Bit 27: PB11_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB12_DT

Bit 28: PB12_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB13_DT

Bit 29: PB13_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB14_DT

Bit 30: PB14_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

PB15_DT

Bit 31: PB15_DT: Interrupt Detection Type for port B I/Os. 0: edge detection. 1: level detection..

IO_IBER

IO_IBER register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IBE rw	PB14_IBE rw	PB13_IBE rw	PB12_IBE rw	PB11_IBE rw	PB10_IBE rw	PB9_IBE rw	PB8_IBE rw	PB7_IBE rw	PB6_IBE rw	PB5_IBE rw	PB4_IBE rw	PB3_IBE rw	PB2_IBE rw	PB1_IBE rw	PB0_IBE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_IBE rw	PA14_IBE rw	PA13_IBE rw	PA12_IBE rw	PA11_IBE rw	PA10_IBE rw	PA9_IBE rw	PA8_IBE rw	PA7_IBE rw	PA6_IBE rw	PA5_IBE rw	PA4_IBE rw	PA3_IBE rw	PA2_IBE rw	PA1_IBE rw	PA0_IBE rw

Toggle fields

PA0_IBE

Bit 0: PA0_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA1_IBE

Bit 1: PA1_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA2_IBE

Bit 2: PA2_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA3_IBE

Bit 3: PA3_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA4_IBE

Bit 4: PA4_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA5_IBE

Bit 5: PA5_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA6_IBE

Bit 6: PA6_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA7_IBE

Bit 7: PA7_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA8_IBE

Bit 8: PA8_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA9_IBE

Bit 9: PA9_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA10_IBE

Bit 10: PA10_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA11_IBE

Bit 11: PA11_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA12_IBE

Bit 12: PA12_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA13_IBE

Bit 13: PA13_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA14_IBE

Bit 14: PA14_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PA15_IBE

Bit 15: PA15_IBE: Interrupt edge selection for Port A I/Os. 0: single edge detection. 1: both edges detection.

PB0_IBE

Bit 16: PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB1_IBE

Bit 17: PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB2_IBE

Bit 18: PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB3_IBE

Bit 19: PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB4_IBE

Bit 20: PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB5_IBE

Bit 21: PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB6_IBE

Bit 22: PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB7_IBE

Bit 23: PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB8_IBE

Bit 24: PB8_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB9_IBE

Bit 25: PB9_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB10_IBE

Bit 26: PB10_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB11_IBE

Bit 27: PB11_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB12_IBE

Bit 28: PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB13_IBE

Bit 29: PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB14_IBE

Bit 30: PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

PB15_IBE

Bit 31: PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. 1: both edges detection..

IO_IEVR

IO_IEVR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IEV rw	PB14_IEV rw	PB13_IEV rw	PB12_IEV rw	PB11_IEV rw	PB10_IEV rw	PB9_IEV rw	PB8_IEV rw	PB7_IEV rw	PB6_IEV rw	PB5_IEV rw	PB4_IEV rw	PB3_IEV rw	PB2_IEV rw	PB1_IEV rw	PB0_IEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_IEV rw	PA14_IEV rw	PA13_IEV rw	PA12_IEV rw	PA11_IEV rw	PA10_IEV rw	PA9_IEV rw	PA8_IEV rw	PA7_IEV rw	PA6_IEV rw	PA5_IEV rw	PA4_IEV rw	PA3_IEV rw	PA2_IEV rw	PA1_IEV rw	PA0_IEV rw

Toggle fields

PA0_IEV

Bit 0: PA0_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA1_IEV

Bit 1: PA1_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA2_IEV

Bit 2: PA2_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA3_IEV

Bit 3: PA3_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA4_IEV

Bit 4: PA4_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA5_IEV

Bit 5: PA5_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA6_IEV

Bit 6: PA6_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA7_IEV

Bit 7: PA7_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA8_IEV

Bit 8: PA8_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA9_IEV

Bit 9: PA9_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA10_IEV

Bit 10: PA10_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA11_IEV

Bit 11: PA11_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA12_IEV

Bit 12: PA12_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA13_IEV

Bit 13: PA13_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA14_IEV

Bit 14: PA14_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PA15_IEV

Bit 15: PA15_IEV : Interrupt polarity event for Port A I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB0_IEV

Bit 16: PB0_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB1_IEV

Bit 17: PB1_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB2_IEV

Bit 18: PB2_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB3_IEV

Bit 19: PB3_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB4_IEV

Bit 20: PB4_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB5_IEV

Bit 21: PB5_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB6_IEV

Bit 22: PB6_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB7_IEV

Bit 23: PB7_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB8_IEV

Bit 24: PB8_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB9_IEV

Bit 25: PB9_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB10_IEV

Bit 26: PB10_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB11_IEV

Bit 27: PB11_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB12_IEV

Bit 28: PB12_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB13_IEV

Bit 29: PB13_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB14_IEV

Bit 30: PB14_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

PB15_IEV

Bit 31: PB15_IEV : Interrupt polarity event for Port B I/Os. 0: falling edge / low level. 1: rising edge / high level..

IO_IER

IO_IER register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_IE rw	PB14_IE rw	PB13_IE rw	PB12_IE rw	PB11_IE rw	PB10_IE rw	PB9_IE rw	PB8_IE rw	PB7_IE rw	PB6_IE rw	PB5_IE rw	PB4_IE rw	PB3_IE rw	PB2_IE rw	PB1_IE rw	PB0_IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_IE rw	PA14_IE rw	PA13_IE rw	PA12_IE rw	PA11_IE rw	PA10_IE rw	PA9_IE rw	PA8_IE rw	PA7_IE rw	PA6_IE rw	PA5_IE rw	PA4_IE rw	PA3_IE rw	PA2_IE rw	PA1_IE rw	PA0_IE rw

Toggle fields

PA0_IE

Bit 0: PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA1_IE

Bit 1: PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA2_IE

Bit 2: PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA3_IE

Bit 3: PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA4_IE

Bit 4: PA4_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA5_IE

Bit 5: PA5_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA6_IE

Bit 6: PA6_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA7_IE

Bit 7: PA7_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA8_IE

Bit 8: PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA9_IE

Bit 9: PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA10_IE

Bit 10: PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA11_IE

Bit 11: PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA12_IE

Bit 12: PA12_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA13_IE

Bit 13: PA13_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA14_IE

Bit 14: PA14_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PA15_IE

Bit 15: PA15_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB0_IE

Bit 16: PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB1_IE

Bit 17: PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB2_IE

Bit 18: PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB3_IE

Bit 19: PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB4_IE

Bit 20: PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB5_IE

Bit 21: PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB6_IE

Bit 22: PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB7_IE

Bit 23: PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB8_IE

Bit 24: PB8_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB9_IE

Bit 25: PB9_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB10_IE

Bit 26: PB10_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB11_IE

Bit 27: PB11_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB12_IE

Bit 28: PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB13_IE

Bit 29: PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB14_IE

Bit 30: PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

PB15_IE

Bit 31: PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. 1: interrupt is enabled..

IO_ISCR

IO_ISCR register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_ISC rw	PB14_ISC rw	PB13_ISC rw	PB12_ISC rw	PB11_ISC rw	PB10_ISC rw	PB9_ISC rw	PB8_ISC rw	PB7_ISC rw	PB6_ISC rw	PB5_ISC rw	PB4_ISC rw	PB3_ISC rw	PB2_ISC rw	PB1_ISC rw	PB0_ISC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_ISC rw	PA14_ISC rw	PA13_ISC rw	PA12_ISC rw	PA11_ISC rw	PA10_ISC rw	PA9_ISC rw	PA8_ISC rw	PA7_ISC rw	PA6_ISC rw	PA5_ISC rw	PA4_ISC rw	PA3_ISC rw	PA2_ISC rw	PA1_ISC rw	PA0_ISC rw

Toggle fields

PA0_ISC

Bit 0: PA0_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA1_ISC

Bit 1: PA1_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA2_ISC

Bit 2: PA2_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA3_ISC

Bit 3: PA3_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA4_ISC

Bit 4: PA4_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA5_ISC

Bit 5: PA5_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA6_ISC

Bit 6: PA6_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA7_ISC

Bit 7: PA7_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA8_ISC

Bit 8: PA8_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA9_ISC

Bit 9: PA9_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA10_ISC

Bit 10: PA10_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA11_ISC

Bit 11: PA11_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA12_ISC

Bit 12: PA12_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA13_ISC

Bit 13: PA13_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA14_ISC

Bit 14: PA14_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PA15_ISC

Bit 15: PA15_ISC: Interrupt status (before mask) for port a I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB0_ISC

Bit 16: PB0_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB1_ISC

Bit 17: PB1_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB2_ISC

Bit 18: PB2_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB3_ISC

Bit 19: PB3_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB4_ISC

Bit 20: PB4_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB5_ISC

Bit 21: PB5_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB6_ISC

Bit 22: PB6_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB7_ISC

Bit 23: PB7_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB8_ISC

Bit 24: PB8_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB9_ISC

Bit 25: PB9_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB10_ISC

Bit 26: PB10_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB11_ISC

Bit 27: PB11_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB12_ISC

Bit 28: PB12_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB13_ISC

Bit 29: PB13_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB14_ISC

Bit 30: PB14_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PB15_ISC

Bit 31: PB15_ISC: Interrupt status (before mask) for port B I/Os. 0: no pending interrupt. 1: event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PWRC_IER

PWRC_IER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WKUP_IE rw	PVD_IE rw	BORH_IE rw

Toggle fields

BORH_IE

Bit 0: BORH_IE: BORH interrupt enable. 0: BORH interrupt is disabled. 1: BORH interrupt is enabled..

PVD_IE

Bit 1: PVD_IE: Programmable Voltage Detector interrupt enable. 0: PVD interrupt is disabled. 1: PVD interrupt is enabled..

WKUP_IE

Bit 2: WKUP_IE: Power Controller Wakeup event interrupt enable. 0: Interrupt on wakeup event seen by the PWRC is disabled. 1: Interrupt on wakeup event seen by the PWRC is enabled..

PWRC_ISCR

PWRC_ISCR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WKUP_ISC rw	PVD_ISC rw	BORH_ISC rw

Toggle fields

BORH_ISC

Bit 0: BORH_ISC: BORH interrupt status. 0: no pending interrupt. 1: voltage went under BORH threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

PVD_ISC

Bit 1: PVD_ISC: Programmable Voltage Detector status. 0: no pending interrupt. 1: voltage went under programmed threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit..

WKUP_ISC

Bit 2: WKUP_ISC: Indicates the Power Controller receives a Wakeup event. 0: no pending interrupt. 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). Cleared by writing 1 in the bit. This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry requests that the PWRC aborts before shutting down the system..

GPIO_SWA_CTRL

GPIO_SWA_CTRL register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															ATB1_nPVD rw

Toggle fields

ATB1_nPVD

Bit 0: ATB1_nPVD: select the analog feature on PB14 between ATB1 and PVD when the PB14 I/O is programmed in analog mode (in the associated GPIO_MODER register): 0: PVD external voltage feature is selected (default). 1: ATB1 feature is selected.

INTAI_DTR

INTAI_DTR register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RFIP_BUSY_STATUS_DT rw	COMP_DT rw			RX_DT rw	TX_DT rw

Toggle fields

TX_DT

Bit 0: TX_DT: detection type on TX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level.

RX_DT

Bit 1: RX_DT: detection type on RX_SEQUENCE signal: 0: detection on edge (default). 1: detection on level.

COMP_DT

Bit 4: COMP_DT: detection type on COMP_OUT (after COMP_POL selection) signal: 0: detection on edge (default). 1: detection on level.

RFIP_BUSY_STATUS_DT

Bit 5: RFIP_BUSY_STATUS_DT: detection type on RFIP_BUSY_STATUS signal: 0: detection on edge (default). 1: detection on level.

INTAI_IBER

INTAI_IBER register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RFIP_BUSY_STATUS_IBE rw	COMP_IBE rw			RX_IBE rw	TX_IBE rw

Toggle fields

TX_IBE

Bit 0: TX_IBE: interrupt edge register on TX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges.

RX_IBE

Bit 1: RX_IBE: interrupt edge register on RX_SEQUENCE signal: 0: detection on single edge (default). 1: detection on both edges.

COMP_IBE

Bit 4: COMP_IBE: interrupt edge register on COMP_OUT signal: 0: detection on single edge (default). 1: detection on both edges.

RFIP_BUSY_STATUS_IBE

Bit 5: RFIP_BUSY_STATUS_IBE: interrupt edge register on RFIP_BUSY_STATUS signal: 0: detection on single edge (default). 1: detection on both edges.

INTAI_IEVR

INTAI_IEVR register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RFIP_BUSY_STATUS_IEV rw	COMP_IEV rw			RX_IEV rw	TX_IEV rw

Toggle fields

TX_IEV

Bit 0: TX_IEV: interrupt polarity event on TX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

RX_IEV

Bit 1: RX_IEV: interrupt polarity event on RX_SEQUENCE signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

COMP_IEV

Bit 4: COMP_IEV: interrupt polarity event on COMP_OUT signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

RFIP_BUSY_STATUS_IEV

Bit 5: RFIP_BUSY_STATUS_IEV: interrupt polarity event on RFIP_BUSY_STATUS signal: 0: detection on falling edge / low level (default). 1: detection on rising edge / high level.

INTAI_IER

INTAI_IER register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RFIP_BUSY_STATUS_IE rw	COMP_IE rw			RX_IE rw	TX_IE rw

Toggle fields

TX_IE

Bit 0: TX_IE: interrupt enable on TX_SEQUENCE signal: 0: TX_SEQUENCE interrupt is disabled (default). 1: TX_SEQUENCE interrupt is enabled.

RX_IE

Bit 1: RX_IE: interrupt enable on RX_SEQUENCE signal: 0: RX_SEQUENCE interrupt is disabled (default). 1: RX_SEQUENCE interrupt is enabled.

COMP_IE

Bit 4: COMP_IE: interrupt enable on COMP_OUT signal: 0: COMP_OUT interrupt is disabled (default). 1: COMP_OUT interrupt is enabled.

RFIP_BUSY_STATUS_IE

Bit 5: RFIP_BUSY_STATUS_IE: interrupt enable on RFIP_BUSY_STATUS signal: 0: RFIP_BUSY_STATUS interrupt is disabled (default). 1: RFIP_BUSY_STATUS interrupt is enabled.

INTAI_ISCR

INTAI_ISCR register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RFIP_BUSY_STATUS_ISC rw	COMP_ISC rw	RX_ISEDGE r	TX_ISEDGE r	RX_ISC rw	TX_ISC rw

Toggle fields

TX_ISC

Bit 0: TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on TX_SEQUENCE detected. 1: activity on TX_SEQUENCE occurred.

RX_ISC

Bit 1: RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: no activity on RX_SEQUENCE detected. 1: activity on RX_SEQUENCE occurred.

TX_ISEDGE

Bit 2: TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: 0: falling edge on TX_SEQUENCE detected. 1: rising edge on TX_SEQUENCE detected..

RX_ISEDGE

Bit 3: RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: 0: falling edge on RX_SEQUENCE detected. 1: rising edge on RX_SEQUENCE detected..

COMP_ISC

Bit 4: COMP_ISC: interrupt status on COMP_OUT (can be a rising or a falling edge depending on INTAI_IEVR and INTAI_IBER): 0: no activity on COMP_OUT detected. 1: activity on COMP_OUT occurred.

RFIP_BUSY_STATUS_ISC

Bit 5: RFIP_BUSY_STATUS_ISC: interrupt status on RFIP_BUSY_STATUS (can be a rising or a falling edge depending on INTAI_IEVR and INTAI_IBER): 0: no activity on RFIP_BUSY_STATUS detected. 1: activity on RFIP_BUSY_STATUS occurred.

SYSCFG_SR1

SYSCFG_SR1 register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RFIP_BUSY_STATUS r

Toggle fields

RFIP_BUSY_STATUS

Bit 5: RFIP_BUSY_STATUS: MR_SUBG BUSY status: Software should check that MR_SUBG IP is not busy (or relay on the related interrupt) before to initiate any system clock frequency switch to operate the switching in a safe way. 0: MR_SUBG is not busy. 1: MR_SUBG is busy.

RF_DTB_CONFIG

RF_DTB_CONFIG register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RF_DTB_CONFIG rw

Toggle fields

RF_DTB_CONFIG

Bits 0-1: Controlling AF7 extended mode: - 00 : MR_SUBG DTB default configuration - 01 : MR_SUBG DTB shuffled configuration - 10 : BUBBLE_DTB configuration - 11 : MR_SUBG DTB default configuration (as per 00).

TIM16

0x40005000: TIM16 address block description

1/79 fields covered.

Toggle register map

Offset	Name	31	28	26	21	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1										UIF_REMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2												OIS1N	OIS1	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR				TS_4_3	SMS_3									MSM	TS_2_0				SMS_2_0
0xc	DIER						BDE	TDE	CCUDE				CC1DE	UDE	BIE	TIE	COMIE				CC1IE	UIE
0x10	SR												CC1OF		BIF	TIF	COMIF				CC1IF	UIF
0x14	EGR														BG	TG	COMG				CC1G	UG
0x18	CCMR1					OC1M_3									OC1CE	OC1M_2_0			OC1PE	OC1FE	CC1S
0x18	CCMR1_in														IC1F				IC1PSC		CC1S
0x20	CCER																		CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIF_CPY					CNT
0x28	PSC						PSC
0x2c	ARR						ARR
0x30	RCR														REP
0x34	CCR1						CCR
0x44	BDTR		BKBID	BKDSRM			MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR									DBL								DBA
0x4c	DMAR						DMAB
0x50	OR1																			TI1_RMP		OR1_0
0x60	AF1											BKCMP1P	BKINP								BKCMP1E	BKINE
0x68	TISEL																		TI1SEL

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIF_REMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: - Counter overflow/underflow - Setting the UG bit - Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller..

URS

Bit 2: URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: - Counter overflow/underflow - Setting the UG bit - Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled..

OPM

Bit 3: OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN).

ARPE

Bit 7: ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered.

CKD

Bits 8-9: CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value.

UIF_REMAP

Bit 11: UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs.

MMS

Bits 4-6: MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO)..

TI1S

Bit 7: TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: Reserved.

OIS1

Bit 8: OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register)..

OIS1N

Bit 9: OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register)..

SMCR

SMCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS_4_3 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MSM rw	TS_2_0 rw				SMS_2_0 rw

Toggle fields

SMS_2_0

Bits 0-2: SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description..

TS_2_0

Bits 4-6: TS[4:0]: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1) Other codes: Reserved Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. See Table 79 in IUM: TIM16 register map and reset values on page 469 for more details on ITRx meaning for each Timer..

MSM

Bit 7: MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event..

SMS_3

Bit 16: SMS[3:0]: Slave mode selection. See SMS_LSB description.

TS_4_3

Bits 20-21: TS[4:0]: Trigger selection. See TS_LSB description.

DIER

DIER register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BDE rw	TDE rw	CCUDE rw				CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled.

CC1IE

Bit 1: CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled.

COMIE

Bit 5: COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled.

TIE

Bit 6: TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled.

BIE

Bit 7: BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled.

UDE

Bit 8: UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled.

CC1DE

Bit 9: CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled.

CCUDE

Bit 13: CCUDE: CC-Update DMA request Enable. Not used in Blue51. Not available in IUM 0: CC-Update DMA request disabled. 1: CC-Update DMA request enabled..

TDE

Bit 14: TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled.

BDE

Bit 15: BDE: Break DMA request Enable. Not used in Blue51. Not available in IUM 0: Break DMA request disabled. 1: Break DMA request enabled..

SR

SR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw	TIF rw	COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity).

COMIF

Bit 5: COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture compare control bits CCxE, CCxNE, OCxMhave been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending.

TIF

Bit 6: TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending.

BIF

Bit 7: BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input.

CC1OF

Bit 9: CC1OF: Capture_Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set.

EGR

EGR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)..

CC1G

Bit 1: CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

COMG

Bit 5: COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output..

TG

Bit 6: TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled..

CCMR1

CCMR1 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OC1CE rw	OC1M_2_0 rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

OC1FE

Bit 2: OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode..

OC1PE

Bit 3: OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note: 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M_2_0

Bits 4-6: OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits..

OC1CE

Bit 7: OC1CE: Output Compare 1 Clear Enable. Not used in Blue51. Not available in IUM 0: OC1REF is not affected by the ocref_clr_int signal. 1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal..

OC1M_3

Bit 16: OC1M[3]: Output Compare 1 mode (bit 3).

CCMR1_in

CCMR1_in register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

IC1PSC

Bits 2-3: IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events.

IC1F

Bits 4-7: Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N= 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8.

CCER

CCER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled.

CC1P

Bit 1: CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. 00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). 01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode. 10: Reserved, do not use this configuration. (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits..

CC1NP

Bit 3: CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer to the description of CC1P. Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). 2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

CNT

CNT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF_CPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: CNT[15:0]: Counter value.

UIF_CPY

Bit 31: UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

PSC register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode')..

ARR

ARR register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

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ARR

Bits 0-15: ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

RCR

RCR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

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REP

Bits 0-7: REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..

CCR1

CCR1 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

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CCR

Bits 0-15: CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)..

BDTR

BDTR register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

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DTG

Bits 0-7: DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63 us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

LOCK

Bits 8-9: LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in TIMx_AF1 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: BKE: Break enable 1; Break inputs (BRK) enabled Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: BKP: Break polarity 0: Break input BRK is active low. 1: Break input BRK is active high Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: AOE: Automatic output enable not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare enable register (TIMx_CCER))..

BKDSRM

Bit 26: BKDSRM: Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (opendrain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

DCR register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers..

DMAR

DMAR register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

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DMAB

Bits 0-15: DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

OR1

OR1 register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TI1_RMP rw		OR1_0 rw

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OR1_0

Bit 0: Not used in Blue51. Not available in IUM.

TI1_RMP

Bits 1-2: TI1_RMP[1:0]: Timer 16 input 1 connection This bit is set and cleared by software. 00: TIM16 TI1 is connected to GPIO 01: TIM16 TI1 is connected to LCO 10: TIM16 TI1 is connected to COMP_OUT 11: TIM16 TI1 is connected to MCO.

AF1

AF1 register

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					BKCMP1P rw	BKINP rw								BKCMP1E rw	BKINE rw

Toggle fields

BKINE

Bit 0: BKINE: BRK BKIN enable. This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is ORed with the other enabled BRK sources. 0: BKIN input disabled. 1: BKIN input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP1E

Bit 1: BKCMP1E: BRK COMP1 enable. This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKINP

Bit 9: BKINP: BRK BKIN input polarity. This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low. 1: BKIN input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

BKCMP1P

Bit 10: BKCMP1P: BRK COMP1 input polarity. This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low. 1: COMP1 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

TISEL

TISEL register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

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TI1SEL

Bits 0-3: TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIMx_CH1 input Others: Reserved.

TIM2

0x40002000: TIM2 address block description

1/119 fields covered.

Toggle register map

Offset	Name	31	27	24	21	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1												UIF_REMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2																TI1S	MMS			CCDS
0x8	SMCR				TS_4_3			SMS_3	ETP	ECE	ETPS		ETF				MSM	TS_2_0			OCCS	SMS_2_0
0xc	DIER									TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR											CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14	EGR																	TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1			OC2M_3				OC1M_3	OC2CE	OC2M_2_0			OC2PE	OC2FE	CC2S		OC1CE	OC1M_2_0			OC1PE	OC1FE	CC1S
0x18	CCMR1_in								IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x1c	CCMR2			OC4M_3				OC3M_3	OC4CE	OC4M_2_0			OC4PE	OC4FE	CC4S		OC3CE	OC3M_2_0			OC3PE	OC3FE	CC3S
0x1c	CCMR2_in								IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x20	CCER								CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT	UIF_CPY							CNT
0x28	PSC								PSC
0x2c	ARR								ARR
0x30	RCR																REP
0x34	CCR1								CCR1
0x38	CCR2								CCR2
0x3c	CCR3								CCR3
0x40	CCR4								CCR4
0x48	DCR											DBL								DBA
0x4c	DMAR								DMAB
0x50	OR1																					TI4_RMP	OR1_1	ETR_RMP
0x60	AF1						ETR_SEL_3	ETR_SEL	ETR_SEL
0x68	TISEL		TI4SEL			TI3SEL							TI2SEL								TI1SEL

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIF_REMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: - Counter overflow/underflow - Setting the UG bit - Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller..

URS

Bit 2: URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: - Counter overflow/underflow - Setting the UG bit - Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled..

OPM

Bit 3: OPM: One pulse mode 0: Counter is not stopped at update event. 1: Counter stops counting at the next update event (clearing the bit CEN).

DIR

Bit 4: DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

CMS

Bits 5-6: CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

ARPE

Bit 7: ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered.

CKD

Bits 8-9: CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value.

UIF_REMAP

Bit 11: UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31..

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

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CCDS

Bit 3: CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs.

MMS

Bits 4-6: MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

TI1S

Bit 7: TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination).

SMCR

SMCR register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS_4_3 rw					SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS_2_0 rw			OCCS rw	SMS_2_0 rw

Toggle fields

SMS_2_0

Bits 0-2: SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. 0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal..

OCCS

Bit 3: OCCS: OCREF clear selection This bit is used to select the OCREF clear source. 0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) 1: OCREF_CLR_INT is connected to ETRF.

TS_2_0

Bits 4-6: TS[4:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1) 00110: Filtered Timer Input 2 (TI2FP2) 00111: External Trigger input (ETRF) Others: Reserved See Table Note:: TIM2 internal trigger connection on page 395 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event..

ETF

Bits 8-11: ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8.

ETPS

Bits 12-13: ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8.

ECE

Bit 14: ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

ETP

Bit 15: ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge..

SMS_3

Bit 16: SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits2:0.

TS_4_3

Bits 20-21: Trigger selection. See TS_2_0_ description.

DIER

DIER register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled.

CC1IE

Bit 1: CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled.

CC2IE

Bit 2: CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled.

CC3IE

Bit 3: CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled.

CC4IE

Bit 4: CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled 1: CC4 interrupt enabled.

TIE

Bit 6: TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled.

UDE

Bit 8: UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled.

CC1DE

Bit 9: CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled.

CC2DE

Bit 10: CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled.

CC3DE

Bit 11: CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled.

CC4DE

Bit 12: CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled.

TDE

Bit 14: TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled.

SR

SR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity).

CC2IF

Bit 2: CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description.

CC3IF

Bit 3: CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description.

CC4IF

Bit 4: CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description.

TIF

Bit 6: TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.. 0: No trigger event occurred. 1: Trigger interrupt pending..

CC1OF

Bit 9: CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set.

CC2OF

Bit 10: CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description.

CC3OF

Bit 11: CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description.

CC4OF

Bit 12: CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description.

EGR

EGR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected)..

CC1G

Bit 1: CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: CC2G: Capture/Compare 2 generation refer to CC1G description.

CC3G

Bit 3: CC3G: Capture/Compare 3 generation refer to CC1G description.

CC4G

Bit 4: CC4G: Capture/Compare 4 generation refer to CC1G description.

TG

Bit 6: TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled..

CCMR1

CCMR1 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M_2_0 rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M_2_0 rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

OC1FE

Bit 2: OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode..

OC1PE

Bit 3: OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note: 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M_2_0

Bits 4-6: OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. 1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved 1011: Reserved 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from 'frozen' mode to 'PWM' mode..

OC1CE

Bit 7: OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF Input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input.

CC2S

Bits 8-9: CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER)..

OC2FE

Bit 10: OC2FE: Output Compare 2 fast enable.

OC2PE

Bit 11: OC2PE: Output Compare 2 preload enable.

OC2M_2_0

Bits 12-14: OC2M[2:0]: Output Compare 2 mode.

OC2CE

Bit 15: OC2CE: Output Compare 2 clear enable.

OC1M_3

Bit 16: OC1M[3]: Output Compare 1 mode (bit 3).

OC2M_3

Bit 24: OC2M[3]: Output Compare 2 mode (bit 3).

CCMR1_in

CCMR1_in register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 1x: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER)..

IC1PSC

Bits 2-3: IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events.

IC1F

Bits 4-7: Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N= 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8.

CC2S

Bits 8-9: CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER)..

IC2PSC

Bits 10-11: IC2PSC[1:0]: Input capture 2 prescaler.

IC2F

Bits 12-15: IC2F: Input capture 2 filter.

CCMR2

CCMR2 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M_3 rw								OC3M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M_2_0 rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M_2_0 rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER)..

OC3FE

Bit 2: OC3FE: Output compare 3 fast enable.

OC3PE

Bit 3: OC3PE: Output compare 3 preload enable.

OC3M_2_0

Bits 4-6: OC3M: Output compare 3 mode.

OC3CE

Bit 7: OC3CE: Output compare 3 clear enable.

CC4S

Bits 8-9: CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER)..

OC4FE

Bit 10: OC4FE: Output Compare 4 fast enable.

OC4PE

Bit 11: OC4PE: Output Compare 4 preload enable.

OC4M_2_0

Bits 12-14: OC4M[2:0]: Output Compare 4 mode.

OC4CE

Bit 15: OC4CE: Output Compare 4 clear enable.

OC3M_3

Bit 16: OC3M[3]: Output Compare 3 mode (bit 3).

OC4M_3

Bit 24: OC4M[3]: Output Compare 4 mode (bit 3).

CCMR2_in

CCMR2_in register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER)..

IC3PSC

Bits 2-3: IC3PSC: Input capture 3 prescaler.

IC3F

Bits 4-7: IC3F: Input capture 3 filter.

CC4S

Bits 8-9: CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER)..

IC4PSC

Bits 10-11: IC4PSC: Input capture 4 prescaler.

IC4F

Bits 12-15: IC4F: Input capture 4 filter.

CCER

CCER register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled.

CC1P

Bit 1: CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations. 00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). 01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode. 10: Reserved, do not use this configuration. 11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NP

Bit 3: CC1NP: Capture/Compare 1 Complementary output Polarity. This field is not used in Blue51. Not available in IUM Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output)..

CC2E

Bit 4: CC2E: Capture/Compare 2 output enable refer to CC1E description.

CC2P

Bit 5: CC2P: Capture/Compare 2 output polarity refer to CC1P description.

CC2NP

Bit 7: CC2NP: Capture/Compare 2 Complementary output Polarity. This field is not used in Blue51. Not available in IUM refer to CC1NP description.

CC3E

Bit 8: CC3E: Capture/Compare 3 output enable refer to CC1E description.

CC3P

Bit 9: CC3P: Capture/Compare 3 output polarity refer to CC1P description.

CC3NP

Bit 11: CC3NP: Capture/Compare 3 Complementary output Polarity. This field is not used in Blue51. Not available in IUM refer to CC1NP description.

CC4E

Bit 12: CC4E: Capture/Compare 4 output enable refer to CC1E description.

CC4P

Bit 13: CC4P: Capture/Compare 4 output polarity refer to CC1P description.

CC4NP

Bit 15: CC4NP: Capture/Compare 4 Complementary output Polarity. This field is not used in Blue51. Not available in IUM refer to CC1NP description.

CNT

CNT register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF_CPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: CNT[15:0]: Counter value.

UIF_CPY

Bit 31: UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..

PSC

PSC register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode')..

ARR

ARR register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..

RCR

RCR register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..

CCR1

CCR1 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle fields

CCR1

Bits 0-15: CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)..

CCR2

CCR2 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle fields

CCR2

Bits 0-15: CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2)..

CCR3

CCR3 register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3 rw

Toggle fields

CCR3

Bits 0-15: CCR3[15:0]: Capture/Compare 3 value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3)..

CCR4

CCR4 register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4 rw

Toggle fields

CCR4

Bits 0-15: CCR4[15:0]: Capture/Compare 4 value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4)..

DCR

DCR register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: Reserved, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers..

DMAR

DMAR register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIM2_CR1 address) + (DBA + DMA index) x 4 where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM2_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR)..

OR1

OR1 register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													TI4_RMP rw	OR1_1 rw	ETR_RMP rw

Toggle fields

ETR_RMP

Bit 0: ETR_RMP: ETR remapping capability 0: TIMx_ETR is not connected to ADC AWD (must be selected when the ETR comes from the ETR input pin) 1: TIMx_ETR is connected to ADC AWD Note: ADC AWD source is 'ORed' with the TIMx_ETR input signals. When ADC AWD is used, it is necessary to make sure that the corresponding TIMx_ETR input pin is not enabled in the alternate function controller..

OR1_1

Bit 1: This field is not used in Blue51. Not available in IUM.

TI4_RMP

Bit 2: TI4_RMP: Input capture 4 remap 0: TIM2 input capture 4 is connected to I/O 1: TIM2 input capture 4 is connected to COMP1-OUT.

AF1

AF1 register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETR_SEL_3 rw	ETR_SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETR_SEL rw

Toggle fields

ETR_SEL

Bits 14-16: ETRSEL[2:0]: External trigger source selection 000: TIMx External trigger legacy mode 001: TIMx External trigger source select COMP1_OUT Other: Reserved Note: These bits can't be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

ETR_SEL_3

Bit 17: ETRSEL[2:0]: External trigger source selection This field is not used in Blue51. Not available in IUM.

TISEL

TISEL register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIMx_CH1 input Others: Reserved.

TI2SEL

Bits 8-11: TI2SEL[3:0]: selects TI2[0] to TI2[15] input 0000: TIMx_CH2 input Others: Reserved.

TI3SEL

Bits 16-19: TI3SEL[3:0]: selects TI3[0] to TI3[15] input 0000: TIMx_CH3 input Others: Reserved.

TI4SEL

Bits 24-27: TI4SEL[3:0]: selects TI4[0] to TI4[15] input 0000: TIMx_CH4 input Others: Reserved.

USART

0x41004000:

28/119 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	RXFFIE	TXFEIE	FIFOEN	M_1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M_0	WAKE	PCE	PS	PEIE	TXEIE_TXFNFIE	TCIE	RXNEIE_RXFNEIE	IDLEIE	TE	RE		UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE				SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK		RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE_TXFNF	TC	RXNE_RXFNE	IDLE	ORE	NF	FE	PE
0x20	ICR															CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1

CR1 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M_1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M_0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE_TXFNFIE rw	TCIE rw	RXNEIE_RXFNEIE rw	IDLEIE rw	TE rw	RE rw		UE rw

Toggle fields

UE

Bit 0: UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are reset. This bit is set and cleared by software. -0: USART prescaler and outputs disabled, low power mode -1: USART enabled.

RE

Bit 2: RE: Receiver enable This bit enables the receiver. It is set and cleared by software. -0: Receiver is disabled -1: Receiver is enabled and begins searching for a start bit.

TE

Bit 3: TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. -0: Transmitter is disabled -1: Transmitter is enabled.

IDLEIE

Bit 4: IDLEIE: IDLE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register.

RXNEIE_RXFNEIE

Bit 5: RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the USART_ISR register.

TCIE

Bit 6: TCIE: Transmission complete interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TC=1 in the USART_ISR register.

TXEIE_TXFNFIE

Bit 7: TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register.

PEIE

Bit 8: PEIE: PE interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated whenever PE=1 in the USART_ISR register.

PS

Bit 9: PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. -0: Even parity -1: Odd parity This bit field can only be written when the USART is disabled (UE=0)..

PCE

Bit 10: PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). -0: Parity control disabled -1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0)..

WAKE

Bit 11: WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. -0: Idle line -1: Address mark This bit field can only be written when the USART is disabled (UE=0)..

M_0

Bit 12: M0: Word length This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit -28 (M1)description. This bit can only be written when the USART is disabled (UE=0)..

MME

Bit 13: MME: Mute mode enable This bit activates the mute mode function of the USART. When set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. -0: Receiver in active mode permanently -1: Receiver can switch between mute mode and active mode.

CMIE

Bit 14: CMIE: Character match interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register..

OVER8

Bit 15: OVER8: Oversampling mode -0: Oversampling by 16 This bit can only be written when the USART is disabled (UE=0)..

DEDT

Bits 16-20: DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0)..

DEAT

Bits 21-25: DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0)..

RTOIE

Bit 26: RTOIE: Receiver timeout interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.

EOBIE

Bit 27: EOBIE: End of Block interrupt enable This bit is set and cleared by software..

M_1

Bit 28: Word length This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0).s.

FIFOEN

Bit 29: FIFOEN :FIFO mode enable This bit is set and cleared by software. -0: FIFO mode is disabled. -1: FIFO mode is enabled..

TXFEIE

Bit 30: TXFEIE :TXFIFO empty interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFE=1 in the USART_ISR register.

RXFFIE

Bit 31: RXFFIE :RXFIFO Full interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when RXFF=1 in the USART_ISR register.

CR2

CR2 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: SLVEN: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. -0: Slave mode disabled. -1: Slave mode enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.

DIS_NSS

Bit 3: DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored. -0: SPI slave selection depends on NSS input pin. -1: SPI slave will be always selected and NSS input pin will be ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value.

ADDM7

Bit 4: ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. -0: 4-bit address detection -1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0).

LBDL

Bit 5: LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. -0: 10-bit break detection -1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0)..

LBDIE

Bit 6: LBDIE: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). -0: Interrupt is inhibited -1: An interrupt is generated whenever LBDF=1 in the USART_ISR register.

LBCL

Bit 8: LBCL: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. -0: The clock pulse of the last data bit is not output to the SCLK pin -1: The clock pulse of the last data bit is output to the SCLK pin Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0)..

CPHA

Bit 9: CPHA: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 137 and Figure 138) -0: The first clock transition is the first data capture edge -1: The second clock transition is the first data capture edge This bit can only be written when the USART is disabled (UE=0)..

CPOL

Bit 10: CPOL: Clock polarity This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship -0: Steady low value on SCLK pin outside transmission window -1: Steady high value on SCLK pin outside transmission window This bit can only be written when the USART is disabled (UE=0)..

CLKEN

Bit 11: CLKEN: Clock enable This bit allows the user to enable the SCLK pin. -0: SCLK pin disabled -1: SCLK pin enabled This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced by hardware to 0. Please refer to Section 23.4: USART implementation on page 483. Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: - UE = 0 - SCEN = 1 - GTPR configuration - CLKEN= 1 - UE = 1.

STOP

Bits 12-13: STOP[1:0]: STOP bits These bits are used for programming the stop bits. -00: 1 stop bit -01: 0.5 stop bit. -10: 2 stop bits -11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0)..

LINEN

Bit 14: LINEN: LIN mode enable This bit is set and cleared by software. -0: LIN mode disabled -1: LIN mode enabled The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bit field can only be written when the USART is disabled (UE=0)..

SWAP

Bit 15: SWAP: Swap TX/RX pins This bit is set and cleared by software. -0: TX/RX pins are used as defined in standard pinout -1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the USART is disabled (UE=0)..

RXINV

Bit 16: RXINV: RX pin active level inversion This bit is set and cleared by software. -0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0)..

TXINV

Bit 17: TXINV: TX pin active level inversion This bit is set and cleared by software. -0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) -1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0)..

DATAINV

Bit 18: DATAINV: Binary data inversion This bit is set and cleared by software. -0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) -1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0)..

MSBFIRST

Bit 19: MSBFIRST: Most significant bit first This bit is set and cleared by software. -0: data is transmitted/received with data bit 0 first, following the start bit. -1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0)..

ABREN

Bit 20: ABREN: Auto baud rate enable This bit is set and cleared by software. -0: Auto baud rate detection is disabled. -1: Auto baud rate detection is enabled..

ABRMOD

Bits 21-22: ABRMOD[1:0]: Auto baud rate mode These bits are set and cleared by software. -00: Measurement of the start bit is used to detect the baud rate. -01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) -10: 0x7F frame detection. -11: 0x55 frame detection This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0)..

RTOEN

Bit 23: RTOEN: Receiver timeout enable This bit is set and cleared by software. -0: Receiver timeout feature disabled. -1: Receiver timeout feature enabled. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register)..

ADD

Bits 24-31: ADD[7:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8- bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).

CR3

CR3 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw				SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR = 1 in the USART_ISR register). -0: Interrupt is inhibited -1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register..

IREN

Bit 1: IREN: IrDA mode enable This bit is set and cleared by software. -0: IrDA disabled -1: IrDA enabled This bit can only be written when the USART is disabled (UE=0)..

IRLP

Bit 2: IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes -0: Normal mode -1: Low-power mode This bit can only be written when the USART is disabled (UE=0)..

HDSEL

Bit 3: HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode -0: Half duplex mode is not selected -1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0)..

NACK

Bit 4: NACK: Smartcard NACK enable -0: NACK transmission in case of parity error is disabled -1: NACK transmission during parity error is enabled This bit field can only be written when the USART is disabled (UE=0)..

SCEN

Bit 5: SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. -0: Smartcard Mode disabled -1: Smartcard Mode enabled This bit field can only be written when the USART is disabled (UE=0)..

DMAR

Bit 6: DMAR: DMA enable receiver This bit is set/reset by software -1: DMA mode is enabled for reception -0: DMA mode is disabled for reception.

DMAT

Bit 7: DMAT: DMA enable transmitter This bit is set/reset by software -1: DMA mode is enabled for transmission -0: DMA mode is disabled for transmission.

RTSE

Bit 8: RTSE: RTS enable -0: RTS hardware flow control disabled -1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0)..

CTSE

Bit 9: CTSE: CTS enable -0: CTS hardware flow control disabled -1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0).

CTSIE

Bit 10: CTSIE: CTS interrupt enable -0: Interrupt is inhibited -1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register.

ONEBIT

Bit 11: ONEBIT: One sample bit method enable This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NF) is disabled. -0: Three sample bit method -1: One sample bit method This bit can only be written when the USART is disabled (UE=0)..

OVRDIS

Bit 12: OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. -0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. -1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USARTx_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0)..

DDRE

Bit 13: DDRE: DMA Disable on Reception Error -0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) -1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=0)..

DEM

Bit 14: DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. -0: DE function is disabled. -1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0)..

DEP

Bit 15: DEP: Driver enable polarity selection -0: DE signal is active high. -1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0)..

SCARCNT

Bits 17-19: SCARCNT[2:0]: Smartcard auto-retry count This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bit field must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to stop retransmission. -0x0: retransmission disabled - No automatic retransmission in transmit mode. -0x1 to 0x7: number of automatic retransmission attempts (before signaling error).

TXFTIE

Bit 23: TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG..

TCBGTIE

Bit 24: TCBGTIE: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register.

RXFTCFG

Bits 25-27: RXFTCFG: Receive FIFO threshold configuration -000:Receive FIFO reaches 1/8 of its depth. -001:Receive FIFO reaches 1/4 of its depth. -010:Receive FIFO reaches 1/2 of its depth. -011:Receive FIFO reaches 3/4 of its depth. -100:Receive FIFO reaches 7/8 of its depth. -101:Receive FIFO becomes full. Remaining combinations: Reserved..

RXFTIE

Bit 28: RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. -0: Interrupt is inhibited -1: An USART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG..

TXFTCFG

Bits 29-31: TXFTCFG: TXFIFO threshold configuration -000:TXFIFO reaches 1/8 of its depth. -001:TXFIFO reaches 1/4 of its depth. -010:TXFIFO reaches 1/2 of its depth. -011:TXFIFO reaches 3/4 of its depth. -100:TXFIFO reaches 7/8 of its depth. -101:TXFIFO becomes empty. Remaining combinations: Reserved..

BRR

BRR register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

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BRR

Bits 0-15: BRR[15:4] BRR[15:4] = USARTDIV[15:4]BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared.

GTPR

GTPR register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

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PSC

Bits 0-7: PSC[7:0]: Prescaler value In IrDA Low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power Baud Rate Used for programming the prescaler for dividing the USART source clock to achieve the lowpower frequency: The source clock is divided by the value given in the register (8 significant bits): -00000000: Reserved - do not program this value -00000001: divides the source clock by 1 -00000010: divides the source clock by 2 ... In Smartcard mode: PSC[4:0]: Prescaler value Used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: -00000: Reserved - do not program this value -00001: divides the source clock by 2 -00010: divides the source clock by 4 -00011: divides the source clock by 6 ... This bit field can only be written when the USART is disabled (UE=0)..

GT

Bits 8-15: GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bit field can only be written when the USART is disabled (UE=0)..

RTOR

RTOR register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

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RTO

Bits 0-23: RTO[23:0]: Receiver timeout value This bit-field gives the Receiver timeout value in terms of number of baud clocks. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the Start Bit of the last received character..

BLEN

Bits 24-31: BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 -> 0 information characters + LEC BLEN = 1 -> 0 information characters + CRC BLEN = 255 -> 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). This bit-field can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1..

RQR

RQR register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

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ABRRQ

Bit 0: ABRRQ: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame..

SBKRQ

Bit 1: SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available..

MMRQ

Bit 2: MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and resets the RWU flag..

RXFRQ

Bit 3: RXFRQ: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: TXFRQ: Transmit data flush request When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to 0 When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes..

ISR

ISR register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r		RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE_TXFNF r	TC r	RXNE_RXFNE r	IDLE r	ORE r	NF r	FE r	PE r

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PE

Bit 0: PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. -0: No parity error -1: Parity error.

FE

Bit 1: FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. -0: No Framing error is detected -1: Framing error or break character is detected.

NF

Bit 2: NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. -0: No noise is detected -1: Noise is detected.

ORE

Bit 3: ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. -0: No overrun error -1: Overrun error is detected.

IDLE

Bit 4: IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. -0: No Idle line is detected -1: Idle line is detected.

RXNE_RXFNE

Bit 5: RXNE/RXFNE:Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. -0: Data is not received -1: Received data is ready to be read..

TC

Bit 6: TC: Transmission complete This bit indicates when the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. An interrupt is generated if TCIE=1 in the USART_CR1 register. -0: Transmission is not complete -1: Transmission is complete.

TXE_TXFNF

Bit 7: TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the USART_TDR. Every write in the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. -0: Data register is full/Transmit FIFO is full. -1: Data register/Transmit FIFO is not full.

LBDF

Bit 8: LBDF: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. -0: LIN Break not detected -1: LIN break detected.

CTSIF

Bit 9: CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. -0: No change occurred on the nCTS status line -1: A change occurred on the nCTS status line.

CTS

Bit 10: CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. -0: nCTS line set -1: nCTS line reset.

RTOF

Bit 11: RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. -0: Timeout value not reached -1: Timeout value reached without any data reception.

EOBF

Bit 12: EOBF: End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. -0: End of Block not reached -1: End of Block (number of characters) reached.

UDR

Bit 13: UDR: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock for data transmission appears while the software has not yet loaded any value into USARTx_DR. -0: No underrun error -1: underrun error.

ABRE

Bit 14: ABRE: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register.

ABRF

Bit 15: ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register..

BUSY

Bit 16: BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). -0: USART is idle (no reception) -1: Reception on going.

CMF

Bit 17: CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. -0: No Character match detected -1: Character Match detected.

SBKF

Bit 18: SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. -0: No break character is transmitted -1: Break character will be transmitted.

RWU

Bit 19: RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. -0: Receiver in active mode -1: Receiver in mute mode.

TEACK

Bit 21: TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period..

REACK

Bit 22: REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering Stop mode..

TXFE

Bit 23: TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. -0: TXFIFO is not empty. -1: TXFIFO is empty..

RXFF

Bit 24: RXFF: RXFIFO Full This bit is set by hardware when RXFIFO is Full. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. -0: RXFIFO is not Full. -1: RXFIFO is Full..

TCBGT

Bit 25: TCBGT: Transmission complete before guard time flagl This bit indicates when the last data written in the USART_TDR has been transmitted correctly out of the shift register . It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if there is no NACK from the smartcard. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. -0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is received from the card) -1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)..

RXFT

Bit 26: RXFT: RXFIFO threshold flag This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. -0: Receive FIFO doesnt reach the programmed threshold. -1: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. -0: TXFIFO doesnt reach the programmed threshold. -1: TXFIFO reached the programmed threshold.

ICR

ICR register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

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PECF

Bit 0: PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.

NECF

Bit 2: NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register..

ORECF

Bit 3: ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFECF: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.

TCCF

Bit 6: TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.

TCBGTCF

Bit 7: TCBGTCF: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LBDCF: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register..

CTSCF

Bit 9: CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.

RTOCF

Bit 11: RTOCF: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register..

EOBCF

Bit 12: EOBCF: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register.

UDRCF

Bit 13: UDRCF:SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register.

CMCF

Bit 17: CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.

RDR

RDR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

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RDR

Bits 0-8: RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 124). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

TDR

TDR register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

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TDR

Bits 0-8: TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USARTx_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 124). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1..

PRESC

PRESC register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

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PRESCALER

Bits 0-3: PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler: -0000: input clock not divided -0001: input clock divided by 2 -0010: input clock divided by 4 -0011: input clock divided by 6 -0100: input clock divided by 8 -0101: input clock divided by 10 -0110: input clock divided by 12 -0111: input clock divided by 16 -1000: input clock divided by 32 -1001: input clock divided by 64 -1010: input clock divided by 128 -1011: input clock divided by 256 Remaing combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be '1011' i.e. input clock divided by 256.