Overall: 3517/3632 fields covered

ADC

0x40012400: Analog to digital convertor

142/142 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR1
0x10 CFGR2
0x14 SMPR
0x20 AWD1TR
0x24 AWD2TR
0x28 CHSELR0
0x28 CHSELR1
0x2c AWD3TR
0x40 DR
0xa0 AWD2CR
0xa4 AWD3CR
0xb4 CALFACT
0x308 CCR
Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCRDY
r/w1c 		EOCAL
r/w1c 		AWD[3]
r/w1c 		AWD[2]
r/w1c 		AWD[1]
r/w1c 		OVR
r/w1c 		EOS
r/w1c 		EOC
r/w1c 		EOSMP
r/w1c 		ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC not yet ready to start conversion
1: Ready: ADC ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotAtEnd: Not at the end of the samplings phase
1: AtEnd: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Channel conversion is not complete
1: Complete: Channel conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Conversion sequence is not complete
1: Complete: Conversion sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOCAL

Bit 11: EOCAL.

Allowed values:
0: NotComplete: Calibration is not complete
1: Complete: Calibration complete

CCRDY

Bit 13: CCRDY.

Allowed values:
0: NotComplete: Channel configuration update not applied
1: Complete: Channel configuration update is applied

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCRDYIE
rw 		EOCALIE
rw 		AWD[3]IE
rw 		AWD[2]IE
rw 		AWD[1]IE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADRDY interrupt disabled
1: Enabled: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: EOSMP interrupt disabled
1: Enabled: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: EOS interrupt disabled
1: Enabled: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

EOCALIE

Bit 11: EOCALIE.

Allowed values:
0: Disabled: End of calibration interrupt disabled
1: Enabled: End of calibration interrupt enabled

CCRDYIE

Bit 13: CCRDYIE.

Allowed values:
0: Disabled: Channel configuration ready interrupt disabled
1: Enabled: Channel configuration ready interrupt enabled

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSTP
r/w1s 		ADSTART
r/w1s 		ADDIS
r/w1s 		ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

ADCAL

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR1

ADC configuration register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CH
rw 		AWD1EN
rw 		AWD1SGL
rw 		CHSELRMOD
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOFF
rw 		WAIT
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		SCANDIR
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA one shot mode selected
1: Circular: DMA circular mode selected

SCANDIR

Bit 2: SCANDIR.

Allowed values:
0: Upward: Upward scan (from CHSEL0 to CHSEL17)
1: Backward: Backward scan (from CHSEL17 to CHSEL0)

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12 bits
1: Bits10: 10 bits
2: Bits8: 8 bits
3: Bits6: 6 bits

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-8: EXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CH4: Timer 2 CH4 event
5: TIM2_CH3: Timer 2 CH3 event
7: EXTI_LINE11: EXTI line 11 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Hardware trigger detection disabled
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: ADC_DR register is preserved with the old data when an overrun is detected
1: Overwrite: ADC_DR register is overwritten with the last conversion result when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

WAIT

Bit 14: WAIT.

Allowed values:
0: Disabled: Wait conversion mode off
1: Enabled: Wait conversion mode on

AUTOFF

Bit 15: AUTOFF.

Allowed values:
0: Disabled: Auto-off mode disabled
1: Enabled: Auto-off mode enabled

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode disabled
1: Enabled: Discontinuous mode enabled

CHSELRMOD

Bit 21: CHSELRMOD.

Allowed values:
0: BitPerInput: Each bit of the ADC_CHSELR register enables an input
1: Sequence: ADC_CHSELR register is able to sequence up to 8 channels

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: AllChannels: Analog watchdog 1 enabled on all channels
1: SingleChannel: Analog watchdog 1 enabled on a single channel

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled
1: Enabled: Analog watchdog 1 enabled

AWD1CH

Bits 26-30: AWD1CH.

Allowed values: 0x0-0x11

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMODE
rw 		LFTRIG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSE
rw
Toggle fields

OVSE

Bit 0: OVSE.

Allowed values:
0: Disabled: Oversampler disabled
1: Enabled: Oversampler enabled

OVSR

Bits 2-4: OVSR0.

Allowed values:
0: Mul2: 2x
1: Mul4: 4x
2: Mul8: 8x
3: Mul16: 16x
4: Mul32: 32x
5: Mul64: 64x
6: Mul128: 128x
7: Mul256: 256x

OVSS

Bits 5-8: OVSS0.

Allowed values:
0: NoShift: No shift
1: Shift1: Shift 1-bit
2: Shift2: Shift 2-bits
3: Shift3: Shift 3-bits
4: Shift4: Shift 4-bits
5: Shift5: Shift 5-bits
6: Shift6: Shift 6-bits
7: Shift7: Shift 7-bits
8: Shift8: Shift 8-bits

TOVS

Bit 9: TOVS.

Allowed values:
0: TriggerAll: All oversampled conversions for a channel are done consecutively after a trigger
1: TriggerEach: Each oversampled conversion for a channel needs a trigger

LFTRIG

Bit 29: LFTRIG.

Allowed values:
0: Disabled: Low Frequency Trigger Mode disabled
1: Enabled: Low Frequency Trigger Mode enabled

CKMODE

Bits 30-31: CKMODE.

Allowed values:
0: ADCLK: ADCCLK (Asynchronous clock mode)
1: PCLK_Div2: PCLK/2 (Synchronous clock mode)
2: PCLK_Div4: PCLK/4 (Synchronous clock mode)
3: PCLK: PCLK (Synchronous clock mode)

SMPR

ADC sampling time register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPSEL[17]
rw 		SMPSEL[16]
rw 		SMPSEL[15]
rw 		SMPSEL[14]
rw 		SMPSEL[13]
rw 		SMPSEL[12]
rw 		SMPSEL[11]
rw 		SMPSEL[10]
rw 		SMPSEL[9]
rw 		SMPSEL[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSEL[7]
rw 		SMPSEL[6]
rw 		SMPSEL[5]
rw 		SMPSEL[4]
rw 		SMPSEL[3]
rw 		SMPSEL[2]
rw 		SMPSEL[1]
rw 		SMPSEL[0]
rw 		SMP[2]
rw 		SMP[1]
rw
Toggle fields

SMP[1]

Bits 0-2: Sampling time selection 1.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles

SMP[2]

Bits 4-6: Sampling time selection 2.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles

SMPSEL[0]

Bit 8: Channel-0 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[1]

Bit 9: Channel-1 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[2]

Bit 10: Channel-2 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[3]

Bit 11: Channel-3 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[4]

Bit 12: Channel-4 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[5]

Bit 13: Channel-5 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[6]

Bit 14: Channel-6 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[7]

Bit 15: Channel-7 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[8]

Bit 16: Channel-8 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[9]

Bit 17: Channel-9 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[10]

Bit 18: Channel-10 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[11]

Bit 19: Channel-11 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[12]

Bit 20: Channel-12 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[13]

Bit 21: Channel-13 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[14]

Bit 22: Channel-14 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[15]

Bit 23: Channel-15 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[16]

Bit 24: Channel-16 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[17]

Bit 25: Channel-17 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

AWD1TR

ADC watchdog threshold register

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

AWD2TR

ADC watchdog threshold register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-11: LT2.

Allowed values: 0x0-0xfff

HT2

Bits 16-27: HT2.

Allowed values: 0x0-0xfff

CHSELR0

channel selection register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL[17]
rw 		CHSEL[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHSEL[15]
rw 		CHSEL[14]
rw 		CHSEL[13]
rw 		CHSEL[12]
rw 		CHSEL[11]
rw 		CHSEL[10]
rw 		CHSEL[9]
rw 		CHSEL[8]
rw 		CHSEL[7]
rw 		CHSEL[6]
rw 		CHSEL[5]
rw 		CHSEL[4]
rw 		CHSEL[3]
rw 		CHSEL[2]
rw 		CHSEL[1]
rw 		CHSEL[0]
rw
Toggle fields

CHSEL[0]

Bit 0: Channel-0 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[1]

Bit 1: Channel-1 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[2]

Bit 2: Channel-2 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[3]

Bit 3: Channel-3 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[4]

Bit 4: Channel-4 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[5]

Bit 5: Channel-5 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[6]

Bit 6: Channel-6 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[7]

Bit 7: Channel-7 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[8]

Bit 8: Channel-8 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[9]

Bit 9: Channel-9 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[10]

Bit 10: Channel-10 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[11]

Bit 11: Channel-11 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[12]

Bit 12: Channel-12 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[13]

Bit 13: Channel-13 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[14]

Bit 14: Channel-14 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[15]

Bit 15: Channel-15 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[16]

Bit 16: Channel-16 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[17]

Bit 17: Channel-17 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSELR1

channel selection register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[8]
rw 		SQ[7]
rw 		SQ[6]
rw 		SQ[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[4]
rw 		SQ[3]
rw 		SQ[2]
rw 		SQ[1]
rw
Toggle fields

SQ[1]

Bits 0-3: 1 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[2]

Bits 4-7: 2 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[3]

Bits 8-11: 3 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[4]

Bits 12-15: 4 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[5]

Bits 16-19: 5 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[6]

Bits 20-23: 6 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[7]

Bits 24-27: 7 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[8]

Bits 28-31: 8 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

AWD3TR

ADC watchdog threshold register

Offset: 0x2c, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-11: LT3.

Allowed values: 0x0-0xfff

HT3

Bits 16-27: HT3.

Allowed values: 0x0-0xfff

DR

ADC data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle fields

DATA

Bits 0-15: DATA.

Allowed values: 0x0-0xffff

AWD2CR

ADC Analog Watchdog 2 Configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH[17]
rw 		AWD2CH[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH[15]
rw 		AWD2CH[14]
rw 		AWD2CH[13]
rw 		AWD2CH[12]
rw 		AWD2CH[11]
rw 		AWD2CH[10]
rw 		AWD2CH[9]
rw 		AWD2CH[8]
rw 		AWD2CH[7]
rw 		AWD2CH[6]
rw 		AWD2CH[5]
rw 		AWD2CH[4]
rw 		AWD2CH[3]
rw 		AWD2CH[2]
rw 		AWD2CH[1]
rw 		AWD2CH[0]
rw
Toggle fields

AWD2CH[0]

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[1]

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[2]

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[3]

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[4]

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[5]

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[6]

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[7]

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[8]

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[9]

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[10]

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[11]

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[12]

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[13]

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[14]

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[15]

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[16]

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[17]

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD3CR

ADC Analog Watchdog 3 Configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH[17]
rw 		AWD3CH[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH[15]
rw 		AWD3CH[14]
rw 		AWD3CH[13]
rw 		AWD3CH[12]
rw 		AWD3CH[11]
rw 		AWD3CH[10]
rw 		AWD3CH[9]
rw 		AWD3CH[8]
rw 		AWD3CH[7]
rw 		AWD3CH[6]
rw 		AWD3CH[5]
rw 		AWD3CH[4]
rw 		AWD3CH[3]
rw 		AWD3CH[2]
rw 		AWD3CH[1]
rw 		AWD3CH[0]
rw
Toggle fields

AWD3CH[0]

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[1]

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[2]

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[3]

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[4]

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[5]

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[6]

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[7]

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[8]

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[9]

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[10]

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[11]

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[12]

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[13]

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[14]

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[15]

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[16]

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[17]

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

CALFACT

ADC Calibration factor

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT
rw
Toggle fields

CALFACT

Bits 0-6: CALFACT.

Allowed values: 0x0-0x7f

CCR

ADC common configuration register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBATEN
rw 		TSEN
rw 		VREFEN
rw 		PRESC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRESC

Bits 18-21: PRESC0.

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

VREFEN

Bit 22: VREFEN.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

TSEN

Bit 23: TSEN.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

VBATEN

Bit 24: VBATEN.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

AES

0x58001800: Advanced encryption standard hardware accelerator 1

40/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DINR
0xc DOUTR
0x10 KEYR0
0x14 KEYR1
0x18 KEYR2
0x1c KEYR3
0x20 IVR0
0x24 IVR1
0x28 IVR2
0x2c IVR3
0x30 KEYR4
0x34 KEYR5
0x38 KEYR6
0x3c KEYR7
0x40 SUSP0R
0x44 SUSP1R
0x48 SUSP2R
0x4c SUSP3R
0x50 SUSP4R
0x54 SUSP5R
0x58 SUSP6R
0x5c SUSP7R
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw 		KEYSIZE
rw 		CHMOD_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GCMPH
rw 		DMAOUTEN
rw 		DMAINEN
rw 		ERRIE
rw 		CCFIE
rw 		ERRC
rw 		CCFC
rw 		CHMOD
rw 		MODE
rw 		DATATYPE
rw 		EN
rw
Toggle fields

EN

Bit 0: AES enable.

Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit

MODE

Bits 3-4: AES operating mode.

Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption

CHMOD

Bits 5-6: AES chaining mode Bit1 Bit0.

Allowed values:
0: ECB: Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
1: CBC: Cipher-block chaining (CBC)
2: CTR: Counter mode (CTR)
3: GCM: Galois counter mode (GCM) and Galois message authentication code (GMAC)

CCFC

Bit 7: Computation Complete Flag Clear.

Allowed values:
1: Clear: Clear computation complete flag

ERRC

Bit 8: Error clear.

Allowed values:
1: Clear: Clear RDERR and WRERR flags

CCFIE

Bit 9: CCF flag interrupt enable.

Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt

DMAINEN

Bit 11: Enable DMA management of data input phase.

Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

Allowed values:
0: Init: Init phase
1: Header: Header phase
2: Payload: Payload phase
3: Final: Final Phase

CHMOD_2

Bit 16: AES chaining mode Bit2.

Allowed values:
0: CHMOD: Mode as per CHMOD (ECB, CBC, CTR, GCM)
1: CCM: Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)

KEYSIZE

Bit 18: Key size selection.

Allowed values:
0: AES128: 128
1: AES256: 256

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

Allowed values: 0x0-0xf

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		WRERR
r 		RDERR
r 		CCF
r
Toggle fields

CCF

Bit 0: Computation complete flag.

Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete

RDERR

Bit 1: Read error flag.

Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected

WRERR

Bit 2: Write error flag.

Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected

BUSY

Bit 3: Busy flag.

Allowed values:
0: Idle: Idle
1: Busy: Busy

DINR

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
rw
Toggle fields

DIN

Bits 0-31: Data Input Register.

Allowed values: 0x0-0xffffffff

DOUTR

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-31: Data output register.

Allowed values: 0x0-0xffffffff

KEYR0

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Data Output Register (LSB key [31:0]).

Allowed values: 0x0-0xffffffff

KEYR1

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (key [63:32]).

Allowed values: 0x0-0xffffffff

KEYR2

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (key [95:64]).

Allowed values: 0x0-0xffffffff

KEYR3

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (MSB key [127:96]).

Allowed values: 0x0-0xffffffff

IVR0

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: initialization vector register (LSB IVR [31:0]).

Allowed values: 0x0-0xffffffff

IVR1

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (IVR [63:32]).

Allowed values: 0x0-0xffffffff

IVR2

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (IVR [95:64]).

Allowed values: 0x0-0xffffffff

IVR3

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

Allowed values: 0x0-0xffffffff

KEYR4

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (MSB key [159:128]).

Allowed values: 0x0-0xffffffff

KEYR5

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (MSB key [191:160]).

Allowed values: 0x0-0xffffffff

KEYR6

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (MSB key [223:192]).

Allowed values: 0x0-0xffffffff

KEYR7

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: AES key register (MSB key [255:224]).

Allowed values: 0x0-0xffffffff

SUSP0R

AES suspend register 0

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 0.

Allowed values: 0x0-0xffffffff

SUSP1R

AES suspend register 1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 1.

Allowed values: 0x0-0xffffffff

SUSP2R

AES suspend register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 2.

Allowed values: 0x0-0xffffffff

SUSP3R

AES suspend register 3

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 3.

Allowed values: 0x0-0xffffffff

SUSP4R

AES suspend register 4

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 4.

Allowed values: 0x0-0xffffffff

SUSP5R

AES suspend register 5

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 5.

Allowed values: 0x0-0xffffffff

SUSP6R

AES suspend register 6

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 6.

Allowed values: 0x0-0xffffffff

SUSP7R

AES suspend register 7

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 7.

Allowed values: 0x0-0xffffffff

COMP

0x40010200: Comparator

25/25 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 COMP1_CSR
0x4 COMP2_CSR
Toggle registers

COMP1_CSR

COMP1_CSR

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		VALUE
r 		INMESEL
rw 		SCALEN
rw 		BRGEN
rw 		BLANKING
rw 		HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLARITY
rw 		INPSEL
rw 		INMSEL
rw 		PWRMODE
rw 		EN
rw
Toggle fields

EN

Bit 0: Comparator 1 enable bit.

Allowed values:
0: Disabled: Comparator X disabled
1: Enabled: Comparator X enabled

PWRMODE

Bits 2-3: Power Mode of the comparator 1.

Allowed values:
0: HighSpeed: High speed / full power
1: MediumSpeed: Medium speed / medium power
2: LowSpeed: Low speed / low power
3: VeryLowSpeed: Very-low speed / ultra-low power

INMSEL

Bits 4-6: Comparator 1 input minus selection bits.

Allowed values:
0: OneQuarterVRef: 1/4 of VRefint
1: OneHalfVRef: 1/2 of VRefint
2: ThreeQuarterVRef: 3/4 of VRefint
3: VRef: VRefint
4: DAC_CH1: DAC Channel 1
6: PB3: PB3
7: GPIO: GPIO pin selected by INMESEL

INPSEL

Bits 7-8: Comparator1 input plus selection bit.

Allowed values:
0: PB4: PB4 connected to input plus
1: PB2: PB2 connected to input plus

POLARITY

Bit 15: Comparator 1 polarity selection bit.

Allowed values:
0: Normal: Comparator X output value not inverted
1: Inverted: Comparator X output value inverted

HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

Allowed values:
0: None: No hysteresis
1: Low: Low hysteresis
2: Medium: Medium hysteresis
3: High: High hysteresis

BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

Allowed values:
0: NoBlanking: No blanking
1: TIM1OC5: TIM1 OC5 selected as blanking source
2: TIM2OC3: TIM2 OC3 selected as blanking source

BRGEN

Bit 22: Scaler bridge enable.

Allowed values:
0: Disabled: Scaler resistor bridge disabled
1: Enabled: Scaler resistor bridge enabled

SCALEN

Bit 23: Voltage scaler enable bit.

Allowed values:
0: Disabled: Voltage scaler disabled
1: Enabled: Voltage scaler enabled

INMESEL

Bits 25-26: comparator 1 input minus extended selection bits..

Allowed values:
0: PA10: PA10 connected to input minus
1: PA11: PA11 connected to input minus
2: PA15: PA15 connected to input minus

VALUE

Bit 30: Comparator 1 output status bit.

Allowed values:
0: Low: Comparator output is low
1: High: Comparator output is high

LOCK

Bit 31: COMP1_CSR register lock bit.

Allowed values:
0: Unlocked: Comparator CSR bits are read-write
1: Locked: Comparator CSR bits are read-only

COMP2_CSR

COMP2_CSR

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		VALUE
r 		INMESEL
rw 		SCALEN
rw 		BRGEN
rw 		BLANKING
rw 		HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLARITY
rw 		WINMODE
rw 		INPSEL
rw 		INMSEL
rw 		PWRMODE
rw 		EN
rw
Toggle fields

EN

Bit 0: Comparator 2 enable bit.

Allowed values:
0: Disabled: Comparator X disabled
1: Enabled: Comparator X enabled

PWRMODE

Bits 2-3: Power Mode of the comparator 2.

Allowed values:
0: HighSpeed: High speed / full power
1: MediumSpeed: Medium speed / medium power
2: LowSpeed: Low speed / low power
3: VeryLowSpeed: Very-low speed / ultra-low power

INMSEL

Bits 4-6: Comparator 2 input minus selection bits.

Allowed values:
0: OneQuarterVRef: 1/4 of VRefint
1: OneHalfVRef: 1/2 of VRefint
2: ThreeQuarterVRef: 3/4 of VRefint
3: VRef: VRefint
4: DAC_CH1: DAC Channel 1
6: PB3: PB3
7: GPIO: GPIO pin selected by INMESEL

INPSEL

Bits 7-8: Comparator 1 input plus selection bit.

Allowed values:
0: PB4: PB4 connected to input plus
1: PB1: PB1 connected to input plus
2: PA15: PA15 connected to input plus

WINMODE

Bit 9: Windows mode selection bit.

Allowed values:
0: Disabled: COMP2 input plus is not connected to COMP1
1: Enabled: COMP2 input plus is connected to COMP1

POLARITY

Bit 15: Comparator 2 polarity selection bit.

Allowed values:
0: Normal: Comparator X output value not inverted
1: Inverted: Comparator X output value inverted

HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

Allowed values:
0: None: No hysteresis
1: Low: Low hysteresis
2: Medium: Medium hysteresis
3: High: High hysteresis

BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

Allowed values:
0: NoBlanking: No blanking
1: TIM1OC5: TIM1 OC5 selected as blanking source
2: TIM2OC3: TIM2 OC3 selected as blanking source

BRGEN

Bit 22: Scaler bridge enable.

Allowed values:
0: Disabled: Scaler resistor bridge disabled
1: Enabled: Scaler resistor bridge enabled

SCALEN

Bit 23: Voltage scaler enable bit.

Allowed values:
0: Disabled: Voltage scaler disabled
1: Enabled: Voltage scaler enabled

INMESEL

Bits 25-26: comparator 2 input minus extended selection bits..

Allowed values:
0: PB2: PB2 connected to input minus
1: PA10: PA10 connected to input minus
2: PA11: PA11 connected to input minus

VALUE

Bit 30: Comparator 2 output status bit.

Allowed values:
0: Low: Comparator output is low
1: High: Comparator output is high

LOCK

Bit 31: CSR register lock bit.

Allowed values:
0: Unlocked: Comparator CSR bits are read-write
1: Locked: Comparator CSR bits are read-only

CRC

0x40023000: Cyclic redundancy check calculation unit

10/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x0 (16-bit) DR16
0x0 (8-bit) DR8
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

Allowed values: 0x0-0xffffffff

DR16

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR16
rw
Toggle fields

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR8
rw
Toggle fields

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-31: General-purpose 32-bit data register bits.

Allowed values: 0x0-0xffffffff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
rw
Toggle fields

RESET

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
Toggle fields

INIT

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle fields

POL

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

DAC

0x40007400: Digital-to-analog converter

24/24 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R[1]
0xc DHR12L[1]
0x10 DHR8R[1]
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR[1]
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR[1]
0x48 SHHR
0x4c SHRR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN[1]
rw 		DMAUDRIE[1]
rw 		DMAEN[1]
rw 		MAMP[1]
rw 		WAVE[1]
rw 		TSEL1
rw 		TEN[1]
rw 		EN[1]
rw
Toggle fields

EN[1]

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[1]

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL1

Bits 2-5: DAC channel1 trigger selection.

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Lptim3Out: LPTIM3 OUT event
14: EXTI9: dac_chx_trg14

WAVE[1]

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[1]

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[1]

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[1]

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[1]

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

SWTRGR

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG[1]
w
Toggle fields

SWTRIG[1]

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

DHR12R[1]

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L[1]

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R[1]

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

Dual DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

Dual DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR[1]

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DACC1DOR.

Allowed values: 0x0-0xfff

SR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST[1]
r 		CAL_FLAG[1]
r 		DMAUDR[1]
rw
Toggle fields

DMAUDR[1]

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[1]

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[1]

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

CCR

calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM[1]
rw
Toggle fields

OTRIM[1]

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

MCR

mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE[1]
rw
Toggle fields

MODE[1]

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

SHSR[1]

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in Sample and Hold mode).

Allowed values: 0x0-0x3ff

SHHR

Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD[1]
rw
Toggle fields

THOLD[1]

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

SHRR

Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH[1]
rw
Toggle fields

TREFRESH[1]

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

DBGMCU

0xe0042000: Microcontroller Debug Unit

18/18 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDCODER
0x4 CR
0x3c APB1FZR1
0x44 APB1FZR2
0x4c APB2FZR
Toggle registers

IDCODER

DBGMCU Identity Code Register

Offset: 0x0, size: 32, reset: 0x10006497, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: Device ID.

REV_ID

Bits 16-31: Revision.

CR

DBGMCU Configuration Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_STANDBY
rw 		DBG_STOP
rw 		DBG_SLEEP
rw
Toggle fields

DBG_SLEEP

Bit 0: Allow debug in SLEEP mode.

Allowed values:
0: Disabled: Debug Sleep Mode Disabled
1: Enabled: Debug Sleep Mode Enabled

DBG_STOP

Bit 1: Allow debug in STOP mode.

Allowed values:
0: Disabled: Debug Stop Mode Disabled
1: Enabled: Debug Stop Mode Enabled

DBG_STANDBY

Bit 2: Allow debug in STANDBY mode.

Allowed values:
0: Disabled: Debug Standby Mode Disabled
1: Enabled: Debug Standby Mode Enabled

APB1FZR1

DBGMCU CPU1 APB1 Peripheral Freeze Register 1

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw 		DBG_I2C3_STOP
rw 		DBG_I2C2_STOP
rw 		DBG_I2C1_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM2_STOP
rw
Toggle fields

DBG_TIM2_STOP

Bit 0: TIM2 stop in CPU1 debug.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DBG_RTC_STOP

Bit 10: RTC stop in CPU1 debug.

Allowed values:
0: Continue: The clock of the RTC counter is fed even if the core is halted
1: Stop: The clock of the RTC counter is stopped when the core is halted

DBG_WWDG_STOP

Bit 11: WWDG stop in CPU1 debug.

Allowed values:
0: Continue: The window watchdog counter clock continues even if the core is halted
1: Stop: The window watchdog counter clock is stopped when the core is halted

DBG_IWDG_STOP

Bit 12: IWDG stop in CPU1 debug.

Allowed values:
0: Continue: The independent watchdog counter clock continues even if the core is halted
1: Stop: The independent watchdog counter clock is stopped when the core is halted

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout stop in CPU1 debug.

Allowed values:
0: NormalMode: Same behavior as in normal mode
1: SMBusTimeoutFrozen: I2Cx SMBUS timeout is frozen

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout stop in CPU1 debug.

Allowed values:
0: NormalMode: Same behavior as in normal mode
1: SMBusTimeoutFrozen: I2Cx SMBUS timeout is frozen

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout stop in CPU1 debug.

Allowed values:
0: NormalMode: Same behavior as in normal mode
1: SMBusTimeoutFrozen: I2Cx SMBUS timeout is frozen

DBG_LPTIM1_STOP

Bit 31: LPTIM1 stop in CPU1 debug.

Allowed values:
0: Continue: LPTIMx counter clock is fed even if the core is halted
1: Stop: LPTIMx counter clock is stopped when the core is halted

APB1FZR2

DBGMCU CPU1 APB1 Peripheral Freeze Register 2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM3_STOP
rw 		DBG_LPTIM2_STOP
rw
Toggle fields

DBG_LPTIM2_STOP

Bit 5: DBG_LPTIM2_STOP.

Allowed values:
0: Continue: LPTIMx counter clock is fed even if the core is halted
1: Stop: LPTIMx counter clock is stopped when the core is halted

DBG_LPTIM3_STOP

Bit 6: DBG_LPTIM3_STOP.

Allowed values:
0: Continue: LPTIMx counter clock is fed even if the core is halted
1: Stop: LPTIMx counter clock is stopped when the core is halted

APB2FZR

DBGMCU CPU1 APB2 Peripheral Freeze Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw 		DBG_TIM16_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM1_STOP
rw
Toggle fields

DBG_TIM1_STOP

Bit 11: DBG_TIM1_STOP.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DBG_TIM16_STOP

Bit 17: DBG_TIM16_STOP.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DMA1

0x40020000: Direct memory access controller

154/189 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 MAR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c MAR [7]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF[7]
r 		HTIF[7]
r 		TCIF[7]
r 		GIF[7]
r 		TEIF[6]
r 		HTIF[6]
r 		TCIF[6]
r 		GIF[6]
r 		TEIF[5]
r 		HTIF[5]
r 		TCIF[5]
r 		GIF[5]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF[4]
r 		HTIF[4]
r 		TCIF[4]
r 		GIF[4]
r 		TEIF[3]
r 		HTIF[3]
r 		TCIF[3]
r 		GIF[3]
r 		TEIF[2]
r 		HTIF[2]
r 		TCIF[2]
r 		GIF[2]
r 		TEIF[1]
r 		HTIF[1]
r 		TCIF[1]
r 		GIF[1]
r
Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF[7]
w 		CHTIF[7]
w 		CTCIF[7]
w 		CGIF[7]
w 		CTEIF[6]
w 		CHTIF[6]
w 		CTCIF[6]
w 		CGIF[6]
w 		CTEIF[5]
w 		CHTIF[5]
w 		CTCIF[5]
w 		CGIF[5]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF[4]
w 		CHTIF[4]
w 		CTCIF[4]
w 		CGIF[4]
w 		CTEIF[3]
w 		CHTIF[3]
w 		CTCIF[3]
w 		CGIF[3]
w 		CTEIF[2]
w 		CHTIF[2]
w 		CTCIF[2]
w 		CGIF[2]
w 		CTEIF[1]
w 		CHTIF[1]
w 		CTCIF[1]
w 		CGIF[1]
w
Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [1]

channel x number of data to transfer register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [2]

channel x number of data to transfer register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [3]

channel x number of data to transfer register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [4]

channel x number of data to transfer register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [5]

channel x number of data to transfer register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [6]

channel x number of data to transfer register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [7]

channel x number of data to transfer register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

DMA2

0x40020400: Direct memory access controller

154/189 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 MAR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c MAR [7]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF[7]
r 		HTIF[7]
r 		TCIF[7]
r 		GIF[7]
r 		TEIF[6]
r 		HTIF[6]
r 		TCIF[6]
r 		GIF[6]
r 		TEIF[5]
r 		HTIF[5]
r 		TCIF[5]
r 		GIF[5]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF[4]
r 		HTIF[4]
r 		TCIF[4]
r 		GIF[4]
r 		TEIF[3]
r 		HTIF[3]
r 		TCIF[3]
r 		GIF[3]
r 		TEIF[2]
r 		HTIF[2]
r 		TCIF[2]
r 		GIF[2]
r 		TEIF[1]
r 		HTIF[1]
r 		TCIF[1]
r 		GIF[1]
r
Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF[7]
w 		CHTIF[7]
w 		CTCIF[7]
w 		CGIF[7]
w 		CTEIF[6]
w 		CHTIF[6]
w 		CTCIF[6]
w 		CGIF[6]
w 		CTEIF[5]
w 		CHTIF[5]
w 		CTCIF[5]
w 		CGIF[5]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF[4]
w 		CHTIF[4]
w 		CTCIF[4]
w 		CGIF[4]
w 		CTEIF[3]
w 		CHTIF[3]
w 		CTCIF[3]
w 		CGIF[3]
w 		CTEIF[2]
w 		CHTIF[2]
w 		CTCIF[2]
w 		CGIF[2]
w 		CTEIF[1]
w 		CHTIF[1]
w 		CTCIF[1]
w 		CGIF[1]
w
Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [1]

channel x number of data to transfer register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [2]

channel x number of data to transfer register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [3]

channel x number of data to transfer register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [4]

channel x number of data to transfer register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [5]

channel x number of data to transfer register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [6]

channel x number of data to transfer register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

13/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

SECM

Bit 17: ecure mode.

SSEC

Bit 18: ecurity of the DMA transfer from the source.

DSEC

Bit 19: ecurity of the DMA transfer to the destination.

PRIV

Bit 20: rivileged mode.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

NDTR [7]

channel x number of data to transfer register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: number of data to transfer (0 to 218 - 1).

Allowed values: 0x0-0x3ffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: peripheral address.

MAR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

DMAMUX

0x40020800: DMA request multiplexer

154/154 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR[0]
0x4 CCR[1]
0x8 CCR[2]
0xc CCR[3]
0x10 CCR[4]
0x14 CCR[5]
0x18 CCR[6]
0x1c CCR[7]
0x20 CCR[8]
0x24 CCR[9]
0x28 CCR[10]
0x2c CCR[11]
0x30 CCR[12]
0x34 CCR[13]
0x80 CSR
0x84 CCFR
0x100 RGCR[0]
0x104 RGCR[1]
0x108 RGCR[2]
0x10c RGCR[3]
0x140 RGSR
0x144 RGCFR
Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: DMA request identification.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: adc: Signal `adc1_dma` selected as request input
6: dat_out1: Signal `dac_out1_dma` selected as request input
7: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
8: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
9: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
10: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
11: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
12: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
13: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
14: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
15: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
16: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
17: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
18: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
19: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
20: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
21: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
22: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
23: tim1_ch1: Signal `tim1_ch1` selected as request input
24: tim1_ch2: Signal `tim1_ch2` selected as request input
25: tim1_ch3: Signal `tim1_ch3` selected as request input
26: tim1_ch4: Signal `tim1_ch4` selected as request input
27: tim1_up: Signal `tim1_up` selected as request input
28: tim1_trig: Signal `tim1_trig` selected as request input
29: tim1_com: Signal `tim1_com` selected as request input
30: tim2_ch1: Signal `tim2_ch1` selected as request input
31: tim2_ch2: Signal `tim2_ch2` selected as request input
32: tim2_ch3: Signal `tim2_ch3` selected as request input
33: tim2_ch4: Signal `tim2_ch4` selected as request input
34: tim2_up: Signal `tim2_up` selected as request input
35: tim16_ch1: Signal `tim16_ch1` selected as request input
36: tim16_up: Signal `tim16_up` selected as request input
37: tim17_ch1: Signal `tim17_ch1` selected as request input
38: tim17_up: Signal `tim17_up` selected as request input
39: aes_in: Signal `aes_in` selected as request input
40: aes_out: Signal `aes_out` selected as request input
41: subghzspi_rx: Signal `subghzspi_rx` selected as request input
42: subghzspi_tx: Signal `subghzspi_tx` selected as request input

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

CSR

request line multiplexer interrupt channel status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF[13]
r 		SOF[12]
r 		SOF[11]
r 		SOF[10]
r 		SOF[9]
r 		SOF[8]
r 		SOF[7]
r 		SOF[6]
r 		SOF[5]
r 		SOF[4]
r 		SOF[3]
r 		SOF[2]
r 		SOF[1]
r 		SOF[0]
r
Toggle fields

SOF[0]

Bit 0: Synchronization Overrun Flag 0.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[1]

Bit 1: Synchronization Overrun Flag 1.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[2]

Bit 2: Synchronization Overrun Flag 2.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[3]

Bit 3: Synchronization Overrun Flag 3.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[4]

Bit 4: Synchronization Overrun Flag 4.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[5]

Bit 5: Synchronization Overrun Flag 5.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[6]

Bit 6: Synchronization Overrun Flag 6.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[7]

Bit 7: Synchronization Overrun Flag 7.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[8]

Bit 8: Synchronization Overrun Flag 8.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[9]

Bit 9: Synchronization Overrun Flag 9.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[10]

Bit 10: Synchronization Overrun Flag 10.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[11]

Bit 11: Synchronization Overrun Flag 11.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[12]

Bit 12: Synchronization Overrun Flag 12.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[13]

Bit 13: Synchronization Overrun Flag 13.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

CCFR

request line multiplexer interrupt channel clear flag register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF[13]
w1c 		CSOF[12]
w1c 		CSOF[11]
w1c 		CSOF[10]
w1c 		CSOF[9]
w1c 		CSOF[8]
w1c 		CSOF[7]
w1c 		CSOF[6]
w1c 		CSOF[5]
w1c 		CSOF[4]
w1c 		CSOF[3]
w1c 		CSOF[2]
w1c 		CSOF[1]
w1c 		CSOF[0]
w1c
Toggle fields

CSOF[0]

Bit 0: Synchronization Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[1]

Bit 1: Synchronization Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[2]

Bit 2: Synchronization Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[3]

Bit 3: Synchronization Clear Overrun Flag 3.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[4]

Bit 4: Synchronization Clear Overrun Flag 4.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[5]

Bit 5: Synchronization Clear Overrun Flag 5.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[6]

Bit 6: Synchronization Clear Overrun Flag 6.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[7]

Bit 7: Synchronization Clear Overrun Flag 7.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[8]

Bit 8: Synchronization Clear Overrun Flag 8.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[9]

Bit 9: Synchronization Clear Overrun Flag 9.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[10]

Bit 10: Synchronization Clear Overrun Flag 10.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[11]

Bit 11: Synchronization Clear Overrun Flag 11.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[12]

Bit 12: Synchronization Clear Overrun Flag 12.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[13]

Bit 13: Synchronization Clear Overrun Flag 13.

Allowed values:
1: Clear: Clear synchronization flag

RGCR[0]

request generator channel x configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

Allowed values: 0x0-0x1f

RGCR[1]

request generator channel x configuration register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

Allowed values: 0x0-0x1f

RGCR[2]

request generator channel x configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

Allowed values: 0x0-0x1f

RGCR[3]

request generator channel x configuration register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

Allowed values:
0: exti0: Signal `EXTIx` selected as synchronization input
1: exti1: Signal `EXTIx` selected as synchronization input
2: exti2: Signal `EXTIx` selected as synchronization input
3: exti3: Signal `EXTIx` selected as synchronization input
4: exti4: Signal `EXTIx` selected as synchronization input
5: exti5: Signal `EXTIx` selected as synchronization input
6: exti6: Signal `EXTIx` selected as synchronization input
7: exti7: Signal `EXTIx` selected as synchronization input
8: exti8: Signal `EXTIx` selected as synchronization input
9: exti9: Signal `EXTIx` selected as synchronization input
10: exti10: Signal `EXTIx` selected as synchronization input
11: exti11: Signal `EXTIx` selected as synchronization input
12: exti12: Signal `EXTIx` selected as synchronization input
13: exti13: Signal `EXTIx` selected as synchronization input
14: exti14: Signal `EXTIx` selected as synchronization input
15: exti15: Signal `EXTIx` selected as synchronization input
16: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
17: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
18: lptim1_out: Signal `lptim1_out` selected as synchronization input
19: lptim2_out: Signal `lptim2_out` selected as synchronization input
20: lptim3_out: Signal `lptim3_out` selected as synchronization input

OIE

Bit 8: Trigger overrun interrupt enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel x enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1).

Allowed values: 0x0-0x1f

RGSR

request generator interrupt status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF[3]
r 		OF[2]
r 		OF[1]
r 		OF[0]
r
Toggle fields

OF[0]

Bit 0: Generator Overrun Flag 0.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[1]

Bit 1: Generator Overrun Flag 1.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[2]

Bit 2: Generator Overrun Flag 2.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[3]

Bit 3: Generator Overrun Flag 3.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

RGCFR

request generator interrupt clear flag register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF[3]
w1c 		COF[2]
w1c 		COF[1]
w1c 		COF[0]
w1c
Toggle fields

COF[0]

Bit 0: Generator Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear overrun flag

COF[1]

Bit 1: Generator Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear overrun flag

COF[2]

Bit 2: Generator Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear overrun flag

COF[3]

Bit 3: Generator Clear Overrun Flag 3.

Allowed values:
1: Clear: Clear overrun flag

EXTI

0x58000800: External interrupt/event controller

145/145 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc PR1
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c PR2
0x80 C1IMR1
0x84 EMR1
0x90 C1IMR2
Toggle registers

RTSR1

rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT22
rw 		RT21
rw 		RT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15
rw 		RT14
rw 		RT13
rw 		RT12
rw 		RT11
rw 		RT10
rw 		RT9
rw 		RT8
rw 		RT7
rw 		RT6
rw 		RT5
rw 		RT4
rw 		RT3
rw 		RT2
rw 		RT1
rw 		RT0
rw
Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT22

Bit 22: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR1

falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT22
rw 		FT21
rw 		FT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15
rw 		FT14
rw 		FT13
rw 		FT12
rw 		FT11
rw 		FT10
rw 		FT9
rw 		FT8
rw 		FT7
rw 		FT6
rw 		FT5
rw 		FT4
rw 		FT3
rw 		FT2
rw 		FT1
rw 		FT0
rw
Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT1

Bit 1: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT2

Bit 2: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT3

Bit 3: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT4

Bit 4: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT5

Bit 5: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT6

Bit 6: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT7

Bit 7: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT8

Bit 8: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT9

Bit 9: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT10

Bit 10: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT11

Bit 11: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT12

Bit 12: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT13

Bit 13: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT14

Bit 14: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT15

Bit 15: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT16

Bit 16: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT21

Bit 21: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT22

Bit 22: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER1

software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI22
rw 		SWI21
rw 		SWI16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI15
rw 		SWI14
rw 		SWI13
rw 		SWI12
rw 		SWI11
rw 		SWI10
rw 		SWI9
rw 		SWI8
rw 		SWI7
rw 		SWI6
rw 		SWI5
rw 		SWI4
rw 		SWI3
rw 		SWI2
rw 		SWI1
rw 		SWI0
rw
Toggle fields

SWI0

Bit 0: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI1

Bit 1: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI2

Bit 2: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI3

Bit 3: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI4

Bit 4: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI5

Bit 5: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI6

Bit 6: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI7

Bit 7: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI8

Bit 8: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI9

Bit 9: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI10

Bit 10: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI11

Bit 11: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI12

Bit 12: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI13

Bit 13: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI14

Bit 14: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI15

Bit 15: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI16

Bit 16: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI21

Bit 21: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI22

Bit 22: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

PR1

EXTI pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIF22
r/w1c 		PIF21
r/w1c 		PIF16
r/w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF15
r/w1c 		PIF14
r/w1c 		PIF13
r/w1c 		PIF12
r/w1c 		PIF11
r/w1c 		PIF10
r/w1c 		PIF9
r/w1c 		PIF8
r/w1c 		PIF7
r/w1c 		PIF6
r/w1c 		PIF5
r/w1c 		PIF4
r/w1c 		PIF3
r/w1c 		PIF2
r/w1c 		PIF1
r/w1c 		PIF0
r/w1c
Toggle fields

PIF0

Bit 0: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF1

Bit 1: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF2

Bit 2: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF3

Bit 3: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF4

Bit 4: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF5

Bit 5: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF6

Bit 6: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF7

Bit 7: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF8

Bit 8: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF9

Bit 9: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF10

Bit 10: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF11

Bit 11: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF12

Bit 12: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF13

Bit 13: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF14

Bit 14: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF15

Bit 15: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF16

Bit 16: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF21

Bit 21: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF22

Bit 22: Configurable event inputs Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

RTSR2

rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT45
rw 		RT34
rw
Toggle fields

RT34

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT45

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR2

falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT45
rw 		FT34
rw
Toggle fields

FT34

Bit 2: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT45

Bit 13: Falling trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER2

software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI45
rw 		SWI34
rw
Toggle fields

SWI34

Bit 2: Software interrupt on event.

Allowed values:
1: Pend: Generates an interrupt request

SWI45

Bit 13: Software interrupt on event 45.

Allowed values:
1: Pend: Generates an interrupt request

PR2

pending register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF45
r/w1c 		PIF34
r/w1c
Toggle fields

PIF34

Bit 2: Configurable event inputs 33 Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF45

Bit 13: Configurable event inputs 45 Pending bit..

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

C1IMR1

interrupt mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw 		IM30
rw 		IM29
rw 		IM28
rw 		IM27
rw 		IM26
rw 		IM25
rw 		IM24
rw 		IM23
rw 		IM22
rw 		IM21
rw 		IM20
rw 		IM19
rw 		IM18
rw 		IM17
rw 		IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw 		IM14
rw 		IM13
rw 		IM12
rw 		IM11
rw 		IM10
rw 		IM9
rw 		IM8
rw 		IM7
rw 		IM6
rw 		IM5
rw 		IM4
rw 		IM3
rw 		IM2
rw 		IM1
rw 		IM0
rw
Toggle fields

IM0

Bit 0: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM1

Bit 1: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM2

Bit 2: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM3

Bit 3: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM4

Bit 4: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM5

Bit 5: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM6

Bit 6: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM7

Bit 7: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM8

Bit 8: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM9

Bit 9: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM10

Bit 10: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM11

Bit 11: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM12

Bit 12: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM13

Bit 13: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM14

Bit 14: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM15

Bit 15: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM16

Bit 16: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM17

Bit 17: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM18

Bit 18: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM19

Bit 19: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM20

Bit 20: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM21

Bit 21: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM22

Bit 22: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM23

Bit 23: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM24

Bit 24: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM25

Bit 25: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM26

Bit 26: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM27

Bit 27: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM28

Bit 28: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM29

Bit 29: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM30

Bit 30: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM31

Bit 31: wakeup with interrupt Mask on event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR1

event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM22
rw 		EM21
rw 		EM20
rw 		EM19
rw 		EM18
rw 		EM17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle fields

EM0

Bit 0: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM1

Bit 1: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM2

Bit 2: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM3

Bit 3: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM4

Bit 4: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM5

Bit 5: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM6

Bit 6: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM7

Bit 7: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM8

Bit 8: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM9

Bit 9: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM10

Bit 10: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM11

Bit 11: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM12

Bit 12: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM13

Bit 13: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM14

Bit 14: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM15

Bit 15: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM17

Bit 17: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM18

Bit 18: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM19

Bit 19: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM20

Bit 20: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM21

Bit 21: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

EM22

Bit 22: Wakeup with event generation Mask on Event input.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

C1IMR2

interrupt mask register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM46
rw 		IM45
rw 		IM44
rw 		IM43
rw 		IM42
rw 		IM38
rw 		IM34
rw
Toggle fields

IM34

Bit 2: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM38

Bit 6: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM42

Bit 10: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM43

Bit 11: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM44

Bit 12: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM45

Bit 13: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

IM46

Bit 14: CPUm Wakeup with interrupt Mask on Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

FLASH

0x58004000: Flash

67/68 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x8 KEYR
0xc OPTKEYR
0x10 SR
0x14 CR
0x18 ECCR
0x20 OPTR
0x24 PCROP1ASR
0x28 PCROP1AER
0x2c WRP1AR
0x30 WRP1BR
0x34 PCROP1BSR
0x38 PCROP1BER
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000600, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EMPTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PES
rw 		DCRST
rw 		ICRST
rw 		DCEN
rw 		ICEN
rw 		PRFTEN
rw 		LATENCY
rw
Toggle fields

LATENCY

Bits 0-2: Latency.

Allowed values:
0: WS0: 0 wait states
1: WS1: 1 wait states
2: WS2: 2 wait states

PRFTEN

Bit 8: Prefetch enable.

Allowed values:
0: Disabled: Prefetch is disabled
1: Enabled: Prefetch is enabled

ICEN

Bit 9: Instruction cache enable.

Allowed values:
0: Disabled: Instruction cache is disabled
1: Enabled: Instruction cache is enabled

DCEN

Bit 10: Data cache enable.

Allowed values:
0: Disabled: Data cache is disabled
1: Enabled: Data cache is enabled

ICRST

Bit 11: Instruction cache reset.

Allowed values:
0: NotReset: Instruction cache is not reset
1: Reset: Instruction cache is reset

DCRST

Bit 12: Data cache reset.

Allowed values:
0: NotReset: Data cache is not reset
1: Reset: Data cache is reset

PES

Bit 15: CPU1 programm erase suspend request.

Allowed values:
0: Granted: Flash program and erase operations granted
1: Suspended: Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACR is set

EMPTY

Bit 16: Flash User area empty.

Allowed values:
0: Programmed: User Flash programmend
1: Empty: User Flash empty

KEYR

Flash key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: KEY.

Allowed values: 0x0-0xffffffff

OPTKEYR

Option byte key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY
w
Toggle fields

OPTKEY

Bits 0-31: Option byte key.

Allowed values: 0x0-0xffffffff

SR

Status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PESD
r 		CFGBSY
r 		BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw 		RDERR
rw 		OPTNV
r 		FASTERR
rw 		MISSERR
rw 		PGSERR
rw 		SIZERR
rw 		PGAERR
rw 		WRPERR
rw 		PROGERR
rw 		OPERR
rw 		EOP
rw
Toggle fields

EOP

Bit 0: End of operation.

Allowed values:
0: NoEvent: No EOP operation occurred
1: Event: An EOP event occurred

OPERR

Bit 1: Operation error.

Allowed values:
0: NoError: No memory opreation error happened
1: Error: Memory operation error happened

PROGERR

Bit 3: Programming error.

Allowed values:
0: NoError: No size programming error happened
1: Error: Programming error happened

WRPERR

Bit 4: Write protected error.

Allowed values:
0: NoError: No write protection error happened
1: Error: Write protection error happened

PGAERR

Bit 5: Programming alignment error.

Allowed values:
0: NoError: No programming alignment error happened
1: Error: Programming alignment error happened

SIZERR

Bit 6: Size error.

Allowed values:
0: NoError: No size error happened
1: Error: Size error happened

PGSERR

Bit 7: Programming sequence error.

Allowed values:
0: NoError: No fast programming sequence error happened
1: Error: Fast programming sequence error happened

MISSERR

Bit 8: Fast programming data miss error.

Allowed values:
0: NoError: No fast programming data miss error happened
1: Error: Fast programming data miss error happened

FASTERR

Bit 9: Fast programming error.

Allowed values:
0: NoError: No fast programming error happened
1: Error: Fast programming error happened

OPTNV

Bit 13: User Option OPTIVAL indication.

Allowed values:
0: Valid: The OBL user option OPTVAL indicates "valid"
1: Invalid: The OBL user option OPTVAL indicates "invalid"

RDERR

Bit 14: PCROP read error.

Allowed values:
0: NoError: No read-only error happened
1: Error: Read-only error happened

OPTVERR

Bit 15: Option validity error.

Allowed values:
0: NoError: No error in option and engineering bits
1: Error: Error in option and engineering bits

BSY

Bit 16: Busy.

Allowed values:
0: Inactive: No write/erase operation is in progress
1: Active: No write/erase operation is in progress

CFGBSY

Bit 18: Programming or erase configuration busy.

Allowed values:
0: Free: PG, PNB, PER, MER bits available for writing
1: Busy: PG, PNB, PER, MER bits not available for writing (operation ongoing)

PESD

Bit 19: Programming / erase operation suspended.

Allowed values:
0: Granted: Flash program and erase operations granted
1: Suspended: Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when the PES bit in FLASH_ACR is set

CR

Flash control register

Offset: 0x14, size: 32, reset: 0xC0000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		OPTLOCK
rw 		OBL_LAUNCH
rw 		RDERRIE
rw 		ERRIE
rw 		EOPIE
rw 		FSTPG
rw 		OPTSTRT
rw 		STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PNB
rw 		MER
rw 		PER
rw 		PG
rw
Toggle fields

PG

Bit 0: Programming.

Allowed values:
0: Disabled: Flash programming disabled
1: Enabled: Flash programming enabled

PER

Bit 1: Page erase.

Allowed values:
0: Disabled: Page erase disabled
1: Enabled: Page erase enabled

MER

Bit 2: Mass erase.

Allowed values:
0: NoErase: No mass erase
1: MassErase: Trigger mass erase

PNB

Bits 3-9: Page number.

Allowed values: 0x0-0x7f

STRT

Bit 16: Start.

Allowed values:
0: Done: Options modification completed or idle

OPTSTRT

Bit 17: Options modification start.

Allowed values:
0: Done: Options modification completed or idle

FSTPG

Bit 18: Fast programming.

Allowed values:
0: Disabled: Fast programming disabled
1: Enabled: Fast programming enabled

EOPIE

Bit 24: End of operation interrupt enable.

Allowed values:
0: Disabled: End of program interrupt disable
1: Enabled: End of program interrupt enable

ERRIE

Bit 25: Error interrupt enable.

Allowed values:
0: Disabled: OPERR Error interrupt disable
1: Enabled: OPERR Error interrupt enable

RDERRIE

Bit 26: PCROP read error interrupt enable.

Allowed values:
0: Disabled: PCROP read error interrupt disable
1: Enabled: PCROP read error interrupt enable

OBL_LAUNCH

Bit 27: Force the option byte loading.

Allowed values:
0: Complete: Option byte loaded
1: NotComplete: Option byte loading to be done

OPTLOCK

Bit 30: Options Lock.

Allowed values:
0: Unlocked: FLASH_CR options are unlocked

LOCK

Bit 31: FLASH_CR Lock.

Allowed values:
0: Unlocked: FLASH_CR is unlocked

ECCR

Flash ECC register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw 		ECCC
rw 		ECCCIE
rw 		SYSF_ECC
r 		ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle fields

ADDR_ECC

Bits 0-16: ECC fail address.

Allowed values: 0x0-0x1ffff

SYSF_ECC

Bit 20: System Flash ECC fail.

Allowed values:
0: NotInFlash: No System Flash memory ECC fail
1: InFlash: System Flash memory ECC fail

ECCCIE

Bit 24: ECC correction interrupt enable.

Allowed values:
0: Disabled: ECCC interrupt disabled
1: Enabled: ECCC interrupt enabled

ECCC

Bit 30: ECC correction.

Allowed values:
0: NoEvent: ECC error corrected
1: Event: No ECC error corrected

ECCD

Bit 31: ECC detection.

Allowed values:
0: NoEvent: Two ECC errors detected
1: Event: No two ECC errors detected

OPTR

Flash option register

Offset: 0x20, size: 32, reset: 0x3FFFF0AA, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_LOCK
rw 		nBOOT0
rw 		nSWBOOT0
rw 		SRAM_RST
rw 		SRAM2_PE
rw 		nBOOT1
rw 		WWDG_SW
rw 		IWDG_STDBY
rw 		IWDG_STOP
rw 		IWDG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_SHDW
rw 		nRST_STDBY
rw 		nRST_STOP
rw 		BOR_LEV
rw 		ESE
rw 		RDP
rw
Toggle fields

RDP

Bits 0-7: Read protection level.

Allowed values:
136: Level1: Level 1, memories readout protection active (writes 0x88)
170: Level0: Level 0, readout protection not active
204: Level2: Level 2, chip readout protection active

ESE

Bit 8: System security enabled flag.

Allowed values:
0: Disabled: Security disabled
1: Enabled: Security enabled

BOR_LEV

Bits 9-11: BOR reset Level.

Allowed values:
0: Level0: BOR level 0. Reset level threshold is around 1.7 V
1: Level1: BOR level 1. Reset level threshold is around 2.0 V
2: Level2: BOR level 2. Reset level threshold is around 2.2 V
3: Level3: BOR level 3. Reset level threshold is around 2.5 V
4: Level4: BOR level 4. Reset level threshold is around 2.8 V

nRST_STOP

Bit 12: nRST_STOP.

Allowed values:
0: Enabled: Reset generated when entering the Standby mode
1: Disabled: No reset generated when entering the Standby mode

nRST_STDBY

Bit 13: nRST_STDBY.

Allowed values:
0: Enabled: Reset generated when entering the Standby mode
1: Disabled: No reset generated when entering the Standby mode

nRST_SHDW

Bit 14: nRSTSHDW.

Allowed values:
0: Enabled: Reset generated when entering the Shutdown mode
1: Disabled: No reset generated when entering the Shutdown mode

IWDG_SW

Bit 16: Independent watchdog selection.

Allowed values:
0: Hardware: Hardware independent watchdog
1: Software: Software independent watchdog

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

Allowed values:
0: Frozen: Independent watchdog counter frozen in Stop mode
1: Running: Independent watchdog counter running in Stop mode

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

Allowed values:
0: Frozen: Independent watchdog counter frozen in Standby mode
1: Running: Independent watchdog counter running in Standby mode

WWDG_SW

Bit 19: Window watchdog selection.

Allowed values:
0: Hardware: Hardware window watchdog
1: Software: Software window watchdog

nBOOT1

Bit 23: Boot configuration.

Allowed values:
0: Clear: When nSWBOOT0 is cleared, select boot mode together with nBOOT0
1: Set: When nSWBOOT0 is cleared, select boot mode together with nBOOT0

SRAM2_PE

Bit 24: SRAM2 parity check enable.

Allowed values:
0: Enabled: SRAM2 Parity check enabled
1: Disabled: SRAM2 Parity check disabled

SRAM_RST

Bit 25: SRAM2 Erase when system reset.

Allowed values:
0: Reset: SRAM1 and SRAM2 erased when a system reset occurs
1: NotReset: SRAM1 and SRAM2 not erased when a system reset occurs

nSWBOOT0

Bit 26: Software BOOT0 selection.

Allowed values:
0: Bit: BOOT0 taken from nBOOT0 in this register
1: Pin: BOOT0 taken from GPIO PH3/BOOT0

nBOOT0

Bit 27: nBOOT0 option bit.

Allowed values:
0: Clear: When nSWBOOT0 is cleared, select boot mode together with nBOOT1
1: Set: When nSWBOOT0 is cleared, select boot mode together with nBOOT1

BOOT_LOCK

Bit 30: CPU1 CM4 Unique Boot entry enable option bit.

Allowed values:
0: Disabled: Boot lock is disabled
1: Enabled: Boot lock is enabled

PCROP1ASR

Flash PCROP zone A Start address register

Offset: 0x24, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1A_STRT
rw
Toggle fields

PCROP1A_STRT

Bits 0-7: PCROP1A area start offset.

Allowed values: 0x0-0xff

PCROP1AER

Flash PCROP zone A End address register

Offset: 0x28, size: 32, reset: 0xFFFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP_RDP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1A_END
rw
Toggle fields

PCROP1A_END

Bits 0-7: PCROP area end offset.

Allowed values: 0x0-0xff

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash WRP area A address register

Offset: 0x2c, size: 32, reset: 0xFF80FFFF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_STRT
rw
Toggle fields

WRP1A_STRT

Bits 0-6: Bank 1 WRP first area start offset.

Allowed values: 0x0-0x7f

WRP1A_END

Bits 16-22: Bank 1 WRP first area A end offset.

Allowed values: 0x0-0x7f

WRP1BR

Flash WRP area B address register

Offset: 0x30, size: 32, reset: 0xFF80FFFF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_STRT
rw
Toggle fields

WRP1B_STRT

Bits 0-6: Bank 1 WRP second area B end offset.

Allowed values: 0x0-0x7f

WRP1B_END

Bits 16-22: Bank 1 WRP second area B start offset.

Allowed values: 0x0-0x7f

PCROP1BSR

Flash PCROP zone B Start address register

Offset: 0x34, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1B_STRT
rw
Toggle fields

PCROP1B_STRT

Bits 0-7: Bank 1 WRP second area B end offset.

Allowed values: 0x0-0xff

PCROP1BER

Flash PCROP zone B End address register

Offset: 0x38, size: 32, reset: 0xFFFFFF00, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1B_END
rw
Toggle fields

PCROP1B_END

Bits 0-7: PCROP1B area end offset.

Allowed values: 0x0-0xff

GPIOA

0x48000000: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
rw 		BR[14]
rw 		BR[13]
rw 		BR[12]
rw 		BR[11]
rw 		BR[10]
rw 		BR[9]
rw 		BR[8]
rw 		BR[7]
rw 		BR[6]
rw 		BR[5]
rw 		BR[4]
rw 		BR[3]
rw 		BR[2]
rw 		BR[1]
rw 		BR[0]
rw
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOB

0x48000400: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
rw 		BR[14]
rw 		BR[13]
rw 		BR[12]
rw 		BR[11]
rw 		BR[10]
rw 		BR[9]
rw 		BR[8]
rw 		BR[7]
rw 		BR[6]
rw 		BR[5]
rw 		BR[4]
rw 		BR[3]
rw 		BR[2]
rw 		BR[1]
rw 		BR[0]
rw
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOC

0x48000800: General-purpose I/Os

117/117 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFC003FFF, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
rw 		BR14
rw 		BR13
rw 		BR6
rw 		BR5
rw 		BR4
rw 		BR3
rw 		BR2
rw 		BR1
rw 		BR0
rw
Toggle fields

BR0

Bit 0: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOH

0x48001c00: General-purpose I/Os

20/20 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x000000C0, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER3
rw
Toggle fields

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT3
rw
Toggle fields

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR3
rw
Toggle fields

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR3
rw
Toggle fields

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR3
r
Toggle fields

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR3
rw
Toggle fields

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR3
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS3
w
Toggle fields

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK3
rw
Toggle fields

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
Toggle fields

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR3
rw
Toggle fields

BR3

Bit 3: Port Reset bit.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

HSEM

0x58001400: Hardware semaphore

163/163 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 R[0]
0x4 R[1]
0x8 R[2]
0xc R[3]
0x10 R[4]
0x14 R[5]
0x18 R[6]
0x1c R[7]
0x20 R[8]
0x24 R[9]
0x28 R[10]
0x2c R[11]
0x30 R[12]
0x34 R[13]
0x38 R[14]
0x3c R[15]
0x80 RLR[0]
0x84 RLR[1]
0x88 RLR[2]
0x8c RLR[3]
0x90 RLR[4]
0x94 RLR[5]
0x98 RLR[6]
0x9c RLR[7]
0xa0 RLR[8]
0xa4 RLR[9]
0xa8 RLR[10]
0xac RLR[11]
0xb0 RLR[12]
0xb4 RLR[13]
0xb8 RLR[14]
0xbc RLR[15]
0x100 IER
0x104 ICR
0x108 ISR
0x10c MISR
0x140 CR
0x144 KEYR
Toggle registers

R[0]

HSEM register HSEM_R0

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[1]

HSEM register HSEM_R1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[2]

HSEM register HSEM_R2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[3]

HSEM register HSEM_R3

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[4]

HSEM register HSEM_R4

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[5]

HSEM register HSEM_R5

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[6]

HSEM register HSEM_R6

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[7]

HSEM register HSEM_R7

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[8]

HSEM register HSEM_R8

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[9]

HSEM register HSEM_R9

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[10]

HSEM register HSEM_R10

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[11]

HSEM register HSEM_R11

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[12]

HSEM register HSEM_R12

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[13]

HSEM register HSEM_R13

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[14]

HSEM register HSEM_R14

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[15]

HSEM register HSEM_R15

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[0]

Semaphore 0 read lock register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[1]

Semaphore 1 read lock register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[2]

Semaphore 2 read lock register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[3]

Semaphore 3 read lock register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[4]

Semaphore 4 read lock register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[5]

Semaphore 5 read lock register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[6]

Semaphore 6 read lock register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[7]

Semaphore 7 read lock register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[8]

Semaphore 8 read lock register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[9]

Semaphore 9 read lock register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[10]

Semaphore 10 read lock register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[11]

Semaphore 11 read lock register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[12]

Semaphore 12 read lock register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[13]

Semaphore 13 read lock register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[14]

Semaphore 14 read lock register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[15]

Semaphore 15 read lock register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-11: Semaphore MASTERID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

IER

HSEM Interrupt enable register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISE[15]
rw 		ISE[14]
rw 		ISE[13]
rw 		ISE[12]
rw 		ISE[11]
rw 		ISE[10]
rw 		ISE[9]
rw 		ISE[8]
rw 		ISE[7]
rw 		ISE[6]
rw 		ISE[5]
rw 		ISE[4]
rw 		ISE[3]
rw 		ISE[2]
rw 		ISE[1]
rw 		ISE[0]
rw
Toggle fields

ISE[0]

Bit 0: Interrupt semaphore 0 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[1]

Bit 1: Interrupt semaphore 1 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[2]

Bit 2: Interrupt semaphore 2 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[3]

Bit 3: Interrupt semaphore 3 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[4]

Bit 4: Interrupt semaphore 4 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[5]

Bit 5: Interrupt semaphore 5 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[6]

Bit 6: Interrupt semaphore 6 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[7]

Bit 7: Interrupt semaphore 7 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[8]

Bit 8: Interrupt semaphore 8 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[9]

Bit 9: Interrupt semaphore 9 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[10]

Bit 10: Interrupt semaphore 10 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[11]

Bit 11: Interrupt semaphore 11 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[12]

Bit 12: Interrupt semaphore 12 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[13]

Bit 13: Interrupt semaphore 13 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[14]

Bit 14: Interrupt semaphore 14 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[15]

Bit 15: Interrupt semaphore 15 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ICR

HSEM Interrupt clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISC[15]
rw 		ISC[14]
rw 		ISC[13]
rw 		ISC[12]
rw 		ISC[11]
rw 		ISC[10]
rw 		ISC[9]
rw 		ISC[8]
rw 		ISC[7]
rw 		ISC[6]
rw 		ISC[5]
rw 		ISC[4]
rw 		ISC[3]
rw 		ISC[2]
rw 		ISC[1]
rw 		ISC[0]
rw
Toggle fields

ISC[0]

Bit 0: Interrupt semaphore 0 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[1]

Bit 1: Interrupt semaphore 1 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[2]

Bit 2: Interrupt semaphore 2 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[3]

Bit 3: Interrupt semaphore 3 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[4]

Bit 4: Interrupt semaphore 4 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[5]

Bit 5: Interrupt semaphore 5 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[6]

Bit 6: Interrupt semaphore 6 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[7]

Bit 7: Interrupt semaphore 7 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[8]

Bit 8: Interrupt semaphore 8 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[9]

Bit 9: Interrupt semaphore 9 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[10]

Bit 10: Interrupt semaphore 10 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[11]

Bit 11: Interrupt semaphore 11 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[12]

Bit 12: Interrupt semaphore 12 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[13]

Bit 13: Interrupt semaphore 13 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[14]

Bit 14: Interrupt semaphore 14 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[15]

Bit 15: Interrupt semaphore 15 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISR

HSEM Interrupt status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISF[15]
r 		ISF[14]
r 		ISF[13]
r 		ISF[12]
r 		ISF[11]
r 		ISF[10]
r 		ISF[9]
r 		ISF[8]
r 		ISF[7]
r 		ISF[6]
r 		ISF[5]
r 		ISF[4]
r 		ISF[3]
r 		ISF[2]
r 		ISF[1]
r 		ISF[0]
r
Toggle fields

ISF[0]

Bit 0: Interrupt semaphore 0 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[1]

Bit 1: Interrupt semaphore 1 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[2]

Bit 2: Interrupt semaphore 2 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[3]

Bit 3: Interrupt semaphore 3 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[4]

Bit 4: Interrupt semaphore 4 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[5]

Bit 5: Interrupt semaphore 5 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[6]

Bit 6: Interrupt semaphore 6 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[7]

Bit 7: Interrupt semaphore 7 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[8]

Bit 8: Interrupt semaphore 8 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[9]

Bit 9: Interrupt semaphore 9 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[10]

Bit 10: Interrupt semaphore 10 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[11]

Bit 11: Interrupt semaphore 11 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[12]

Bit 12: Interrupt semaphore 12 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[13]

Bit 13: Interrupt semaphore 13 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[14]

Bit 14: Interrupt semaphore 14 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[15]

Bit 15: Interrupt semaphore 15 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

MISR

HSEM Masked interrupt status register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISF[15]
r 		MISF[14]
r 		MISF[13]
r 		MISF[12]
r 		MISF[11]
r 		MISF[10]
r 		MISF[9]
r 		MISF[8]
r 		MISF[7]
r 		MISF[6]
r 		MISF[5]
r 		MISF[4]
r 		MISF[3]
r 		MISF[2]
r 		MISF[1]
r 		MISF[0]
r
Toggle fields

MISF[0]

Bit 0: Masked interrupt semaphore 0 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[1]

Bit 1: Masked interrupt semaphore 1 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[2]

Bit 2: Masked interrupt semaphore 2 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[3]

Bit 3: Masked interrupt semaphore 3 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[4]

Bit 4: Masked interrupt semaphore 4 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[5]

Bit 5: Masked interrupt semaphore 5 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[6]

Bit 6: Masked interrupt semaphore 6 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[7]

Bit 7: Masked interrupt semaphore 7 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[8]

Bit 8: Masked interrupt semaphore 8 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[9]

Bit 9: Masked interrupt semaphore 9 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[10]

Bit 10: Masked interrupt semaphore 10 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[11]

Bit 11: Masked interrupt semaphore 11 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[12]

Bit 12: Masked interrupt semaphore 12 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[13]

Bit 13: Masked interrupt semaphore 13 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[14]

Bit 14: Masked interrupt semaphore 14 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[15]

Bit 15: Masked interrupt semaphore 15 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

CR

HSEM Clear register

Offset: 0x140, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
w
Toggle fields

MASTERID

Bits 8-11: MASTERID.

Allowed values: 0x0-0xf

KEY

Bits 16-31: Semaphore clear Key.

Allowed values: 0x0-0xffff

KEYR

HSEM Interrupt clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

KEY

Bits 16-31: Semaphore Clear Key.

Allowed values: 0x0-0xffff

I2C1

0x40005400: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s 		STOP
r/w1s 		START
r/w1s 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
r/w1s 		TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c 		TIMOUTCF
w1c 		PECCF
w1c 		OVRCF
w1c 		ARLOCF
w1c 		BERRCF
w1c 		STOPCF
w1c 		NACKCF
w1c 		ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C2

0x40005800: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s 		STOP
r/w1s 		START
r/w1s 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
r/w1s 		TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c 		TIMOUTCF
w1c 		PECCF
w1c 		OVRCF
w1c 		ARLOCF
w1c 		BERRCF
w1c 		STOPCF
w1c 		NACKCF
w1c 		ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C3

0x40005c00: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s 		STOP
r/w1s 		START
r/w1s 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
r/w1s 		TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c 		TIMOUTCF
w1c 		PECCF
w1c 		OVRCF
w1c 		ARLOCF
w1c 		BERRCF
w1c 		STOPCF
w1c 		NACKCF
w1c 		ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

IWDG

0x40003000: Independent watchdog

6/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) KR
0x4 (16-bit) PR
0x8 (16-bit) RLR
0xc (16-bit) SR
Toggle registers

KR

Key register

Offset: 0x0, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

Prescaler register

Offset: 0x4, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6 (+): DivideBy256: Divider /256

RLR

Reload register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

Allowed values:
0: Idle: No update on-going
1: Busy: Update on-going

RVU

Bit 1: Watchdog counter reload value update.

Allowed values:
0: Idle: No update on-going
1: Busy: Update on-going

WVU

Bit 2: Watchdog counter window value update.

Allowed values:
0: Idle: No update on-going
1: Busy: Update on-going

LPTIM1

0x40007c00: Low-power timer

51/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

Allowed values:
1: Set: Compare match

ARRM

Bit 1: Autoreload match.

Allowed values:
1: Set: Autoreload match

EXTTRIG

Bit 2: External trigger edge event.

Allowed values:
1: Set: External trigger edge event

CMPOK

Bit 3: Compare register update OK.

Allowed values:
1: Set: Compare register update OK

ARROK

Bit 4: Autoreload register update OK.

Allowed values:
1: Set: Autoreload register update OK

UP

Bit 5: Counter direction change down to up.

Allowed values:
1: Set: Counter direction change down to up

DOWN

Bit 6: Counter direction change up to down.

Allowed values:
1: Set: Counter direction change up to down

UE

Bit 7: LPTIM update event occurred.

Allowed values:
1: Set: LPTIM update event occurred

REPOK

Bit 8: Repetition register update Ok.

Allowed values:
1: Set: Repetition register update OK

ICR

interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

Allowed values:
1: Clear: Compare match Clear Flag

ARRMCF

Bit 1: Autoreload match Clear Flag.

Allowed values:
1: Clear: Autoreload match Clear Flag

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

Allowed values:
1: Clear: External trigger valid edge Clear Flag

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

Allowed values:
1: Clear: Compare register update OK Clear Flag

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

Allowed values:
1: Clear: Autoreload register update OK Clear Flag

UPCF

Bit 5: Direction change to UP Clear Flag.

Allowed values:
1: Clear: Direction change to up Clear Flag

DOWNCF

Bit 6: Direction change to down Clear Flag.

Allowed values:
1: Clear: Direction change to down Clear Flag

UECF

Bit 7: Update event clear flag.

Allowed values:
1: Clear: Clear update event flag

REPOKCF

Bit 8: Repetition register update OK clear flag.

Allowed values:
1: Clear: Clear REPOK flag

IER

interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0: Disabled: CMPM interrupt disabled
1: Enabled: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0: Disabled: ARRM interrupt disabled
1: Enabled: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0: Disabled: EXTTRIG interrupt disabled
1: Enabled: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0: Disabled: CMPOK interrupt disabled
1: Enabled: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0: Disabled: ARROK interrupt disabled
1: Enabled: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable.

Allowed values:
0: Disabled: UP interrupt disabled
1: Enabled: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

Allowed values:
0: Disabled: DOWN interrupt disabled
1: Enabled: DOWN interrupt enabled

UEIE

Bit 7: Update event interrupt enable.

Allowed values:
0: Disabled: Update event interrupt disabled
1: Enabled: Update event interrupt enabled

REPOKIE

Bit 8: Repetition register update OK interrupt Enable.

Allowed values:
0: Disabled: Repetition register update OK interrupt disabled
1: Enabled: Repetition register update OK interrupt enabled

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

Allowed values:
0: Internal: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: External: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: CKPOL.

Allowed values:
0: RisingEdge: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
1: FallingEdge: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
2: BothEdges: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.

CKFLT

Bits 3-4: CKFLT.

Allowed values:
0: Immediate: Any external clock signal level change is considered as a valid transition
1: Clocks2: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
2: Clocks4: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
3: Clocks8: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

TRGFLT

Bits 6-7: TRGFLT.

Allowed values:
0: Immediate: Any trigger active level change is considered as a valid trigger
1: Clocks2: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
2: Clocks4: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
3: Clocks8: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

PRESC

Bits 9-11: PRESC.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div8: /8
4: Div16: /16
5: Div32: /32
6: Div64: /64
7: Div128: /128

TRIGSEL

Bits 13-15: TRIGSEL.

Allowed values:
0: Trig0: lptim_ext_trig0
1: Trig1: lptim_ext_trig1
2: Trig2: lptim_ext_trig2
3: Trig3: lptim_ext_trig3
4: Trig4: lptim_ext_trig4
5: Trig5: lptim_ext_trig5
6: Trig6: lptim_ext_trig6
7: Trig7: lptim_ext_trig7

TRIGEN

Bits 17-18: TRIGEN.

Allowed values:
0: SW: Software trigger (counting start is initiated by software)
1: RisingEdge: Rising edge is the active edge
2: FallingEdge: Falling edge is the active edge
3: BothEdges: Both edges are active edges

TIMOUT

Bit 19: TIMOUT.

Allowed values:
0: Disabled: A trigger event arriving when the timer is already started will be ignored
1: Enabled: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: WAVE.

Allowed values:
0: Inactive: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Active: Activate the Set-once mode

WAVPOL

Bit 21: WAVPOL.

Allowed values:
0: Positive: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
1: Negative: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers

PRELOAD

Bit 22: PRELOAD.

Allowed values:
0: Immediate: Registers are updated after each APB bus write access
1: EndOfPeriod: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: COUNTMODE.

Allowed values:
0: Internal: The counter is incremented following each internal clock pulse
1: External: The counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: ENC.

Allowed values:
0: Disabled: Encoder mode disabled
1: Enabled: Encoder mode enabled

CR

control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

Allowed values:
0: Disabled: LPTIM is disabled
1: Enabled: LPTIM is enabled

SNGSTRT

Bit 1: SNGSTRT.

Allowed values:
1: Start: LPTIM start in Single mode

CNTSTRT

Bit 2: CNTSTRT.

Allowed values:
1: Start: Timer start in Continuous mode

COUNTRST

Bit 3: COUNTRST.

Allowed values:
0: Idle: Triggering of reset is possible
1: Busy: Reset in progress, do not write 1 to this field

RSTARE

Bit 4: RSTARE.

Allowed values:
0: Disabled: CNT Register reads do not trigger reset
1: Enabled: CNT Register reads trigger reset of LPTIM

CMP

compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

Allowed values: 0x0-0xffff

ARR

autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

Allowed values: 0x0-0xffff

CNT

counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

OR

option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

Allowed values:
0: IO: LPTIM1 input 1 is connected to I/O
1: COMP1_OUT: LPTIM1 input 1 is connected to COMP1_OUT

OR_1

Bit 1: Option register bit 1.

Allowed values:
0: IO: LPTIM1 input 2 is connected to I/O
1: COMP2_OUT: LPTIM1 input 2 is connected to COMP2_OUT

RCR

repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

Allowed values: 0x0-0xff

LPTIM2

0x40009400: Low-power timer

50/50 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

Allowed values:
1: Set: Compare match

ARRM

Bit 1: Autoreload match.

Allowed values:
1: Set: Autoreload match

EXTTRIG

Bit 2: External trigger edge event.

Allowed values:
1: Set: External trigger edge event

CMPOK

Bit 3: Compare register update OK.

Allowed values:
1: Set: Compare register update OK

ARROK

Bit 4: Autoreload register update OK.

Allowed values:
1: Set: Autoreload register update OK

UP

Bit 5: Counter direction change down to up.

Allowed values:
1: Set: Counter direction change down to up

DOWN

Bit 6: Counter direction change up to down.

Allowed values:
1: Set: Counter direction change up to down

UE

Bit 7: LPTIM update event occurred.

Allowed values:
1: Set: LPTIM update event occurred

REPOK

Bit 8: Repetition register update Ok.

Allowed values:
1: Set: Repetition register update OK

ICR

interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

Allowed values:
1: Clear: Compare match Clear Flag

ARRMCF

Bit 1: Autoreload match Clear Flag.

Allowed values:
1: Clear: Autoreload match Clear Flag

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

Allowed values:
1: Clear: External trigger valid edge Clear Flag

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

Allowed values:
1: Clear: Compare register update OK Clear Flag

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

Allowed values:
1: Clear: Autoreload register update OK Clear Flag

UPCF

Bit 5: Direction change to UP Clear Flag.

Allowed values:
1: Clear: Direction change to up Clear Flag

DOWNCF

Bit 6: Direction change to down Clear Flag.

Allowed values:
1: Clear: Direction change to down Clear Flag

UECF

Bit 7: Update event clear flag.

Allowed values:
1: Clear: Clear update event flag

REPOKCF

Bit 8: Repetition register update OK clear flag.

Allowed values:
1: Clear: Clear REPOK flag

IER

interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0: Disabled: CMPM interrupt disabled
1: Enabled: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0: Disabled: ARRM interrupt disabled
1: Enabled: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0: Disabled: EXTTRIG interrupt disabled
1: Enabled: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0: Disabled: CMPOK interrupt disabled
1: Enabled: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0: Disabled: ARROK interrupt disabled
1: Enabled: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable.

Allowed values:
0: Disabled: UP interrupt disabled
1: Enabled: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

Allowed values:
0: Disabled: DOWN interrupt disabled
1: Enabled: DOWN interrupt enabled

UEIE

Bit 7: Update event interrupt enable.

Allowed values:
0: Disabled: Update event interrupt disabled
1: Enabled: Update event interrupt enabled

REPOKIE

Bit 8: Repetition register update OK interrupt Enable.

Allowed values:
0: Disabled: Repetition register update OK interrupt disabled
1: Enabled: Repetition register update OK interrupt enabled

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

Allowed values:
0: Internal: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: External: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: CKPOL.

Allowed values:
0: RisingEdge: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
1: FallingEdge: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
2: BothEdges: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.

CKFLT

Bits 3-4: CKFLT.

Allowed values:
0: Immediate: Any external clock signal level change is considered as a valid transition
1: Clocks2: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
2: Clocks4: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
3: Clocks8: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

TRGFLT

Bits 6-7: TRGFLT.

Allowed values:
0: Immediate: Any trigger active level change is considered as a valid trigger
1: Clocks2: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
2: Clocks4: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
3: Clocks8: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

PRESC

Bits 9-11: PRESC.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div8: /8
4: Div16: /16
5: Div32: /32
6: Div64: /64
7: Div128: /128

TRIGSEL

Bits 13-15: TRIGSEL.

Allowed values:
0: Trig0: lptim_ext_trig0
1: Trig1: lptim_ext_trig1
2: Trig2: lptim_ext_trig2
3: Trig3: lptim_ext_trig3
4: Trig4: lptim_ext_trig4
5: Trig5: lptim_ext_trig5
6: Trig6: lptim_ext_trig6
7: Trig7: lptim_ext_trig7

TRIGEN

Bits 17-18: TRIGEN.

Allowed values:
0: SW: Software trigger (counting start is initiated by software)
1: RisingEdge: Rising edge is the active edge
2: FallingEdge: Falling edge is the active edge
3: BothEdges: Both edges are active edges

TIMOUT

Bit 19: TIMOUT.

Allowed values:
0: Disabled: A trigger event arriving when the timer is already started will be ignored
1: Enabled: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: WAVE.

Allowed values:
0: Inactive: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Active: Activate the Set-once mode

WAVPOL

Bit 21: WAVPOL.

Allowed values:
0: Positive: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
1: Negative: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers

PRELOAD

Bit 22: PRELOAD.

Allowed values:
0: Immediate: Registers are updated after each APB bus write access
1: EndOfPeriod: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: COUNTMODE.

Allowed values:
0: Internal: The counter is incremented following each internal clock pulse
1: External: The counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: ENC.

Allowed values:
0: Disabled: Encoder mode disabled
1: Enabled: Encoder mode enabled

CR

control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

Allowed values:
0: Disabled: LPTIM is disabled
1: Enabled: LPTIM is enabled

SNGSTRT

Bit 1: SNGSTRT.

Allowed values:
1: Start: LPTIM start in Single mode

CNTSTRT

Bit 2: CNTSTRT.

Allowed values:
1: Start: Timer start in Continuous mode

COUNTRST

Bit 3: COUNTRST.

Allowed values:
0: Idle: Triggering of reset is possible
1: Busy: Reset in progress, do not write 1 to this field

RSTARE

Bit 4: RSTARE.

Allowed values:
0: Disabled: CNT Register reads do not trigger reset
1: Enabled: CNT Register reads trigger reset of LPTIM

CMP

compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

Allowed values: 0x0-0xffff

ARR

autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

Allowed values: 0x0-0xffff

CNT

counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

OR

option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_
rw
Toggle fields

OR_

Bits 0-1: Option register bit 1.

Allowed values:
0: IO: Input 1 is connected to I/O
1: COMP1_OUT: Input 1 is connected to COMP1_OUT
2: COMP2_OUT: Input 1 is connected to COMP2_OUT
3: OR_COMP1_COMP2: Input 1 is connected to COMP1_OUT OR COMP2_OUT

RCR

repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

Allowed values: 0x0-0xff

LPTIM3

0x40009800: Low-power timer

50/50 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

Allowed values:
1: Set: Compare match

ARRM

Bit 1: Autoreload match.

Allowed values:
1: Set: Autoreload match

EXTTRIG

Bit 2: External trigger edge event.

Allowed values:
1: Set: External trigger edge event

CMPOK

Bit 3: Compare register update OK.

Allowed values:
1: Set: Compare register update OK

ARROK

Bit 4: Autoreload register update OK.

Allowed values:
1: Set: Autoreload register update OK

UP

Bit 5: Counter direction change down to up.

Allowed values:
1: Set: Counter direction change down to up

DOWN

Bit 6: Counter direction change up to down.

Allowed values:
1: Set: Counter direction change up to down

UE

Bit 7: LPTIM update event occurred.

Allowed values:
1: Set: LPTIM update event occurred

REPOK

Bit 8: Repetition register update Ok.

Allowed values:
1: Set: Repetition register update OK

ICR

interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

Allowed values:
1: Clear: Compare match Clear Flag

ARRMCF

Bit 1: Autoreload match Clear Flag.

Allowed values:
1: Clear: Autoreload match Clear Flag

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

Allowed values:
1: Clear: External trigger valid edge Clear Flag

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

Allowed values:
1: Clear: Compare register update OK Clear Flag

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

Allowed values:
1: Clear: Autoreload register update OK Clear Flag

UPCF

Bit 5: Direction change to UP Clear Flag.

Allowed values:
1: Clear: Direction change to up Clear Flag

DOWNCF

Bit 6: Direction change to down Clear Flag.

Allowed values:
1: Clear: Direction change to down Clear Flag

UECF

Bit 7: Update event clear flag.

Allowed values:
1: Clear: Clear update event flag

REPOKCF

Bit 8: Repetition register update OK clear flag.

Allowed values:
1: Clear: Clear REPOK flag

IER

interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0: Disabled: CMPM interrupt disabled
1: Enabled: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0: Disabled: ARRM interrupt disabled
1: Enabled: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0: Disabled: EXTTRIG interrupt disabled
1: Enabled: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0: Disabled: CMPOK interrupt disabled
1: Enabled: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0: Disabled: ARROK interrupt disabled
1: Enabled: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable.

Allowed values:
0: Disabled: UP interrupt disabled
1: Enabled: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

Allowed values:
0: Disabled: DOWN interrupt disabled
1: Enabled: DOWN interrupt enabled

UEIE

Bit 7: Update event interrupt enable.

Allowed values:
0: Disabled: Update event interrupt disabled
1: Enabled: Update event interrupt enabled

REPOKIE

Bit 8: Repetition register update OK interrupt Enable.

Allowed values:
0: Disabled: Repetition register update OK interrupt disabled
1: Enabled: Repetition register update OK interrupt enabled

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

Allowed values:
0: Internal: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: External: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: CKPOL.

Allowed values:
0: RisingEdge: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
1: FallingEdge: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
2: BothEdges: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.

CKFLT

Bits 3-4: CKFLT.

Allowed values:
0: Immediate: Any external clock signal level change is considered as a valid transition
1: Clocks2: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
2: Clocks4: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
3: Clocks8: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

TRGFLT

Bits 6-7: TRGFLT.

Allowed values:
0: Immediate: Any trigger active level change is considered as a valid trigger
1: Clocks2: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
2: Clocks4: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
3: Clocks8: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

PRESC

Bits 9-11: PRESC.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div8: /8
4: Div16: /16
5: Div32: /32
6: Div64: /64
7: Div128: /128

TRIGSEL

Bits 13-15: TRIGSEL.

Allowed values:
0: Trig0: lptim_ext_trig0
1: Trig1: lptim_ext_trig1
2: Trig2: lptim_ext_trig2
3: Trig3: lptim_ext_trig3
4: Trig4: lptim_ext_trig4
5: Trig5: lptim_ext_trig5
6: Trig6: lptim_ext_trig6
7: Trig7: lptim_ext_trig7

TRIGEN

Bits 17-18: TRIGEN.

Allowed values:
0: SW: Software trigger (counting start is initiated by software)
1: RisingEdge: Rising edge is the active edge
2: FallingEdge: Falling edge is the active edge
3: BothEdges: Both edges are active edges

TIMOUT

Bit 19: TIMOUT.

Allowed values:
0: Disabled: A trigger event arriving when the timer is already started will be ignored
1: Enabled: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: WAVE.

Allowed values:
0: Inactive: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Active: Activate the Set-once mode

WAVPOL

Bit 21: WAVPOL.

Allowed values:
0: Positive: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
1: Negative: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers

PRELOAD

Bit 22: PRELOAD.

Allowed values:
0: Immediate: Registers are updated after each APB bus write access
1: EndOfPeriod: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: COUNTMODE.

Allowed values:
0: Internal: The counter is incremented following each internal clock pulse
1: External: The counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: ENC.

Allowed values:
0: Disabled: Encoder mode disabled
1: Enabled: Encoder mode enabled

CR

control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

Allowed values:
0: Disabled: LPTIM is disabled
1: Enabled: LPTIM is enabled

SNGSTRT

Bit 1: SNGSTRT.

Allowed values:
1: Start: LPTIM start in Single mode

CNTSTRT

Bit 2: CNTSTRT.

Allowed values:
1: Start: Timer start in Continuous mode

COUNTRST

Bit 3: COUNTRST.

Allowed values:
0: Idle: Triggering of reset is possible
1: Busy: Reset in progress, do not write 1 to this field

RSTARE

Bit 4: RSTARE.

Allowed values:
0: Disabled: CNT Register reads do not trigger reset
1: Enabled: CNT Register reads trigger reset of LPTIM

CMP

compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

Allowed values: 0x0-0xffff

ARR

autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

Allowed values: 0x0-0xffff

CNT

counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

OR

option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_
rw
Toggle fields

OR_

Bits 0-1: Option register bit 1.

Allowed values:
0: IO: Input 1 is connected to I/O
1: COMP1_OUT: Input 1 is connected to COMP1_OUT
2: COMP2_OUT: Input 1 is connected to COMP2_OUT
3: OR_COMP1_COMP2: Input 1 is connected to COMP1_OUT OR COMP2_OUT

RCR

repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

Allowed values: 0x0-0xff

LPUART

0x40008000: Universal synchronous asynchronous receiver transmitter

84/84 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: DEDT.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: DEAT.

Allowed values: 0x0-0x1f

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		STOP
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bit

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: Address of the LPUART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

Allowed values: 0x0-0xfffff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w
Toggle fields

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt and status register

Offset: 0x1c, size: 32, reset: 0x008000C0, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r 		CTSIF
r 		TXFNF
r 		TC
r 		RXFNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NE

Bit 2: NE.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXFNE

Bit 5: RXFNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXFNF

Bit 7: TXFNF.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c 		CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w1c 		TCCF
w1c 		IDLECF
w1c 		ORECF
w1c 		NCF
w1c 		FECF
w1c 		PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div6: /6
4: Div8: /8
5: Div10: /10
6: Div12: /12
7: Div16: /16
8: Div32: /32
9: Div64: /64
10: Div128: /128
11: Div256: /256

PKA

0x58002000: Public key accelerator

13/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 CLRFR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRIE
rw 		RAMERRIE
rw 		PROCENDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw 		START
rw 		EN
rw
Toggle fields

EN

Bit 0: PKA enable..

Allowed values:
0: Disabled: Disable PKA
1: Enabled: Enable PKA

START

Bit 1: start the operation.

Allowed values:
1: Start: Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM - This bit is always read as 0

MODE

Bits 8-13: PKA operation code.

Allowed values:
0: MontgomeryCompExp: Montgomery parameter computation then modular exponentiation
1: MontgomeryComp: Montgomery parameter computation only
2: MontgomeryExp: Modular exponentiation only (Montgomery parameter must be loaded first)
7: RSA: RSA CRT exponentiation
8: ModularInv: Modular inversion
9: ArithmeticAdd: Arithmetic addition
10: ArithmeticSub: Arithmetic subtraction
11: ArithmeticMul: Arithmetic multiplication
12: ArithmeticComp: Arithmetic comparison
13: ModularRed: Modular reduction
14: ModularAdd: Modular addition
15: ModularSub: Modular subtraction
16: ModularMul: Montgomery multiplication
32: MontgomeryCompScalar: Montgomery parameter computation then ECC scalar multiplication
34: MontgomeryScalar: ECC scalar multiplication only (Montgomery parameter must be loaded first)
36: ECDSASign: ECDSA sign
38: ECDSAVerif: ECDSA verification
40: Elliptic: Point on elliptic curve Fp check

PROCENDIE

Bit 17: PROCENDIE.

Allowed values:
0: Disabled: No interrupt is generated when PROCENDF flag is set in PKA_SR
1: Enabled: An interrupt is generated when PROCENDF flag is set in PKA_SR

RAMERRIE

Bit 19: RAM error interrupt enable.

Allowed values:
0: Disabled: No interrupt is generated when RAMERRF flag is set in PKA_SR
1: Enabled: An interrupt is generated when RAMERRF flag is set in PKA_SR

ADDRERRIE

Bit 20: Address error interrupt enable.

Allowed values:
0: Disabled: No interrupt is generated when ADDRERRF flag is set in PKA_SR
1: Enabled: An interrupt is generated when ADDRERRF flag is set in PKA_SR

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRF
r 		RAMERRF
r 		PROCENDF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BUSY

Bit 16: PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started..

Allowed values:
0: Idle: No operation in pgoress
1: Busy: Operation in progress

PROCENDF

Bit 17: PKA End of Operation flag.

Allowed values:
0: InProgress: Operation in progress
1: Completed: PKA operation is completed - set when BUSY is deasserted

RAMERRF

Bit 19: PKA RAM error flag.

Allowed values:
0: NoError: No error
1: Error: An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress)

ADDRERRF

Bit 20: Address error flag.

Allowed values:
0: NoError: No error
1: Error: Address access is out of range (unmapped address)

CLRFR

clear flag register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRFC
w 		RAMERRFC
w 		PROCENDFC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PROCENDFC

Bit 17: Clear PKA End of Operation flag.

Allowed values:
1: Clear: Clear PROCENDF flag

RAMERRFC

Bit 19: Clear PKA RAM error flag.

Allowed values:
1: Clear: Clear RAMERRF flag

ADDRERRFC

Bit 20: Clear Address error flag.

Allowed values:
1: Clear: Clear ADDRERRF flag

PWR

0x58000400: Power control

143/143 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc CR4
0x10 SR1
0x14 SR2
0x18 SCR
0x1c CR5
0x20 PUCRA
0x24 PDCRA
0x28 PUCRB
0x2c PDCRB
0x30 PUCRC
0x34 PDCRC
0x58 PUCRH
0x5c PDCRH
0x88 EXTSCR
0x90 SUBGHZSPICR
Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000200, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw 		VOS
rw 		DBP
rw 		FPDS
rw 		FPDR
rw 		SUBGHZSPINSSSEL
rw 		LPMS
rw
Toggle fields

LPMS

Bits 0-2: Low-power mode selection for CPU1.

Allowed values:
0: Stop0: Stop 0 mode
1: Stop1: Stop 1 mode
2: Stop2: Stop 2 mode
3: Standby: Standby mode
4: Shutdown: Shutdown mode

SUBGHZSPINSSSEL

Bit 3: sub-GHz SPI NSS source select.

Allowed values:
0: SUBGHZSPICR: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled)
1: LPTIM3: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)

FPDR

Bit 4: Flash memory power down mode during LPRun for CPU1.

Allowed values:
0: Idle: Flash memory in Idle mode when system is in LPRun mode
1: PowerDown: Flash memory in Power-down mode when system is in LPRun mode

FPDS

Bit 5: Flash memory power down mode during LPSleep for CPU1.

Allowed values:
0: Idle: Flash memory in Idle mode when system is in LPSleep mode
1: PowerDown: Flash memory in Power-down mode when system is in LPSleep mode

DBP

Bit 8: Disable backup domain write protection.

Allowed values:
0: Disabled: Access to RTC and backup registers disabled
1: Enabled: Access to RTC and backup registers enabled

VOS

Bits 9-10: Voltage scaling range selection.

Allowed values:
1: V1_2: 1.2 V (range 1)
2: V1_0: 1.0 V (range 2)

LPR

Bit 14: Low-power run.

Allowed values:
0: MainMode: Voltage regulator in Main mode in Low-power run mode
1: LowPowerMode: Voltage regulator in low-power mode in Low-power run mode

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVME3
rw 		PLS
rw 		PVDE
rw
Toggle fields

PVDE

Bit 0: Power voltage detector enable.

Allowed values:
0: Disabled: PVD Disabled
1: Enabled: PVD Enabled

PLS

Bits 1-3: Power voltage detector level selection..

Allowed values:
0: V2_0: 2.0V
1: V2_2: 2.2V
2: V2_4: 2.4V
3: V2_5: 2.5V
4: V2_6: 2.6V
5: V2_8: 2.8V
6: V2_9: 2.9V
7: External: External input analog voltage PVD_IN (compared internally to VREFINT)

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

Allowed values:
0: Disabled: PVM3 (VDDA monitoring versus 1.62 V threshold) disable
1: Enabled: PVM3 (VDDA monitoring versus 1.62 V threshold) enable

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00008000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIWUL
rw 		EWRFIRQ
rw 		EWRFBUSY
rw 		APC
rw 		RRS
rw 		EWPVD
rw 		EULPEN
rw 		EWUP3
rw 		EWUP2
rw 		EWUP1
rw
Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1 for CPU1.

Allowed values:
0: Disabled: WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode)

EWUP2

Bit 1: Enable Wakeup pin WKUP2 for CPU1.

Allowed values:
0: Disabled: WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode)

EWUP3

Bit 2: Enable Wakeup pin WKUP3 for CPU1.

Allowed values:
0: Disabled: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode)

EULPEN

Bit 7: Ultra-low-power enable.

Allowed values:
0: Disabled: Disable (the supply voltage is monitored continuously)
1: Enabled: Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically

EWPVD

Bit 8: Enable wakeup PVD for CPU1.

Allowed values:
0: Disabled: PVD not enabled by the sub-GHz radio active state
1: Enabled: PVD enabled while the sub-GHz radio is active

RRS

Bit 9: SRAM2 retention in Standby mode.

Allowed values:
0: PowerOff: SRAM2 powered off in Standby mode (SRAM2 content lost)
1: OnLPR: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)

APC

Bit 10: Apply pull-up and pull-down configuration from CPU1.

Allowed values:
0: Disabled: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied
1: Enabled: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os

EWRFBUSY

Bit 11: Enable Radio BUSY Wakeup from Standby for CPU1.

Allowed values:
0: Disabled: Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU1 when a rising or a falling edge occurs
1: Enabled: Radio Busy is enabled and triggers a wakeup from Standby event to CPU1 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4

EWRFIRQ

Bit 13: akeup for CPU1.

Allowed values:
0: Disabled: Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU1.
1: Enabled: Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU1.

EIWUL

Bit 15: Enable internal wakeup line for CPU1.

Allowed values:
0: Disabled: Internal wakeup line interrupt to CPU1 disabled
1: Enabled: Internal wakeup line interrupt to CPU1 enabled

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRFBUSYP
rw 		VBRS
rw 		VBE
rw 		WP3
rw 		WP2
rw 		WP1
rw
Toggle fields

WP1

Bit 0: Wakeup pin WKUP1 polarity.

Allowed values:
0: RisingEdge: Detection on high level (rising edge)
1: FallingEdge: Detection on low level (falling edge)

WP2

Bit 1: Wakeup pin WKUP2 polarity.

Allowed values:
0: RisingEdge: Detection on high level (rising edge)
1: FallingEdge: Detection on low level (falling edge)

WP3

Bit 2: Wakeup pin WKUP3 polarity.

Allowed values:
0: RisingEdge: Detection on high level (rising edge)
1: FallingEdge: Detection on low level (falling edge)

VBE

Bit 8: VBAT battery charging enable.

Allowed values:
0: Disabled: VBAT battery charging disabled
1: Enabled: VBAT battery charging enabled

VBRS

Bit 9: VBAT battery charging resistor selection.

Allowed values:
0: R5k: VBAT charging through a 5 kΩ resistor
1: R1_5k: VBAT charging through a 1.5 kΩ resistor

WRFBUSYP

Bit 11: Wakeup Radio BUSY polarity.

Allowed values:
0: RisingEdge: Detection on high level (rising edge)
1: FallingEdge: Detection on low level (falling edge)

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUFI
r 		WRFBUSYF
r 		WPVDF
r 		WUF3
r 		WUF2
r 		WUF1
r
Toggle fields

WUF1

Bit 0: Wakeup flag 1.

Allowed values:
0: Clear: No wakeup event detected on WKUP1
1: Wakeup: Wakeup event detected on WKUP1

WUF2

Bit 1: Wakeup flag 2.

Allowed values:
0: Clear: No wakeup event detected on WKUP2
1: Wakeup: Wakeup event detected on WKUP2

WUF3

Bit 2: Wakeup flag 3.

Allowed values:
0: Clear: No wakeup event detected on WKUP3
1: Wakeup: Wakeup event detected on WKUP3

WPVDF

Bit 8: Wakeup PVD flag.

Allowed values:
0: Clear: No wakeup event detected on PVD
1: Wakeup: Wakeup event detected on PVD

WRFBUSYF

Bit 11: Radio BUSY wakeup flag.

Allowed values:
0: Clear: No wakeup event detected on radio busy
1: Wakeup: Wakeup event detected on radio busy

WUFI

Bit 15: Internal wakeup interrupt flag.

Allowed values:
0: Clear: All internal wakeup sources are cleared
1: Wakeup: wakeup is detected on the internal wakeup line

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO3
r 		PVDO
r 		VOSF
r 		REGLPF
r 		REGLPS
r 		FLASHRDY
r 		REGMRS
r 		RFEOLF
r 		LDORDY
r 		SMPSRDY
r 		RFBUSYMS
r 		RFBUSYS
r
Toggle fields

RFBUSYS

Bit 1: Radio BUSY signal status.

Allowed values:
0: NotBusy: radio busy signal low (not busy)
1: Busy: radio busy signal high (busy)

RFBUSYMS

Bit 2: Radio BUSY masked signal status.

Allowed values:
0: NotBusy: radio busy masked signal low (not busy)
1: Busy: radio busy masked signal high (busy)

SMPSRDY

Bit 3: SMPS ready flag.

Allowed values:
0: NotReady: SMPS step-down converter not ready or off
1: Ready: SMPS step-down converter ready

LDORDY

Bit 4: LDO ready flag.

Allowed values:
0: NotReady: LDO not ready or off
1: Ready: LDO ready

RFEOLF

Bit 5: Radio end of life flag.

Allowed values:
0: Above: Supply voltage above radio end-of-life operating low level
1: Below: Supply voltage below radio end-of-life operating low level

REGMRS

Bit 6: regulator2 low power flag.

Allowed values:
0: V_DD: Main regulator supplied directly from VDD
1: LDO_SMPS: Main regulator supplied through LDO or SMPS

FLASHRDY

Bit 7: Flash ready.

Allowed values:
0: NotReady: Flash memory not ready to be accessed
1: Ready: Flash memory ready to be accessed

REGLPS

Bit 8: regulator1 started.

Allowed values:
0: NotReady: LPR not ready
1: Ready: LPR ready

REGLPF

Bit 9: regulator1 low power flag.

Allowed values:
0: Main: Main regulator (MR) ready and used
1: LowPower: Low-power regulator (LPR) used

VOSF

Bit 10: Voltage scaling flag.

Allowed values:
0: Ready: Regulator ready in the selected voltage range
1: Change: Regulator output voltage changed to the required voltage level

PVDO

Bit 11: Power voltage detector output.

Allowed values:
0: Above: VDD or voltage level on PVD_IN above the selected PVD threshold
1: Below: VDD or voltage level on PVD_IN below the selected PVD threshold

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

Allowed values:
0: Above: VDDA voltage above PVM3 threshold (around 1.62 V)
1: Below: VDDA voltage below PVM3 threshold (around 1.62 V)

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CWRFBUSYF
w 		CWPVDF
w 		CWUF3
w 		CWUF2
w 		CWUF1
w
Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1.

Allowed values:
1: Clear: Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0.

CWUF2

Bit 1: Clear wakeup flag 2.

Allowed values:
1: Clear: Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0.

CWUF3

Bit 2: Clear wakeup flag 3.

Allowed values:
1: Clear: Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0.

CWPVDF

Bit 8: Clear wakeup PVD interrupt flag.

Allowed values:
1: Clear: Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0.

CWRFBUSYF

Bit 11: Clear wakeup Radio BUSY flag.

Allowed values:
1: Clear: Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0.

CR5

Power control register 5

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSEN
rw 		RFEOLEN
rw
Toggle fields

RFEOLEN

Bit 14: Enable Radio End Of Life detector enabled.

Allowed values:
0: Disabled: Radio end-of-life detector disabled
1: Enabled: Radio end-of-life detector enabled

SMPSEN

Bit 15: Enable SMPS Step Down converter SMPS mode enabled..

Allowed values:
0: Disabled: SMPS step-down converter SMPS mode disabled (LDO mode enabled)
1: Enabled: SMPS step-down converter SMPS mode enabled

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: PU0.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU1

Bit 1: PU1.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU2

Bit 2: PU2.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU3

Bit 3: PU3.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU4

Bit 4: PU4.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU5

Bit 5: PU5.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU6

Bit 6: PU6.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU7

Bit 7: PU7.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU8

Bit 8: PU8.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU9

Bit 9: PU9.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU10

Bit 10: PU10.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU11

Bit 11: PU11.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU12

Bit 12: PU12.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU13

Bit 13: Port PA[y] pull-up bit y (y=0 to 13).

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU14

Bit 14: PU14.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PU15

Bit 15: Port PA15 pull-up.

Allowed values:
0: Disabled: Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: PD0.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD1

Bit 1: PD1.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD2

Bit 2: PD2.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD3

Bit 3: PD3.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD4

Bit 4: PD4.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD5

Bit 5: PD5.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD6

Bit 6: PD6.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD7

Bit 7: PD7.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD8

Bit 8: PD8.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD9

Bit 9: PD9.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD10

Bit 10: PD10.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD11

Bit 11: PD11.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD12

Bit 12: Port PA[y] pull-down (y=0 to 12).

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD13

Bit 13: PD13.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD14

Bit 14: ull-down.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD15

Bit 15: PD15.

Allowed values:
0: Disabled: Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: PU0.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU1

Bit 1: PU1.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU2

Bit 2: PU2.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU3

Bit 3: PU3.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU4

Bit 4: PU4.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU5

Bit 5: PU5.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU6

Bit 6: PU6.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU7

Bit 7: PU7.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU8

Bit 8: PU8.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU9

Bit 9: PU9.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU10

Bit 10: PU10.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU11

Bit 11: PU11.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU12

Bit 12: PU12.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU13

Bit 13: PU13.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU14

Bit 14: PU14.

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PU15

Bit 15: Port PB[y] pull-up (y=0 to 15).

Allowed values:
0: Disabled: Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: PD0.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD1

Bit 1: PD1.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD2

Bit 2: PD2.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD3

Bit 3: Port PB[y] pull-down (y=0 to 3).

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD4

Bit 4: PD4.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD5

Bit 5: PD5.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD6

Bit 6: PD6.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD7

Bit 7: PD7.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD8

Bit 8: PD8.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD9

Bit 9: PD9.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD10

Bit 10: PD10.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD11

Bit 11: PD11.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD12

Bit 12: PD12.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD13

Bit 13: PD13.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD14

Bit 14: PD14.

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD15

Bit 15: Port PB[y] pull-down (y=5 to 15).

Allowed values:
0: Disabled: Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: PU0.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU1

Bit 1: PU1.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU2

Bit 2: PU2.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU3

Bit 3: PU3.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU4

Bit 4: PU4.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU5

Bit 5: PU5.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU6

Bit 6: PU6.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU13

Bit 13: PU13.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU14

Bit 14: PU14.

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PU15

Bit 15: Port PC[y] pull-up (y=13 to 15).

Allowed values:
0: Disabled: Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: PD0.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD1

Bit 1: PD1.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD2

Bit 2: PD2.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD3

Bit 3: PD3.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD4

Bit 4: PD4.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD5

Bit 5: PD5.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD6

Bit 6: PD6.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD13

Bit 13: PD13.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD14

Bit 14: PD14.

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PD15

Bit 15: Port PC[y] pull-down (y=13 to 15).

Allowed values:
0: Disabled: Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU3
rw
Toggle fields

PU3

Bit 3: pull-up.

Allowed values:
0: Disabled: Disable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PH[y] bit is also set

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD3
rw
Toggle fields

PD3

Bit 3: pull-down.

Allowed values:
0: Disabled: Disable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)
1: Enabled: Enable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)

EXTSCR

Power extended status and status clear register

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1DS
r 		C1STOPF
r 		C1STOP2F
r 		C1SBF
r 		C1CSSF
w
Toggle fields

C1CSSF

Bit 0: Clear CPU1 Stop Standby flags.

Allowed values:
1: Clear: Setting this bit clears the C1STOPF and C1SBF bits

C1SBF

Bit 8: System Standby flag for CPU1. (no core states retained).

Allowed values:
0: NoStandby: System has not been in Standby mode
1: Standby: System has been in Standby mode

C1STOP2F

Bit 9: System Stop2 flag for CPU1. (partial core states retained).

Allowed values:
0: NoStop: System has not been in Stop 2 mode
1: Stop: System has been in Stop 2 mode

C1STOPF

Bit 10: System Stop0, 1 flag for CPU1. (All core states retained).

Allowed values:
0: NoStop: System has not been in Stop 0 or 1 mode
1: Stop: System has been in Stop 0 or 1 mode

C1DS

Bit 14: CPU1 deepsleep mode.

Allowed values:
0: RunningOrSleep: CPU is running or in sleep
1: DeepSleep: CPU is in Deep-Sleep

SUBGHZSPICR

Power SPI3 control register

Offset: 0x90, size: 32, reset: 0x00008000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSS
rw
Toggle fields

NSS

Bit 15: sub-GHz SPI NSS control.

Allowed values:
0: Low: Sub-GHz SPI NSS signal at level low
1: High: Sub-GHz SPI NSS signal is at level high

RCC

0x58000000: Reset and clock control

176/204 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc PLLCFGR
0x18 CIER
0x1c CIFR
0x20 CICR
0x28 AHB1RSTR
0x2c AHB2RSTR
0x30 AHB3RSTR
0x38 APB1RSTR1
0x3c APB1RSTR2
0x40 APB2RSTR
0x44 APB3RSTR
0x48 AHB1ENR
0x4c AHB2ENR
0x50 AHB3ENR
0x58 APB1ENR1
0x5c APB1ENR2
0x60 APB2ENR
0x64 APB3ENR
0x68 AHB1SMENR
0x6c AHB2SMENR
0x70 AHB3SMENR
0x78 APB1SMENR1
0x7c APB1SMENR2
0x80 APB2SMENR
0x84 APB3SMENR
0x88 CCIPR
0x90 BDCR
0x94 CSR
0x108 EXTCFGR
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000061, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLRDY
r 		PLLON
rw 		HSEBYPPWR
rw 		HSEPRE
rw 		CSSON
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIKERDY
r 		HSIASFS
rw 		HSIRDY
r 		HSIKERON
rw 		HSION
rw 		MSIRANGE
rw 		MSIRGSEL
rw 		MSIPLLEN
rw 		MSIRDY
r 		MSION
rw
Toggle fields

MSION

Bit 0: MSI clock enable.

Allowed values:
0: Disabled: MSI oscillator off
1: Enabled: MSI oscillator on

MSIRDY

Bit 1: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready).

Allowed values:
0: NotReady: MSI oscillator not ready
1: Ready: MSI oscillator ready

MSIPLLEN

Bit 2: MSI clock PLL enable.

Allowed values:
0: Off: MSI PLL Off
1: On: MSI PLL On

MSIRGSEL

Bit 3: MSI range control selection.

Allowed values:
0: CSR: MSI frequency range defined by MSISRANGE[3:0] in the RCC_CSR register
1: CR: MSI frequency range defined by MSIRANGE[3:0] in the RCC_CR register

MSIRANGE

Bits 4-7: MSI clock ranges.

Allowed values:
0: Range100K: range 0 around 100 kHz
1: Range200K: range 1 around 200 kHz
2: Range400K: range 2 around 400 kHz
3: Range800K: range 3 around 800 kHz
4: Range1M: range 4 around 1 MHz
5: Range2M: range 5 around 2 MHz
6: Range4M: range 6 around 4 MHz (reset value)
7: Range8M: range 7 around 8 MHz
8: Range16M: range 8 around 16 MHz
9: Range24M: range 9 around 24 MHz
10: Range32M: range 10 around 32 MHz
11: Range48M: range 11 around 48 MHz

HSION

Bit 8: HSI16 clock enable.

Allowed values:
0: Disabled: HSI16 oscillator off
1: Enabled: HSI16 oscillator on

HSIKERON

Bit 9: HSI16 always enable for peripheral kernel clocks..

Allowed values:
0: NotForced: No effect on HSI16 oscillator
1: Forced: HSI16 oscillator forced on even in Stop modes

HSIRDY

Bit 10: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready).

Allowed values:
0: NotReady: HSI16 oscillator not ready
1: Ready: HSI16 oscillator ready

HSIASFS

Bit 11: HSI16 automatic start from Stop.

Allowed values:
0: Disabled: HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock
1: Enabled: HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock

HSIKERDY

Bit 12: HSI16 kernel clock ready flag for peripherals requests..

Allowed values:
0: NotReady: HSI16 oscillator not ready
1: Ready: HSI16 oscillator ready

HSEON

Bit 16: HSE32 clock enable.

Allowed values:
0: Disabled: HSE32 oscillator for CPU disabled
1: Enabled: HSE32 oscillator for CPU enabled

HSERDY

Bit 17: HSE32 clock ready flag.

Allowed values:
0: NotReady: HSE32 oscillator not ready
1: Ready: HSE32 oscillator ready

CSSON

Bit 19: HSE32 Clock security system enable.

Allowed values:
0: Disabled: HSE32 CSS off
1: Enabled: HSE32 CSS on if the HSE32 oscillator is stable and off if not

HSEPRE

Bit 20: HSE32 sysclk prescaler.

Allowed values:
0: Div1: SYSCLK not divided (HSE32)
1: Div2: SYSCLK divided by two (HSE32/2)

HSEBYPPWR

Bit 21: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO..

Allowed values:
0: PB0: PB0 selected
1: VDDTCXO: VDDTCXO selected

PLLON

Bit 24: Main PLL enable.

Allowed values:
0: Off: Main PLL Off
1: On: Main PLL On

PLLRDY

Bit 25: Main PLL clock ready flag.

Allowed values:
0: Unlocked: PLL unlocked
1: Locked: PLL Locked

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw 		HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw 		MSICAL
r
Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

Allowed values: 0x0-0xff

MSITRIM

Bits 8-15: MSI clock trimming.

Allowed values: 0x0-0xff

HSICAL

Bits 16-23: HSI16 clock calibration.

Allowed values: 0x0-0xff

HSITRIM

Bits 24-30: HSI16 clock trimming.

Allowed values: 0x0-0x3f

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00070000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
rw 		MCOSEL
rw 		PPRE2F
r 		PPRE1F
r 		HPREF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw 		PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI16: HSI16 oscillator used as system clock
2: HSE32: HSE32 oscillator used as system clock
3: PLLR: PLLRCLK used as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI16: HSI16 oscillator used as system clock
2: HSE32: HSE32 oscillator used as system clock
3: PLLR: PLLRCLK used as system clock

HPRE

Bits 4-7: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.).

Allowed values:
1: Div3: SYSCLK divided by 3
2: Div5: SYSCLK divided by 5
5: Div6: SYSCLK divided by 6
6: Div10: SYSCLK divided by 10
7: Div32: SYSCLK divided by 32
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

PPRE1

Bits 8-10: PCLK1 low-speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 11-13: PCLK2 high-speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

Allowed values:
0: MSI: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI16: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock

HPREF

Bit 16: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1).

Allowed values:
0: NotApplied: HCLK1 prescaler value not yet applied
1: Applied: HCLK1 prescaler value applied

PPRE1F

Bit 17: PCLK1 prescaler flag (APB1).

Allowed values:
0: NotApplied: PCLK1 prescaler value not yet applied
1: Applied: PCLK1 prescaler value applied

PPRE2F

Bit 18: PCLK2 prescaler flag (APB2).

Allowed values:
0: NotApplied: PCLK2 prescaler value not yet applied
1: Applied: PCLK2 prescaler value applied

MCOSEL

Bits 24-27: Microcontroller clock output.

Allowed values:
0: NoClock: No clock
1: SYSCLK: SYSCLK clock selected
2: MSI: MSI oscillator clock selected
3: HSI16: HSI16 oscillator clock selected
4: HSE32: HSE32 oscillator clock selected
5: PLLR: Main PLLRCLK clock selected
6: LSI: LSI oscillator clock selected
8: LSE: LSE oscillator clock selected
13: PLLP: Main PLLPCLK clock selected
14: PLLQ: Main PLLQCLK clock selected

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: No division
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16

PLLCFGR

PLL configuration register

Offset: 0xc, size: 32, reset: 0x22040100, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLR
rw 		PLLREN
rw 		PLLQ
rw 		PLLQEN
rw 		PLLP
rw 		PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw 		PLLM
rw 		PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: Main PLL entry clock source.

Allowed values:
0: NoClock: No clock sent to PLL
1: MSI: MSI clock selected as PLL clock entry
2: HSI16: HSI16 clock selected as PLL clock entry
3: HSE32: HSE32 clock selected as PLL clock entry

PLLM

Bits 4-6: Division factor for the main PLL input clock.

Allowed values:
0: Div1: VCO input = PLL input / PLLM
1: Div2: VCO input = PLL input / PLLM
2: Div3: VCO input = PLL input / PLLM
3: Div4: VCO input = PLL input / PLLM
4: Div5: VCO input = PLL input / PLLM
5: Div6: VCO input = PLL input / PLLM
6: Div7: VCO input = PLL input / PLLM
7: Div8: VCO input = PLL input / PLLM

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

Allowed values: 0x6-0x7f

PLLPEN

Bit 16: Main PLL PLLPCLK output enable.

Allowed values:
0: Disabled: PLLCLK output disabled
1: Enabled: PLLCLK output enabled

PLLP

Bits 17-21: Main PLL division factor for PLLPCLK..

Allowed values:
1: Div2: PLL = VCO/(N+1)
2: Div3: PLL = VCO/(N+1)
3: Div4: PLL = VCO/(N+1)
4: Div5: PLL = VCO/(N+1)
5: Div6: PLL = VCO/(N+1)
6: Div7: PLL = VCO/(N+1)
7: Div8: PLL = VCO/(N+1)
8: Div9: PLL = VCO/(N+1)
9: Div10: PLL = VCO/(N+1)
10: Div11: PLL = VCO/(N+1)
11: Div12: PLL = VCO/(N+1)
12: Div13: PLL = VCO/(N+1)
13: Div14: PLL = VCO/(N+1)
14: Div15: PLL = VCO/(N+1)
15: Div16: PLL = VCO/(N+1)
16: Div17: PLL = VCO/(N+1)
17: Div18: PLL = VCO/(N+1)
18: Div19: PLL = VCO/(N+1)
19: Div20: PLL = VCO/(N+1)
20: Div21: PLL = VCO/(N+1)
21: Div22: PLL = VCO/(N+1)
22: Div23: PLL = VCO/(N+1)
23: Div24: PLL = VCO/(N+1)
24: Div25: PLL = VCO/(N+1)
25: Div26: PLL = VCO/(N+1)
26: Div27: PLL = VCO/(N+1)
27: Div28: PLL = VCO/(N+1)
28: Div29: PLL = VCO/(N+1)
29: Div30: PLL = VCO/(N+1)
30: Div31: PLL = VCO/(N+1)
31: Div32: PLL = VCO/(N+1)

PLLQEN

Bit 24: Main PLL PLLQCLK output enable.

Allowed values:
0: Disabled: PLLCLK output disabled
1: Enabled: PLLCLK output enabled

PLLQ

Bits 25-27: Main PLL division factor for PLLQCLK.

Allowed values:
1: Div2: PLL = VCO/(N+1)
2: Div3: PLL = VCO/(N+1)
3: Div4: PLL = VCO/(N+1)
4: Div5: PLL = VCO/(N+1)
5: Div6: PLL = VCO/(N+1)
6: Div7: PLL = VCO/(N+1)
7: Div8: PLL = VCO/(N+1)

PLLREN

Bit 28: Main PLL PLLRCLK output enable.

Allowed values:
0: Disabled: PLLCLK output disabled
1: Enabled: PLLCLK output enabled

PLLR

Bits 29-31: Main PLL division factor for PLLRCLK.

Allowed values:
1: Div2: PLL = VCO/(N+1)
2: Div3: PLL = VCO/(N+1)
3: Div4: PLL = VCO/(N+1)
4: Div5: PLL = VCO/(N+1)
5: Div6: PLL = VCO/(N+1)
6: Div7: PLL = VCO/(N+1)
7: Div8: PLL = VCO/(N+1)

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		MSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 1: LSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MSIRDYIE

Bit 2: MSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 3: HSI16 ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 4: HSE32 ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 5: PLL ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSF
r 		CSSF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		MSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

LSERDYF

Bit 1: LSE ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

MSIRDYF

Bit 2: MSI ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

HSIRDYF

Bit 3: HSI16 ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

HSERDYF

Bit 4: HSE32 ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

PLLRDYF

Bit 5: PLL ready interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

CSSF

Bit 8: HSE32 Clock security system interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

Allowed values:
0: NotInterrupted: Not interrupted
1: Interrupted: Interrupted

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSC
w 		CSSC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		MSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 1: LSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

MSIRDYC

Bit 2: MSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 3: HSI16 ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 4: HSE32 ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLRDYC

Bit 5: PLL ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

CSSC

Bit 8: HSE32 Clock security system interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		DMAMUX1RST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

DMA2RST

Bit 1: DMA2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

DMAMUX1RST

Bit 2: DMAMUX1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

CRCRST

Bit 12: CRC reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHRST
rw 		HSEMRST
rw 		RNGRST
rw 		AESRST
rw 		PKARST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PKARST

Bit 16: PKARST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

AESRST

Bit 17: AESRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

RNGRST

Bit 18: RNGRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

HSEMRST

Bit 19: HSEMRST.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

FLASHRST

Bit 25: Flash interface reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw 		DACRST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

SPI2S2RST

Bit 14: SPI2S2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

USART2RST

Bit 17: USART2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

DACRST

Bit 29: DAC reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3RST
rw 		LPTIM2RST
rw 		LPUART1RST
rw
Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

LPTIM2RST

Bit 5: Low-power timer 2 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

LPTIM3RST

Bit 6: Low-power timer 3 reset.

Allowed values:
0: NoReset: No effect
1: Reset: Reset peripheral

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17RST
rw 		TIM16RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		SPI1RST
rw 		TIM1RST
rw 		ADCRST
rw
Toggle fields

ADCRST

Bit 9: ADC reset.

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

USART1RST

Bit 14: USART1 reset.

TIM16RST

Bit 17: TIM16 timer reset.

TIM17RST

Bit 18: TIM17 timer reset.

APB3RSTR

APB3 peripheral reset register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPIRST
rw
Toggle fields

SUBGHZSPIRST

Bit 0: Sub-GHz radio SPI reset.

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		DMAMUX1EN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: CPU1 DMA1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DMA2EN

Bit 1: CPU1 DMA2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DMAMUX1EN

Bit 2: CPU1 DMAMUX1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CRCEN

Bit 12: CPU1 CRC clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: CPU1 IO port A clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOBEN

Bit 1: CPU1 IO port B clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOCEN

Bit 2: CPU1 IO port C clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOHEN

Bit 7: CPU1 IO port H clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x02080000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHEN
rw 		HSEMEN
rw 		RNGEN
rw 		AESEN
rw 		PKAEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PKAEN

Bit 16: PKAEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AESEN

Bit 17: AESEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

RNGEN

Bit 18: RNGEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

HSEMEN

Bit 19: HSEMEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

FLASHEN

Bit 25: CPU1 Flash interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1ENR1

APB1 peripheral clock enable register 1

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw 		DAC1EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2EN
rw 		WWDGEN
rw 		RTCAPBEN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: CPU1 TIM2 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

RTCAPBEN

Bit 10: CPU1 RTC APB clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

WWDGEN

Bit 11: CPU1 Window watchdog clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI2S2EN

Bit 14: CPU1 SPI2S2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART2EN

Bit 17: CPU1 USART2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C1EN

Bit 21: CPU1 I2C1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C2EN

Bit 22: CPU1 I2C2 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C3EN

Bit 23: CPU1 I2C3 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DAC1EN

Bit 29: CPU1 DAC1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LPTIM1EN

Bit 31: CPU1 Low power timer 1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3EN
rw 		LPTIM2EN
rw 		LPUART1EN
rw
Toggle fields

LPUART1EN

Bit 0: CPU1 Low power UART 1 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LPTIM2EN

Bit 5: CPU1 Low power timer 2 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LPTIM3EN

Bit 6: CPU1 Low power timer 3 clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB2ENR

APB2 peripheral clock enable register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17EN
rw 		TIM16EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		SPI1EN
rw 		TIM1EN
rw 		ADCEN
rw
Toggle fields

ADCEN

Bit 9: CPU1 ADC clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM1EN

Bit 11: CPU1 TIM1 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI1EN

Bit 12: CPU1 SPI1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART1EN

Bit 14: CPU1 USART1clocks enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM16EN

Bit 17: CPU1 TIM16 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM17EN

Bit 18: CPU1 TIM17 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB3ENR

APB3 peripheral clock enable register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPIEN
rw
Toggle fields

SUBGHZSPIEN

Bit 0: sub-GHz radio SPI clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHB1SMENR

AHB1 peripheral clocks enable in Sleep modes register

Offset: 0x68, size: 32, reset: 0x00001007, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw 		DMAMUX1SMEN
rw 		DMA2SMEN
rw 		DMA1SMEN
rw
Toggle fields

DMA1SMEN

Bit 0: DMA1 clock enable during CPU1 CSleep mode..

DMA2SMEN

Bit 1: DMA2 clock enable during CPU1 CSleep mode.

DMAMUX1SMEN

Bit 2: DMAMUX1 clock enable during CPU1 CSleep mode..

CRCSMEN

Bit 12: CRC clock enable during CPU1 CSleep mode..

AHB2SMENR

AHB2 peripheral clocks enable in Sleep modes register

Offset: 0x6c, size: 32, reset: 0x00000087, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOHSMEN
rw 		GPIOCSMEN
rw 		GPIOBSMEN
rw 		GPIOASMEN
rw
Toggle fields

GPIOASMEN

Bit 0: IO port A clock enable during CPU1 CSleep mode..

GPIOBSMEN

Bit 1: IO port B clock enable during CPU1 CSleep mode..

GPIOCSMEN

Bit 2: IO port C clock enable during CPU1 CSleep mode..

GPIOHSMEN

Bit 7: IO port H clock enable during CPU1 CSleep mode..

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x03870000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASHSMEN
rw 		SRAM2SMEN
rw 		SRAM1SMEN
rw 		RNGSMEN
rw 		AESSMEN
rw 		PKASMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PKASMEN

Bit 16: PKA accelerator clock enable during CPU1 CSleep mode..

AESSMEN

Bit 17: AES accelerator clock enable during CPU1 CSleep mode..

RNGSMEN

Bit 18: True RNG clocks enable during CPU1 Csleep and CStop modes.

SRAM1SMEN

Bit 23: SRAM1 interface clock enable during CPU1 CSleep mode..

SRAM2SMEN

Bit 24: SRAM2 memory interface clock enable during CPU1 CSleep mode.

FLASHSMEN

Bit 25: Flash interface clock enable during CPU1 CSleep mode..

APB1SMENR1

APB1 peripheral clocks enable in Sleep mode register 1

Offset: 0x78, size: 32, reset: 0xA0E24C01, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw 		DACSMEN
rw 		I2C3SMEN
rw 		I2C2SMEN
rw 		I2C1SMEN
rw 		USART2SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S2SMEN
rw 		WWDGSMEN
rw 		RTCAPBSMEN
rw 		TIM2SMEN
rw
Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

RTCAPBSMEN

Bit 10: RTC bus clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

WWDGSMEN

Bit 11: Window watchdog clocks enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI2S2SMEN

Bit 14: SPI2S2 clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART2SMEN

Bit 17: USART2 clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C1SMEN

Bit 21: I2C1 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C2SMEN

Bit 22: I2C2 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C3SMEN

Bit 23: I2C3 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DACSMEN

Bit 29: DAC clock enable during CPU1 CSleep mode..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LPTIM1SMEN

Bit 31: Low power timer 1 clock enable during CPU1 Csleep and CStop mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1SMENR2

APB1 peripheral clocks enable in Sleep mode register 2

Offset: 0x7c, size: 32, reset: 0x00000061, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3SMEN
rw 		LPTIM2SMEN
rw 		LPUART1SMEN
rw
Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clock enable during CPU1 Csleep and CStop modes..

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LPTIM2SMEN

Bit 5: Low power timer 2 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LPTIM3SMEN

Bit 6: Low power timer 3 clock enable during CPU1 Csleep and CStop modes.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB2SMENR

APB2 peripheral clocks enable in Sleep mode register

Offset: 0x80, size: 32, reset: 0x00065A00, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17SMEN
rw 		TIM16SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw 		SPI1SMEN
rw 		TIM1SMEN
rw 		ADCSMEN
rw
Toggle fields

ADCSMEN

Bit 9: ADC clocks enable during CPU1 Csleep and CStop modes.

TIM1SMEN

Bit 11: TIM1 timer clock enable during CPU1 CSleep mode..

SPI1SMEN

Bit 12: SPI1 clock enable during CPU1 CSleep mode..

USART1SMEN

Bit 14: USART1 clock enable during CPU1 Csleep and CStop modes..

TIM16SMEN

Bit 17: TIM16 timer clock enable during CPU1 CSleep mode..

TIM17SMEN

Bit 18: TIM17 timer clock enable during CPU1 CSleep mode..

APB3SMENR

APB3 peripheral clock enable in Sleep mode register

Offset: 0x84, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBGHZSPISMEN
rw
Toggle fields

SUBGHZSPISMEN

Bit 0: Sub-GHz radio SPI clock enable during Sleep and Stop modes.

CCIPR

Peripherals independent clock configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNGSEL
rw 		ADCSEL
rw 		LPTIM3SEL
rw 		LPTIM2SEL
rw 		LPTIM1SEL
rw 		I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw 		I2C1SEL
rw 		LPUART1SEL
rw 		SPI2S2SEL
rw 		USART2SEL
rw 		USART1SEL
rw
Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

USART2SEL

Bits 2-3: USART2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

SPI2S2SEL

Bits 8-9: SPI2S2 I2S clock source selection.

Allowed values:
1: PLLQ: PLLQ clock selected
2: HSI16: HSI16 clock selected
3: I2S: External input I2S_CKIN selected

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

I2C1SEL

Bits 12-13: I2C1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

I2C2SEL

Bits 14-15: I2C2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

I2C3SEL

Bits 16-17: I2C3 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

LPTIM3SEL

Bits 22-23: Low power timer 3 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

ADCSEL

Bits 28-29: ADC clock source selection.

Allowed values:
0: NoClock: No clock selected
1: HSI16: HSI16 clock selected
2: PLLP: PLLP clock selected
3: SYSCLK: SYSCLK clock selected

RNGSEL

Bits 30-31: RNG clock source selection.

Allowed values:
0: PLLQ: PLLQ clock selected
1: LSI: LSI clock selected
2: LSE: LSE clock selected
3: MSI: MSI clock selected

BDCR

Backup domain control register

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw 		LSCOEN
rw 		BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		LSESYSRDY
r 		RTCSEL
rw 		LSESYSEN
rw 		LSECSSD
r 		LSECSSON
rw 		LSEDRV
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enable.

Allowed values:
0: Off: LSE oscillator off
1: On: LSE oscillator on

LSERDY

Bit 1: LSE oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: LSE oscillator bypass.

Allowed values:
0: Disabled: LSE oscillator not bypassed
1: Enabled: LSE oscillator bypassed

LSEDRV

Bits 3-4: LSE oscillator drive capability.

Allowed values:
0: Low: Xtal mode lower driving capability
1: MedLow: Xtal mode medium-low driving capability
2: MedHigh: Xtal mode medium-high driving capability
3: High: Xtal mode higher driving capability

LSECSSON

Bit 5: CSS on LSE enable.

Allowed values:
0: Disabled: CSS on LSE disabled
1: Enabled: CSS on LSE enabled

LSECSSD

Bit 6: CSS on LSE failure Detection.

Allowed values:
0: NoFailure: No failure detected on LSE
1: Failure: Failure detected on LSE

LSESYSEN

Bit 7: LSE system clock enable.

Allowed values:
0: Disabled: LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode
1: Enabled: LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock selected
2: LSI: LSI oscillator clock selected
3: HSE32: HSE32 oscillator clock divided by 32 selected

LSESYSRDY

Bit 11: LSE system clock ready.

Allowed values:
0: NotReady: LSE system clock not ready
1: Ready: LSE system clock ready

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC kernel clock disabled
1: Enabled: RTC kernel clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: NotActive: Reset not activated
1: Reset: Entire Backup domain reset

LSCOEN

Bit 24: Low speed clock output enable.

Allowed values:
0: Disabled: LSCO disabled
1: Enabled: LSCO enabled

LSCOSEL

Bit 25: Low speed clock output selection.

Allowed values:
0: LSI: LSI clock selected
1: LSE: LSE clock selected

CSR

Control/status register

Offset: 0x94, size: 32, reset: 0x0C01C600, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
r 		WWDGRSTF
r 		IWDGRSTF
r 		SFTRSTF
r 		BORRSTF
r 		PINRSTF
r 		OBLRSTF
r 		RFILARSTF
r 		RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFRST
rw 		RFRSTF
r 		MSISRANGE
rw 		LSIPRE
rw 		LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable.

Allowed values:
0: Off: LSI oscillator off
1: On: LSI oscillator on

LSIRDY

Bit 1: LSI oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

LSIPRE

Bit 4: LSI frequency prescaler.

Allowed values:
0: Div1: LSI clock not divided
1: Div128: LSI clock divided by 128

MSISRANGE

Bits 8-11: MSI clock ranges.

Allowed values:
4: f_1MHz: Range 4 around 1 MHz
5: f_2MHz: Range 5 around 2 MHz
6: f_4MHz: Range 6 around 4 MHz (reset value)
7: f_8MHz: Range 7 around 8 MHz

RFRSTF

Bit 14: Radio in reset status flag.

Allowed values:
0: NoReset: Sub-GHz radio out of reset
1: Reset: Sub-GHz radio in reset

RFRST

Bit 15: Radio reset.

Allowed values:
0: Removed: Sub-GHz radio software reset removed
1: Reset: Sub-GHz radio software reset active

RMVF

Bit 23: Remove reset flag.

Allowed values:
0: NoEffect: No effect
1: Clear: Reset flags reset

RFILARSTF

Bit 24: Radio illegal access flag.

Allowed values:
0: NoIllegalCommand: No SUBGHZ radio illegal command occurred
1: IllegalCommand: SUBGHZ radio illegal command occurred

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

PINRSTF

Bit 26: Pin reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

BORRSTF

Bit 27: BOR flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

LPWRRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset occurred
1: Reset: Reset occurred

EXTCFGR

Extended clock recovery register

Offset: 0x108, size: 32, reset: 0x00030000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHDHPREF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHDHPRE
rw
Toggle fields

SHDHPRE

Bits 0-3: HCLK3 shared prescaler (AHB3, Flash, and SRAM2).

Allowed values:
1: Div3: SYSCLK divided by 3
2: Div5: SYSCLK divided by 5
5: Div6: SYSCLK divided by 6
6: Div10: SYSCLK divided by 10
7: Div32: SYSCLK divided by 32
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

SHDHPREF

Bit 16: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2).

Allowed values:
0: NotApplied: HCLK3 prescaler value not yet applied
1: Applied: HCLK3 prescaler value applied

RNG

0x58001000: True random number generator

16/17 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x10 HTCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00800000, access: read-write

9/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFIGLOCK
rw 		CONDRST
rw 		RNG_CONFIG1
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2
rw 		NISTC
rw 		RNG_CONFIG3
rw 		CED
rw 		IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: True random number generator enable.

Allowed values:
0: Disabled: Random number generator is disabled
1: Enabled: Random number generator is enabled

IE

Bit 3: Interrupt Enable.

Allowed values:
0: Disabled: RNG interrupt is disabled
1: Enabled: RNG interrupt is enabled

CED

Bit 5: Interrupt Enable.

Allowed values:
0: Enabled: Clock error detection is enabled
1: Disabled: Clock error detection is disabled

RNG_CONFIG3

Bits 8-11: RNG_CONFIG3.

Allowed values:
0: ConfigB: Recommended value for config B (not NIST certifiable)
13: ConfigA: Recommended value for config A (NIST certifiable)

NISTC

Bit 12: NISTC.

Allowed values:
0: Default: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used
1: Custom: Custom values for NIST compliant RNG

RNG_CONFIG2

Bits 13-15: RNG_CONFIG2.

Allowed values:
0: ConfigA_B: Recommended value for config A and B

CLKDIV

Bits 16-19: CLKDIV.

Allowed values:
0: Div1: Internal RNG clock after divider is similar to incoming RNG clock
1: Div2: Divide RNG clock by 2^1
2: Div4: Divide RNG clock by 2^2
3: Div8: Divide RNG clock by 2^3
4: Div16: Divide RNG clock by 2^4
5: Div32: Divide RNG clock by 2^5
6: Div64: Divide RNG clock by 2^6
7: Div128: Divide RNG clock by 2^7
8: Div256: Divide RNG clock by 2^8
9: Div512: Divide RNG clock by 2^9
10: Div1024: Divide RNG clock by 2^10
11: Div2048: Divide RNG clock by 2^11
12: Div4096: Divide RNG clock by 2^12
13: Div8192: Divide RNG clock by 2^13
14: Div16384: Divide RNG clock by 2^14
15: Div32768: Divide RNG clock by 2^15

RNG_CONFIG1

Bits 20-25: RNG_CONFIG1.

Allowed values:
15: ConfigA: Recommended value for config A (NIST certifiable)
24: ConfigB: Recommended value for config B (not NIST certifiable)

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: CONFIGLOCK.

Allowed values:
0: Enabled: Writes to the RNG_CR configuration bits [29:4] are allowed
1: Disabled: Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
r/w0c 		CEIS
r/w0c 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: Data Ready.

Allowed values:
0: Invalid: The RNG_DR register is not yet valid, no random data is available
1: Valid: The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.

CECS

Bit 1: Clock error current status.

Allowed values:
0: Correct: The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
1: Slow: The RNG clock is too slow

SECS

Bit 2: Seed error current status.

Allowed values:
0: NoFault: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
1: Fault: At least one faulty sequence has been detected - see ref manual for details

CEIS

Bit 5: Clock error interrupt status.

Allowed values:
0: Clear: Clear flag

SEIS

Bit 6: Seed error interrupt status.

Allowed values:
0: Clear: Clear flag

DR

data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data.

Allowed values: 0x0-0xffffffff

HTCR

health test control register

Offset: 0x10, size: 32, reset: 0x00005A4E, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG
rw
Toggle fields

HTCFG

Bits 0-31: health test configuration.

Allowed values:
43636: Recommended: Recommended value for RNG certification (0x0000_AA74)
391711420: Magic: Magic number to be written before any write (0x1759_0ABC)

RTC

0x40002800: Real-time clock

133/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x5c SCR
0x70 ALR[A]BINR
0x74 ALR[B]BINR
Toggle registers

TR

Time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

Date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

SSR

Sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-31: Synchronous binary counter.

Allowed values: 0x0-0xffff

ICSR

Initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCDU
rw 		BIN
rw 		INIT
rw 		INITF
r 		RSF
r/w0c 		INITS
r 		SHPF
r 		WUTWF
r
Toggle fields

WUTWF

Bit 2: Wakeup timer write flag.

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: Shift operation pending.

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: Initialization status flag.

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: Registers synchronization flag.

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: Initialization flag.

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: Initialization mode.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

BIN

Bits 8-9: Binary mode.

Allowed values:
0: BCD: Free running BCD calendar mode (Binary mode disabled)
1: Binary: Free running Binary mode (BCD mode disabled)
2: BinBCD: Free running BCD calendar and Binary modes
3: BinBCD2: Free running BCD calendar and Binary modes

BCDU

Bits 10-12: BCD update.

Allowed values:
0: Bit7: 1s increment each time SS[7:0]=0
1: Bit8: 1s increment each time SS[8:0]=0
2: Bit9: 1s increment each time SS[9:0]=0
3: Bit10: 1s increment each time SS[10:0]=0
4: Bit11: 1s increment each time SS[11:0]=0
5: Bit12: 1s increment each time SS[12:0]=0
6: Bit13: 1s increment each time SS[13:0]=0
7: Bit14: 1s increment each time SS[14:0]=0

RECALPF

Bit 16: Recalibration pending Flag.

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

Pre-scaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

Allowed values: 0x0-0x7f

WUTR

Wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUTOCLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

Allowed values: 0x0-0xffff

WUTOCLR

Bits 16-31: Wakeup auto-reload output clear value.

Allowed values: 0x0-0xffff

CR

Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw 		TAMPALRM_TYPE
rw 		TAMPALRM_PU
rw 		TAMPOE
rw 		TAMPTS
rw 		ITSE
rw 		COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
w 		ADD1H
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALR[B]IE
rw 		ALR[A]IE
rw 		TSE
rw 		WUTE
rw 		ALR[B]E
rw 		ALR[A]E
rw 		SSRUIE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: Timestamp event active edge.

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: RTC_REFIN reference clock detection enable (50 or 60 Hz).

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: Bypass the shadow registers.

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: Hour format.

Allowed values:
0: TwentyFourHour: 24 hour/day format
1: AmPm: AM/PM hour format

SSRUIE

Bit 7: SSR underflow interrupt enable.

Allowed values:
0: Disabled: SSR underflow interrupt disabled
1: Enabled: SSR underflow interrupt enabled

ALR[A]E

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

ALR[B]E

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

WUTE

Bit 10: Wakeup timer enable.

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: timestamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALR[A]IE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

ALR[B]IE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

WUTIE

Bit 14: Wakeup timer interrupt enable.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: Timestamp interrupt enable.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: Add 1 hour (summer time change).

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: Subtract 1 hour (winter time change).

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: Backup.

Allowed values:
0: DSTNotChanged: Daylight Saving Time change has not been performed
1: DSTChanged: Daylight Saving Time change has been performed

COSEL

Bit 19: Calibration output selection.

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: Output polarity.

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: Output selection.

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: Calibration output enable.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ITSE

Bit 24: timestamp on internal event enable.

Allowed values:
0: Disabled: Internal event timestamp disabled
1: Enabled: Internal event timestamp enabled

TAMPTS

Bit 25: Activate timestamp on tamper detection event.

Allowed values:
0: Disabled: Tamper detection event does not cause a RTC timestamp to be saved
1: Enabled: Save RTC timestamp on tamper detection event

TAMPOE

Bit 26: Tamper detection output enable on TAMPALRM.

Allowed values:
0: Disabled: The tamper flag is not routed on TAMPALRM
1: Enabled: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL

TAMPALRM_PU

Bit 29: TAMPALRM pull-up enable.

Allowed values:
0: NoPullUp: No pull-up is applied on TAMPALRM output
1: PullUp: A pull-up is applied on TAMPALRM output

TAMPALRM_TYPE

Bit 30: TAMPALRM output type.

Allowed values:
0: PushPull: TAMPALRM is push-pull output
1: OpenDrain: TAMPALRM is open-drain output

OUT2EN

Bit 31: RTC_OUT2 output enable.

Allowed values:
0: Disabled: RTC output 2 disable
1: Enabled: RTC output 2 enable

WPR

Write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

Allowed values:
0: Activate: Activate write protection (any value that is not the keys)
83: Deactivate2: Key 2
202: Deactivate1: Key 1

CALR

Calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		LPCAL
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

Allowed values: 0x0-0x1ff

LPCAL

Bit 12: Calibration low-power mode.

Allowed values:
0: RTCCLK: Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required
1: CkApre: Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode

CALW16

Bit 13: CALW16.

Allowed values:
1: SixteenSeconds: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: Use a 16-second calibration cycle period.

Allowed values:
1: EightSeconds: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: Use an 8-second calibration cycle period.

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

SHIFTR

Shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: Add one second.

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

Timestamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
r 		HT
r 		HU
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
r 		MNU
r 		ST
r 		SU
r
Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

Timestamp date register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
r 		MT
r 		MU
r 		DT
r 		DU
r
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

Timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-31: Sub second value.

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCLR
rw 		MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

Allowed values: 0x0-0x3f

SSCLR

Bit 31: Clear synchronous counter on alarm (Binary mode only).

Allowed values:
0: FreeRunning: The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running
1: ALRMBINR: The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCLR
rw 		MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-29: Mask the most-significant bits starting at this bit.

Allowed values: 0x0-0x3f

SSCLR

Bit 31: Clear synchronous counter on alarm (Binary mode only).

Allowed values:
0: FreeRunning: The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running
1: ALRMBINR: The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]

SR

Status register (interrupts)

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRUF
r 		ITSF
r 		TSOVF
r 		TSF
r 		WUTF
r 		ALR[B]F
r 		ALR[A]F
r
Toggle fields

ALR[A]F

Bit 0: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

ALR[B]F

Bit 1: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

WUTF

Bit 2: Wakeup timer flag.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 3: Timestamp flag.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 4: Timestamp overflow flag.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSF

Bit 5: Internal timestamp flag.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

SSRUF

Bit 6: SSR underflow flag.

Allowed values:
1: Underflow: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1

MISR

Masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRUMF
r 		ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALR[B]MF
r 		ALR[A]MF
r
Toggle fields

ALR[A]MF

Bit 0: Alarm A masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

ALR[B]MF

Bit 1: Alarm B masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

WUTMF

Bit 2: Wakeup timer masked flag.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSMF

Bit 3: Timestamp masked flag.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVMF

Bit 4: Timestamp overflow masked flag.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSMF

Bit 5: Internal timestamp masked flag.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

SSRUMF

Bit 6: SSR underflow masked flag.

Allowed values:
1: Underflow: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1

SCR

Status clear register (interrupts)

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSSRUF
w 		CITSF
w 		CTSOVF
w 		CTSF
w 		CWUTF
w 		CALRBF
w 		CALRAF
w
Toggle fields

CALRAF

Bit 0: Clear alarm A flag.

Allowed values:
1: Clear: Clear interrupt flag

CALRBF

Bit 1: Clear alarm B flag.

Allowed values:
1: Clear: Clear interrupt flag

CWUTF

Bit 2: Clear wakeup timer flag.

Allowed values:
1: Clear: Clear interrupt flag

CTSF

Bit 3: Clear timestamp flag.

Allowed values:
1: Clear: Clear interrupt flag

CTSOVF

Bit 4: Clear timestamp overflow flag.

Allowed values:
1: Clear: Clear interrupt flag

CITSF

Bit 5: Clear internal timestamp flag.

Allowed values:
1: Clear: Clear interrupt flag

CSSRUF

Bit 6: Clear SSR underflow flag.

Allowed values:
1: Clear: Clear interrupt flag

ALR[A]BINR

Alarm A binary mode register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

Allowed values: 0x0-0xffffffff

ALR[B]BINR

Alarm B binary mode register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-31: Synchronous counter alarm value in Binary mode.

Allowed values: 0x0-0xffffffff

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

54/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
r/w0c 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: CHSIDE.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: UDR.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTRTEN
rw 		I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: CHLEN.

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: DATLEN.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: CKPOL.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2SSTD.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCMSYNC.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2SCFG.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2SE.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2SMOD.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

ASTRTEN

Bit 12: ASTRTEN.

Allowed values:
0: AsyncStartDisabled: Asynchronous start disabled
1: AsyncStartEnabled: Asynchronous start enabled

I2SPR

prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2SDIV.

Allowed values: 0x2-0xff

ODD

Bit 8: ODD.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: MCKOE.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

54/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
r/w0c 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: CHSIDE.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: UDR.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTRTEN
rw 		I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: CHLEN.

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: DATLEN.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: CKPOL.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2SSTD.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCMSYNC.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2SCFG.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2SE.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2SMOD.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

ASTRTEN

Bit 12: ASTRTEN.

Allowed values:
0: AsyncStartDisabled: Asynchronous start disabled
1: AsyncStartEnabled: Asynchronous start enabled

I2SPR

prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2SDIV.

Allowed values: 0x2-0xff

ODD

Bit 8: ODD.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: MCKOE.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI3

0x58010000: Serial peripheral interface/Inter-IC sound

54/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
r/w0c 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: CHSIDE.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: UDR.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASTRTEN
rw 		I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: CHLEN.

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: DATLEN.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: CKPOL.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2SSTD.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCMSYNC.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2SCFG.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2SE.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2SMOD.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

ASTRTEN

Bit 12: ASTRTEN.

Allowed values:
0: AsyncStartDisabled: Asynchronous start disabled
1: AsyncStartEnabled: Asynchronous start enabled

I2SPR

prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2SDIV.

Allowed values: 0x2-0xff

ODD

Bit 8: ODD.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: MCKOE.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SYSCFG

0x40010000: System configuration controller

67/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MEMRMP
0x4 CFGR1
0x8 EXTICR1
0xc EXTICR2
0x10 EXTICR3
0x14 EXTICR4
0x18 SCSR
0x1c CFGR2
0x20 SWPR
0x24 SKR
0x208 RFDCR
Toggle registers

MEMRMP

memory remap register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM_MODE
rw
Toggle fields

MEM_MODE

Bits 0-2: Memory mapping selection.

Allowed values:
0: MainFlash: Main Flash memory mapped at 0x0000_0000
1: SystemFlash: System Flash memory mapped at 0x0000_0000
3: SRAM: Embedded SRAM mapped at 0x0000_0000

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x7C000001, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw 		I2C_PB9_FMP
rw 		I2C_PB8_FMP
rw 		I2C_PB7_FMP
rw 		I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOSTEN
rw
Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

Allowed values:
0: Disabled: I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation
1: Enabled: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

Allowed values:
0: Standard: PB6 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB6 and the Speed control is bypassed

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

Allowed values:
0: Standard: PB7 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB7 and the Speed control is bypassed

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

Allowed values:
0: Standard: PB8 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB8 and the Speed control is bypassed

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

Allowed values:
0: Standard: PB9 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB9 and the Speed control is bypassed

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle fields

EXTI0

Bits 0-2: EXTI 0 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI1

Bits 4-6: EXTI 1 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI2

Bits 8-10: EXTI 2 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI3

Bits 12-14: EXTI 3 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt
7: PH: Select PHx as the source input for the EXTIx external interrupt

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle fields

EXTI4

Bits 0-2: EXTI 4 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI5

Bits 4-6: EXTI 5 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI6

Bits 8-10: EXTI 6 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI7

Bits 12-14: EXTI 7 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle fields

EXTI8

Bits 0-2: EXTI 8 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt

EXTI9

Bits 4-6: EXTI 9 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt

EXTI10

Bits 8-10: EXTI 10 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt

EXTI11

Bits 12-14: EXTI 11 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle fields

EXTI12

Bits 0-2: EXTI12 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt

EXTI13

Bits 4-6: EXTI13 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI14

Bits 8-10: EXTI14 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

EXTI15

Bits 12-14: EXTI15 configuration bits.

Allowed values:
0: PA: Select PAx as the source input for the EXTIx external interrupt
1: PB: Select PBx as the source input for the EXTIx external interrupt
2: PC: Select PCx as the source input for the EXTIx external interrupt

SCSR

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKASRAMBSY
r 		SRAMBSY
r 		SRAM2ER
rw
Toggle fields

SRAM2ER

Bit 0: SRAM2 erase.

Allowed values:
1: Erase: Start SRAM2 erase operation

SRAMBSY

Bit 1: SRAM1, SRAM2 and PKA SRAM busy by erase operation.

Allowed values:
0: Idle: No SRAM1 or SRAM2 erase operation is ongoing
1: Busy: SRAM1 or SRAM2 erase operation is ongoing

PKASRAMBSY

Bit 8: PKA SRAM busy by erase operation.

Allowed values:
0: Idle: No PKA SRAM erase operation is ongoing
1: Busy: PKA SRAM erase operation is ongoing

CFGR2

CFGR2

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw 		ECCL
rw 		PVDL
rw 		SPL
rw 		CLL
rw
Toggle fields

CLL

Bit 0: CPU1 LOCKUP (Hardfault) output enable bit.

Allowed values:
0: Disconnected: CPU LOCKUP output disconnected from TIM1/16/17 break input
1: Connected: CPU LOCKUP output connected to TIM1/16/17 break input

SPL

Bit 1: SRAM2 parity lock bit.

Allowed values:
0: Disconnected: SRAM2 parity error signal disconnected from TIM1/16/17 break input
1: Connected: SRAM2 parity error signal connected to TIM1/16/17 break input

PVDL

Bit 2: PVD lock enable bit.

Allowed values:
0: Disconnected: PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application
1: Connected: PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only

ECCL

Bit 3: ECC Lock.

Allowed values:
0: Disconnected: ECC error disconnected from TIM1/16/17 break input
1: Connected: ECC error connected to TIM1/16/17 break input

SPF

Bit 8: SRAM2 parity error flag.

Allowed values:
0: Nominal: No SRAM2 parity error detected
1: Error: SRAM2 parity error detected

SWPR

SWPR

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP
rw 		P30WP
rw 		P29WP
rw 		P28WP
rw 		P27WP
rw 		P26WP
rw 		P25WP
rw 		P24WP
rw 		P23WP
rw 		P22WP
rw 		P21WP
rw 		P20WP
rw 		P19WP
rw 		P18WP
rw 		P17WP
rw 		P16WP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP
rw 		P14WP
rw 		P13WP
rw 		P12WP
rw 		P11WP
rw 		P10WP
rw 		P9WP
rw 		P8WP
rw 		P7WP
rw 		P6WP
rw 		P5WP
rw 		P4WP
rw 		P3WP
rw 		P2WP
rw 		P1WP
rw 		P0WP
rw
Toggle fields

P0WP

Bit 0: SRAM2 1Kbyte page 0 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P1WP

Bit 1: SRAM2 1Kbyte page 1 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P2WP

Bit 2: SRAM2 1Kbyte page 2 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P3WP

Bit 3: SRAM2 1Kbyte page 3 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P4WP

Bit 4: SRAM2 1Kbyte page 4 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P5WP

Bit 5: SRAM2 1Kbyte page 5 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P6WP

Bit 6: SRAM2 1Kbyte page 6 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P7WP

Bit 7: SRAM2 1Kbyte page 7 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P8WP

Bit 8: SRAM2 1Kbyte page 8 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P9WP

Bit 9: SRAM2 1Kbyte page 9 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P10WP

Bit 10: SRAM2 1Kbyte page 10 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P11WP

Bit 11: SRAM2 1Kbyte page 11 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P12WP

Bit 12: SRAM2 1Kbyte page 12 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P13WP

Bit 13: SRAM2 1Kbyte page 13 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P14WP

Bit 14: SRAM2 1Kbyte page 14 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P15WP

Bit 15: SRAM2 1Kbyte page 15 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P16WP

Bit 16: SRAM2 1Kbyte page 16 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P17WP

Bit 17: SRAM2 1Kbyte page 17 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P18WP

Bit 18: SRAM2 1Kbyte page 18 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P19WP

Bit 19: SRAM2 1Kbyte page 19 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P20WP

Bit 20: SRAM2 1Kbyte page 20 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P21WP

Bit 21: SRAM2 1Kbyte page 21 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P22WP

Bit 22: SRAM2 1Kbyte page 22 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P23WP

Bit 23: SRAM2 1Kbyte page 23 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P24WP

Bit 24: SRAM2 1Kbyte page 24 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P25WP

Bit 25: SRAM2 1Kbyte page 25 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P26WP

Bit 26: SRAM2 1Kbyte page 26 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P27WP

Bit 27: SRAM2 1Kbyte page 27 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P28WP

Bit 28: SRAM2 1Kbyte page 28 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P29WP

Bit 29: SRAM2 1Kbyte page 29 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P30WP

Bit 30: SRAM2 1Kbyte page 30 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

P31WP

Bit 31: SRAM2 1Kbyte page 31 write protection.

Allowed values:
0: Disabled: SRAM2 1 KB page protection disabled
1: Enabled: SRAM2 1 KB page protection enabled

SKR

SKR

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

Allowed values:
17: WriteProtect: Activate SRAM2ER bits write protection
83: Step2: Step 2 to remove SRAM2ER bits write protection
202: Step1: Step 1 to remove SRAM2ER bits write protection

RFDCR

radio debug control register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFTBSEL
rw
Toggle fields

RFTBSEL

Bit 0: radio debug test bus selection.

Allowed values:
0: Digital: Digital test bus selected on RF_ADTB[3:0]
1: Analog: Analog test bus selected on RF_ADTB[3:0]

TAMP

0x4000b000: Tamper and backup registers

74/74 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc FLTCR
0x2c IER
0x30 SR
0x34 MISR
0x3c SCR
0x40 COUNTR
0x100 BKP[0]R
0x104 BKP[1]R
0x108 BKP[2]R
0x10c BKP[3]R
0x110 BKP[4]R
0x114 BKP[5]R
0x118 BKP[6]R
0x11c BKP[7]R
0x120 BKP[8]R
0x124 BKP[9]R
0x128 BKP[10]R
0x12c BKP[11]R
0x130 BKP[12]R
0x134 BKP[13]R
0x138 BKP[14]R
0x13c BKP[15]R
0x140 BKP[16]R
0x144 BKP[17]R
0x148 BKP[18]R
0x14c BKP[19]R
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw 		ITAMP6E
rw 		ITAMP5E
rw 		ITAMP3E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3E
rw 		TAMP2E
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: TAMP1E.

Allowed values:
0: Disabled: Tamper detection on TAMP_INx is disabled
1: Enabled: Tamper detection on TAMP_IN3 is enabled

TAMP2E

Bit 1: TAMP2E.

Allowed values:
0: Disabled: Tamper detection on TAMP_INx is disabled
1: Enabled: Tamper detection on TAMP_IN3 is enabled

TAMP3E

Bit 2: TAMP2E.

Allowed values:
0: Disabled: Tamper detection on TAMP_INx is disabled
1: Enabled: Tamper detection on TAMP_IN3 is enabled

ITAMP3E

Bit 18: ITAMP3E.

Allowed values:
0: Disabled: Internal tamper x disabled
1: Enabled: Internal tamper x enabled

ITAMP5E

Bit 20: ITAMP5E.

Allowed values:
0: Disabled: Internal tamper x disabled
1: Enabled: Internal tamper x enabled

ITAMP6E

Bit 21: ITAMP6E.

Allowed values:
0: Disabled: Internal tamper x disabled
1: Enabled: Internal tamper x enabled

ITAMP8E

Bit 23: ITAMP8E.

Allowed values:
0: Disabled: Internal tamper x disabled
1: Enabled: Internal tamper x enabled

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3TRG
rw 		TAMP2TRG
rw 		TAMP1TRG
rw 		BKERASE
rw 		TAMP3MSK
rw 		TAMP2MSK
rw 		TAMP1MSK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3NOER
rw 		TAMP2NOER
rw 		TAMP1NOER
rw
Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

Allowed values:
0: Erase: Tamper x event erases the backup registers
1: NotErase: Tamper x event does not erase the backup registers

TAMP2NOER

Bit 1: TAMP2NOER.

Allowed values:
0: Erase: Tamper x event erases the backup registers
1: NotErase: Tamper x event does not erase the backup registers

TAMP3NOER

Bit 2: TAMP3NOER.

Allowed values:
0: Erase: Tamper x event erases the backup registers
1: NotErase: Tamper x event does not erase the backup registers

TAMP1MSK

Bit 16: TAMP1MSK.

Allowed values:
0: ResetBySoftware: Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection
1: ResetByHardware: Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set

TAMP2MSK

Bit 17: TAMP2MSK.

Allowed values:
0: ResetBySoftware: Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection
1: ResetByHardware: Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set

TAMP3MSK

Bit 18: TAMP3MSK.

Allowed values:
0: ResetBySoftware: Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection
1: ResetByHardware: Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set

BKERASE

Bit 23: Backup registerserase.

Allowed values:
1: Reset: Reset backup registers

TAMP1TRG

Bit 24: TAMP1TRG.

Allowed values:
0: FilteredLowOrUnfilteredHigh: If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event
1: FilteredHighOrUnfilteredLow: If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event

TAMP2TRG

Bit 25: TAMP2TRG.

Allowed values:
0: FilteredLowOrUnfilteredHigh: If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event
1: FilteredHighOrUnfilteredLow: If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event

TAMP3TRG

Bit 26: TAMP3TRG.

Allowed values:
0: FilteredLowOrUnfilteredHigh: If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event
1: FilteredHighOrUnfilteredLow: If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event

CR3

TAMP control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITAMP8NOER
rw 		ITAMP6NOER
rw 		ITAMP5NOER
rw 		ITAMP3NOER
rw
Toggle fields

ITAMP3NOER

Bit 2: ITAMP3NOER.

Allowed values:
0: Erase: Internal tamper x event erases the backup registers
1: NotErase: Internal tamper x event does not erase the backup registers

ITAMP5NOER

Bit 4: ITAMP5NOER.

Allowed values:
0: Erase: Internal tamper x event erases the backup registers
1: NotErase: Internal tamper x event does not erase the backup registers

ITAMP6NOER

Bit 5: ITAMP6NOER.

Allowed values:
0: Erase: Internal tamper x event erases the backup registers
1: NotErase: Internal tamper x event does not erase the backup registers

ITAMP8NOER

Bit 7: ITAMP8NOER.

Allowed values:
0: Erase: Internal tamper x event erases the backup registers
1: NotErase: Internal tamper x event does not erase the backup registers

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

Allowed values:
0: Hz_1: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
1: Hz_2: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
2: Hz_4: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
3: Hz_8: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
4: Hz_16: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
5: Hz_32: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
6: Hz_64: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
7: Hz_128: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)

TAMPFLT

Bits 3-4: TAMPFLT.

Allowed values:
0: NoFilter: Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)"
1: Filter2: Tamper event is activated after 2 consecutive samples at the active level"
2: Filter4: Tamper event is activated after 4 consecutive samples at the active level"
3: Filter8: Tamper event is activated after 8 consecutive samples at the active level"

TAMPPRCH

Bits 5-6: TAMPPRCH.

Allowed values:
0: Cycles1: 1 RTCCLK cycle
1: Cycles2: 2 RTCCLK cycles
2: Cycles4: 4 RTCCLK cycles
3: Cycles8: 8 RTCCLK cycles

TAMPPUDIS

Bit 7: TAMPPUDIS.

Allowed values:
0: Enabled: Precharge TAMP_INx pins before sampling (enable internal pull-up)
1: Disabled: Disable precharge of TAMP_INx pins

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw 		ITAMP6IE
rw 		ITAMP5IE
rw 		ITAMP3IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3IE
rw 		TAMP2IE
rw 		TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

Allowed values:
0: Disabled: Tamper x interrupt disabled
1: Enabled: Tampoer x interrupt enabled

TAMP2IE

Bit 1: TAMP2IE.

Allowed values:
0: Disabled: Tamper x interrupt disabled
1: Enabled: Tampoer x interrupt enabled

TAMP3IE

Bit 2: TAMP3IE.

Allowed values:
0: Disabled: Tamper x interrupt disabled
1: Enabled: Tampoer x interrupt enabled

ITAMP3IE

Bit 18: ITAMP3IE.

Allowed values:
0: Disabled: Internal tamper x interrupt disabled
1: Enabled: Internal tamper x interrupt enabled

ITAMP5IE

Bit 20: ITAMP5IE.

Allowed values:
0: Disabled: Internal tamper x interrupt disabled
1: Enabled: Internal tamper x interrupt enabled

ITAMP6IE

Bit 21: ITAMP6IE.

Allowed values:
0: Disabled: Internal tamper x interrupt disabled
1: Enabled: Internal tamper x interrupt enabled

ITAMP8IE

Bit 23: ITAMP8IE.

Allowed values:
0: Disabled: Internal tamper x interrupt disabled
1: Enabled: Internal tamper x interrupt enabled

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r 		ITAMP6F
r 		ITAMP5F
r 		ITAMP3F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
r 		TAMP2F
r 		TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Tamper detected

TAMP2F

Bit 1: TAMP2F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Tamper detected

TAMP3F

Bit 2: TAMP3F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Tamper detected

ITAMP3F

Bit 18: ITAMP3F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Internal tamper detected

ITAMP5F

Bit 20: ITAMP5F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Internal tamper detected

ITAMP6F

Bit 21: ITAMP6F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Internal tamper detected

ITAMP8F

Bit 23: ITAMP8F.

Allowed values:
0: Idle: No tamper detected
1: Tamper: Internal tamper detected

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP6MF
r 		ITAMP5MF
r 		ITAMP3MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Tamper detected - Masked

TAMP2MF

Bit 1: TAMP2MF.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Tamper detected - Masked

TAMP3MF

Bit 2: TAMP3MF.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Tamper detected - Masked

ITAMP3MF

Bit 18: ITAMP3MF.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Internal tamper detected - Masked

ITAMP5MF

Bit 20: ITAMP5MF.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Internal tamper detected - Masked

ITAMP6MF

Bit 21: ITAMP6MF.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Internal tamper detected - Masked

ITAMP8MF

Bit 23: ITAMP8MF.

Allowed values:
0: Idle: No tamper detected - Masked
1: Tamper: Internal tamper detected - Masked

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w 		CITAMP6F
w 		CITAMP5F
w 		CITAMP3F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP3F
w 		CTAMP2F
w 		CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

Allowed values:
1: Clear: Clear tamper flag

CTAMP2F

Bit 1: CTAMP2F.

Allowed values:
1: Clear: Clear tamper flag

CTAMP3F

Bit 2: CTAMP3F.

Allowed values:
1: Clear: Clear tamper flag

CITAMP3F

Bit 18: CITAMP3F.

Allowed values:
1: Clear: Clear tamper flag

CITAMP5F

Bit 20: CITAMP5F.

Allowed values:
1: Clear: Clear tamper flag

CITAMP6F

Bit 21: CITAMP6F.

Allowed values:
1: Clear: Clear tamper flag

CITAMP8F

Bit 23: CITAMP8F.

Allowed values:
1: Clear: Clear tamper flag

COUNTR

monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: COUNT.

Allowed values: 0x0-0xffffffff

BKP[0]R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[1]R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[2]R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[3]R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[4]R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[5]R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[6]R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[7]R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[8]R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[9]R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[10]R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[11]R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[12]R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[13]R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[14]R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[15]R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[16]R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[17]R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[18]R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[19]R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

TIM1

0x40012c00: Advanced-control timers

182/190 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 AF1
0x64 AF2
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0: Disabled: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
1: Enabled: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS[6]
rw 		OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw 		OIS[3]N
rw 		OIS[3]
rw 		OIS[2]N
rw 		OIS[2]
rw 		OIS[1]N
rw 		OIS[1]
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

Allowed values:
0: Reset: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset
1: Enable: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)
2: Update: Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer
3: ComparePulse: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2)
4: CompareOC1: Compare - OC1REFC signal is used as trigger output (TRGO2)
5: CompareOC2: Compare - OC2REFC signal is used as trigger output (TRGO2)
6: CompareOC3: Compare - OC3REFC signal is used as trigger output (TRGO2)
7: CompareOC4: Compare - OC4REFC signal is used as trigger output (TRGO2)
8: CompareOC5: Compare - OC5REFC signal is used as trigger output (TRGO2)
9: CompareOC6: Compare - OC6REFC signal is used as trigger output (TRGO2)
10: PulseOC4: Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2
11: PulseOC6: Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2
12: RisingOC4_6: Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2
13: RisingOC4_FallingOC6: Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2
14: RisingOC5_6: Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2
15: RisingOC5_FallingOC6: Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw 		SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: DisabledOrCombined: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter
1: EncoderMode1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level
2: EncoderMode2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level
3: EncoderMode3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input
4: ResetMode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers
5: GatedMode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled
6: TriggerMode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled
7: ExtClockMode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled (see SMS[0:2])
1: CombinedResetTrigger: SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

TS2

Bits 20-21: Trigger selection.

DIER

DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c 		CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c 		CC[4]OF
r/w0c 		CC[3]OF
r/w0c 		CC[2]OF
r/w0c 		CC[1]OF
r/w0c 		B2IF
r/w0c 		BIF
r/w0c 		TIF
r/w0c 		COMIF
r/w0c 		CC[4]IF
r/w0c 		CC[3]IF
r/w0c 		CC[2]IF
r/w0c 		CC[1]IF
r/w0c 		UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

B2IF

Bit 8: Break 2 interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC2S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC4S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw 		CC[6]E
rw 		CC[5]P
rw 		CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]NE
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]NE
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

BK2F

Bits 20-23: Break 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

BKDSRM

Bit 26: BKDSRM.

Allowed values:
0: Armed: Break input BRK is armed
1: Disarmed: Break input BRK is disarmed

BK2DSRM

Bit 27: Break2 Disarm.

Allowed values:
0: Armed: Break input BRK2 is armed
1: Disarmed: Break input BRK2 is disarmed

BKBID

Bit 28: BKBID.

Allowed values:
0: Input: Break input BRK in input mode
1: Bidirectional: Break input BRK in bidirectional mode

BK2BID

Bit 29: Break2 bidirectional.

Allowed values:
0: Input: Break input BRK2 in input mode
1: Bidirectional: Break input BRK2 in bidirectional mode

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x11

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

Allowed values: 0x0-0xffffffff

OR1

option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw 		TIM1_ETR_ADC1_RMP
rw
Toggle fields

TIM1_ETR_ADC1_RMP

Bits 0-1: TIM1_ETR_ADC1 remapping capability.

Allowed values:
0: Select: TIM1_ETR is not connected to ADC AWDx (must be selected when the ETR comes from the ETR input pin)
1: ADC_AWD1: TIM1_ETR is connected to ADC AWD1
2: ADC_AWD2: TIM1_ETR is connected to ADC AWD2
3: ADC_AWD3: TIM1_ETR is connected to ADC AWD3

TI1_RMP

Bit 4: Input Capture 1 remap.

Allowed values:
0: IO: TIM1 input capture 1 is connected to I/O
1: COMP1: TIM1 input capture 1 is connected to COMP1 output

CCMR3_Output

capture/compare mode register 3

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw 		OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw 		OC[6]M
rw 		OC[6]PE
rw 		OC[6]FE
rw 		OC[5]CE
rw 		OC[5]M
rw 		OC[5]PE
rw 		OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

Allowed values:
0: Disabled: No effect of OC5REF on OC1REFC
1: Enabled: OC1REFC is the logical AND of OC1REFC and OC5REF

GC5C2

Bit 30: Group Channel 5 and Channel 2.

Allowed values:
0: Disabled: No effect of OC5REF on OC2REFC
1: Enabled: OC2REFC is the logical AND of OC2REFC and OC5REF

GC5C3

Bit 31: Group Channel 5 and Channel 3.

Allowed values:
0: Disabled: No effect of OC5REF on OC3REFC
1: Enabled: OC3REFC is the logical AND of OC3REFC and OC5REF

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

AF1

alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

Allowed values:
0: Disabled: BKIN input disabled
1: Enabled: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable.

Allowed values:
0: Disabled: COMP1 input disabled
1: Enabled: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable.

Allowed values:
0: Disabled: COMP2 input disabled
1: Enabled: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BKCMP1P

Bit 10: BRK COMP1 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BKCMP2P

Bit 11: BRK COMP2 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

ETRSEL

Bits 14-17: ETR source selection.

Allowed values:
0: Legacy: ETR legacy mode
1: COMP1: COMP1 output
2: COMP2: COMP2 output

AF2

Alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

Allowed values:
0: Disabled: BKIN input disabled
1: Enabled: BKIN input enabled

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

Allowed values:
0: Disabled: COMP1 input disabled
1: Enabled: COMP1 input enabled

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

Allowed values:
0: Disabled: COMP2 input disabled
1: Enabled: COMP2 input enabled

BK2INP

Bit 9: BRK2 BKIN2 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

TISEL

timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw 		TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

Allowed values:
0: Selected: TIM1_CHx input selected

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input.

Allowed values:
0: Selected: TIM1_CHx input selected

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input.

Allowed values:
0: Selected: TIM1_CHx input selected

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input.

Allowed values:
0: Selected: TIM1_CHx input selected

TIM16

0x40014400: General-purpose timers

65/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 AF1
0x68 TISEL
Toggle registers

CR1

TIM16/TIM17 control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0: Disabled: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
1: Enabled: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31

CR2

TIM16/TIM17 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw 		OIS[1]
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: CCUS.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: CCDS.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

TIM16/TIM17 DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

SR

TIM16/TIM17 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c 		BIF
r/w0c 		COMIF
r/w0c 		CC[1]IF
r/w0c 		UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

TIM16/TIM17 event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

TIM16/TIM17 capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

TIM16/TIM17 capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

TIM16/TIM17 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

TIM16/TIM17 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPYorRes
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPYorRes

Bit 31: UIF Copy.

PSC

TIM16/TIM17 prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

TIM16/TIM17 auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

TIM16/TIM17 repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

TIM16/TIM17 break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

Allowed values:
0: Armed: Break input BRK is armed
1: Disarmed: Break input BRK is disarmed

BKBID

Bit 28: Break Bidirectional.

Allowed values:
0: Input: Break input BRK in input mode
1: Bidirectional: Break input BRK in bidirectional mode

DCR

TIM16/TIM17 DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x11

DMAR

TIM16/TIM17 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0x0-0xffff

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Timer 17 input 1 connection.

Allowed values:
0: GPIO: TI1 is connected to GPIO
1: LSI: TI1 is connected to LSI
2: LSE: TI1 is connected to LSE
3: RTC: TI1 is connected to RTC wake-up interrupt

AF1

TIM16 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

Allowed values:
0: Disabled: BKIN input disabled
1: Enabled: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable.

Allowed values:
0: Disabled: COMP1 input disabled
1: Enabled: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable.

Allowed values:
0: Disabled: COMP2 input disabled
1: Enabled: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BKCMP1P

Bit 10: BRK COMP1 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BKCMP2P

Bit 11: BRK COMP2 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

TISEL

TIM16 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TISEL
rw
Toggle fields

TISEL

Bits 0-3: TISEL.

Allowed values:
0: Selected: TIM1_CH1 input selected

TIM17

0x40014800: General-purpose timers

65/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 AF1
0x68 TISEL
Toggle registers

CR1

TIM16/TIM17 control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0: Disabled: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
1: Enabled: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31

CR2

TIM16/TIM17 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw 		OIS[1]
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: CCUS.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: CCDS.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

TIM16/TIM17 DMA/interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

SR

TIM16/TIM17 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c 		BIF
r/w0c 		COMIF
r/w0c 		CC[1]IF
r/w0c 		UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

TIM16/TIM17 event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

TIM16/TIM17 capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

TIM16/TIM17 capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

TIM16/TIM17 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

TIM16/TIM17 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPYorRes
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPYorRes

Bit 31: UIF Copy.

PSC

TIM16/TIM17 prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

TIM16/TIM17 auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

TIM16/TIM17 repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

TIM16/TIM17 break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

Allowed values:
0: Armed: Break input BRK is armed
1: Disarmed: Break input BRK is disarmed

BKBID

Bit 28: Break Bidirectional.

Allowed values:
0: Input: Break input BRK in input mode
1: Bidirectional: Break input BRK in bidirectional mode

DCR

TIM16/TIM17 DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x11

DMAR

TIM16/TIM17 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0x0-0xffff

OR1

TIM17 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Timer 17 input 1 connection.

Allowed values:
0: GPIO: TI1 is connected to GPIO
1: LSI: TI1 is connected to LSI
2: LSE: TI1 is connected to LSE
3: RTC: TI1 is connected to RTC wake-up interrupt

AF1

TIM17 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

Allowed values:
0: Disabled: BKIN input disabled
1: Enabled: BKIN input enabled

BKCMP1E

Bit 1: BRK COMP1 enable.

Allowed values:
0: Disabled: COMP1 input disabled
1: Enabled: COMP1 input enabled

BKCMP2E

Bit 2: BRK COMP2 enable.

Allowed values:
0: Disabled: COMP2 input disabled
1: Enabled: COMP2 input enabled

BKINP

Bit 9: BRK BKIN input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BKCMP1P

Bit 10: BRK COMP1 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

BKCMP2P

Bit 11: BRK COMP2 input polarity.

Allowed values:
0: NotInverted: Input polarity not inverted
1: Inverted: Input polarity inverted

TISEL

TIM17 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TISEL
rw
Toggle fields

TISEL

Bits 0-3: TISEL.

Allowed values:
0: Selected: TIM1_CH1 input selected

TIM2

0x40000000: General-purpose-timers

106/111 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 AF1
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

Allowed values:
0: Disabled: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
1: Enabled: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: DisabledOrCombined: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter
1: EncoderMode1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level
2: EncoderMode2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level
3: EncoderMode3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input
4: ResetMode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers
5: GatedMode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled
6: TriggerMode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled
7: ExtClockMode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

Allowed values:
0: Disabled: Slave mode disabled (see SMS[0:2])
1: CombinedResetTrigger: SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c 		CC[3]OF
r/w0c 		CC[2]OF
r/w0c 		CC[1]OF
r/w0c 		TIF
r/w0c 		CC[4]IF
r/w0c 		CC[3]IF
r/w0c 		CC[2]IF
r/w0c 		CC[1]IF
r/w0c 		UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC2S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC4S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x11

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0x0-0xffff

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR_RMP
rw
Toggle fields

ETR_RMP

Bit 1: External trigger remap.

Allowed values:
0: GPIO: TIM2 ETR is connected to GPIO: Refer to Alternate Function mapping
1: TIM2_ETR: LSE internal clock is connected to TIM2_ETR input

TI4_RMP

Bits 2-3: Input capture 4 remap.

Allowed values:
0: GPIO: TIM2 TI4 is connected to GPIO: Refer to Alternate Function mapping
1: COMP_1: TIM2 TI4 is connected to COMP1_OUT
2: COMP_2: TIM2 TI4 is connected to COMP2_OUT
3: COMP_12: TIM2 TI4 is connected to a logical OR between COMP1_OUT and COMP2_OUT

AF1

TIM2 alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-17: External trigger source selection.

Allowed values:
0: Legacy: ETR legacy mode
1: COMP1: COMP1 output
2: COMP2: COMP2 output

TISEL

TIM2 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

Allowed values:
0: Selected: TIM1_CHx input selected

TI2SEL

Bits 8-11: TI2SEL.

Allowed values:
0: Selected: TIM1_CHx input selected

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in low-power mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: Receive data register not empty/RXFIFO not empty interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: Transmit data register empty/TXFIFO not full interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: stop bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: OVRDIS: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

request register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

interrupt and status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NE

Bit 2: NE.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: UDR.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c 		CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c 		EOBCF
w1c 		RTOCF
w1c 		CTSCF
w1c 		LBDCF
w1c 		TCBGTCF
w1c 		TCCF
w1c 		TXFECF
w1c 		IDLECF
w1c 		ORECF
w1c 		NCF
w1c 		FECF
w1c 		PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from low-power mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in low-power mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: Receive data register not empty/RXFIFO not empty interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: Transmit data register empty/TXFIFO not full interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: stop bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: OVRDIS: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

request register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

interrupt and status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NE
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NE

Bit 2: NE.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: UDR.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c 		CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c 		EOBCF
w1c 		RTOCF
w1c 		CTSCF
w1c 		LBDCF
w1c 		TCBGTCF
w1c 		TCCF
w1c 		TXFECF
w1c 		IDLECF
w1c 		ORECF
w1c 		NCF
w1c 		FECF
w1c 		PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from low-power mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

VREFBUF

0x40010030: Voltage reference buffer

5/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r 		VRS
rw 		HIZ
rw 		ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer mode enable.

Allowed values:
0: Disabled: Internal voltage reference mode disable (external voltage reference mode)
1: Enabled: Internal voltage reference mode (reference buffer enable or hold mode) enable

HIZ

Bit 1: High impedance mode.

Allowed values:
0: Connected: VREF+ pin is internally connected to the voltage reference buffer output
1: HighZ: VREF+ pin is high impedance

VRS

Bit 2: Voltage reference scale.

Allowed values:
0: V2_048: Voltage reference set to VREF_OUT1 (around 2.048 V)
1: V2_5: Voltage reference set to VREF_OUT2 (around 2.5 V)

VRR

Bit 3: Voltage reference buffer ready.

Allowed values:
0: NotReady: The voltage reference buffer output is not ready
1: Ready: The voltage reference buffer output reached the requested level

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code.

Allowed values: 0x0-0x3f

WWDG

0x40002c00: System window watchdog

6/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR
0x4 (16-bit) CFR
0x8 (16-bit) SR
Toggle registers

CR

Control register

Offset: 0x0, size: 16, reset: 0x0000007F, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, size: 16, reset: 0x0000007F, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTB
N/A 		EWI
w 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

Allowed values: 0x0-0x7f

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

WDGTB

Bits 11-13: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

SR

Status register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
r/w0c
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered