STM32C031 1.4 STM32C031 CM0 r0p0 little true true 2 false 8 32 0x20 0x00000000 0xFFFFFFFF ADC Analog to Digital Converter ADC 0x40012400 0x0 0x400 registers ADC ADC interrupt 12 ISR ISR ADC interrupt and status register 0x0 0x20 0x00000000 0xFFFFFFFF ADRDY ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 1 read-write oneToClear ADRDYR read NotReady ADC not yet ready to start conversion 0 Ready ADC ready to start conversion 1 ADRDYW write Clear Clear the ADC ready flag 1 EOSMP End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1. 1 1 read-write oneToClear EOSMPR read NotAtEnd Not at the end of the samplings phase 0 AtEnd End of sampling phase reached 1 EOSMPW write Clear Clear the sampling phase flag 1 EOC End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. 2 1 read-write oneToClear EOCR read NotComplete Channel conversion is not complete 0 Complete Channel conversion complete 1 EOCW write Clear Clear the channel conversion flag 1 EOS End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. 3 1 read-write oneToClear EOSR read NotComplete Conversion sequence is not complete 0 Complete Conversion sequence complete 1 EOSW write Clear Clear the conversion sequence flag 1 OVR ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. 4 1 read-write oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear the overrun flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 read-write oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear the analog watchdog event flag 1 EOCAL End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. 11 1 read-write oneToClear EOCALR read NotComplete Calibration is not complete 0 Complete Calibration complete 1 EOCALW write Clear Clear the calibration flag 1 CCRDY Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. 13 1 read-write oneToClear CCRDYR read NotComplete Channel configuration update not applied 0 Complete Channel configuration update is applied 1 CCRDYW write Clear Clear the channel configuration flag 1 IER IER ADC interrupt enable register 0x4 0x20 0x00000000 0xFFFFFFFF ADRDYIE ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write ADRDYIE Disabled ADRDY interrupt disabled 0 Enabled ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 1 EOSMPIE End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 1 1 read-write EOSMPIE Disabled EOSMP interrupt disabled 0 Enabled EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 1 EOCIE End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 2 1 read-write EOCIE Disabled EOC interrupt disabled 0 Enabled EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 1 EOSIE End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 3 1 read-write EOSIE Disabled EOS interrupt disabled 0 Enabled EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 1 OVRIE Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 4 1 read-write OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 read-write AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 EOCALIE End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 11 1 read-write EOCALIE Disabled End of calibration interrupt disabled 0 Enabled End of calibration interrupt enabled 1 CCRDYIE Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 13 1 read-write CCRDYIE Disabled Channel configuration ready interrupt disabled 0 Enabled Channel configuration ready interrupt enabled 1 CR CR ADC control register 0x8 0x20 0x00000000 0xFFFFFFFF ADEN ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0) 0 1 read-write oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 ADDIS ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to 1 is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing) 1 1 read-write oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADSTART ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored. 2 1 read-write oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 ADSTP ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to 1 is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC) 4 1 read-write oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 ADVREGEN ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 28 1 read-write ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 ADCAL ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing). 31 1 read-write oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 CFGR1 CFGR1 ADC configuration register 1 0xC 0x20 0x00000000 0xFFFFFFFF DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 0 1 read-write DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 DMACFG Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 355 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 1 1 read-write DMACFG OneShot DMA one shot mode selected 0 Circular DMA circular mode selected 1 SCANDIR Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 2 1 read-write SCANDIR Upward Upward scan (from CHSEL0 to CHSEL17) 0 Backward Backward scan (from CHSEL17 to CHSEL0) 1 RES Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN = 0. 3 2 read-write RES Bits12 12 bits 0 Bits10 10 bits 1 Bits8 8 bits 2 Bits6 6 bits 3 ALIGN Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 353 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 5 1 read-write ALIGN Right Right alignment 0 Left Left alignment 1 EXTSEL External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 6 3 read-write EXTSEL TIM1_TRGO2 Timer 1 TRGO 2 event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM3_TRGO Timer 3 TRGO event 3 TIM15_TRGO Timer 15 TRGO event 4 EXTI11 EXTI line 11 event 7 EXTEN External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 10 2 read-write EXTEN Disabled Hardware trigger detection disabled 0 RisingEdge Hardware trigger detection on the rising edge 1 FallingEdge Hardware trigger detection on the falling edge 2 BothEdges Hardware trigger detection on both the rising and falling edges 3 OVRMOD Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 12 1 read-write OVRMOD Preserve ADC_DR register is preserved with the old data when an overrun is detected 0 Overwrite ADC_DR register is overwritten with the last conversion result when an overrun is detected 1 CONT Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 13 1 read-write CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 WAIT Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 14 1 read-write WAIT Disabled Wait conversion mode off 0 Enabled Wait conversion mode on 1 AUTOFF Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 15 1 read-write AUTOFF Disabled Auto-off mode disabled 0 Enabled Auto-off mode enabled 1 DISCEN Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 16 1 read-write DISCEN Disabled Discontinuous mode disabled 0 Enabled Discontinuous mode enabled 1 CHSELRMOD Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 21 1 read-write CHSELRMOD BitPerInput Each bit of the ADC_CHSELR register enables an input 0 Sequence ADC_CHSELR register is able to sequence up to 8 channels 1 AWD1SGL Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 22 1 read-write AWD1SGL AllChannels Analog watchdog 1 enabled on all channels 0 SingleChannel Analog watchdog 1 enabled on a single channel 1 AWD1EN Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 23 1 read-write AWD1EN Disabled Analog watchdog 1 disabled 0 Enabled Analog watchdog 1 enabled 1 AWD1CH Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 26 5 read-write 0 17 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 0x00000000 0xFFFFFFFF OVSE Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 1 read-write OVSE Disabled Oversampler disabled 0 Enabled Oversampler enabled 1 OVSR Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 2 3 read-write OVSR Mul2 2x 0 Mul4 4x 1 Mul8 8x 2 Mul16 16x 3 Mul32 32x 4 Mul64 64x 5 Mul128 128x 6 Mul256 256x 7 OVSS Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 5 4 read-write OVSS NoShift No shift 0 Shift1 Shift 1-bit 1 Shift2 Shift 2-bits 2 Shift3 Shift 3-bits 3 Shift4 Shift 4-bits 4 Shift5 Shift 5-bits 5 Shift6 Shift 6-bits 6 Shift7 Shift 7-bits 7 Shift8 Shift 8-bits 8 TOVS Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 9 1 read-write TOVS TriggerAll All oversampled conversions for a channel are done consecutively after a trigger 0 TriggerEach Each oversampled conversion for a channel needs a trigger 1 LFTRIG Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). 29 1 read-write LFTRIG Disabled Low Frequency Trigger Mode disabled 0 Enabled Low Frequency Trigger Mode enabled 1 CKMODE ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 30 2 read-write CKMODE ADCLK ADCCLK (Asynchronous clock mode) 0 PCLK_Div2 PCLK/2 (Synchronous clock mode) 1 PCLK_Div4 PCLK/4 (Synchronous clock mode) 2 PCLK PCLK (Synchronous clock mode) 3 SMPR SMPR ADC sampling time register 0x14 0x20 0x00000000 0xFFFFFFFF 2 0x4 1-2 SMP%s Sampling time selection %s 0 3 read-write SMP1 Cycles1_5 1.5 ADC clock cycles 0 Cycles3_5 3.5 ADC clock cycles 1 Cycles7_5 7.5 ADC clock cycles 2 Cycles12_5 12.5 ADC clock cycles 3 Cycles19_5 19.5 ADC clock cycles 4 Cycles39_5 39.5 ADC clock cycles 5 Cycles79_5 79.5 ADC clock cycles 6 Cycles160_5 160.5 ADC clock cycles 7 23 0x1 0-22 SMPSEL%s Channel-%s sampling time selection 8 1 read-write SMPSEL0 Smp1 Sampling time of CHANNELx use the setting of SMP1 register 0 Smp2 Sampling time of CHANNELx use the setting of SMP2 register 1 AWD1TR AWD1TR ADC watchdog threshold register 0x20 0x20 0x0FFF0000 0xFFFFFFFF LT1 Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359. 0 12 read-write 0 4095 HT1 Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359. 16 12 read-write 0 4095 AWD2TR AWD2TR ADC watchdog threshold register 0x24 0x20 0x0FFF0000 0xFFFFFFFF LT2 Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359. 0 12 read-write 0 4095 HT2 Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359. 16 12 read-write 0 4095 CHSELR0 CHSELR_MOD0 ADC channel selection register [alternate] 0x28 0x20 0x00000000 0xFFFFFFFF 23 0x1 0-22 CHSEL%s Channel-%s selection 0 1 read-write CHSEL0 NotSelected Input Channel is not selected for conversion 0 Selected Input Channel is selected for conversion 1 CHSELR1 CHSELR_MOD1 ADC channel selection register [alternate] CHSELR0 0x28 0x20 0x00000000 0xFFFFFFFF 8 0x4 1-8 SQ%s %s conversion of the sequence 0 4 read-write SQ1 Ch0 Channel 0 selected for the Nth conversion 0 Ch1 Channel 1 selected for the Nth conversion 1 Ch2 Channel 2 selected for the Nth conversion 2 Ch3 Channel 3 selected for the Nth conversion 3 Ch4 Channel 4 selected for the Nth conversion 4 Ch5 Channel 5 selected for the Nth conversion 5 Ch6 Channel 6 selected for the Nth conversion 6 Ch7 Channel 7 selected for the Nth conversion 7 Ch8 Channel 8 selected for the Nth conversion 8 Ch9 Channel 9 selected for the Nth conversion 9 Ch10 Channel 10 selected for the Nth conversion 10 Ch11 Channel 11 selected for the Nth conversion 11 Ch12 Channel 12 selected for the Nth conversion 12 Ch13 Channel 13 selected for the Nth conversion 13 Ch14 Channel 14 selected for the Nth conversion 14 EOS End of sequence 15 AWD3TR AWD3TR ADC watchdog threshold register 0x2C 0x20 0x0FFF0000 0xFFFFFFFF LT3 Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359. 0 12 read-write 0 4095 HT3 Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359. 16 12 read-write 0 4095 DR DR ADC data register 0x40 0x20 0x00000000 0xFFFFFFFF DATA Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 353. Just after a calibration is complete, DATA[6:0] contains the calibration factor. 0 16 read-only 0 65535 AWD2CR AWD2CR ADC Analog Watchdog 2 Configuration register 0xA0 0x20 0x00000000 0xFFFFFFFF 23 0x1 0-22 AWD2CH%s Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 1 read-write AWD2CH0 NotMonitored ADC analog channel-x is not monitored by AWD2 0 Monitored ADC analog channel-x is monitored by AWD2 1 AWD3CR AWD3CR ADC Analog Watchdog 3 Configuration register 0xA4 0x20 0x00000000 0xFFFFFFFF 23 0x1 0-22 AWD3CH%s Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 1 read-write AWD3CH0 NotMonitored ADC analog channel-x is not monitored by AWD3 0 Monitored ADC analog channel-x is monitored by AWD3 1 CALFACT CALFACT ADC Calibration factor 0xB4 0x20 0x00000000 0xFFFFFFFF CALFACT Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection. 0 7 read-write 0 127 CCR CCR ADC common configuration register 0x308 0x20 0x00000000 0xFFFFFFFF PRESC ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 18 4 read-write PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 22 1 read-write VREFEN Disabled The selected ADC channel disabled 0 Enabled The selected ADC channel enabled 1 TSEN Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 23 1 read-write CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR CRC data register 0x0 0x20 0xFFFFFFFF 0xFFFFFFFF DR Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 read-write 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR CRC independent data register 0x4 0x20 0x00000000 0xFFFFFFFF IDR General-purpose 32-bit data register bits 0 32 read-write 0 4294967295 CR CR CRC control register 0x8 0x20 0x00000000 0xFFFFFFFF RESET RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 read-write RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size These bits control the size of the polynomial. 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data These bits control the reversal of the bit order of the input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT CRC initial value 0x10 0x20 0xFFFFFFFF 0xFFFFFFFF INIT Programmable initial CRC value This register is used to write the CRC initial value. 0 32 read-write 0 4294967295 POL POL CRC polynomial 0x14 0x20 0x04C11DB7 0xFFFFFFFF POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32 read-write 0 4294967295 DBG DBG register block DBG 0x40015800 0x0 0x400 registers IDCODE IDCODE DBG device ID code register 0x0 0x20 0x10000453 0xFFFFFFFF DEV_ID Device identifier This bitfield indicates the device ID. 0 12 read-only REV_ID Revision identifier This bitfield indicates the revision of the device. 16 16 read-only CR CR DBG configuration register 0x4 0x20 0x00000000 0xFFFFFFFF DBG_STOP Debug Stop mode 1 1 read-write DBG_STANDBY Debug Standby and Shutdown modes 2 1 read-write APB_FZ1 APB_FZ1 DBG APB freeze register 1 0x8 0x20 0x00000000 0xFFFFFFFF DBG_TIM3_STOP Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted: 1 1 read-write DBG_RTC_STOP Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted: 10 1 read-write DBG_WWDG_STOP Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted: 11 1 read-write DBG_IWDG_STOP Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted: 12 1 read-write DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout when core is halted 21 1 read-write APB_FZ2 APB_FZ2 DBG APB freeze register 2 0xC 0x20 0x00000000 0xFFFFFFFF DBG_TIM1_STOP Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted: 11 1 read-write DBG_TIM14_STOP Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted: 15 1 read-write DBG_TIM16_STOP Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted: 17 1 read-write DBG_TIM17_STOP Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted: 18 1 read-write DMA DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 channel 1 interrupt 9 DMA1_Channel2_3 DMA1 channel 2 and 3 interrupts 10 ISR ISR DMA interrupt status register 0x0 0x20 0x00000000 0xFFFFFFFF 3 0x4 1-3 GIF%s Channel %s Global interrupt flag 0 1 read-only GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 3 0x4 1-3 TCIF%s Channel %s Transfer Complete flag 1 1 read-only TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 3 0x4 1-3 HTIF%s Channel %s Half Transfer Complete flag 2 1 read-only HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 3 0x4 1-3 TEIF%s Channel %s Transfer Error flag 3 1 read-only TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 IFCR IFCR DMA interrupt flag clear register 0x4 0x20 0x00000000 0xFFFFFFFF 3 0x4 1-3 CGIF%s Channel %s Global interrupt clear 0 1 write-only CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 3 0x4 1-3 CTCIF%s Channel %s Transfer Complete clear 1 1 write-only CTCIF1 Clear Clears the TCIF flag in the ISR register 1 3 0x4 1-3 CHTIF%s Channel %s Half Transfer clear 2 1 write-only CHTIF1 Clear Clears the HTIF flag in the ISR register 1 3 0x4 1-3 CTEIF%s Channel %s Transfer Error clear 3 1 write-only CTEIF1 Clear Clears the TEIF flag in the ISR register 1 3 0x14 1-3 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 DMA channel 1 configuration register 0x0 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write EN Disabled Channel disabled 0 Enabled Channel enabled 1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 1 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 2 1 read-write HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 3 1 read-write TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 4 1 read-write DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 5 1 read-write CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 6 1 read-write PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 7 1 read-write PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 8 2 read-write PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 10 2 read-write PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 12 2 read-write PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 14 1 read-write MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 NDTR CNDTR1 DMA channel 1 number of data to transfer register 0x4 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 16 read-write 0 65535 PAR CPAR1 DMA channel 1 peripheral address register 0x8 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 32 read-write MAR CMAR1 DMA channel 1 memory address register 0xC 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 32 read-write DMAMUX DMAMUX register block DMAMUX 0x40020800 0x0 0x800 registers DMAMUX_DMA1_Channel4_5 DMAMUX and DMA1 channel 4 and 5 interrupts 11 3 0x4 0-2 CCR%s C%sCR DMA Multiplexer Channel %s Control register 0x0 0x20 0x00000000 0xFFFFFFFF DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 6 read-write SOIE Synchronization overrun interrupt enable 8 1 read-write SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 EGE Event generation enable 9 1 read-write EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SE Synchronization enable 16 1 read-write SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write 0 31 SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources). 24 5 read-write CSR CSR DMAMUX request line multiplexer interrupt channel status register 0x80 0x20 0x00000000 0xFFFFFFFF 3 0x1 0-2 SOF%s Synchronization Overrun Flag %s 0 1 read-only SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CFR CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 0x20 0x00000000 0xFFFFFFFF 3 0x1 0-2 CSOF%s Synchronization Clear Overrun Flag %s 0 1 write-only oneToClear CSOF0W Clear Clear synchronization flag 1 4 0x4 0-3 RGCR%s RG%sCR DMAMUX request generator channel %s configuration register 0x100 0x20 0x00000000 0xFFFFFFFF SIG_ID Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 0 5 read-write OIE Trigger overrun interrupt enable 8 1 read-write OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 GE DMA request generator channel x enable 16 1 read-write GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 GPOL DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 17 2 read-write GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GNBREQ Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled. 19 5 read-write 0 31 RGSR RGSR DMAMUX request generator interrupt status register 0x140 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 OF%s Generator Overrun Flag %s 0 1 read-only OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR DMAMUX request generator interrupt clear flag register 0x144 0x20 0x00000000 0xFFFFFFFF 4 0x1 0-3 COF%s Generator Clear Overrun Flag %s 0 1 write-only oneToClear COF0W Clear Clear overrun flag 1 EXTI EXTI address block description EXTI 0x40021800 0x0 0x400 registers PVM VDDIO2 monitor interrupt (EXTI line 34 1 EXTI0_1 EXTI line 0 and 1 interrupt 5 EXTI2_3 EXTI line 2 and 3 interrupt 6 EXTI4_15 EXTI line 4 and 15 interrupt 7 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 0 1 read-write RT1 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 1 1 read-write RT2 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 2 1 read-write RT3 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 3 1 read-write RT4 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 4 1 read-write RT5 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 5 1 read-write RT6 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 6 1 read-write RT7 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 7 1 read-write RT8 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 8 1 read-write RT9 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 9 1 read-write RT10 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 10 1 read-write RT11 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 11 1 read-write RT12 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 12 1 read-write RT13 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 13 1 read-write RT14 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 14 1 read-write RT15 Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. 15 1 read-write FTSR1 FTSR1 EXTI falling trigger selection register 1 0x4 0x20 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 0 1 read-write FT1 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 1 1 read-write FT2 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 2 1 read-write FT3 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 3 1 read-write FT4 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 4 1 read-write FT5 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 5 1 read-write FT6 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 6 1 read-write FT7 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 7 1 read-write FT8 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 8 1 read-write FT9 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 9 1 read-write FT10 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 10 1 read-write FT11 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 11 1 read-write FT12 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 12 1 read-write FT13 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 13 1 read-write FT14 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 14 1 read-write FT15 Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. 15 1 read-write SWIER1 SWIER1 EXTI software interrupt event register 1 0x8 0x20 0x00000000 0xFFFFFFFF SWI0 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 0 1 read-write SWI1 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 1 1 read-write SWI2 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 2 1 read-write SWI3 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 3 1 read-write SWI4 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 4 1 read-write SWI5 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 5 1 read-write SWI6 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 6 1 read-write SWI7 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 7 1 read-write SWI8 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 8 1 read-write SWI9 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 9 1 read-write SWI10 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 10 1 read-write SWI11 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 11 1 read-write SWI12 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 12 1 read-write SWI13 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 13 1 read-write SWI14 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 14 1 read-write SWI15 Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. 15 1 read-write RPR1 RPR1 EXTI rising edge pending register 1 0xC 0x20 0x00000000 0xFFFFFFFF RPIF0 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 0 1 read-write RPIF1 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 1 1 read-write RPIF2 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 2 1 read-write RPIF3 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 3 1 read-write RPIF4 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 4 1 read-write RPIF5 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 5 1 read-write RPIF6 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 6 1 read-write RPIF7 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 7 1 read-write RPIF8 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 8 1 read-write RPIF9 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 9 1 read-write RPIF10 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 10 1 read-write RPIF11 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 11 1 read-write RPIF12 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 12 1 read-write RPIF13 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 13 1 read-write RPIF14 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 14 1 read-write RPIF15 Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 15 1 read-write FPR1 FPR1 EXTI falling edge pending register 1 0x10 0x20 0x00000000 0xFFFFFFFF FPIF0 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 0 1 read-write FPIF1 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 1 1 read-write FPIF2 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 2 1 read-write FPIF3 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 3 1 read-write FPIF4 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 4 1 read-write FPIF5 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 5 1 read-write FPIF6 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 6 1 read-write FPIF7 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 7 1 read-write FPIF8 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 8 1 read-write FPIF9 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 9 1 read-write FPIF10 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 10 1 read-write FPIF11 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 11 1 read-write FPIF12 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 12 1 read-write FPIF13 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 13 1 read-write FPIF14 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 14 1 read-write FPIF15 Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. 15 1 read-write EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved 0 8 read-write EXTI1 8 8 read-write EXTI2 16 8 read-write EXTI3 24 8 read-write EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved 0 8 read-write EXTI1 8 8 read-write EXTI2 16 8 read-write EXTI3 24 8 read-write EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved 0 8 read-write EXTI1 8 8 read-write EXTI2 16 8 read-write EXTI3 24 8 read-write EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved 0 8 read-write EXTI1 8 8 read-write EXTI2 16 8 read-write EXTI3 24 8 read-write IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 0x20 0xFFF80000 0xFFFFFFFF IM CPU wakeup with interrupt mask 0 16 read-write IM19 IM19 19 1 read-write IM23 IM23 23 1 read-write IM25 IM25 25 1 read-write IM31 IM31 31 1 read-write EMR1 EMR1 EXTI CPU wakeup with event mask register 0x84 0x20 0x00000000 0xFFFFFFFF EM CPU wakeup with event generation mask 0 16 read-write EM19 EM19 19 1 read-write EM23 EM23 23 1 read-write EM25 EM25 25 1 read-write EM31 EM31 31 1 read-write FLASH FLASH register block FLASH 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 3 ACR ACR FLASH access control register 0x0 0x20 read-write 0x00040600 0xFFFEFFFF LATENCY Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read. 0 3 read-write PRFTEN CPU Prefetch enable 8 1 read-write ICEN CPU Instruction cache enable 9 1 read-write ICRST CPU Instruction cache reset This bit can be written only when the instruction cache is disabled. 11 1 read-write EMPTY Main flash memory area empty This bit indicates whether the first location of the Main flash memory area was read as erased or as programmed during OBL. It is not affected by the system reset. Software may need to change this bit value after a flash memory program or erase operation. The bit can be set and reset by software. 16 1 read-write DBG_SWEN Debug access software enable Software may use this bit to enable/disable the debugger read access. 18 1 read-write KEYR KEYR FLASH key register 0x8 0x20 write-only 0x00000000 0xFFFFFFFF KEY FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB 0 32 write-only OPTKEYR OPTKEYR FLASH option key register 0xC 0x20 write-only 0x00000000 0xFFFFFFFF OPTKEY Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F 0 32 write-only SR SR FLASH status register 0x10 0x20 read-write 0x00000000 0xFFF0FFFF EOP End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1. 0 1 read-write OPERR Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing '1'. 1 1 read-write PROGERR Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1. 3 1 read-write WRPERR Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1. 4 1 read-write PGAERR Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1. 5 1 read-write SIZERR Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1. 6 1 read-write PGSERR Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1. 7 1 read-write MISSERR Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1. 8 1 read-write FASTERR Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1. 9 1 read-write RDERR PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1. 14 1 read-write OPTVERR Option and Engineering bits loading validity error Set by hardware when the options and engineering bits read may not be the one configured by the user or production. If options and engineering bits haven't been properly loaded, OPTVERR is set again after each system reset. Option bytes that fail loading are forced to a safe value, see Section4.4.2: FLASH option byte programming. Cleared by writing 1. 15 1 read-write BSY1 Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. 16 1 read-only CFGBSY Programming or erase configuration busy. This flag is set and reset by hardware. For flash program operation, it is set when the first word is sent, and cleared after the second word is sent when the operation completes or ends with an error. For flash erase operation, it is set when setting the STRT bit of the FLASH_CR register and cleared when the operation completes or ends with an error. When set, a programming or erase operation is ongoing and the corresponding settings in the FLASH control register (FLASH_CR) are used (busy) and cannot be changed. Any other flash operation launch must be postponed. When cleared, the programming and erase settings in the FLASH control register (FLASH_CR) can be modified. Note: The CFGBSY bit is also set when attempting to write locked flash memory (with the first byte sent). When the CFGBSY bit is set, writing into the FLASH_CR register causes HardFault.To clear the CFGBSY bit, send a double word to the flash memory and wait until the access is finished (otherwise the CFGBSY bit remains set). 18 1 read-only CR CR FLASH control register 0x14 0x20 read-write 0xC0000000 0xFFFFFFFF PG Flash memory programming enable 0 1 read-write PER Page erase enable 1 1 read-write MER1 Mass erase When set, this bit triggers the mass erase, that is, all user pages. 2 1 read-write PNB Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the Main memory are not allowed. See Table6 and Table7. 3 6 read-write STRT Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. 16 1 read-write OPTSTRT Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. 17 1 read-write FSTPG Fast programming enable 18 1 read-write EOPIE End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. 24 1 read-write ERRIE Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. 25 1 read-write RDERRIE PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. 26 1 read-write OBL_LAUNCH Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. 27 1 read-write SEC_PROT Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset. 28 1 read-write OPTLOCK Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. 30 1 read-write LOCK FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write OPTR OPTR FLASH option register 0x20 0x20 read-write 0x00000000 0x00000000 RDP Read protection level Other: Level 1, memories read protection active 0 8 read-write BOR_EN Brown out reset enable 8 1 read-write BORR_LEV BOR threshold at rising V_DD supply Rising V_DD crossings this threshold releases the reset signal. 9 2 read-write BORF_LEV BOR threshold at falling V_DD supply Falling V_DD crossings this threshold activates the reset signal. 11 2 read-write NRST_STOP None 13 1 read-write NRST_STDBY None 14 1 read-write NRST_SHDW None 15 1 read-write IWDG_SW None 16 1 read-write IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 read-write IWGD_STDBY None 18 1 read-write WWDG_SW Window watchdog selection 19 1 read-write HSE_NOT_REMAPPED HSE remapping enable/disable When cleared, the bit remaps the HSE clock source from PF0-OSC_IN/PF1-OSC_OUT pins to PC14-OSCX_IN/PC15-OSCX_OUT. Thus PC14-OSCX_IN/PC15-OSCX_OUT are shared by both LSE and HSE and the two clock sources cannot be use simultaneously. On packages with less than 48 pins, the remapping is always enabled (PF0-OSC_IN/PF1-OSC_OUT are not available), regardless of this bit. As all STM32C011xx packages have less than 48 pins, this bit is only applicable to STM32C031xx. Note: On 48 pins packages, when HSE_NOT_REMAPPED is reset, HSE cannot be used in bypass mode. Refer to product errata sheet for more details. 21 1 read-write RAM_PARITY_CHECK SRAM parity check control enable/disable 22 1 read-write SECURE_MUXING_EN Multiple-bonding security The bit allows enabling automatic I/O configuration to prevent conflicts on I/Os connected (bonded) onto the same pin. If the software sets one of the I/Os connected to the same pin as active by configuring the SYSCFG_CFGR3 register, enabling this bit automatically forces the other I/Os in digital input mode, regardless of their software configuration. When the bit is disabled, the SYSCFG_CFGR3 register setting is ignored, all GPIOs linked to a given pin are active and can be set in the mode specified by the corresponding GPIOx_MODER register. The user software must ensure that there is no conflict between GPIOs. 23 1 read-write NBOOT_SEL BOOT0 signal source selection This option bit defines the source of the BOOT0 signal. 24 1 read-write NBOOT1 Boot configuration Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit configuration), this bit selects boot mode from the Main flash memory, SRAM or the System memory. Refer to Section3: Boot configuration. 25 1 read-write NBOOT0 nBOOT0 option bit 26 1 read-write NRST_MODE NRST pin configuration 27 2 read-write IRHEN Internal reset holder enable bit 29 1 read-write PCROP1ASR PCROP1ASR FLASH PCROP area A start address register 0x24 0x20 read-write 0x00000000 0xFFFFFF00 PCROP1A_STRT PCROP1A area start offset Contains the offset of the first subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device. 0 9 read-write PCROP1AER PCROP1AER FLASH PCROP area A end address register 0x28 0x20 read-write 0x00000000 0x7FFFFF00 PCROP1A_END PCROP1A area end offset Contains the offset of the last subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device. 0 9 read-write PCROP_RDP PCROP area erase upon RDP level regression This bit determines whether the PCROP area (and the totality of the PCROP area boundary pages) is erased by the mass erase triggered by the RDP level regression from Level 1 to Level 0: The software can only set this bit. It is automatically reset upon mass erase following the RDP regression from Level 1 to Level 0. 31 1 read-write WRP1AR WRP1AR FLASH WRP area A address register 0x2C 0x20 read-write 0x00000000 0xFFC0FFC0 WRP1A_STRT WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device. 0 7 read-write WRP1A_END WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device. 16 7 read-write WRP1BR WRP1BR FLASH WRP area B address register 0x30 0x20 read-write 0x00000000 0xFFC0FFC0 WRP1B_STRT WRP area B start offset This bitfield contains the offset of the first page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device. 0 7 read-write WRP1B_END WRP area B end offset This bitfield contains the offset of the last page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device. 16 7 read-write PCROP1BSR PCROP1BSR FLASH PCROP area B start address register 0x34 0x20 read-write 0x00000000 0xFFFFFF00 PCROP1B_STRT PCROP1B area start offset Contains the offset of the first subpage of the PCROP1B area. Note: The number of effective bits depends on the size of the flash memory in the device. 0 9 read-write PCROP1BER PCROP1BER FLASH PCROP area B end address register 0x38 0x20 read-write 0x00000000 0xFFFFFF00 PCROP1B_END PCROP1B area end offset Contains the offset of the last subpage of the PCROP1B area. Note: The number of effective bits depends on the size of the flash memory in the device. 0 9 read-write SECR SECR FLASH security register 0x80 0x20 read-write 0x00000000 0xFFFEFF00 SEC_SIZE Securable memory area size Contains the number of securable flash memory pages. Note: The number of effective bits depends on the size of the flash memory in the device. 0 7 read-write BOOT_LOCK used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). 16 1 read-write GPIOA GPIOA address block description GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xEBFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 read-write OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x24000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 16 0x1 0-15 ID%s Port input data pin %s 0 1 read-only InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 OD%s Port output data pin %s 0 1 read-write OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BS%s Port x set pin %s 0 1 write-only BitSet Set Sets the corresponding ODx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 write-only BitReset Reset Resets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 read-write Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 AFSEL%s Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os 0 4 read-write AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF 8 0x4 8-15 AFSEL%s Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os 0 4 read-write BRR BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 BR%s Port x reset pin %s 0 1 write-only BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB GPIOB address block description GPIO 0x50000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xEBFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x24000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOC GPIOC address block description GPIO 0x50000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xEBFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x24000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOD GPIOD address block description GPIO 0x50000C00 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xEBFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x24000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOF GPIOF address block description GPIO 0x50001400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 0xEBFFFFFF 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 read-write OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 0x0C000000 0xFFFFFFFF 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 read-write PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 0x24000000 0xFFFFFFFF 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 read-write IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 I2C1 I2C register block I2C 0x40005400 0x0 0x400 registers I2C global interrupt (combined with EXTI 23) 23 CR1 CR1 I2C control register 1 0x0 0x20 0x00000000 0xFFFFFFFF PE Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 read-write PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 read-write TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 read-write RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match Interrupt enable (slave only) 3 1 read-write ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received Interrupt enable 4 1 read-write NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE Stop detection Interrupt enable 5 1 read-write STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR) 6 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) 7 1 read-write ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 read-write DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 read-write ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 read-write TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 read-write RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 read-write SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 read-write NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . Note: WUPEN can be set only when DNF = 0000 18 1 read-write WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 read-write GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 20 1 read-write SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 21 1 read-write SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 22 1 read-write ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 23 1 read-write PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 I2C control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SADD Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. 0 10 read-write 0 1023 RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 read-write RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 read-write ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 read-write HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set. 13 1 read-write oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect. 14 1 read-write oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 read-write oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 read-write 0 255 RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 read-write RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 read-write AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 26 1 read-write oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 OAR1 OAR1 I2C own address 1 register 0x8 0x20 0x00000000 0xFFFFFFFF OA1 Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0. 0 10 read-write 0 1023 OA1MODE Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 read-write OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 read-write OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 I2C own address 2 register 0xC 0x20 0x00000000 0xFFFFFFFF OA2 Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0. 1 7 read-write 0 127 OA2MSK Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 read-write OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 read-write OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR I2C timing register 0x10 0x20 0x00000000 0xFFFFFFFF SCLL SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings. 0 8 read-write 0 255 SCLH SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing. 8 8 read-write 0 255 SDADEL Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing. 16 4 read-write 0 15 SCLDEL Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing. 20 4 read-write 0 15 PRESC Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to ) and for SCL high and low level counters (refer to ). tPRESC = (PRESC+1) x tI2CCLK 28 4 read-write 0 15 TIMEOUTR TIMEOUTR I2C timeout register 0x14 0x20 0x00000000 0xFFFFFFFF TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. 0 12 read-write 0 4095 TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 read-write TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 read-write TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. 16 12 read-write 0 4095 TEXTEN Extended clock timeout enable 31 1 read-write TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR I2C interrupt and status register 0x18 0x20 0x00000001 0xFFFFFFFF TXE Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0. 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 TXIS Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0. 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 RXNE Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0. 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 ADDR Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0. 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 NACKF Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0. 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 STOPF Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0. 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 TC Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0. 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TCR Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set. 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 BERR Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0. 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 ARLO Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0. 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 OVR Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0. 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 PECERR PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 TIMEOUT Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 ALERT SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 BUSY Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE=0. 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 ADDCODE Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. 17 7 read-only 0 127 ICR ICR I2C interrupt clear register 0x1C 0x20 0x00000000 0xFFFFFFFF ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. 3 1 write-only oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register. 4 1 write-only oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 STOPCF STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. 5 1 write-only oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 BERRCF Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. 8 1 write-only oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 ARLOCF Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. 9 1 write-only oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 OVRCF Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. 10 1 write-only oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 PECCF PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 11 1 write-only oneToClear PECCF Clear Clears the PEC flag in ISR register 1 TIMOUTCF Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 12 1 write-only oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 ALERTCF Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . 13 1 write-only oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 PECR PECR I2C PEC register 0x20 0x20 0x00000000 0xFFFFFFFF PEC Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0. 0 8 read-only 0 255 RXDR RXDR I2C receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RXDATA 8-bit receive data Data byte received from the I2C bus 0 8 read-only 0 255 TXDR TXDR I2C transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TXDATA 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE=1. 0 8 read-write 0 255 IWDG IWDG register block IWDG 0x40003000 0x0 0x400 registers KR KR IWDG key register 0x0 0x10 0x00000000 0x0000FFFF KEY Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see ) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected) 0 16 write-only KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR IWDG prescaler register 0x4 0x10 0x00000000 0x0000FFFF PR Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset. 0 3 read-write PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR IWDG reload register 0x8 0x10 0x00000FFF 0x0000FFFF RL Watchdog counter reload value These bits are write access protected see . They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the . The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the status register (IWDG_SR) is reset. 0 12 read-write 0 4095 SR SR IWDG status register 0xC 0x10 0x00000000 0x0000FFFF PVU Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset. 0 1 read-only RVU Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset. 1 1 read-only WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset. 2 1 read-only WINR WINR IWDG window register 0x10 0x10 0x00000FFF 0x0000FFFF WIN Watchdog counter window value These bits are write access protected, see , they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the (IWDG_SR) is reset. 0 12 read-write 0 4095 PWR PWR address block description PWR 0x40007000 0x0 0x400 registers CR1 CR1 PWR control register 1 0x0 0x20 0x00000208 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode 0 3 read-write FPD_STOP Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. 3 1 read-write FPD_SLP Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode. 5 1 read-write CR3 CR3 PWR control register 3 0x8 0x20 0x00008000 0xFFFFFFFF EWUP1 Enable WKUP1 wakeup pin When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register. 0 1 read-write EWUP2 Enable WKUP2 wakeup pin When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register. 1 1 read-write EWUP3 Enable WKUP3 wakeup pin When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register. 2 1 read-write EWUP4 Enable WKUP4 wakeup pin When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. 3 1 read-write EWUP6 Enable WKUP6 wakeup pin When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register. 5 1 read-write APC Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. 10 1 read-write EIWUL Enable internal wakeup line When set, a rising edge on the internal wakeup line triggers a wakeup event. 15 1 read-write CR4 CR4 PWR control register 4 0xC 0x20 0x00000000 0xFFFFFFFF WP1 WKUP1 wakeup pin polarity WKUP1 external wakeup signal polarity (level or edge) to generate wakeup condition: 0 1 read-write WP2 WKUP2 wakeup pin polarity WKUP2 external wakeup signal polarity (level or edge) to generate wakeup condition: 1 1 read-write WP3 WKUP3 wakeup pin polarity WKUP3 external wakeup signal polarity (level or edge) to generate wakeup condition: 2 1 read-write WP4 WKUP4 wakeup pin polarity WKUP4 external wakeup signal polarity (level or edge) to generate wakeup condition: 3 1 read-write WP6 WKUP6 wakeup pin polarity WKUP6 external wakeup signal polarity (level or edge) to generate wakeup condition: 5 1 read-write SR1 SR1 PWR status register 1 0x10 0x20 0x00000000 0xFFFFFFFF WUF1 Wakeup flag 1 This bit is set when a wakeup condition is detected on WKUP1 wakeup pin. It is cleared by setting the CWUF1 bit of the PWR_SCR register. 0 1 read-only WUF2 Wakeup flag 2 This bit is set when a wakeup condition is detected on WKUP2 wakeup pin. It is cleared by setting the CWUF2 bit of the PWR_SCR register. 1 1 read-only WUF3 Wakeup flag 3 This bit is set when a wakeup condition is detected on WKUP3 wakeup pin. It is cleared by setting the CWUF3 bit of the PWR_SCR register. 2 1 read-only WUF4 Wakeup flag 4 This bit is set when a wakeup condition is detected on WKUP4 wakeup pin. It is cleared by setting the CWUF4 bit of the PWR_SCR register. 3 1 read-only WUF6 Wakeup flag 6 This bit is set when a wakeup condition is detected on WKUP6 wakeup pin. It is cleared by setting the CWUF6 bit of the PWR_SCR register. 5 1 read-only SBF Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. 8 1 read-only WUFI Wakeup flag internal This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. 15 1 read-only SR2 SR2 PWR status register 2 0x14 0x20 0x00000000 0xFFFFFFFF FLASH_RDY Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory. 7 1 read-only SCR SCR PWR status clear register 0x18 0x20 0x00000000 0xFFFFFFFF CWUF1 Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. 0 1 write-only CWUF2 Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. 1 1 write-only CWUF3 Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. 2 1 write-only CWUF4 Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. 3 1 write-only CWUF6 Clear wakeup flag 6 Setting this bit clears the WUF6 flag in the PWR_SR1 register. 5 1 write-only CSBF Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. 8 1 write-only PUCRA PUCRA PWR Port A pull-up control register 0x20 0x20 0x00000000 0xFFFFFFFF PU0 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 0 1 read-write PU1 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 1 1 read-write PU2 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 2 1 read-write PU3 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 3 1 read-write PU4 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 4 1 read-write PU5 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 5 1 read-write PU6 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 6 1 read-write PU7 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 7 1 read-write PU8 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 8 1 read-write PU9 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 9 1 read-write PU10 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 10 1 read-write PU11 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 11 1 read-write PU12 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 12 1 read-write PU13 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 13 1 read-write PU14 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 14 1 read-write PU15 Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. 15 1 read-write PDCRA PDCRA PWR Port A pull-down control register 0x24 0x20 0x00000000 0xFFFFFFFF PD0 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 0 1 read-write PD1 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 1 1 read-write PD2 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 2 1 read-write PD3 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 3 1 read-write PD4 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 4 1 read-write PD5 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 5 1 read-write PD6 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 6 1 read-write PD7 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 7 1 read-write PD8 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 8 1 read-write PD9 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 9 1 read-write PD10 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 10 1 read-write PD11 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 11 1 read-write PD12 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 12 1 read-write PD13 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 13 1 read-write PD14 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 14 1 read-write PD15 Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. 15 1 read-write PUCRB PUCRB PWR Port B pull-up control register 0x28 0x20 0x00000000 0xFFFFFFFF PU0 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 0 1 read-write PU1 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 1 1 read-write PU2 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 2 1 read-write PU3 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 3 1 read-write PU4 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 4 1 read-write PU5 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 5 1 read-write PU6 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 6 1 read-write PU7 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 7 1 read-write PU8 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 8 1 read-write PU9 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 9 1 read-write PU10 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 10 1 read-write PU11 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 11 1 read-write PU12 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 12 1 read-write PU13 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 13 1 read-write PU14 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 14 1 read-write PU15 Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available 15 1 read-write PDCRB PDCRB PWR Port B pull-down control register 0x2C 0x20 0x00000000 0xFFFFFFFF PD0 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 0 1 read-write PD1 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 1 1 read-write PD2 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 2 1 read-write PD3 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 3 1 read-write PD4 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 4 1 read-write PD5 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 5 1 read-write PD6 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 6 1 read-write PD7 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 7 1 read-write PD8 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 8 1 read-write PD9 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 9 1 read-write PD10 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 10 1 read-write PD11 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 11 1 read-write PD12 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 12 1 read-write PD13 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 13 1 read-write PD14 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 14 1 read-write PD15 Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available 15 1 read-write PUCRC PUCRC PWR Port C pull-up control register 0x30 0x20 0x00000000 0xFFFFFFFF PU6 Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available 6 1 read-write PU7 Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available 7 1 read-write PU13 Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available 13 1 read-write PU14 Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available 14 1 read-write PU15 Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available 15 1 read-write PDCRC PDCRC PWR Port C pull-down control register 0x34 0x20 0x00000000 0xFFFFFFFF PD6 Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available. 6 1 read-write PD7 Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available. 7 1 read-write PD13 Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available. 13 1 read-write PD14 Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available. 14 1 read-write PD15 Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available. 15 1 read-write PUCRD PUCRD PWR Port D pull-up control register 0x38 0x20 0x00000000 0xFFFFFFFF PU0 Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. 0 1 read-write PU1 Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. 1 1 read-write PU2 Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. 2 1 read-write PU3 Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. 3 1 read-write PDCRD PDCRD PWR Port D pull-down control register 0x3C 0x20 0x00000000 0xFFFFFFFF PD0 Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. 0 1 read-write PD1 Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. 1 1 read-write PD2 Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. 2 1 read-write PD3 Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. 3 1 read-write PUCRF PUCRF PWR Port F pull-up control register 0x48 0x20 0x00000000 0xFFFFFFFF PU0 Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available. 0 1 read-write PU1 Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available. 1 1 read-write PU2 Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available. 2 1 read-write PDCRF PDCRF PWR Port F pull-down control register 0x4C 0x20 0x00000000 0xFFFFFFFF PD0 Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available. 0 1 read-write PD1 Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available. 1 1 read-write PD2 Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available. 2 1 read-write RCC RCC address block description RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 4 CR CR RCC clock control register 0x0 0x20 0x00001540 0xFFFFFFFF SYSDIV System clock division factor This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock: 2 3 read-write HSIKERDIV HSI48 kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock: 5 3 read-write HSION HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source. 8 1 read-write HSIKERON HSI48 always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock. Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode. 9 1 read-write HSIRDY HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles. 10 1 read-only HSIDIV HSI48 clock division factor This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock: 11 3 read-write HSEON HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock. 16 1 read-write HSERDY HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles. 17 1 read-only HSEBYP HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled. 18 1 read-write CSSON Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset. 19 1 read-write ICSCR ICSCR RCC internal clock source calibration register 0x4 0x20 0x00004000 0xFFFFFF00 HSICAL HSI48 clock calibration This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64. 0 8 read-only HSITRIM HSI48 clock trimming The value of this bitfield contributes to the HSICAL[7:0] bitfield value. It allows HSI48 clock frequency user trimming. The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value. 8 7 read-write CFGR CFGR RCC clock configuration register 0x8 0x20 0x00000000 0xFFFFFFFF SW System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. 0 3 read-write SWS System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved 3 3 read-only HPRE AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 8 4 read-write PPRE APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1 12 3 read-write MCO2SEL Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. 16 4 read-write MCO2PRE Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled. 20 4 read-write MCOSEL Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO. 24 4 read-write MCOPRE Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled. 28 4 read-write CIER CIER RCC clock interrupt enable register 0x18 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: 0 1 read-write LSERDYIE LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: 1 1 read-write HSIRDYIE HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization: 3 1 read-write HSERDYIE HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: 4 1 read-write CIFR CIFR RCC clock interrupt flag register 0x1C 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0 1 read-only LSERDYF LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 1 1 read-only HSIRDYF HSI16 ready interrupt flag This flag indicates a pending interrupt upon HSI16 clock getting ready. Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 3 1 read-only HSERDYF HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. 4 1 read-only CSSF HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 8 1 read-only LSECSSF LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. 9 1 read-only CICR CICR RCC clock interrupt clear register 0x20 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0 1 write-only LSERDYC LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 1 1 write-only HSIRDYC HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag. 3 1 write-only HSERDYC HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 4 1 write-only CSSC Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. 8 1 write-only LSECSSC LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. 9 1 write-only IOPRSTR IOPRSTR RCC I/O port reset register 0x24 0x20 0x00000000 0xFFFFFFFF GPIOARST I/O port A reset This bit is set and cleared by software. 0 1 read-write GPIOBRST I/O port B reset This bit is set and cleared by software. 1 1 read-write GPIOCRST I/O port C reset This bit is set and cleared by software. 2 1 read-write GPIODRST I/O port D reset This bit is set and cleared by software. 3 1 read-write GPIOFRST I/O port F reset This bit is set and cleared by software. 5 1 read-write AHBRSTR AHBRSTR RCC AHB peripheral reset register 0x28 0x20 0x00000000 0xFFFFFFFF DMA1RST DMA1 and DMAMUX reset Set and cleared by software. 0 1 read-write FLASHRST Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode. 8 1 read-write CRCRST CRC reset Set and cleared by software. 12 1 read-write APBRSTR1 APBRSTR1 RCC APB peripheral reset register 1 0x2C 0x20 0x00000000 0xFFFFFFFF TIM3RST TIM3 timer reset Set and cleared by software. 1 1 read-write USART2RST USART2 reset Set and cleared by software. 17 1 read-write I2C1RST I2C1 reset Set and cleared by software. 21 1 read-write DBGRST Debug support reset Set and cleared by software. 27 1 read-write PWRRST Power interface reset Set and cleared by software. 28 1 read-write APBRSTR2 APBRSTR2 RCC APB peripheral reset register 2 0x30 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG reset Set and cleared by software. 0 1 read-write TIM1RST TIM1 timer reset Set and cleared by software. 11 1 read-write SPI1RST SPI1 reset Set and cleared by software. 12 1 read-write USART1RST USART1 reset Set and cleared by software. 14 1 read-write TIM14RST TIM14 timer reset Set and cleared by software. 15 1 read-write TIM16RST TIM16 timer reset Set and cleared by software. 17 1 read-write TIM17RST TIM16 timer reset Set and cleared by software. 18 1 read-write ADCRST ADC reset Set and cleared by software. 20 1 read-write IOPENR IOPENR RCC I/O port clock enable register 0x34 0x20 0x00000000 0xFFFFFFFF GPIOAEN I/O port A clock enable This bit is set and cleared by software. 0 1 read-write GPIOBEN I/O port B clock enable This bit is set and cleared by software. 1 1 read-write GPIOCEN I/O port C clock enable This bit is set and cleared by software. 2 1 read-write GPIODEN I/O port D clock enable This bit is set and cleared by software. 3 1 read-write GPIOFEN I/O port F clock enable This bit is set and cleared by software. 5 1 read-write AHBENR AHBENR RCC AHB peripheral clock enable register 0x38 0x20 0x00000100 0xFFFFFFFF DMA1EN DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. 0 1 read-write FLASHEN Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode. 8 1 read-write CRCEN CRC clock enable Set and cleared by software. 12 1 read-write APBENR1 APBENR1 RCC APB peripheral clock enable register 1 0x3C 0x20 0x00000000 0xFFFFFFFF TIM3EN TIM3 timer clock enable Set and cleared by software. 1 1 read-write RTCAPBEN RTC APB clock enable Set and cleared by software. 10 1 read-write WWDGEN WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. 11 1 read-write USART2EN USART2 clock enable Set and cleared by software. 17 1 read-write I2C1EN I2C1 clock enable Set and cleared by software. 21 1 read-write DBGEN Debug support clock enable Set and cleared by software. 27 1 read-write PWREN Power interface clock enable Set and cleared by software. 28 1 read-write APBENR2 APBENR2 RCC APB peripheral clock enable register 2 0x40 0x20 0x00000000 0xFFFFFFFF SYSCFGEN SYSCFG clock enable Set and cleared by software. 0 1 read-write TIM1EN TIM1 timer clock enable Set and cleared by software. 11 1 read-write SPI1EN SPI1 clock enable Set and cleared by software. 12 1 read-write USART1EN USART1 clock enable Set and cleared by software. 14 1 read-write TIM14EN TIM14 timer clock enable Set and cleared by software. 15 1 read-write TIM16EN TIM16 timer clock enable Set and cleared by software. 17 1 read-write TIM17EN TIM16 timer clock enable Set and cleared by software. 18 1 read-write ADCEN ADC clock enable Set and cleared by software. 20 1 read-write IOPSMENR IOPSMENR RCC I/O port in Sleep mode clock enable register 0x44 0x20 0x0000002F 0xFFFFFFFF GPIOASMEN I/O port A clock enable during Sleep mode Set and cleared by software. 0 1 read-write GPIOBSMEN I/O port B clock enable during Sleep mode Set and cleared by software. 1 1 read-write GPIOCSMEN I/O port C clock enable during Sleep mode Set and cleared by software. 2 1 read-write GPIODSMEN I/O port D clock enable during Sleep mode Set and cleared by software. 3 1 read-write GPIOFSMEN I/O port F clock enable during Sleep mode Set and cleared by software. 5 1 read-write AHBSMENR AHBSMENR RCC AHB peripheral clock enable in Sleep/Stop mode register 0x48 0x20 0x00001301 0xFFFFFFFF DMA1SMEN DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. 0 1 read-write FLASHSMEN Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 8 1 read-write SRAMSMEN SRAM clock enable during Sleep mode Set and cleared by software. 9 1 read-write CRCSMEN CRC clock enable during Sleep mode Set and cleared by software. 12 1 read-write APBSMENR1 APBSMENR1 RCC APB peripheral clock enable in Sleep/Stop mode register 1 0x4C 0x20 0x186F7C03 0xFFFFFFFF TIM3SMEN TIM3 timer clock enable during Sleep mode Set and cleared by software. 1 1 read-write RTCAPBSMEN RTC APB clock enable during Sleep mode Set and cleared by software. 10 1 read-write WWDGSMEN WWDG clock enable during Sleep and Stop modes Set and cleared by software. 11 1 read-write USART2SMEN USART2 clock enable during Sleep and Stop modes Set and cleared by software. 17 1 read-write I2C1SMEN I2C1 clock enable during Sleep and Stop modes Set and cleared by software. 21 1 read-write DBGSMEN Debug support clock enable during Sleep mode Set and cleared by software. 27 1 read-write PWRSMEN Power interface clock enable during Sleep mode Set and cleared by software. 28 1 read-write APBSMENR2 APBSMENR2 RCC APB peripheral clock enable in Sleep/Stop mode register 2 0x50 0x20 0x0017D801 0xFFFFFFFF SYSCFGSMEN SYSCFG clock enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write TIM1SMEN TIM1 timer clock enable during Sleep mode Set and cleared by software. 11 1 read-write SPI1SMEN SPI1 clock enable during Sleep mode Set and cleared by software. 12 1 read-write USART1SMEN USART1 clock enable during Sleep and Stop modes Set and cleared by software. 14 1 read-write TIM14SMEN TIM14 timer clock enable during Sleep mode Set and cleared by software. 15 1 read-write TIM16SMEN TIM16 timer clock enable during Sleep mode Set and cleared by software. 17 1 read-write TIM17SMEN TIM16 timer clock enable during Sleep mode Set and cleared by software. 18 1 read-write ADCSMEN ADC clock enable during Sleep mode Set and cleared by software. 20 1 read-write CCIPR CCIPR RCC peripherals independent clock configuration register 0x54 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows: 0 2 read-write I2C1SEL I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows: 12 2 read-write I2S1SEL I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows: 14 2 read-write ADCSEL ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC: 30 2 read-write CSR1 CSR1 RCC control/status register 1 0x5C 0x20 0x00000000 0xFFFFFFFF LSEON LSE oscillator enable Set and cleared by software to enable LSE oscillator: 0 1 read-write LSERDY LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 1 1 read-only LSEBYP LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 2 1 read-write LSEDRV LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. 3 2 read-write LSECSSON CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit. 5 1 read-write LSECSSD CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE): 6 1 read-only RTCSEL RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00. 8 2 read-write RTCEN RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. 15 1 read-write RTCRST RTC domain software reset Set and cleared by software to reset the RTC domain: 16 1 read-write LSCOEN Low-speed clock output (LSCO) enable Set and cleared by software. 24 1 read-write LSCOSEL Low-speed clock output selection Set and cleared by software to select the low-speed output clock: 25 1 read-write CSR2 CSR2 RCC control/status register 2 0x60 0x20 0x00000000 0x00FFFFFF LSION LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator: 0 1 read-write LSIRDY LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. 1 1 read-only RMVF Remove reset flags Set by software to clear the reset flags. 23 1 read-write OBLRSTF Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit. 25 1 read-only PINRSTF Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit. 26 1 read-only PWRRSTF BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit. 27 1 read-only SFTRSTF Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit. 28 1 read-only IWDGRSTF Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit. 29 1 read-only WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit. 30 1 read-only LPWRRSTF Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared. 31 1 read-only RTC RTC register block RTC 0x40002800 0x0 0x400 registers RTC RTC interrupts (EXTI lines 19) 2 TR TR RTC time register 0x0 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 DR DR RTC date register 0x4 0x20 0x00002101 0xFFFFFFFF DU Date units in BCD format 0 4 read-write 0 15 DT Date tens in BCD format 4 2 read-write 0 3 MU Month units in BCD format 8 4 read-write 0 15 MT Month tens in BCD format 12 1 read-write 0 1 WDU Week day units ... 13 3 read-write 1 7 YU Year units in BCD format 16 4 read-write 0 15 YT Year tens in BCD format 20 4 read-write 0 15 SSR SSR RTC sub second register 0x8 0x20 0x00000000 0xFFFFFFFF SS Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 16 read-only 0 65535 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 0xFFFFFFFF ALRAWF Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0 1 read-only SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Power-on reset state). 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to . 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER RTC prescaler register 0x10 0x20 0x007F00FF 0xFFFFFFFF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 read-write 0 32767 PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 read-write 0 127 CR CR RTC control register 0x18 0x20 0x00000000 0xFFFFFFFF TSEDGE Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF. 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 read-write FMT TwentyFourHour 24 hour/day format 0 AmPm AM/PM hour format 1 ALRAE Alarm A enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 ALRAIE Alarm A interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 TSIE Timestamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write BKP DSTNotChanged Daylight Saving Time change has not been performed 0 DSTChanged Daylight Saving Time change has been performed 1 COSEL Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to . 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity This bit is used to configure the polarity of TAMPALRM output. 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection These bits are used to select the flag to be routed to TAMPALRM output. 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable This bit enables the CALIB output 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 TAMPALRM_PU TAMPALRM pull-up enable 29 1 read-write TAMPALRM_PU NoPullUp No pull-up is applied on TAMPALRM output 0 PullUp A pull-up is applied on TAMPALRM output 1 TAMPALRM_TYPE TAMPALRM output type 30 1 read-write TAMPALRM_TYPE PushPull TAMPALRM is push-pull output 0 OpenDrain TAMPALRM is open-drain output 1 OUT2EN RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different of 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different of 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSELdifferent of 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1. 31 1 read-write OUT2EN Disabled RTC output 2 disable 0 Enabled RTC output 2 enable 1 WPR WPR RTC write protection register 0x24 0x20 0x00000000 0xFFFFFFFF KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection. 0 8 write-only KEY Activate Activate write protection (any value that is not the keys) 0 Deactivate2 Key 2 83 Deactivate1 Key 1 202 CALR CALR RTC calibration register 0x28 0x20 0x00000000 0xFFFFFFFF CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See . 0 9 read-write 0 511 CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration. 13 1 read-write CALW16 SixteenSeconds When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration. 14 1 read-write CALW8 EightSeconds When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALP Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 CALP) - CALM. Refer to . 15 1 read-write CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 SHIFTR SHIFTR RTC shift control register 0x2C 0x20 0x00000000 0xFFFFFFFF SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. 0 15 write-only 0 32767 ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 write-only ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR RTC timestamp time register 0x30 TSDR TSDR RTC timestamp date register 0x34 TSSSR TSSSR RTC timestamp sub second register 0x38 ALRMAR ALRMAR Alarm register 0x40 0x20 0x00000000 0xFFFFFFFF SU Second units in BCD format 0 4 read-write 0 15 ST Second tens in BCD format 4 3 read-write 0 7 MSK1 Alarm seconds mask 7 1 read-write MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MNU Minute units in BCD format 8 4 read-write 0 15 MNT Minute tens in BCD format 12 3 read-write 0 7 MSK2 Alarm minutes mask 15 1 read-write HU Hour units in BCD format 16 4 read-write 0 15 HT Hour tens in BCD format 20 2 read-write 0 3 PM AM/PM notation 22 1 read-write PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 read-write DU Date units or day in BCD format 24 4 read-write 0 15 DT Date tens in BCD format 28 2 read-write 0 3 WDSEL Week day selection 30 1 read-write WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 MSK4 Alarm date mask 31 1 read-write ALRMASSR ALRMASSR Alarm sub-second register 0x44 0x20 0x00000000 0xFFFFFFFF SS Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 0 15 read-write 0 32767 MASKSS Mask the most-significant bits starting at this bit 2: SS[14:2] are dont care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are dont care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are dont care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are dont care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is dont care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 read-write SR SR RTC status register 0x50 0x20 0x00000000 0xFFFFFFFF ALRAF Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). 0 1 read-only ALRAF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR) 1 TSF Timestamp flag This flag is set by hardware when a timestamp event occurs. 3 1 read-only TSF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVF Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 MISR MISR RTC masked interrupt status register 0x54 0x20 0x00000000 0xFFFFFFFF ALRAMF Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs. 0 1 read-only ALRAMF Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 TSMF Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. 3 1 read-only TSMF TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSOVMF Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 read-only TSOVMF Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 SCR SCR RTC status clear register 0x5C 0x20 0x00000000 0xFFFFFFFF CALRAF Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. 0 1 write-only CALRAF Clear Clear interrupt flag 1 CTSF Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. 3 1 write-only CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. 4 1 write-only SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI SPI/I2S global interrupt 25 CR1 CR1 SPI control register 1 0x0 0x10 0x00000000 0x0000FFFF CPHA Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode. 0 1 read-write CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CPOL Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode. 1 1 read-write CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 MSTR Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode. 2 1 read-write MSTR Slave Slave configuration 0 Master Master configuration 1 BR Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode. 3 3 read-write BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 SPE SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page 1349. This bit is not used in I2S mode. 6 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 LSBFIRST Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode. 7 1 read-write LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SSI Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode. 8 1 read-write SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 SSM Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode. 9 1 read-write SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 RXONLY Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode. 10 1 read-write RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 CRCL CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. This bit is not used in I2S mode. 11 1 read-write CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 CRCNEXT Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode. 12 1 read-write CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCEN Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. This bit is not used in I2S mode. 13 1 read-write CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 BIDIOE Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode. 14 1 read-write BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 BIDIMODE Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode. 15 1 read-write BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 CR2 CR2 SPI control register 2 0x4 0x10 0x00000700 0x0000FFFF RXDMAEN Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. 0 1 read-write RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. 1 1 read-write TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable Note: This bit is not used in I2S mode and SPI TI mode. 2 1 read-write SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode. 3 1 read-write NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode. 4 1 read-write FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). 5 1 read-write ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 read-write RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 read-write TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I2S mode. 8 4 read-write DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode. 12 1 read-write FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in IS mode. 13 1 read-write LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in IS mode. 14 1 read-write LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR SPI status register 0x8 0x10 0x00000002 0x0000FFFF RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CHSIDE Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode. 2 1 read-only CHSIDE Left Channel left has to be transmitted or has been received 0 Right Channel right has to be transmitted or has been received 1 UDR Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence. Note: This bit is not used in SPI mode. 3 1 read-only UDRR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 CRCERR CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode. 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page 1359 for the software sequence. Note: This bit is not used in I2S mode. 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence. 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and . 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPI_SR is read by software. 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in IS mode and in SPI receive-only mode while CRC calculation is enabled. 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode. 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR SPI data register 0xC 0x10 0x00000000 0x0000FFFF DR Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. 0 16 read-write 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR SPI CRC polynomial register 0x10 0x10 0x00000007 0x0000FFFF CRCPOLY CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. 0 16 read-write 0 65535 RXCRCR RXCRCR SPI Rx CRC register 0x14 0x10 0x00000000 0x0000FFFF RXCRC Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode. 0 16 read-only 0 65535 TXCRCR TXCRCR SPI Tx CRC register 0x18 0x10 0x00000000 0x0000FFFF TXCRC Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. 0 16 read-only 0 65535 I2SCFGR I2SCFGR SPI_I2S configuration register 0x1C 0x10 0x00000000 0x0000FFFF CHLEN Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. 0 1 read-write CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 DATLEN Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode. 1 2 read-write DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CKPOL Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. 3 1 read-write CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 I2SSTD I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode. 4 2 read-write I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 PCMSYNC PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. 7 1 read-write PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SCFG I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode. 8 2 read-write I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 I2SE I2S enable Note: This bit is not used in SPI mode. 10 1 read-write I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SMOD I2S mode selection Note: This bit should be configured when the SPI is disabled. 11 1 read-write I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 ASTRTEN Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information. 12 1 read-write ASTRTEN AsyncStartDisabled Asynchronous start disabled 0 AsyncStartEnabled Asynchronous start enabled 1 I2SPR I2SPR SPI_I2S prescaler register 0x20 0x10 0x00000002 0x0000FFFF I2SDIV I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode. 0 8 read-write 2 255 ODD Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode. 8 1 read-write ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 MCKOE Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode. 9 1 read-write MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 SYSCFG SYSCFG register block SYSCFG 0x40010000 0x0 0x400 registers CFGR1 CFGR1 SYSCFG configuration register 1 0x0 0x20 0x00000000 0xFFFFFFF0 MEM_MODE Memory mapping selection bits This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to for more details. x0: Main Flash memory 0 2 read-write PA11_RMP PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. 3 1 read-write PA12_RMP PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. 4 1 read-write IR_POL IR output polarity selection 5 1 read-write IR_MOD IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: 6 2 read-write I2C_PB6_FMP Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 16 1 read-write I2C_PB7_FMP Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 17 1 read-write I2C_PB8_FMP Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 18 1 read-write I2C_PB9_FMP Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 19 1 read-write I2C1_FMP Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. 20 1 read-write I2C_PA9_FMP Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 22 1 read-write I2C_PA10_FMP Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 23 1 read-write I2C_PC14_FMP Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. 24 1 read-write CFGR2 CFGR2 SYSCFG configuration register 2 0x18 0x20 0x00000000 0xFFFFFFFF LOCKUP_LOCK Cortex<Superscript><Default Font>-M0+ LOCKUP enable This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript><Default Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input. 0 1 read-write CFGR3 CFGR3 SYSCFG configuration register 3 0x3C 0x20 0x00000000 0xFFFFFFFF PINMUX0 Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Pin F2 of WLCSP14 package GPIO assignment 1x: Reserved 0 2 read-write PINMUX1 Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 2 2 read-write PINMUX2 Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved 4 2 read-write PINMUX3 Pin GPIO multiplexer 3 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 6 2 read-write PINMUX4 Pin GPIO multiplexer 4 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved 8 2 read-write PINMUX5 Pin GPIO multiplexer 5 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 10 2 read-write ITLINE0 ITLINE0 SYSCFG interrupt line 0 status register 0x80 0x20 0x00000000 0xFFFFFFFF WWDG Window watchdog interrupt pending flag 0 1 read-only ITLINE2 ITLINE2 SYSCFG interrupt line 2 status register 0x88 0x20 0x00000000 0xFFFFFFFF RTC RTC interrupt request pending (EXTI line 19) 1 1 read-only ITLINE3 ITLINE3 SYSCFG interrupt line 3 status register 0x8C 0x20 0x00000000 0xFFFFFFFF FLASH_ITF Flash interface interrupt request pending 1 1 read-only ITLINE4 ITLINE4 SYSCFG interrupt line 4 status register 0x90 0x20 0x00000000 0xFFFFFFFF RCC Reset and clock control interrupt request pending 0 1 read-only ITLINE5 ITLINE5 SYSCFG interrupt line 5 status register 0x94 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTI line 0 interrupt request pending 0 1 read-only EXTI1 EXTI line 1 interrupt request pending 1 1 read-only ITLINE6 ITLINE6 SYSCFG interrupt line 6 status register 0x98 0x20 0x00000000 0xFFFFFFFF EXTI2 EXTI line 2 interrupt request pending 0 1 read-only EXTI3 EXTI line 3 interrupt request pending 1 1 read-only ITLINE7 ITLINE7 SYSCFG interrupt line 7 status register 0x9C 0x20 0x00000000 0xFFFFFFFF EXTI4 EXTI line 4 interrupt request pending 0 1 read-only EXTI5 EXTI line 5 interrupt request pending 1 1 read-only EXTI6 EXTI line 6 interrupt request pending 2 1 read-only EXTI7 EXTI line 7 interrupt request pending 3 1 read-only EXTI8 EXTI line 8 interrupt request pending 4 1 read-only EXTI9 EXTI line 9 interrupt request pending 5 1 read-only EXTI10 EXTI line 10 interrupt request pending 6 1 read-only EXTI11 EXTI line 11 interrupt request pending 7 1 read-only EXTI12 EXTI line 12 interrupt request pending 8 1 read-only EXTI13 EXTI line 13 interrupt request pending 9 1 read-only EXTI14 EXTI line 14 interrupt request pending 10 1 read-only EXTI15 EXTI line 15 interrupt request pending 11 1 read-only ITLINE9 ITLINE9 SYSCFG interrupt line 9 status register 0xA4 0x20 0x00000000 0xFFFFFFFF DMA1_CH1 DMA1 channel 1interrupt request pending 0 1 read-only ITLINE10 ITLINE10 SYSCFG interrupt line 10 status register 0xA8 0x20 0x00000000 0xFFFFFFFF DMA1_CH2 DMA1 channel 2 interrupt request pending 0 1 read-only DMA1_CH3 DMA1 channel 3 interrupt request pending 1 1 read-only ITLINE11 ITLINE11 SYSCFG interrupt line 11 status register 0xAC 0x20 0x00000000 0xFFFFFFFF DMAMUX DMAMUX interrupt request pending 0 1 read-only ITLINE12 ITLINE12 SYSCFG interrupt line 12 status register 0xB0 0x20 0x00000000 0xFFFFFFFF ADC ADC interrupt request pending 0 1 read-only ITLINE13 ITLINE13 SYSCFG interrupt line 13 status register 0xB4 0x20 0x00000000 0xFFFFFFFF TIM1_CCU Timer 1 commutation interrupt request pending 0 1 read-only TIM1_TRG Timer 1 trigger interrupt request pending 1 1 read-only TIM1_UPD Timer 1 update interrupt request pending 2 1 read-only TIM1_BRK Timer 1 break interrupt request pending 3 1 read-only ITLINE14 ITLINE14 SYSCFG interrupt line 14 status register 0xB8 0x20 0x00000000 0xFFFFFFFF TIM1_CC Timer 1 capture compare interrupt request pending 0 1 read-only ITLINE16 ITLINE16 SYSCFG interrupt line 16 status register 0xC0 0x20 0x00000000 0xFFFFFFFF TIM3 Timer 3 interrupt request pending 0 1 read-only ITLINE19 ITLINE19 SYSCFG interrupt line 19 status register 0xCC 0x20 0x00000000 0xFFFFFFFF TIM14 Timer 14 interrupt request pending 0 1 read-only ITLINE21 ITLINE21 SYSCFG interrupt line 21 status register 0xD4 0x20 0x00000000 0xFFFFFFFF TIM16 Timer 16 interrupt request pending 0 1 read-only ITLINE22 ITLINE22 SYSCFG interrupt line 22 status register 0xD8 0x20 0x00000000 0xFFFFFFFF TIM17 Timer 17 interrupt request pending 0 1 read-only ITLINE23 ITLINE23 SYSCFG interrupt line 23 status register 0xDC 0x20 0x00000000 0xFFFFFFFF I2C1 I2C1 interrupt request pending, combined with EXTI line 23 0 1 read-only ITLINE25 ITLINE25 SYSCFG interrupt line 25 status register 0xE4 0x20 0x00000000 0xFFFFFFFF SPI1 SPI1 interrupt request pending 0 1 read-only ITLINE27 ITLINE27 SYSCFG interrupt line 27 status register 0xEC 0x20 0x00000000 0xFFFFFFFF USART1 USART1 interrupt request pending, combined with EXTI line 25 0 1 read-only ITLINE28 ITLINE28 SYSCFG interrupt line 28 status register 0xF0 0x20 0x00000000 0xFFFFFFFF USART2 USART2 interrupt request pending (EXTI line 26) 0 1 read-only TIM1 Advanced-control timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 break, update, trigger and commutation interrupts 13 TIM1_CC TIM1 Capture Compare interrupt 14 CR1 CR1 TIM1 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT. 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write CR2 CR2 TIM1 control register 2 0x4 0x20 0x00000000 0xFFFFFFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write TI1S TI1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 20 4 read-write SMCR SMCR TIM1 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write OCCS OCREF clear selection This bit is used to select the OCREF clear source. 3 1 read-write TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write DIER DIER TIM1 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 read-write COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM1 status register 0x10 0x20 0x00000000 0xFFFFFFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 8 1 read-write zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 SBIF System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 13 1 read-write zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 CC5IF Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output) 16 1 read-write zeroToClear read write CC6IF Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output) 17 1 read-write zeroToClear read write EGR EGR TIM1 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 8 1 write-only B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Input CCMR1_Input TIM1 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM1 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM1 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM1 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM1 capture/compare enable register 0x20 0x20 0x00000000 0xFFFFFFFF 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM1 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM1 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM1 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR TIM1 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 BDTR BDTR TIM1 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BK2F Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 20 4 read-write BK2E Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 24 1 read-write BK2P Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 25 1 read-write BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BK2DSRM Break2 Disarm Refer to BKDSRM description 27 1 read-write BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write BK2BID Break2 bidirectional Refer to BKBID description 29 1 read-write DCR DCR TIM1 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. 8 5 read-write 0 18 DMAR DMAR TIM1 DMA address for full transfer 0x4C 0x20 0x00000000 0xFFFFFFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 32 read-write CCMR3_Output CCMR3_Output TIM1 capture/compare mode register 3 0x54 0x20 0x00000000 0xFFFFFFFF 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 5-6 OC%sM Output compare %s mode 4 3 read-write 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCR5 CCR5 capture/compare register 0x58 0x20 0x00000000 0xFFFFFFFF CCR Capture/Compare value 0 16 read-write 0 65535 GC5C1 Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 29 1 read-write GC5C2 Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 30 1 read-write GC5C3 Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 31 1 read-write CCR6 CCR6 capture/compare register 0x5C 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 4 read-write AF2 AF2 TIM1 Alternate function register 2 0x64 0x20 0x00000001 0xFFFFFFFF BK2INE BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timers BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BK2INP BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write TISEL TISEL TIM1 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write TI2SEL selects TI2[0] to TI2[15] input Others: Reserved 8 4 read-write TI3SEL selects TI3[0] to TI3[15] input Others: Reserved 16 4 read-write TI4SEL selects TI4[0] to TI4[15] input Others: Reserved 24 4 read-write TIM3 General-purpose timer TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 gloabal interrupt 16 CR1 CR1 TIM3 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 4 1 read-write DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 5 2 read-write CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write CR2 CR2 TIM3 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 4 3 read-write TI1S TI1 selection 7 1 read-write TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 SMCR SMCR TIM3 slave mode control register 0x8 0x20 0x00000000 0xFFFFFFFF SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 3 read-write OCCS OCREF clear selection This bit is used to select the OCREF clear source 3 1 read-write TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 4 3 read-write MSM Master/Slave mode 7 1 read-write MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 8 4 read-write ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 12 2 read-write ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 14 1 read-write ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 15 1 read-write ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 16 1 read-write TS2 Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 20 2 read-write DIER DIER TIM3 DMA/Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 TIE Trigger interrupt enable 6 1 read-write TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 TDE Trigger DMA request enable 14 1 read-write TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR TIM3 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 TIF Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 6 1 read-write zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM3 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 6 1 write-only TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 CCMR1_Input CCMR1_Input TIM3 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 2 0x8 1-2 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CC2S Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 8 2 read-write CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CCMR1_Output CCMR1_Output TIM3 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 read-write OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR2_Input CCMR2_Input TIM3 capture/compare mode register 2 [alternate] 0x1C 0x20 0x00000000 0xFFFFFFFF CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 2 read-write CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 read-write 2 0x8 3-4 IC%sF Input capture %s filter 4 4 read-write CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 8 2 read-write CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CCMR2_Output CCMR2_Output TIM3 capture/compare mode register 2 [alternate] CCMR2_Input 0x1C 0x20 0x00000000 0xFFFFFFFF 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 read-write 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 read-write 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 read-write 2 0x8 3-4 OC%sM Output compare %s mode 4 3 read-write 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 read-write 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM3 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM3 counter [alternate] 0x24 0x20 0x00000000 0xFFFFFFFF CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register 31 1 read-write CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM3 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM3 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 DCR DCR TIM3 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write 0 31 DBL DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ... 8 5 read-write 0 18 DMAR DMAR TIM3 DMA address for full transfer 0x4C 0x10 0x00000000 0x0000FFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 TIM3 alternate function option register 1 0x60 0x20 0x00000000 0xFFFFFFFF ETRSEL ETR source selection These bits select the ETR input source. Others: Reserved 14 4 read-write TISEL TISEL TIM3 timer input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved 0 4 read-write TI2SEL TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved 8 4 read-write TI3SEL TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved 16 4 read-write TIM14 General-purpose timers TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 gloabal interrupt 19 CR1 CR1 TIM14 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write DIER DIER TIM14 Interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 SR SR TIM14 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM14 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 CCMR1_Input CCMR1_Input TIM14 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCMR1_Output CCMR1_Output TIM14 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM14 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CNT CNT TIM14 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. 31 1 read-write CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM14 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM14 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 TISEL TISEL TIM14 timer input selection register 0x68 0x10 0x00000000 0x0000FFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write TIM16 General-purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 21 CR1 CR1 TIM16 control register 1 0x0 0x10 0x00000000 0x0000FFFF CEN Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 1 read-write CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1 1 read-write UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 2 1 read-write URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One pulse mode 3 1 read-write OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 read-write ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 8 2 read-write CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 read-write CR2 CR2 TIM16 control register 2 0x4 0x10 0x00000000 0x0000FFFF CCPC Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 1 read-write CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 2 1 read-write CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 read-write CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 read-write OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 read-write OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 DIER DIER TIM16 DMA/interrupt enable register 0xC 0x10 0x00000000 0x0000FFFF UIE Update interrupt enable 0 1 read-write UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 read-write CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 read-write COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE Break interrupt enable 7 1 read-write BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 read-write UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 read-write CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 SR SR TIM16 status register 0x10 0x10 0x00000000 0x0000FFFF UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 1 read-write zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 read-write zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 read-write zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 7 1 read-write zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 read-write zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 EGR EGR TIM16 event generation register 0x14 0x10 0x00000000 0x0000FFFF UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0 1 write-only UG Update Re-initializes the timer counter and generates an update of the registers. 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 write-only CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 5 1 write-only COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 7 1 write-only BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 CCMR1_Input CCMR1_Input TIM16 capture/compare mode register 1 [alternate] 0x18 0x20 0x00000000 0xFFFFFFFF CC1S Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 0 2 read-write CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 read-write ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 1 0x0 1-1 IC%sF Input capture %s filter 4 4 read-write ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 CCMR1_Output CCMR1_Output TIM16 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 0x20 0x00000000 0xFFFFFFFF 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 read-write CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 read-write OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 read-write OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 read-write OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 read-write CCER CCER TIM16 capture/compare enable register 0x20 0x10 0x00000000 0x0000FFFF 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 read-write CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 read-write CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 read-write CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 read-write CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT TIM16 counter 0x24 0x20 0x00000000 0xFFFFFFFF CNT Counter value 0 16 read-write 0 65535 UIFCPY UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM16 prescaler 0x28 0x10 0x00000000 0x0000FFFF PSC Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). 0 16 read-write 0 65535 ARR ARR TIM16 auto-reload register 0x2C 0x10 0x0000FFFF 0x0000FFFF ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 0 16 read-write 0 65535 RCR RCR TIM16 repetition counter register 0x30 0x10 0x00000000 0x0000FFFF REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 read-write 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 0x00000000 0x0000FFFF CCR Capture/Compare value 0 16 read-write 0 65535 BDTR BDTR TIM16 break and dead-time register 0x44 0x20 0x00000000 0xFFFFFFFF DTG Dead-time generator setup 0 8 read-write 0 255 LOCK Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 8 2 read-write LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 10 1 read-write OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 11 1 read-write OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 12 1 read-write BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 13 1 read-write BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 14 1 read-write AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). 15 1 read-write MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 16 4 read-write BKDSRM Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 26 1 read-write BKBID Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 28 1 read-write DCR DCR TIM16 DMA control register 0x48 0x10 0x00000000 0x0000FFFF DBA DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 5 read-write DBL DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... 8 5 read-write DMAR DMAR TIM16 DMA address for full transfer 0x4C 0x10 0x00000000 0x0000FFFF DMAB DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 0 16 read-write AF1 AF1 TIM16 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write TISEL TISEL TIM16 input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write TIM17 General-purpose timers TIM 0x40014800 0x0 0x400 registers TIM17 TIM17 global interrupt 22 CR1 CR1 TIM17 control register 1 0x0 CR2 CR2 TIM17 control register 2 0x4 DIER DIER TIM17 DMA/interrupt enable register 0xC SR SR TIM17 status register 0x10 EGR EGR TIM17 event generation register 0x14 CCMR1_Input CCMR1_Input TIM17 capture/compare mode register 1 [alternate] 0x18 CCMR1_Output CCMR1_Output TIM17 capture/compare mode register 1 [alternate] CCMR1_Input 0x18 CCER CCER TIM17 capture/compare enable register 0x20 CNT CNT TIM17 counter 0x24 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC TIM17 prescaler 0x28 ARR ARR TIM17 auto-reload register 0x2C RCR RCR TIM17 repetition counter register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR TIM17 break and dead-time register 0x44 DCR DCR TIM17 DMA control register 0x48 DMAR DMAR TIM17 DMA address for full transfer 0x4C AF1 AF1 TIM17 alternate function register 1 0x60 0x20 0x00000001 0xFFFFFFFF BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 1 read-write BKINP BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 9 1 read-write TISEL TISEL TIM17 input selection register 0x68 0x20 0x00000000 0xFFFFFFFF TI1SEL selects TI1[0] to TI1[15] input Others: Reserved 0 4 read-write USART1 USART register block USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt (combined with EXTI 25) 27 CR1 CR1_enabled USART control register 1 [alternate] 0x0 0x20 0x00000000 0xFFFFFFFF UE USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. 0 1 read-write UE Disabled UART is disabled 0 Enabled UART is enabled 1 UESM USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985. 1 1 read-write UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 RE Receiver enable This bit enables the receiver. It is set and cleared by software. 2 1 read-write RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 TE Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. 3 1 read-write TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 IDLEIE IDLE interrupt enable This bit is set and cleared by software. 4 1 read-write IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 RXNEIE RXFIFO not empty interrupt enable This bit is set and cleared by software. 5 1 read-write RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 TCIE Transmission complete interrupt enable This bit is set and cleared by software. 6 1 read-write TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 TXEIE TXFIFO not full interrupt enable This bit is set and cleared by software. 7 1 read-write TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 PEIE PE interrupt enable This bit is set and cleared by software. 8 1 read-write PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 PS Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0). 9 1 read-write PS Even Even parity 0 Odd Odd parity 1 PCE Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0). 10 1 read-write PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 WAKE Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 11 1 read-write WAKE Idle Idle line 0 Address Address mask 1 M0 Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0). 12 1 read-write M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 MME Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 13 1 read-write MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 CMIE Character match interrupt enable This bit is set and cleared by software. 14 1 read-write CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 OVER8 Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. 15 1 read-write OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 DEDT Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 16 5 read-write 0 31 DEAT Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 21 5 read-write 0 31 RTOIE Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. . 26 1 read-write RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 EOBIE End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 27 1 read-write EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 M1 Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. 28 1 read-write M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 FIFOEN FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. 29 1 read-write FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 TXFEIE TXFIFO empty interrupt enable This bit is set and cleared by software. 30 1 read-write TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 RXFFIE RXFIFO Full interrupt enable This bit is set and cleared by software. 31 1 read-write RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 CR2 CR2 USART control register 2 0x4 0x20 0x00000000 0xFFFFFFFF SLVEN Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 0 1 read-write SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 DIS_NSS When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 3 1 read-write DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 ADDM7 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 4 1 read-write ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 LBDL LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 5 1 read-write LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 LBDIE LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 6 1 read-write LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBCL Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 read-write LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 CPHA Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 read-write CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 CPOL Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 10 1 read-write CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CLKEN Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1 11 1 read-write CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 STOP stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0). 12 2 read-write STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 LINEN LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to . 14 1 read-write LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 SWAP Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 15 1 read-write SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 RXINV RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0). 16 1 read-write RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 TXINV TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0). 17 1 read-write TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 DATAINV Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 18 1 read-write DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 MSBFIRST Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). 19 1 read-write MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 ABREN Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 20 1 read-write ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 ABRMOD Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 21 2 read-write ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 RTOEN Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to . 23 1 read-write RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ADD Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). 24 8 read-write 0 255 CR3 CR3 USART control register 3 0x8 0x20 0x00000000 0xFFFFFFFF EIE Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register). 0 1 read-write EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 IREN IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 1 1 read-write IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 IRLP IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 2 1 read-write IRLP Normal Normal mode 0 LowPower Low-power mode 1 HDSEL Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0). 3 1 read-write HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 NACK Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 4 1 read-write NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 SCEN Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 5 1 read-write SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 DMAR DMA enable receiver This bit is set/reset by software 6 1 read-write DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 DMAT DMA enable transmitter This bit is set/reset by software 7 1 read-write DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 RTSE RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 read-write RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 CTSE CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 read-write CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 CTSIE CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 10 1 read-write CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 ONEBIT One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0). 11 1 read-write ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 OVRDIS Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data 12 1 read-write OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 DDRE DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 13 1 read-write DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 DEM Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. . 14 1 read-write DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DEP Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 15 1 read-write DEP High DE signal is active high 0 Low DE signal is active low 1 SCARCNT Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 17 3 read-write 0 7 WUS Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985. 20 2 read-write WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 WUFIE Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985. 22 1 read-write WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 TXFTIE TXFIFO threshold interrupt enable This bit is set and cleared by software. 23 1 read-write TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 TCBGTIE Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 24 1 read-write TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 RXFTCFG Receive FIFO threshold configuration Remaining combinations: Reserved 25 3 read-write RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 RXFTIE RXFIFO threshold interrupt enable This bit is set and cleared by software. 28 1 read-write RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 TXFTCFG TXFIFO threshold configuration Remaining combinations: Reserved 29 3 read-write TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 BRR BRR USART baud rate register 0xC 0x20 0x00000000 0xFFFFFFFF BRR USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 0 16 read-write 0 65535 GTPR GTPR USART guard time and prescaler register 0x10 0x20 0x00000000 0xFFFFFFFF PSC Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to . 0 8 read-write 0 255 GT Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 8 read-write 0 255 RTOR RTOR USART receiver timeout register 0x14 0x20 0x00000000 0xFFFFFFFF RTO Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character. 0 24 read-write 0 16777215 BLEN Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. 24 8 read-write 0 255 RQR RQR USART request register 0x18 0x20 0x00000000 0xFFFFFFFF ABRRQ Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to . 0 1 write-only ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. 1 1 write-only SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 MMRQ Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. 2 1 write-only MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. 3 1 write-only RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 TXFRQ Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. 4 1 write-only TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 ISR ISR_enabled USART interrupt and status register [alternate] 0x1C 0x20 0x008000C0 0xF0FFFFFF PE Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 0 1 read-only PE NoError No parity error 0 Error Parity error 1 FE Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR. 1 1 read-only FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 NE Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR. 2 1 read-only NE NoNoise No noise is detected 0 Noise Noise is detected 1 ORE Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. 3 1 read-only ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. 4 1 read-only IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 RXFNE RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register. 5 1 read-only RXFNE NoData Data is not received 0 DataReady Received data is ready to be read 1 TC Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set. 6 1 read-only TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission. 7 1 read-only TXFNF Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 LBDF LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to . 8 1 read-only LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 CTSIF CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 9 1 read-only CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 CTS CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. 10 1 read-only CTS Set CTS line set 0 Reset CTS line reset 1 RTOF Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. 11 1 read-only RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 EOBF End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to . 12 1 read-only EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 UDR SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to . 13 1 read-only UDR NoUnderrun No underrun error 0 Underrun underrun error 1 ABRE Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 14 1 read-only ABRF Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. 15 1 read-only BUSY Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 16 1 read-only BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CMF Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register. 17 1 read-only CMF NoMatch No Character match detected 0 Match Character match detected 1 SBKF Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 18 1 read-only SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 19 1 read-only RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 WUF Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 20 1 read-only TEACK Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. 21 1 read-only REACK Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to . 22 1 read-only TXFE TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register. 23 1 read-only TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 RXFF RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register. 24 1 read-only RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TCBGT Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985. 25 1 read-only TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFT RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. 26 1 read-only RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TXFT TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register. 27 1 read-only TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 ICR ICR USART interrupt flag clear register 0x20 0x20 0x00000000 0xFFFFFFFF PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. 0 1 write-only oneToClear PECF Clear Clears the PE flag in the ISR register 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. 1 1 write-only oneToClear FECF Clear Clears the FE flag in the ISR register 1 NECF Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. 2 1 write-only oneToClear NECF Clear Clears the NF flag in the ISR register 1 ORECF Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. 3 1 write-only oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 IDLECF Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. 4 1 write-only oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 TXFECF TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. 5 1 write-only oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 TCCF Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. 6 1 write-only oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. 7 1 write-only oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 LBDCF LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to . 8 1 write-only oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 CTSCF CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to . 9 1 write-only oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985. 11 1 write-only oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 EOBCF End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to . 12 1 write-only oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 UDRCF SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to 13 1 write-only oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 CMCF Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. 17 1 write-only oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 WUCF Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985. 20 1 write-only oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 RDR RDR USART receive data register 0x24 0x20 0x00000000 0xFFFFFFFF RDR Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 0 9 read-only 0 511 TDR TDR USART transmit data register 0x28 0x20 0x00000000 0xFFFFFFFF TDR Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1. 0 9 read-write 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 0x00000000 0xFFFFFFFF PRESCALER Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. 0 4 read-write PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 global interrupt (combined with EXTI 25) 28 WWDG WWDG register block WWDG 0x40002C00 0x0 0x400 registers WWDG Window watchdog interrupt 0 CR CR WWDG control register 0x0 0x10 0x0000007F 0x0000FFFF T 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 0 7 read-write 0 127 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 7 1 read-write WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR WWDG configuration register 0x4 0x10 0x0000007F 0x0000FFFF W 7-bit window value These bits contain the window value to be compared with the down-counter. 0 7 read-write 0 127 EWI Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. 9 1 read-write EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base The timebase of the prescaler can be modified as follows: 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 SR SR WWDG status register 0x8 0x10 0x00000000 0x0000FFFF EWIF Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled. 0 1 read-write zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0