STM32F3x4 1.8 STM32F3x4 CM4 r1p0 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0xC0000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Lok Key 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 L0,L1,L2,L3,L4,L5,L6,L7 AFR%s Alternate function selection for port x bit y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 H8,H9,H10,H11,H12,H13,H14,H15 AFR%s Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR Port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR Port bit reset register 0x28 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x0C000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR Port bit reset register 0x28 GPIOD 0x48000C00 GPIOF 0x48001400 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSE Disabled Spread spectrum disabled 0 Enabled Spread spectrum enabled 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 IODEF PushPull I/Os are forced to output push-pull low 0 Floating I/Os are in input floating 1 SYNCPOL Synchronization pin polarity 3 1 SYNCPOL FallingEdge Falling edge only 0 RisingEdge Rising edge and high level 1 AM Acquisition mode 2 1 AM Normal Normal acquisition mode (acquisition starts as soon as START bit is set) 0 Synchronized Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) 1 START Start a new acquisition 1 1 START NoStarted Acquisition not started 0 Started Start a new acquisition 1 TSCE Touch sensing controller enable 0 1 TSCE Disabled Touch sensing controller disabled 0 Enabled Touch sensing controller enabled 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 MCEIE Disabled Max count error interrupt disabled 0 Enabled Max count error interrupt enabled 1 EOAIE End of acquisition interrupt enable 0 1 EOAIE Disabled End of acquisition interrupt disabled 0 Enabled End of acquisition interrupt enabled 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-write 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF 8 0x4 1-8 G%s_IO1 G%s_IO1 Schmitt trigger hysteresis mode 0 1 G1_IO1 Disabled Gx_IOy Schmitt trigger hysteresis disabled 0 Enabled Gx_IOy Schmitt trigger hysteresis enabled 1 8 0x4 1-8 G%s_IO2 G%s_IO2 Schmitt trigger hysteresis mode 1 1 8 0x4 1-8 G%s_IO3 G%s_IO3 Schmitt trigger hysteresis mode 2 1 8 0x4 1-8 G%s_IO4 G%s_IO4 Schmitt trigger hysteresis mode 3 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 analog switch enable 0 1 G1_IO1 Disabled Gx_IOy analog switch disabled (opened) 0 Enabled Gx_IOy analog switch enabled (closed) 1 8 0x4 1-8 G%s_IO2 G%s_IO2 analog switch enable 1 1 8 0x4 1-8 G%s_IO3 G%s_IO3 analog switch enable 2 1 8 0x4 1-8 G%s_IO4 G%s_IO4 analog switch enable 3 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 sampling mode 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as sampling capacitor 1 8 0x4 1-8 G%s_IO2 G%s_IO2 sampling mode 1 1 8 0x4 1-8 G%s_IO3 G%s_IO3 sampling mode 2 1 8 0x4 1-8 G%s_IO4 G%s_IO4 sampling mode 3 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 8 0x4 1-8 G%s_IO1 G%s_IO1 channel mode 0 1 G1_IO1 Disabled Gx_IOy unused 0 Enabled Gx_IOy used as channel 1 8 0x4 1-8 G%s_IO2 G%s_IO2 channel mode 1 1 8 0x4 1-8 G%s_IO3 G%s_IO3 channel mode 2 1 8 0x4 1-8 G%s_IO4 G%s_IO4 channel mode 3 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 8 0x1 1-8 G%sS Analog I/O group x status 16 1 read-only G1S Ongoing Acquisition on analog I/O group x is ongoing or not started 0 Complete Acquisition on analog I/O group x is complete 1 8 0x1 1-8 G%sE Analog I/O group x enable 0 1 read-write G1E Disabled Acquisition on analog I/O group x disabled 0 Enabled Acquisition on analog I/O group x enabled 1 8 0x4 1-8 IOG%sCR IOG%sCR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 CRC cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 32 0 4294967295 CR CR Control register 0x8 0x20 read-write 0x00000000 RESET reset bit 0 1 RESETW write Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size 3 2 POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data 5 2 REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data 7 1 REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL CRC polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 4 ACR ACR Flash access control register 0x0 0x20 0x00000030 LATENCY LATENCY 0 3 read-write LATENCY WS0 0 wait states, if 0 < HCLK <= 24 MHz 0 WS1 1 wait state, if 24 < HCLK <= 48 MHz 1 WS2 2 wait states, if 48 < HCLK <= 72 MHz 2 PRFTBE PRFTBE 4 1 read-write PRFTBE Disabled Prefetch is disabled 0 Enabled Prefetch is enabled 1 PRFTBS PRFTBS 5 1 read-only PRFTBS Disabled Prefetch buffer is disabled 0 Enabled Prefetch buffer is enabled 1 HLFCYA Flash half cycle access enable 3 1 read-write HLFCYA Disabled Half cycle is disabled 0 Enabled Half cycle is enabled 1 KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 FKEYR Flash Key 0 32 0 4294967295 OPTKEYR OPTKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 0 4294967295 SR SR Flash status register 0xC 0x20 0x00000000 EOP End of operation 5 1 read-write EOPR read NoEvent No EOP event occurred 0 Event An EOP event occurred 1 EOPW write Reset Reset EOP event 1 WRPRTERR Write protection error 4 1 read-write WRPRTERRR read NoError No write protection error occurred 0 Error A write protection error occurred 1 WRPRTERRW write Reset Reset write protection error 1 PGERR Programming error 2 1 read-write PGERRR read NoError No programming error occurred 0 Error A programming error occurred 1 PGERRW write Reset Reset programming error 1 BSY Busy 0 1 read-only BSYR Inactive No write/erase operation is in progress 0 Active No write/erase operation is in progress 1 CR CR Flash control register 0x10 0x20 read-write 0x00000080 OBL_LAUNCH Force option byte loading 13 1 OBL_LAUNCH Inactive Force option byte loading inactive 0 Active Force option byte loading active 1 EOPIE End of operation interrupt enable 12 1 EOPIE Disabled End of operation interrupt disabled 0 Enabled End of operation interrupt enabled 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Error interrupt generation disabled 0 Enabled Error interrupt generation enabled 1 OPTWRE Option bytes write enable 9 1 OPTWRE Disabled Option byte write enabled 0 Enabled Option byte write disabled 1 LOCK Lock 7 1 LOCKR read Unlocked FLASH_CR register is unlocked 0 Locked FLASH_CR register is locked 1 LOCKW write Lock Lock the FLASH_CR register 1 STRT Start 6 1 STRT Start Trigger an erase operation 1 OPTER Option byte erase 5 1 OPTER OptionByteErase Erase option byte activated 1 OPTPG Option byte programming 4 1 OPTPG OptionByteProgramming Program option byte activated 1 MER Mass erase 2 1 MER MassErase Erase activated for all user sectors 1 PER Page erase 1 1 PER PageErase Erase activated for selected page 1 PG Programming 0 1 PG Program Flash programming activated 1 AR AR Flash address register 0x14 0x20 write-only 0x00000000 FAR Flash address 0 32 0 4294967295 OBR OBR Option byte register 0x1C 0x20 read-only 0xFFFFFF0F OPTERR Option byte error 0 1 OPTERR OptionByteError The loaded option byte and its complement do not match 1 WDG_SW WDG_SW 8 1 WDG_SW Hardware Hardware watchdog 0 Software Software watchdog 1 nRST_STOP nRST_STOP 9 1 nRST_STOP Reset Reset generated when entering Stop mode 0 NoReset No reset generated 1 nRST_STDBY nRST_STDBY 10 1 nRST_STDBY Reset Reset generated when entering Standby mode 0 NoReset No reset generated 1 nBOOT1 BOOT1 12 1 nBOOT1 Disabled Together with BOOT0, select the device boot mode 0 Enabled Together with BOOT0, select the device boot mode 1 VDDA_MONITOR VDDA_MONITOR 13 1 VDDA_MONITOR Disabled VDDA power supply supervisor disabled 0 Enabled VDDA power supply supervisor enabled 1 SRAM_PARITY_CHECK SRAM_PARITY_CHECK 14 1 Data0 Data0 16 8 0 255 Data1 Data1 24 8 0 255 RDPRT Read protection Level status 1 2 RDPRT Level0 Level 0 0 Level1 Level 1 1 Level2 Level 2 3 WRPR WRPR Write protection register 0x20 0x20 read-only 0xFFFFFFFF WRP Write protect 0 32 0 4294967295 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000083 HSION Internal High Speed clock enable 0 1 read-write HSION Off Clock Off 0 On Clock On 1 HSIRDY Internal High Speed clock ready flag 1 1 read-only HSIRDYR NotReady Clock not ready 0 Ready Clock ready 1 HSITRIM Internal High Speed clock trimming 3 5 read-write 0 31 HSICAL Internal High Speed clock Calibration 8 8 read-only 0 255 HSEON External High Speed clock enable 16 1 read-write HSERDY External High Speed clock ready flag 17 1 read-only HSEBYP External High Speed clock Bypass 18 1 read-write HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 CSSON Clock Security System enable 19 1 read-write CSSON Off Clock security system disabled (clock detector OFF) 0 On Clock security system enable (clock detector ON if the HSE is ready, OFF if not) 1 PLLON PLL enable 24 1 read-write PLLRDY PLL clock ready flag 25 1 read-only CFGR CFGR Clock configuration register (RCC_CFGR) 0x4 0x20 0x00000000 SW System clock Switch 0 2 read-write SW HSI HSI selected as system clock 0 HSE HSE selected as system clock 1 PLL PLL selected as system clock 2 SWS System Clock Switch Status 2 2 read-only SWSR HSI HSI oscillator used as system clock 0 HSE HSE oscillator used as system clock 1 PLL PLL used as system clock 2 HPRE AHB prescaler 4 4 read-write HPRE Div2 SYSCLK divided by 2 8 Div4 SYSCLK divided by 4 9 Div8 SYSCLK divided by 8 10 Div16 SYSCLK divided by 16 11 Div64 SYSCLK divided by 64 12 Div128 SYSCLK divided by 128 13 Div256 SYSCLK divided by 256 14 Div512 SYSCLK divided by 512 15 Div1 SYSCLK not divided true PPRE1 APB Low speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB high speed prescaler (APB2) 11 3 read-write PLLSRC PLL entry clock source 16 1 read-write PLLSRC HSI_Div2 HSI divided by 2 selected as PLL input clock 0 HSE_Div_PREDIV HSE divided by PREDIV selected as PLL input clock 1 PLLXTPRE HSE divider for PLL entry 17 1 read-write PLLXTPRE Div1 HSE clock not divided 0 Div2 HSE clock divided by 2 1 PLLMUL PLL Multiplication Factor 18 4 read-write PLLMUL Mul2 PLL input clock x2 0 Mul3 PLL input clock x3 1 Mul4 PLL input clock x4 2 Mul5 PLL input clock x5 3 Mul6 PLL input clock x6 4 Mul7 PLL input clock x7 5 Mul8 PLL input clock x8 6 Mul9 PLL input clock x9 7 Mul10 PLL input clock x10 8 Mul11 PLL input clock x11 9 Mul12 PLL input clock x12 10 Mul13 PLL input clock x13 11 Mul14 PLL input clock x14 12 Mul15 PLL input clock x15 13 Mul16 PLL input clock x16 14 Mul16x PLL input clock x16 15 MCO Microcontroller clock output 24 3 read-write MCO NoMCO MCO output disabled, no clock on MCO 0 LSI Internal low speed (LSI) oscillator clock selected 2 LSE External low speed (LSE) oscillator clock selected 3 SYSCLK System clock selected 4 HSI Internal RC 8 MHz (HSI) oscillator clock selected 5 HSE External 4-32 MHz (HSE) oscillator clock selected 6 PLL PLL clock selected (divided by 1 or 2, depending en PLLNODIV) 7 MCOPRE Microcontroller Clock Output Prescaler 28 3 MCOPRE Div1 MCO is divided by 1 0 Div2 MCO is divided by 2 1 Div4 MCO is divided by 4 2 Div8 MCO is divided by 8 3 Div16 MCO is divided by 16 4 Div32 MCO is divided by 32 5 Div64 MCO is divided by 64 6 Div128 MCO is divided by 128 7 PLLNODIV Do not divide PLL to MCO 31 1 PLLNODIV Div2 PLL is divided by 2 for MCO 0 Div1 PLL is not divided for MCO 1 CIR CIR Clock interrupt register (RCC_CIR) 0x8 0x20 0x00000000 LSIRDYF LSI Ready Interrupt flag 0 1 read-only LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE Ready Interrupt flag 1 1 read-only HSIRDYF HSI Ready Interrupt flag 2 1 read-only HSERDYF HSE Ready Interrupt flag 3 1 read-only PLLRDYF PLL Ready Interrupt flag 4 1 read-only CSSF Clock Security System Interrupt flag 7 1 read-only CSSFR NotInterrupted No clock security interrupt caused by HSE clock failure 0 Interrupted Clock security interrupt caused by HSE clock failure 1 LSIRDYIE LSI Ready Interrupt Enable 8 1 read-write LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE Ready Interrupt Enable 9 1 read-write HSIRDYIE HSI Ready Interrupt Enable 10 1 read-write HSERDYIE HSE Ready Interrupt Enable 11 1 read-write PLLRDYIE PLL Ready Interrupt Enable 12 1 read-write LSIRDYC LSI Ready Interrupt Clear 16 1 write-only LSIRDYCW Clear Clear interrupt flag 1 LSERDYC LSE Ready Interrupt Clear 17 1 write-only HSIRDYC HSI Ready Interrupt Clear 18 1 write-only HSERDYC HSE Ready Interrupt Clear 19 1 write-only PLLRDYC PLL Ready Interrupt Clear 20 1 write-only CSSC Clock security system interrupt clear 23 1 write-only CSSCW Clear Clear CSSF flag 1 APB2RSTR APB2RSTR APB2 peripheral reset register (RCC_APB2RSTR) 0xC 0x20 read-write 0x00000000 SYSCFGRST SYSCFG and COMP reset 0 1 SYSCFGRST Reset Reset the selected module 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI 1 reset 12 1 USART1RST USART1 reset 14 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 HRTIM1RST High Resolution Timer1 reset 29 1 APB1RSTR APB1RSTR APB1 peripheral reset register (RCC_APB1RSTR) 0x10 0x20 read-write 0x00000000 TIM2RST Timer 2 reset 0 1 TIM2RST Reset Reset the selected module 1 TIM3RST Timer 3 reset 1 1 TIM6RST Timer 6 reset 4 1 TIM7RST Timer 7 reset 5 1 WWDGRST Window watchdog reset 11 1 USART2RST USART 2 reset 17 1 USART3RST USART3 reset 18 1 I2C1RST I2C1 reset 21 1 CANRST CAN reset 25 1 PWRRST Power interface reset 28 1 DAC1RST DAC interface reset 29 1 DAC2RST DAC2 interface reset 26 1 AHBENR AHBENR AHB Peripheral Clock enable register (RCC_AHBENR) 0x14 0x20 read-write 0x00000014 DMA1EN DMA1 clock enable 0 1 DMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SRAMEN SRAM interface clock enable 2 1 FLITFEN FLITF clock enable 4 1 CRCEN CRC clock enable 6 1 IOPAEN I/O port A clock enable 17 1 IOPBEN I/O port B clock enable 18 1 IOPCEN I/O port C clock enable 19 1 IOPDEN I/O port D clock enable 20 1 IOPFEN I/O port F clock enable 22 1 TSCEN Touch sensing controller clock enable 24 1 ADC12EN ADC1 and ADC2 clock enable 28 1 ADC34EN ADC3 and ADC4 clock enable 29 1 APB2ENR APB2ENR APB2 peripheral clock enable register (RCC_APB2ENR) 0x18 0x20 read-write 0x00000000 SYSCFGEN SYSCFG clock enable 0 1 SYSCFGEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM1EN TIM1 Timer clock enable 11 1 SPI1EN SPI 1 clock enable 12 1 USART1EN USART1 clock enable 14 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 HRTIM1EN High Resolution Timer 1 clock enable 29 1 APB1ENR APB1ENR APB1 peripheral clock enable register (RCC_APB1ENR) 0x1C 0x20 read-write 0x00000000 TIM2EN Timer 2 clock enable 0 1 TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN Timer 3 clock enable 1 1 TIM6EN Timer 6 clock enable 4 1 TIM7EN Timer 7 clock enable 5 1 WWDGEN Window watchdog clock enable 11 1 USART2EN USART 2 clock enable 17 1 I2C1EN I2C 1 clock enable 21 1 CANEN CAN clock enable 25 1 PWREN Power interface clock enable 28 1 DAC1EN DAC interface clock enable 29 1 USART3EN USART3 clock enable 18 1 DAC2EN DAC2 interface clock enable 26 1 BDCR BDCR Backup domain control register (RCC_BDCR) 0x20 0x20 0x00000000 LSEON External Low Speed oscillator enable 0 1 read-write LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 LSERDY External Low Speed oscillator ready 1 1 read-only LSERDYR NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP External Low Speed oscillator bypass 2 1 read-write LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSEDRV LSE oscillator drive capability 3 2 read-write LSEDRV Low Low drive capacity 0 MediumHigh Medium-high drive capacity 1 MediumLow Medium-low drive capacity 2 High High drive capacity 3 RTCSEL RTC clock source selection 8 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 RTCEN RTC clock enable 15 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 BDRST Backup domain software reset 16 1 read-write BDRST Disabled Reset not activated 0 Enabled Reset the entire RTC domain 1 CSR CSR Control/status register (RCC_CSR) 0x24 0x20 0x0C000000 LSION Internal low speed oscillator enable 0 1 read-write LSION Off LSI oscillator Off 0 On LSI oscillator On 1 LSIRDY Internal low speed oscillator ready 1 1 read-only LSIRDYR NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 RMVF Remove reset flag 24 1 read-write RMVFW write Clear Clears the reset flag 1 V18PWRRSTF Reset flag of the 1.8 V domain 23 1 V18PWRRSTFR read NoReset No reset has occured 0 Reset A reset has occured 1 OBLRSTF Option byte loader reset flag 25 1 read-write PINRSTF PIN reset flag 26 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write SFTRSTF Software reset flag 28 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write LPWRRSTF Low-power reset flag 31 1 read-write AHBRSTR AHBRSTR AHB peripheral reset register 0x28 0x20 read-write 0x00000000 IOPARST I/O port A reset 17 1 IOPARST Reset Reset the selected module 1 IOPBRST I/O port B reset 18 1 IOPCRST I/O port C reset 19 1 IOPDRST I/O port D reset 20 1 IOPFRST I/O port F reset 22 1 TSCRST Touch sensing controller reset 24 1 ADC12RST ADC1 and ADC2 reset 28 1 CFGR2 CFGR2 Clock configuration register 2 0x2C 0x20 read-write 0x00000000 PREDIV PREDIV division factor 0 4 PREDIV Div1 PREDIV input clock not divided 0 Div2 PREDIV input clock divided by 2 1 Div3 PREDIV input clock divided by 3 2 Div4 PREDIV input clock divided by 4 3 Div5 PREDIV input clock divided by 5 4 Div6 PREDIV input clock divided by 6 5 Div7 PREDIV input clock divided by 7 6 Div8 PREDIV input clock divided by 8 7 Div9 PREDIV input clock divided by 9 8 Div10 PREDIV input clock divided by 10 9 Div11 PREDIV input clock divided by 11 10 Div12 PREDIV input clock divided by 12 11 Div13 PREDIV input clock divided by 13 12 Div14 PREDIV input clock divided by 14 13 Div15 PREDIV input clock divided by 15 14 Div16 PREDIV input clock divided by 16 15 ADC12PRES ADC1 and ADC2 prescaler 4 5 ADC12PRES NoClock No clock 0 Div1 PLL clock not divided 16 Div2 PLL clock divided by 2 17 Div4 PLL clock divided by 4 18 Div6 PLL clock divided by 6 19 Div8 PLL clock divided by 8 20 Div10 PLL clock divided by 10 21 Div12 PLL clock divided by 12 22 Div16 PLL clock divided by 16 23 Div32 PLL clock divided by 32 24 Div64 PLL clock divided by 64 25 Div128 PLL clock divided by 128 26 Div256 PLL clock divided by 256 27 CFGR3 CFGR3 Clock configuration register 3 0x30 0x20 read-write 0x00000000 USART1SW USART1 clock source selection 0 2 USART1SW PCLK PCLK selected as USART clock source 0 SYSCLK SYSCLK selected as USART clock source 1 LSE LSE selected as USART clock source 2 HSI HSI selected as USART clock source 3 I2C1SW I2C1 clock source selection 4 1 I2C1SW HSI HSI clock selected as I2C clock source 0 SYSCLK SYSCLK clock selected as I2C clock source 1 TIM1SW Timer1 clock source selection 8 1 TIM1SW PCLK2 PCLK2 clock (doubled frequency when prescaled) 0 PLL PLL vco output (running up to 144 MHz) 1 DMA1 DMA controller 1 DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 channel 1 interrupt 11 DMA1_CH2 DMA1 channel 2 interrupt 12 DMA1_CH3 DMA1 channel 3 interrupt 13 DMA1_CH4 DMA1 channel 4 interrupt 14 DMA1_CH5 DMA1 channel 5 interrupt 15 DMA1_CH6 DMA1 channel 6 interrupt 16 DMA1_CH7 DMA1 channel 7interrupt 17 ISR ISR DMA interrupt status register (DMA_ISR) 0x0 0x20 read-only 0x00000000 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 IFCR IFCR DMA interrupt flag clear register (DMA_IFCR) 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 DMA channel configuration register (DMA_CCR) 0x0 0x20 read-write 0x00000000 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 HTIE Half Transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 NDTR CNDTR1 DMA channel 1 number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 0 65535 PAR CPAR1 DMA channel 1 peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 DMA channel 1 memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 TIM2 General purpose timer TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 OCCS OCREF clear selection 3 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection bit3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 32 CNT32 CNT32 32-bit counter register CNT 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 read-write 0 4294967295 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 32 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 TS Trigger selection 4 3 MSM Master/Slave mode 7 1 SMS_3 Slave mode selection bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 2 0x1 1-2 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x10 read-write 0x00000000 REP Repetition counter value 0 8 0 255 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 BKF Break filter 16 4 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 TIM16 General-purpose-timers TIM 0x40014400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 SR SR status register 0x10 0x10 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x10 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 OR OR option register 0x50 0x20 read-write 0x00000000 TIM17 General purpose timer TIM 0x40014800 0x0 0x400 registers CR1 CR1 control register 1 0x0 CR2 CR2 control register 2 0x4 DIER DIER DMA/Interrupt enable register 0xC SR SR status register 0x10 EGR EGR event generation register 0x14 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 CCER CCER capture/compare enable register 0x20 CNT CNT counter 0x24 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 ARR ARR auto-reload register 0x2C RCR RCR repetition counter register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR break and dead-time register 0x44 DCR DCR DMA control register 0x48 DMAR DMAR DMA address for full transfer 0x4C USART1 Universal synchronous asynchronous receiver-transmitter USART 0x40013800 0x0 0x400 registers USART1_EXTI25 USART1 global interrupt and EXTI Line 25 interrupt 37 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable deassertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M Word length 12 1 M Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP IrDA low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN IrDA mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR mantissa of USARTDIV 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 read-write 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 REACK Receive enable acknowledge flag 22 1 TEACK Transmit enable acknowledge flag 21 1 WUF Wakeup from Stop mode flag 20 1 RWU Receiver wakeup from Mute mode 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF Send break flag 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF character match flag 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY Busy flag 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF Auto baud rate flag 15 1 ABRE Auto baud rate error 14 1 EOBF End of block flag 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF Receiver timeout 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS flag 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTS interrupt flag 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LIN break detection flag 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE Transmit data register empty 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC Transmission complete 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE Read data register not empty 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE Idle line detected 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE Overrun error 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF Noise detected flag 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE Framing error 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE Parity error 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 read-write 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 EOBCF End of timeout clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 USART2 0x40004400 USART2_EXTI26 USART2 global interrupt and EXTI Line 26 interrupt 38 USART3 0x40004800 USART3_EXTI28 USART3 global interrupt and EXTI Line 28 interrupt 39 SPI2 Serial peripheral interface/Inter-IC2 SPI 0x40003800 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL CRC length 11 1 CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold 12 1 FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission 14 1 LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CHSIDE Channel side 2 1 read-only CHSIDE Left Channel left has to be transmitted or has been received 0 Right Channel right has to be transmitted or has been received 1 UDR Underrun flag 3 1 read-only UDRR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x10 read-write 0x00000000 I2SMOD I2S mode selection 11 1 I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 I2SE I2S Enable 10 1 I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SCFG I2S configuration mode 8 2 I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 PCMSYNC PCM frame synchronization 7 1 PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SSTD I2S standard selection 4 2 I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 CKPOL Steady state clock polarity 3 1 CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 DATLEN Data length to be transferred 1 2 DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 I2SPR I2SPR I2S prescaler register 0x20 0x10 read-write 0x00000010 MCKOE Master clock output enable 9 1 MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 ODD Odd factor for the prescaler 8 1 ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 I2SDIV I2S Linear prescaler 0 8 2 255 I2S2ext 0x40003400 I2S3ext 0x40004000 SPI1 Serial peripheral interface/Inter-IC2 SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 CRCL Data frame format 11 1 CRCL EightBit 8-bit CRC length 0 SixteenBit 16-bit CRC length 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 NSSP NSS pulse management 3 1 NSSP NoPulse No NSS pulse 0 PulseGenerated NSS pulse generated 1 FRF Frame format 4 1 FRF Motorola SPI Motorola mode 0 TI SPI TI mode 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 DS Data size 8 4 DS FourBit 4-bit 3 FiveBit 5-bit 4 SixBit 6-bit 5 SevenBit 7-bit 6 EightBit 8-bit 7 NineBit 9-bit 8 TenBit 10-bit 9 ElevenBit 11-bit 10 TwelveBit 12-bit 11 ThirteenBit 13-bit 12 FourteenBit 14-bit 13 FifteenBit 15-bit 14 SixteenBit 16-bit 15 FRXTH FIFO reception threshold 12 1 FRXTH Half RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 0 Quarter RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_RX Even Number of data to transfer for receive is even 0 Odd Number of data to transfer for receive is odd 1 LDMA_TX Last DMA transfer for transmission 14 1 LDMA_TX Even Number of data to transfer for transmit is even 0 Odd Number of data to transfer for transmit is odd 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CHSIDE Channel side 2 1 read-only CHSIDE Left Channel left has to be transmitted or has been received 0 Right Channel right has to be transmitted or has been received 1 UDR Underrun flag 3 1 read-only UDRR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE Frame format error 8 1 read-only FRER NoError No frame format error 0 Error A frame format error occurred 1 FRLVL FIFO reception level 9 2 read-only FRLVLR Empty Rx FIFO Empty 0 Quarter Rx 1/4 FIFO 1 Half Rx 1/2 FIFO 2 Full Rx FIFO full 3 FTLVL FIFO transmission level 11 2 read-only FTLVLR Empty Tx FIFO Empty 0 Quarter Tx 1/4 FIFO 1 Half Tx 1/2 FIFO 2 Full Tx FIFO full 3 DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x10 read-write 0x00000000 I2SMOD I2S mode selection 11 1 I2SMOD SPIMode SPI mode is selected 0 I2SMode I2S mode is selected 1 I2SE I2S Enable 10 1 I2SE Disabled I2S peripheral is disabled 0 Enabled I2S peripheral is enabled 1 I2SCFG I2S configuration mode 8 2 I2SCFG SlaveTx Slave - transmit 0 SlaveRx Slave - receive 1 MasterTx Master - transmit 2 MasterRx Master - receive 3 PCMSYNC PCM frame synchronization 7 1 PCMSYNC Short Short frame synchronisation 0 Long Long frame synchronisation 1 I2SSTD I2S standard selection 4 2 I2SSTD Philips I2S Philips standard 0 MSB MSB justified standard 1 LSB LSB justified standard 2 PCM PCM standard 3 CKPOL Steady state clock polarity 3 1 CKPOL IdleLow I2S clock inactive state is low level 0 IdleHigh I2S clock inactive state is high level 1 DATLEN Data length to be transferred 1 2 DATLEN SixteenBit 16-bit data length 0 TwentyFourBit 24-bit data length 1 ThirtyTwoBit 32-bit data length 2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLEN SixteenBit 16-bit wide 0 ThirtyTwoBit 32-bit wide 1 I2SPR I2SPR I2S prescaler register 0x20 0x10 read-write 0x00000010 MCKOE Master clock output enable 9 1 MCKOE Disabled Master clock output is disabled 0 Enabled Master clock output is enabled 1 ODD Odd factor for the prescaler 8 1 ODD Even Real divider value is I2SDIV * 2 0 Odd Real divider value is (I2SDIV * 2) + 1 1 I2SDIV I2S Linear prescaler 0 8 2 255 SPI3 0x40003C00 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers TAMP_STAMP Tamper and TimeStamp interrupts 2 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line3 interrupt 7 EXTI2_TSC EXTI Line2 and Touch sensing interrupts 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 EXTI9_5 EXTI Line5 to Line9 interrupts 23 EXTI15_10 EXTI Line15 to Line10 interrupts 40 FPU Floating point unit interrupt 81 IMR1 IMR1 Interrupt mask register 0x0 0x20 read-write 0x1F800000 MR0 Interrupt Mask on line 0 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 MR23 Interrupt Mask on line 23 23 1 MR24 Interrupt Mask on line 24 24 1 MR25 Interrupt Mask on line 25 25 1 MR26 Interrupt Mask on line 26 26 1 MR27 Interrupt Mask on line 27 27 1 MR28 Interrupt Mask on line 28 28 1 MR29 Interrupt Mask on line 29 29 1 MR30 Interrupt Mask on line 30 30 1 MR31 Interrupt Mask on line 31 31 1 EMR1 EMR1 Event mask register 0x4 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 MR23 Event Mask on line 23 23 1 MR24 Event Mask on line 24 24 1 MR25 Event Mask on line 25 25 1 MR26 Event Mask on line 26 26 1 MR27 Event Mask on line 27 27 1 MR28 Event Mask on line 28 28 1 MR29 Event Mask on line 29 29 1 MR30 Event Mask on line 30 30 1 MR31 Event Mask on line 31 31 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR17 Rising trigger event configuration of line 17 17 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR20 Rising trigger event configuration of line 20 20 1 TR21 Rising trigger event configuration of line 21 21 1 TR22 Rising trigger event configuration of line 22 22 1 TR29 Rising trigger event configuration of line 29 29 1 TR30 Rising trigger event configuration of line 30 30 1 TR31 Rising trigger event configuration of line 31 31 1 FTSR1 FTSR1 Falling Trigger selection register 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR17 Falling trigger event configuration of line 17 17 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR20 Falling trigger event configuration of line 20 20 1 TR21 Falling trigger event configuration of line 21 21 1 TR22 Falling trigger event configuration of line 22 22 1 TR29 Falling trigger event configuration of line 29 29 1 TR30 Falling trigger event configuration of line 30. 30 1 TR31 Falling trigger event configuration of line 31 31 1 SWIER1 SWIER1 Software interrupt event register 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER17 Software Interrupt on line 17 17 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER20 Software Interrupt on line 20 20 1 SWIER21 Software Interrupt on line 21 21 1 SWIER22 Software Interrupt on line 22 22 1 SWIER29 Software Interrupt on line 29 29 1 SWIER30 Software Interrupt on line 309 30 1 SWIER31 Software Interrupt on line 319 31 1 PR1 PR1 Pending register 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 oneToClear PR0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR0W write Clear Clears pending bit 1 PR1 Pending bit 1 1 1 oneToClear read write PR2 Pending bit 2 2 1 oneToClear read write PR3 Pending bit 3 3 1 oneToClear read write PR4 Pending bit 4 4 1 oneToClear read write PR5 Pending bit 5 5 1 oneToClear read write PR6 Pending bit 6 6 1 oneToClear read write PR7 Pending bit 7 7 1 oneToClear read write PR8 Pending bit 8 8 1 oneToClear read write PR9 Pending bit 9 9 1 oneToClear read write PR10 Pending bit 10 10 1 oneToClear read write PR11 Pending bit 11 11 1 oneToClear read write PR12 Pending bit 12 12 1 oneToClear read write PR13 Pending bit 13 13 1 oneToClear read write PR14 Pending bit 14 14 1 oneToClear read write PR15 Pending bit 15 15 1 oneToClear read write PR16 Pending bit 16 16 1 oneToClear read write PR17 Pending bit 17 17 1 oneToClear read write PR18 Pending bit 18 18 1 oneToClear read write PR19 Pending bit 19 19 1 oneToClear read write PR20 Pending bit 20 20 1 oneToClear read write PR21 Pending bit 21 21 1 oneToClear read write PR22 Pending bit 22 22 1 oneToClear read write PR29 Pending bit 29 29 1 oneToClear read write PR30 Pending bit 30 30 1 oneToClear read write PR31 Pending bit 31 31 1 oneToClear read write IMR2 IMR2 Interrupt mask register 0x20 0x20 read-write 0xFFFFFFFC MR32 Interrupt Mask on external/internal line 32 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR33 Interrupt Mask on external/internal line 33 1 1 MR34 Interrupt Mask on external/internal line 34 2 1 MR35 Interrupt Mask on external/internal line 35 3 1 EMR2 EMR2 Event mask register 0x24 0x20 read-write 0x00000000 MR32 Event mask on external/internal line 32 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR33 Event mask on external/internal line 33 1 1 MR34 Event mask on external/internal line 34 2 1 MR35 Event mask on external/internal line 35 3 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 0x20 read-write 0x00000000 TR32 Rising trigger event configuration bit of line 32 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 TR33 Rising trigger event configuration bit of line 33 1 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 0x20 read-write 0x00000000 TR32 Falling trigger event configuration bit of line 32 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 TR33 Falling trigger event configuration bit of line 33 1 1 SWIER2 SWIER2 Software interrupt event register 0x30 0x20 read-write 0x00000000 SWIER32 Software interrupt on line 32 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWIER33 Software interrupt on line 33 1 1 PR2 PR2 Pending register 0x34 0x20 read-write 0x00000000 PR32 Pending bit on line 32 0 1 oneToClear PR32R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR32W write Clear Clears pending bit 1 PR33 Pending bit on line 33 1 1 oneToClear read write PWR Power control PWR 0x40007000 0x0 0x400 registers CR CR power control register 0x0 0x20 read-write 0x00000000 LPDS Low-power deep sleep 0 1 PDDS Power down deepsleep 1 1 PDDS STOP_MODE Enter Stop mode when the CPU enters deepsleep 0 STANDBY_MODE Enter Standby mode when the CPU enters deepsleep 1 CWUF Clear wakeup flag 2 1 CSBF Clear standby flag 3 1 PVDE Power voltage detector enable 4 1 PLS PVD level selection 5 3 DBP Disable backup domain write protection 8 1 CSR CSR power control/status register 0x4 0x20 0x00000000 WUF Wakeup flag 0 1 read-only SBF Standby flag 1 1 read-only PVDO PVD output 2 1 read-only EWUP1 Enable WKUP1 pin 8 1 read-write EWUP2 Enable WKUP2 pin 9 1 read-write I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV_EXTI23 I2C1 event interrupt and EXTI Line23 interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 Control register 1 0x0 0x20 0x00000000 PE Peripheral enable 0 1 read-write PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 read-write TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 read-write RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 read-write ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 read-write NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 read-write STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 read-write TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 read-write ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 read-write DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 read-write ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 SWRST Software reset 13 1 write-only TXDMAEN DMA transmission requests enable 14 1 read-write TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 read-write RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 read-write SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 read-write NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 read-write WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 read-write GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 read-write SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 read-write SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 read-write ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 read-write PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit 9:8 (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 I2C2 0x40005800 I2C3 0x40007800 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WVU Watchdog counter window value update 2 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 0 4095 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers PVD PVD through EXTI line detection interrupt 1 CR CR Control register 0x0 0x10 read-write 0x0000007F T 7-bit counter 0 7 0 127 WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 7 2 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 MT Zero Month tens is 0 0 One Month tens is 1 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 CR CR control register 0x8 0x20 read-write 0x00000000 WUCKSEL Wakeup clock selection 0 3 WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Time-stamp event active edge 3 1 TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers 5 1 BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 FMT Twenty_Four_Hour 24 hour/day format 0 AM_PM AM/PM hour format 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable 10 1 WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE Time stamp enable 11 1 TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Time-stamp interrupt enable 15 1 TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) 16 1 ADD1HW write Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) 17 1 SUB1HW write Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup 18 1 BKP DST_Not_Changed Daylight Saving Time change has not been performed 0 DST_Changed Daylight Saving Time change has been performed 1 COSEL Calibration output selection 19 1 COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity 20 1 POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection 21 2 OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable 23 1 COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ISR ISR initialization and status register 0xC 0x20 0x00000007 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only ALRAWFR UpdateNotAllowed Alarm update not allowed 0 UpdateAllowed Alarm update allowed 1 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending 3 1 read-write SHPFR read NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 2 0x1 A,B ALR%sF Alarm %s flag 8 1 read-write zeroToClear ALRAFR read Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 ALRAFW write Clear This flag is cleared by software by writing 0 0 WUTF Wakeup timer flag 10 1 read-write zeroToClear WUTFR read Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 WUTFW write Clear This flag is cleared by software by writing 0 0 TSF Time-stamp flag 11 1 read-write zeroToClear TSFR read TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSFW write Clear This flag is cleared by software by writing 0 0 TSOVF Time-stamp overflow flag 12 1 read-write zeroToClear TSOVFR read Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSOVFW write Clear This flag is cleared by software by writing 0 0 TAMP1F Tamper detection flag 13 1 read-write zeroToClear TAMP1FR read Tampered This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input 1 TAMP1FW write Clear Flag cleared by software writing 0 0 TAMP2F RTC_TAMP2 detection flag 14 1 read-write zeroToClear read write TAMP3F RTC_TAMP3 detection flag 15 1 read-write zeroToClear read write RECALPF Recalibration pending Flag 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 15 0 32767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 0 65535 2 0x4 A,B ALRM%sR ALRM%sR Alarm %s register 0x1C 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 0 255 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 0 65535 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR time stamp time register 0x30 TSDR TSDR time stamp date register 0x34 TSSSR TSSSR timestamp sub second register 0x38 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 Eight_Second When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 Sixteen_Second When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALM Calibration minus 0 9 0 511 TAFCR TAFCR tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 TAMP1E Tamper 1 detection enable 0 1 TAMP1E Disabled RTC_TAMPx input detection disabled 0 Enabled RTC_TAMPx input detection enabled 1 TAMP1TRG Active level for tamper 1 1 1 TAMP1TRG RisingEdge If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. 0 FallingEdge If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event 1 TAMPIE Tamper interrupt enable 2 1 TAMPIE Disabled Tamper interrupt disabled 0 Enabled Tamper interrupt enabled 1 TAMP2E Tamper 2 detection enable 3 1 TAMP2TRG Active level for tamper 2 4 1 TAMP3E Tamper 3 detection enable 5 1 TAMP3TRG Active level for tamper 3 6 1 TAMPTS Activate timestamp on tamper detection event 7 1 TAMPTS NoSave Tamper detection event does not cause a timestamp to be saved 0 Save Save timestamp on tamper detection event 1 TAMPFREQ Tamper sampling frequency 8 3 TAMPFREQ Div32768 RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0 Div16384 RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 1 Div8192 RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 2 Div4096 RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 3 Div2048 RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 4 Div1024 RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 5 Div512 RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 6 Div256 RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) 7 TAMPFLT Tamper filter count 11 2 TAMPFLT Immediate Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) 0 Samples2 Tamper event is activated after 2 consecutive samples at the active level 1 Samples4 Tamper event is activated after 4 consecutive samples at the active level 2 Samples8 Tamper event is activated after 8 consecutive samples at the active level 3 TAMPPRCH Tamper precharge duration 13 2 TAMPPRCH Cycles1 1 RTCCLK cycle 0 Cycles2 2 RTCCLK cycles 1 Cycles4 4 RTCCLK cycles 2 Cycles8 8 RTCCLK cycles 3 TAMPPUDIS TAMPER pull-up disable 15 1 TAMPPUDIS Enabled Precharge RTC_TAMPx pins before sampling (enable internal pull-up) 0 Disabled Disable precharge of RTC_TAMPx pins 1 PC13VALUE PC13 value 18 1 PC13VALUE Low If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low 0 High If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high 1 PC13MODE PC13 mode 19 1 PC13MODE Floating PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode 0 PushPull PCx is forced to push-pull output if LSE is disabled 1 PC14VALUE PC14 value 20 1 PC14MODE PC 14 mode 21 1 PC15VALUE PC15 value 22 1 PC15MODE PC15 mode 23 1 2 0x4 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 0 15 SS Sub seconds value 0 15 0 32767 32 0x4 0-31 BKP%sR BKP%sR backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 0 4294967295 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6_DAC1 TIM6 global and DAC12 underrun interrupts 54 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x20 0x00000000 CNT Low counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Low Auto-reload value 0 16 0 65535 TIM7 TIM 0x40001400 TIM7_DAC2 TIM7 global interrupt 55 DAC1 Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC channel X DMA mode disabled 0 Enabled DAC channel X DMA mode enabled 1 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true TSEL1 DAC channel1 trigger selection 3 3 TSEL1 Tim6Trgo Timer 6 TRGO event 0 Tim3Trgo Timer 3 TRGO event 1 Tim7Trgo Timer 7 TRGO event 2 Tim15Trgo Timer15 TRGO or HRTM1_DACTRG1 event 3 Tim2Trgo Timer 2 TRGO event 4 DacTrg2 HRTIM1_DACTRG2 (DAC1) or HRTM1_DACTRG3 (DAC2) event 5 Exti9 EXTI line 9 6 Software Software trigger 7 TSEL2 DAC channel2 trigger selection 19 3 2 0x10 1-2 TEN%s DAC channel%s trigger enable 2 1 TEN1 Disabled DAC channel X trigger disabled 0 Enabled DAC channel X trigger enabled 1 2 0x10 1-2 BOFF%s DAC channel%s output buffer disable 1 1 BOFF1 Enabled DAC channel X output buffer enabled 0 Disabled DAC channel X output buffer disabled 1 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC channel X disabled 0 Enabled DAC channel X enabled 1 SWTRIGR SWTRIGR software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 Disabled DAC channel X software trigger disabled 0 Enabled DAC channel X software trigger enabled 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data 0 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data 4 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output 0 12 SR SR status register 0x34 0x20 read-write 0x00000000 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 DAC2 0x40009800 DBGMCU Debug support DBGMCU 0xE0042000 0x0 0x400 registers WWDG Window Watchdog interrupt 0 IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x00000000 DEV_ID Device Identifier 0 12 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Debug Sleep mode 0 1 DBG_STOP Debug Stop Mode 1 1 DBG_STANDBY Debug Standby Mode 2 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1_FZ APB1FZ APB Low Freeze Register 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIM3_STOP Debug Timer 3 stopped when Core is halted 1 1 DBG_TIM4_STOP Debug Timer 4 stopped when Core is halted 2 1 DBG_TIM5_STOP Debug Timer 5 stopped when Core is halted 3 1 DBG_TIM6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_TIM7_STOP Debug Timer 7 stopped when Core is halted 5 1 DBG_TIM12_STOP Debug Timer 12 stopped when Core is halted 6 1 DBG_TIM13_STOP Debug Timer 13 stopped when Core is halted 7 1 DBG_TIMER14_STOP Debug Timer 14 stopped when Core is halted 8 1 DBG_TIM18_STOP Debug Timer 18 stopped when Core is halted 9 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted 21 1 I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted 22 1 DBG_CAN_STOP Debug CAN stopped when core is halted 25 1 APB2_FZ APB2FZ APB High Freeze Register 0xC 0x20 read-write 0x00000000 DBG_TIM15_STOP Debug Timer 15 stopped when Core is halted 2 1 DBG_TIM16_STOP Debug Timer 16 stopped when Core is halted 3 1 DBG_TIM17_STO Debug Timer 17 stopped when Core is halted 4 1 DBG_TIM19_STOP Debug Timer 19 stopped when Core is halted 5 1 TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers RTC_WKUP RTC Wakeup interrupt through the EXTI line 3 TIM1_BRK_TIM15 TIM1 Break/TIM15 global interruts 24 TIM1_UP_TIM16 TIM1 Update/TIM16 global interrupts 25 TIM1_TRG_COM_TIM17 TIM1 trigger and commutation/TIM17 interrupts 26 TIM1_CC TIM1 capture compare interrupt 27 RTCAlarm RTC alarm interrupt 41 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 MMS2 Master mode selection 2 20 4 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 OCCS OCREF clear selection 3 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS3 Slave mode selection bit 3 16 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 C5IF Capture/Compare 5 interrupt flag 16 1 C6IF Capture/Compare 6 interrupt flag 17 1 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation 8 1 B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 CCMR3_Output CCMR3_Output capture/compare mode register 3 (output mode) 0x54 0x20 read-write 0x00000000 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 CCR5 CCR5 capture/compare register 0x58 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x5C 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 OR OR option registers 0x60 0x20 read-write 0x00000000 TIM1_ETR_ADC1_RMP TIM1_ETR_ADC1 remapping capability 0 2 TIM1_ETR_ADC4_RMP TIM1_ETR_ADC4 remapping capability 2 2 ADC1 Analog-to-Digital Converter ADC 0x50000000 0x0 0xB9 registers ADC1_2 ADC1 and ADC2 global interrupt 18 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF JQOVF 10 1 oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JEOS JEOS 6 1 oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 JEOC JEOC 5 1 oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 OVR OVR 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 EOS EOS 3 1 oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 EOC EOC 2 1 oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOSMP EOSMP 1 1 oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 ADRDY ADRDY 0 1 oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE JQOVFIE 10 1 JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JEOSIE JEOSIE 6 1 JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 JEOCIE JEOCIE 5 1 JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 OVRIE OVRIE 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 EOSIE EOSIE 3 1 EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 EOCIE EOCIE 2 1 EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSMPIE EOSMPIE 1 1 EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 ADRDYIE ADRDYIE 0 1 ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADCAL ADCAL 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 ADCALDIF ADCALDIF 30 1 ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 ADVREGEN ADVREGEN 28 2 ADVREGEN Intermediate Intermediate state required when moving the ADC voltage regulator between states 0 Enabled ADC voltage regulator enabled 1 Disabled ADC voltage regulator disabled 2 ADSTP ADSTP 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP JADSTP 5 1 oneToSet read write ADSTART ADSTART 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART JADSTART 3 1 oneToSet read write ADDIS ADDIS 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADEN ADEN 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 AWD1CH AWDCH1CH 26 5 0 18 JAUTO JAUTO 25 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 JAWD1EN JAWD1EN 24 1 JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 AWD1EN AWD1EN 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL AWD1SGL 22 1 AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 JQM JQM 21 1 JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 JDISCEN JDISCEN 20 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCNUM DISCNUM 17 3 0 7 DISCEN DISCEN 16 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 AUTDLY AUTDLY 14 1 AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 CONT CONT 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD OVRMOD 12 1 OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 EXTEN EXTEN 10 2 EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 EXTSEL EXTSEL 6 4 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 EXTI11 EXTI line 11 6 HRTIM_ADCTRG1 HRTIM_ADCTRG1 event 7 HRTIM_ADCTRG3 HRTIM_ADCTRG3 event 8 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 ALIGN ALIGN 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 RES RES 3 2 RES Bits12 12-bit 0 Bits10 10-bit 1 Bits8 8-bit 2 Bits6 6-bit 3 DMACFG DMACFG 1 1 DMACFG OneShot DMA One Shot Mode selected 0 Circular DMA circular mode selected 1 DMAEN DMAEN 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 9 0x3 1-9 SMP%s Channel %s sample time selection 3 3 SMP1 Cycles1_5 1.5 ADC clock cycles 0 Cycles2_5 2.5 ADC clock cycles 1 Cycles4_5 4.5 ADC clock cycles 2 Cycles7_5 7.5 ADC clock cycles 3 Cycles19_5 19.5 ADC clock cycles 4 Cycles61_5 61.5 ADC clock cycles 5 Cycles181_5 181.5 ADC clock cycles 6 Cycles601_5 601.5 ADC clock cycles 7 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 9 0x3 10-18 SMP%s Channel %s sample time selection 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 0 4095 LT1 LT1 0 12 0 4095 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 8 0 255 LT2 LT2 0 8 0 255 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x0FFF0000 HT3 HT3 16 8 0 255 LT3 LT3 0 8 0 255 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 1 18 L L3 0 4 0 15 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 RDATA Regular data 0 16 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 4 0x6 1-4 JSQ%s %s conversion in injected sequence 8 5 0 19 JEXTEN JEXTEN 6 2 JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 JEXTSEL JEXTSEL 2 4 JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 EXTI15 EXTI line 15 6 TIM1_TRGO2 Timer 1 TRGO2 event 8 HRTIM_ADCTRG2 HRTIM_ADCTRG2 event 9 HRTIM_ADCTRG4 HRTIM_ADCTRG4 event 10 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 JL JL 0 2 0 3 4 0x4 1-4 OFR%s OFR%s offset register %s 0x60 0x20 read-write 0x00000000 OFFSET_EN Offset X Enable 31 1 OFFSET_EN Disabled Offset disabled 0 Enabled Offset enabled 1 OFFSET_CH Channel selection for the data offset X 26 5 0 31 OFFSET Data offset X for the channel programmed into bits OFFSET_CH 0 12 0 4095 4 0x4 1-4 JDR%s JDR%s injected data register %s 0x80 0x20 read-only 0x00000000 JDATA Injected data 0 16 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 18 0x1 0-17 AWD2CH%s AWD2CH 1 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 18 0x1 0-17 AWD3CH%s AWD3CH 1 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 18 0x1 0-17 DIFSEL%s Differential mode for channel %s 1 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D CALFACT_D 16 7 0 127 CALFACT_S CALFACT_S 0 7 0 127 ADC2 0x50000100 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x400 registers CFGR1 CFGR1 configuration register 1 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection bits 0 2 MEM_MODE MainFlash Main Flash memory mapped at 0x0000_0000 0 SystemFlash System Flash memory mapped at 0x0000_0000 1 MainFlash2 Main Flash memory mapped at 0x0000_0000 2 SRAM Embedded SRAM mapped at 0x0000_0000 3 TIM1_ITR3_RMP Timer 1 ITR3 selection 6 1 TIM1_ITR3_RMP NotRemapped Not remapped 0 Remapped TIM1_ITR3 = TIM17_OC 1 DAC_TRIG_RMP DAC trigger remap (when TSEL = 001) 7 1 DAC_TRIG_RMP NotRemapped Not remapped 0 Remapped DAC trigger is TIM3_TRGO 1 TIM16_DMA_RMP TIM16 DMA request remapping bit 11 1 TIM16_DMA_RMP NotRemapped TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 0 Remapped TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 1 TIM17_DMA_RMP TIM17 DMA request remapping bit 12 1 TIM17_DMA_RMP NotRemapped TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 0 Remapped TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 1 TIM6_DAC1_CH1_DMA_RMP TIM6 and DAC1 DMA request remapping bit 13 1 TIM6_DAC1_CH1_DMA_RMP NotRemapped TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 0 Remapped TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 1 TIM7_DAC1_CH2_DMA_RMP TIM7 and DAC2 DMA request remapping bit 14 1 TIM7_DAC1_CH2_DMA_RMP NotRemapped Not remapped 0 Remapped TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 1 I2C_PB6_FMP Fast Mode Plus (FM+) driving capability activation bits. 16 1 I2C_PB6_FMP Standard PB6 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB6 and the Speed control is bypassed 1 I2C_PB7_FMP Fast Mode Plus (FM+) driving capability activation bits. 17 1 I2C_PB7_FMP Standard PB7 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB7 and the Speed control is bypassed 1 I2C_PB8_FMP Fast Mode Plus (FM+) driving capability activation bits. 18 1 I2C_PB8_FMP Standard PB8 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB8 and the Speed control is bypassed 1 I2C_PB9_FMP Fast Mode Plus (FM+) driving capability activation bits. 19 1 I2C_PB9_FMP Standard PB9 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB9 and the Speed control is bypassed 1 I2C1_FMP I2C1 Fast Mode Plus 20 1 I2C1_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits 1 I2C2_FMP I2C2 Fast Mode Plus 21 1 I2C2_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits 1 ENCODER_MODE Encoder mode 22 2 ENCODER_MODE NoRedirection No redirection 0 MapTim2Tim15 TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 1 MapTim3Tim15 TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 2 FPU_IE5 Inexact interrupt enable 31 1 read-write FPU_IE5 Disabled Inexact interrupt disable 0 Enabled Inexact interrupt enable 1 FPU_IE4 Input denormal interrupt enable 30 1 read-write FPU_IE4 Disabled Input denormal interrupt disable 0 Enabled Input denormal interrupt enable 1 FPU_IE3 Overflow interrupt enable 29 1 read-write FPU_IE3 Disabled Overflow interrupt disable 0 Enabled Overflow interrupt enable 1 FPU_IE2 Underflow interrupt enable 28 1 read-write FPU_IE2 Disabled Underflow interrupt disable 0 Enabled Underflow interrupt enable 1 FPU_IE1 Devide-by-zero interrupt enable 27 1 read-write FPU_IE1 Disabled Devide-by-zero interrupt disable 0 Enabled Devide-by-zero interrupt enable 1 FPU_IE0 Invalid operation interrupt enable 26 1 read-write FPU_IE0 Disabled Invalid operation interrupt disable 0 Enabled Invalid operation interrupt enable 1 DAC2_CH1_DMA_RMP DAC2 channel1 DMA remap 15 1 read-write DAC2_CH1_DMA_RMP NotRemapped Not remapped 0 Remapped DAC2_CH1 DMA requests mapped on DMA1 channel 5 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI 3 configuration bits 12 4 ExtiAbcde PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 EXTI2 EXTI 2 configuration bits 8 4 EXTI1 EXTI 1 configuration bits 4 4 EXTI0 EXTI 0 configuration bits 0 4 ExtiAbcdef PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PF Select PFx as the source input for the EXTIx external interrupt 5 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI 7 configuration bits 12 4 EXTI6 EXTI 6 configuration bits 8 4 EXTI5 EXTI 5 configuration bits 4 4 EXTI4 EXTI 4 configuration bits 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI 11 configuration bits 12 4 EXTI10 EXTI 10 configuration bits 8 4 EXTI9 EXTI 9 configuration bits 4 4 EXTI8 EXTI 8 configuration bits 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI 15 configuration bits 12 4 EXTI14 EXTI 14 configuration bits 8 4 EXTI13 EXTI 13 configuration bits 4 4 EXTI12 EXTI 12 configuration bits 0 4 CFGR2 CFGR2 configuration register 2 0x18 0x20 read-write 0x00000000 LOCKUP_LOCK Cortex-M0 LOCKUP bit enable bit 0 1 LOCKUP_LOCK Disconnected Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT. 0 Connected Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs 1 SRAM_PARITY_LOCK SRAM parity lock bit 1 1 SRAM_PARITY_LOCK Disconnected SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs 0 Connected SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs 1 PVD_LOCK PVD lock enable bit 2 1 PVD_LOCK Disconnected PVD interrupt disconnected from TIM15/16/17 Break input 0 Connected PVD interrupt connected to TIM15/16/17 Break input 1 BYP_ADDR_PAR Bypass address bit 29 in parity calculation 4 1 BYP_ADDR_PAR NoBypass The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated 0 Bypass The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated 1 SRAM_PEF SRAM parity flag 8 1 SRAM_PEFR read NoParityError No SRAM parity error detected 0 ParityErrorDetected SRAM parity error detected 1 SRAM_PEFW write Clear Clear SRAM parity error flag 1 RCR RCR CCM SRAM protection register 0x4 0x20 read-write 0x00000000 PAGE0_WP CCM SRAM page write protection bit 0 1 PAGE0_WP Disabled Write protection of pagex is disabled 0 Enabled Write protection of pagex is enabled 1 PAGE1_WP CCM SRAM page write protection bit 1 1 PAGE2_WP CCM SRAM page write protection bit 2 1 PAGE3_WP CCM SRAM page write protection bit 3 1 CFGR3 CFGR3 configuration register 3 0x50 0x20 read-write 0x00000000 DAC1_TRIG5_RMP DAC1_CH1 / DAC1_CH2 Trigger remap 17 1 DAC1_TRIG5_RMP NotRemapped Not remapped 0 Remapped DAC trigger is HRTIM1_DAC1_TRIG2 1 DAC1_TRIG3_RMP DAC1_CH1 / DAC1_CH2 Trigger remap 16 1 DAC1_TRIG3_RMP Tim15 DAC trigger is TIM15_TRGO 0 HrTim1 DAC trigger is HRTIM1_DAC1_TRIG1 1 I2C1_RX_DMA_RMP I2C1_RX DMA remapping bit 4 2 I2C1_RX_DMA_RMP MapDma1Ch7 I2C1_RX mapped on DMA1 CH7 0 MapDma1Ch3 I2C1_RX mapped on DMA1 CH3 1 MapDma1Ch5 I2C1_RX mapped on DMA1 CH5 2 SPI1_TX_DMA_RMP SPI1_TX DMA remapping bit 2 2 SPI1_TX_DMA_RMP MapDma1Ch3 SPI1_TX mapped on DMA1 CH3 0 MapDma1Ch5 SPI1_TX mapped on DMA1 CH5 1 MapDma1Ch7 SPI1_TX mapped on DMA1 CH7 2 SPI1_RX_DMA_RMP SPI1_RX DMA remapping bit 0 2 SPI1_RX_DMA_RMP MapDma1Ch3 SPI1_RX mapped on DMA1 CH2 0 MapDma1Ch5 SPI1_RX mapped on DMA1 CH4 1 MapDma1Ch7 SPI1_RX mapped on DMA1 CH6 2 I2C1_TX_DMA_RMP I2C1_TX DMA remapping bit 6 2 I2C1_TX_DMA_RMP MapDma1Ch6 I2C1_TX mapped on DMA1 CH6 0 MapDma1Ch2 I2C1_TX mapped on DMA1 CH2 1 MapDma1Ch4 I2C1_TX mapped on DMA1 CH4 2 ADC2_DMA_RMP ADC2 DMA remapping bit 8 2 ADC2_DMA_RMP MapDma2 ADC2 mapped on DMA2 0 MapDma1Ch2 ADC2 mapped on DMA1 channel 2 2 MapDma1Ch4 ADC2 mapped on DMA1 channel 4 3 OPAMP Operational Amplifier 0x40010000 0x0 0x400 registers OPAMP2_CSR OPAMP2 control register 0x3C 0x20 0x00000000 OPAMP2EN OPAMP2 enable 0 1 read-write OPAMP2EN Disabled OPAMP2 is disabled 0 Enabled OPAMP2 is enabled 1 FORCE_VP FORCE_VP 1 1 read-write FORCE_VP Normal Normal operating mode 0 Calibration Calibration mode. Non-inverting input connected to calibration reference 1 VP_SEL OPAMP Non inverting input selection 2 2 read-write VP_SEL PB14 PB14 used as OPAMP2 non-inverting input 1 PB0 PB0 used as OPAMP2 non-inverting input 2 PA7 PA7 used as OPAMP2 non-inverting input 3 VM_SEL OPAMP inverting input selection 5 2 read-write VM_SEL PC5 PC5 (VM0) used as OPAMP2 inverting input 0 PA5 PA5 (VM1) used as OPAMP2 inverting input 1 PGA Resistor feedback output (PGA mode) 2 Follower Follower mode 3 TCM_EN Timer controlled Mux mode enable 7 1 read-write TCM_EN Disabled Timer controlled mux disabled 0 Enabled Timer controlled mux enabled 1 VMS_SEL OPAMP inverting input secondary selection 8 1 read-write VMS_SEL PC5 PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1 0 PA5 PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1 1 VPS_SEL OPAMP Non inverting input secondary selection 9 2 read-write VPS_SEL PB14 PB14 used as OPAMP2 non-inverting input when TCM_EN=1 1 PB0 PB0 used as OPAMP2 non-inverting input when TCM_EN=1 2 PA7 PA7 used as OPAMP2 non-inverting input when TCM_EN=1 3 CALON Calibration mode enable 11 1 read-write CALON Disabled Calibration mode disabled 0 Enabled Calibration mode enabled 1 CALSEL Calibration selection 12 2 read-write CALSEL Percent3_3 VREFOPAMP=3.3% VDDA 0 Percent10 VREFOPAMP=10% VDDA 1 Percent50 VREFOPAMP=50% VDDA 2 Percent90 VREFOPAMP=90% VDDA 3 PGA_GAIN Gain in PGA mode 14 4 read-write PGA_GAIN Gain2 Gain 2 0 Gain4 Gain 4 1 Gain8 Gain 8 2 Gain16 Gain 16 4 Gain2_VM0 Gain 2, feedback connected to VM0 8 Gain4_VM0 Gain 4, feedback connected to VM0 9 Gain8_VM0 Gain 8, feedback connected to VM0 10 Gain16_VM0 Gain 16, feedback connected to VM0 11 Gain2_VM1 Gain 2, feedback connected to VM1 12 Gain4_VM1 Gain 4, feedback connected to VM1 13 Gain8_VM1 Gain 8, feedback connected to VM1 14 Gain16_VM1 Gain 16, feedback connected to VM1 15 USER_TRIM User trimming enable 18 1 read-write USER_TRIM Disabled User trimming disabled 0 Enabled User trimming enabled 1 TRIMOFFSETP Offset trimming value (PMOS) 19 5 read-write 0 31 TRIMOFFSETN Offset trimming value (NMOS) 24 5 read-write 0 31 TSTREF TSTREF 29 1 read-write TSTREF Output VREFOPAMP2 is output 0 NotOutput VREFOPAMP2 is not output 1 OUTCAL OPAMP ouput status flag 30 1 read-only OUTCAL Low Non-inverting < inverting 0 High Non-inverting > inverting 1 LOCK OPAMP lock 31 1 read-write LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 COMP General purpose comparators 0x40010000 0x0 0x400 registers COMP1_2_3 COMP1_2_3 interrupt combined with EXTI lines 21, 22, 29 64 COMP4_5_6 COMP4_5_6 interrupt combined with EXTI lines 30, 31, 32 65 COMP2_CSR control and status register 0x20 0x20 0x00000000 COMP2EN Comparator 2 enable 0 1 read-write COMP2EN Disabled Comparator disabled 0 Enabled Comparator enabled 1 COMP2INMSEL Comparator 2 inverting input selection 4 3 read-write COMP2INMSEL OneQuarterVRef 1/4 of VRefint 0 OneHalfVRef 1/2 of VRefint 1 ThreeQuarterVRef 3/4 of VRefint 2 VRef VRefint 3 PA4_DAC1_CH1 PA4 or DAC1_CH1 output if enabled 4 DAC1_CH2 DAC1_CH2 5 PA2 PA2 6 COMP2OUTSEL Comparator 2 output selection 10 4 read-write COMP2OUTSEL NoSelection No selection 0 Timer1BreakInput Timer 1 break input 1 Timer1BreakInput2 Timer 1 break input 2 2 Timer1OCRefClearInput Timer 1 OCREF_CLR input 6 Timer1InputCapture1 Timer 1 input capture 1 7 Timer2InputCapture4 Timer 2 input capture 4 8 Timer2OCRefClearInput Timer 2 OCREF_CLR input 9 Timer3InputCapture1 Timer 3 input capture 1 10 Timer3OCRefClearInput Timer 3 OCREF_CLR input 11 COMP2POL Comparator 2 output polarity 15 1 read-write COMP2POL NotInverted Output is not inverted 0 Inverted Output is inverted 1 COMP2_BLANKING Comparator 2 blanking source 18 3 read-write COMP2_BLANKING NoBlanking No blanking 0 TIM1OC5 TIM1 OC5 selected as blanking source 1 TIM2OC3 TIM2 OC3 selected as blanking source 2 TIM3OC3 TIM3 OC3 selected as blanking source 3 COMP2OUT Comparator 2 output 30 1 read-only COMP2OUT Low Non-inverting input below inverting input 0 High Non-inverting input above inverting input 1 COMP2LOCK Comparator 2 lock 31 1 read-write COMP2LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 COMP2INMSEL3 Comparator 2 inverting input selection 22 1 read-write COMP4_CSR control and status register 0x28 0x20 0x00000000 COMP4EN Comparator 4 enable 0 1 read-write COMP4EN Disabled Comparator disabled 0 Enabled Comparator enabled 1 COMP4INMSEL Comparator 4 inverting input selection 4 3 read-write COMP4INMSEL OneQuarterVRef 1/4 of VRefint 0 OneHalfVRef 1/2 of VRefint 1 ThreeQuarterVRef 3/4 of VRefint 2 VRef VRefint 3 PA4_DAC1_CH1 PA4 or DAC1_CH1 output if enabled 4 DAC1_CH2 DAC1_CH2 5 PB2 PB2 7 COMP4OUTSEL Comparator 4 output selection 10 4 read-write COMP4OUTSEL NoSelection No selection 0 Timer1BreakInput Timer 1 break input 1 Timer1BreakInput2 Timer 1 break input 2 2 Timer3InputCapture3 Timer 3 input capture 3 6 Timer15InputCapture2 Timer 15 input capture 2 8 Timer15OCRefClearInput Timer 15 OCREF_CLR input 10 Timer3OCRefClearInput Timer 3 OCREF_CLR input 11 COMP4POL Comparator 4 output polarity 15 1 read-write COMP4POL NotInverted Output is not inverted 0 Inverted Output is inverted 1 COMP4_BLANKING Comparator 4 blanking source 18 3 read-write COMP4_BLANKING NoBlanking No blanking 0 TIM3OC4 TIM3 OC4 selected as blanking source 1 TIM15OC1 TIM15 OC1 selected as blanking source 3 COMP4OUT Comparator 4 output 30 1 read-only COMP4OUT Low Non-inverting input below inverting input 0 High Non-inverting input above inverting input 1 COMP4LOCK Comparator 4 lock 31 1 read-write COMP4LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 COMP4INMSEL3 Comparator 4 inverting input selection 22 1 read-write COMP6_CSR control and status register 0x30 0x20 0x00000000 COMP6EN Comparator 6 enable 0 1 read-write COMP6EN Disabled Comparator disabled 0 Enabled Comparator enabled 1 COMP6INMSEL Comparator 6 inverting input selection 4 3 read-write COMP6INMSEL OneQuarterVRef 1/4 of VRefint 0 OneHalfVRef 1/2 of VRefint 1 ThreeQuarterVRef 3/4 of VRefint 2 VRef VRefint 3 PA4_DAC1_CH1 PA4 or DAC1_CH1 output if enabled 4 DAC1_CH2 DAC1_CH2 5 PB15 PB15 7 COMP6OUTSEL Comparator 6 output selection 10 4 read-write COMP6OUTSEL NoSelection No selection 0 Timer1BreakInput Timer 1 break input 1 Timer1BreakInput2 Timer 1 break input 2 2 Timer2InputCapture2 Timer 2 input capture 2 6 Timer2OCRefClearInput Timer 2 OCREF_CLR input 8 Timer16OCRefClearInput Timer 16 OCREF_CLR input 9 Timer16InputCapture1 Timer 16 input capture 1 10 COMP6POL Comparator 6 output polarity 15 1 read-write COMP6POL NotInverted Output is not inverted 0 Inverted Output is inverted 1 COMP6_BLANKING Comparator 6 blanking source 18 3 read-write COMP6_BLANKING NoBlanking No blanking 0 TIM2OC4 TIM2 OC4 selected as blanking source 3 TIM15OC2 TIM15 OC2 selected as blanking source 4 COMP6OUT Comparator 6 output 30 1 read-only COMP6OUT Low Non-inverting input below inverting input 0 High Non-inverting input above inverting input 1 COMP6LOCK Comparator 6 lock 31 1 read-write COMP6LOCK Unlocked Comparator CSR bits are read-write 0 Locked Comparator CSR bits are read-only 1 COMP6INMSEL3 Comparator 6 inverting input selection 22 1 read-write TIM3 General purpose timer TIM 0x40000400 0x0 0x400 registers TIM3_IRQ Timer 3 global interrupt 29 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 0 65535 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 CAN Controller area network CAN 0x40006400 0x0 0x400 registers USB_HP_CAN_TX USB High Priority/CAN_TX interrupts 19 USB_LP_CAN_RX0 USB Low Priority/CAN_RX0 interrupts 20 CAN_RX1 CAN_RX1 interrupt 21 CAN_SCE CAN_SCE interrupt 22 MCR MCR master control register 0x0 0x20 read-write 0x00010002 DBF DBF 16 1 RESET RESET 15 1 TTCM TTCM 7 1 ABOM ABOM 6 1 AWUM AWUM 5 1 NART NART 4 1 RFLM RFLM 3 1 TXFP TXFP 2 1 SLEEP SLEEP 1 1 INRQ INRQ 0 1 MSR MSR master status register 0x4 0x20 0x00000C02 RX RX 11 1 read-only SAMP SAMP 10 1 read-only RXM RXM 9 1 read-only TXM TXM 8 1 read-only SLAKI SLAKI 4 1 read-write WKUI WKUI 3 1 read-write ERRI ERRI 2 1 read-write SLAK SLAK 1 1 read-only INAK INAK 0 1 read-only TSR TSR transmit status register 0x8 0x20 0x1C000000 3 0x1 0-2 LOW%s Lowest priority flag for mailbox %s 29 1 read-only 3 0x1 0-2 TME%s Lowest priority flag for mailbox %s 26 1 read-only CODE CODE 24 2 read-only 3 0x8 0-2 ABRQ%s ABRQ%s 7 1 read-write 3 0x8 0-2 TERR%s TERR%s 3 1 read-write 3 0x8 0-2 ALST%s ALST%s 2 1 read-write 3 0x8 0-2 TXOK%s TXOK%s 1 1 read-write 3 0x8 0-2 RQCP%s RQCP%s 0 1 read-write 2 0x4 0-1 RF%sR RF%sR receive FIFO %s register 0xC 0x20 0x00000000 RFOM RFOM0 5 1 read-write RFOM0W write Release Set by software to release the output mailbox of the FIFO 1 FOVR FOVR0 4 1 read-write FOVR0R read NoOverrun No FIFO x overrun 0 Overrun FIFO x overrun 1 FOVR0W write Clear Clear flag 1 FULL FULL0 3 1 read-write FULL0R read NotFull FIFO x is not full 0 Full FIFO x is full 1 FULL0W write Clear Clear flag 1 FMP FMP0 0 2 read-only IER IER interrupt enable register 0x14 0x20 read-write 0x00000000 SLKIE SLKIE 17 1 SLKIE Disabled No interrupt when SLAKI bit is set 0 Enabled Interrupt generated when SLAKI bit is set 1 WKUIE WKUIE 16 1 WKUIE Disabled No interrupt when WKUI is set 0 Enabled Interrupt generated when WKUI bit is set 1 ERRIE ERRIE 15 1 ERRIE Disabled No interrupt will be generated when an error condition is pending in the CAN_ESR 0 Enabled An interrupt will be generation when an error condition is pending in the CAN_ESR 1 LECIE LECIE 11 1 LECIE Disabled ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection 0 Enabled ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection 1 BOFIE BOFIE 10 1 BOFIE Disabled ERRI bit will not be set when BOFF is set 0 Enabled ERRI bit will be set when BOFF is set 1 EPVIE EPVIE 9 1 EPVIE Disabled ERRI bit will not be set when EPVF is set 0 Enabled ERRI bit will be set when EPVF is set 1 EWGIE EWGIE 8 1 EWGIE Disabled ERRI bit will not be set when EWGF is set 0 Enabled ERRI bit will be set when EWGF is set 1 FOVIE1 FOVIE1 6 1 FOVIE1 Disabled No interrupt when FOVR is set 0 Enabled Interrupt generation when FOVR is set 1 FFIE1 FFIE1 5 1 FFIE1 Disabled No interrupt when FULL bit is set 0 Enabled Interrupt generated when FULL bit is set 1 FMPIE1 FMPIE1 4 1 FMPIE1 Disabled No interrupt generated when state of FMP[1:0] bits are not 00b 0 Enabled Interrupt generated when state of FMP[1:0] bits are not 00b 1 FOVIE0 FOVIE0 3 1 FOVIE0 Disabled No interrupt when FOVR bit is set 0 Enabled Interrupt generated when FOVR bit is set 1 FFIE0 FFIE0 2 1 FFIE0 Disabled No interrupt when FULL bit is set 0 Enabled Interrupt generated when FULL bit is set 1 FMPIE0 FMPIE0 1 1 FMPIE0 Disabled No interrupt generated when state of FMP[1:0] bits are not 00 0 Enabled Interrupt generated when state of FMP[1:0] bits are not 00b 1 TMEIE TMEIE 0 1 TMEIE Disabled No interrupt when RQCPx bit is set 0 Enabled Interrupt generated when RQCPx bit is set 1 ESR ESR error status register 0x18 0x20 0x00000000 REC REC 24 8 read-only TEC TEC 16 8 read-only LEC LEC 4 3 read-write LEC NoError No Error 0 Stuff Stuff Error 1 Form Form Error 2 Ack Acknowledgment Error 3 BitRecessive Bit recessive Error 4 BitDominant Bit dominant Error 5 Crc CRC Error 6 Custom Set by software 7 BOFF BOFF 2 1 read-only EPVF EPVF 1 1 read-only EWGF EWGF 0 1 read-only BTR BTR bit timing register 0x1C 0x20 read-write 0x01230000 SILM SILM 31 1 SILM Normal Normal operation 0 Silent Silent Mode 1 LBKM LBKM 30 1 LBKM Disabled Loop Back Mode disabled 0 Enabled Loop Back Mode enabled 1 SJW SJW 24 2 TS2 TS2 20 3 TS1 TS1 16 4 BRP BRP 0 10 3 0x10 0-2 TX%s CAN Transmit cluster 0x180 TIR TI0R TX mailbox identifier register 0x0 0x20 read-write 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 IDE Standard Standard identifier 0 Extended Extended identifier 1 RTR RTR 1 1 RTR Data Data frame 0 Remote Remote frame 1 TXRQ TXRQ 0 1 TDTR TDT0R mailbox data length control and time stamp register 0x4 0x20 read-write 0x00000000 TIME TIME 16 16 TGT TGT 8 1 DLC DLC 0 4 0 8 TDLR TDL0R mailbox data low register 0x8 0x20 read-write 0x00000000 4 0x8 0-3 DATA%s DATA%s 0 8 TDHR TDH0R mailbox data high register 0xC 0x20 read-write 0x00000000 4 0x8 4-7 DATA%s DATA%s 0 8 2 0x10 0-1 RX%s CAN Receive cluster 0x1B0 RIR RI0R receive FIFO mailbox identifier register 0x0 0x20 read-only 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 IDE Standard Standard identifier 0 Extended Extended identifier 1 RTR RTR 1 1 RTR Data Data frame 0 Remote Remote frame 1 RDTR RDT0R receive FIFO mailbox data length control and time stamp register 0x4 0x20 read-only 0x00000000 TIME TIME 16 16 FMI FMI 8 8 DLC DLC 0 4 0 8 RDLR RDL0R receive FIFO mailbox data low register 0x8 0x20 read-only 0x00000000 4 0x8 0-3 DATA%s DATA%s 0 8 RDHR RDH0R receive FIFO mailbox data high register 0xC 0x20 read-only 0x00000000 4 0x8 4-7 DATA%s DATA%s 0 8 FMR FMR filter master register 0x200 0x20 read-write 0x2A1C0E01 CAN2SB CAN2 start bank 8 6 FINIT Filter init mode 0 1 FM1R FM1R filter mode register 0x204 0x20 read-write 0x00000000 28 0x1 0-27 FBM%s Filter mode 0 1 FS1R FS1R filter scale register 0x20C 0x20 read-write 0x00000000 28 0x1 0-27 FSC%s Filter scale configuration 0 1 FFA1R FFA1R filter FIFO assignment register 0x214 0x20 read-write 0x00000000 28 0x1 0-27 FFA%s Filter FIFO assignment for filter %s 0 1 FA1R FA1R CAN filter activation register 0x21C 0x20 read-write 0x00000000 28 0x1 0-27 FACT%s Filter active 0 1 28 0x8 0-27 FB%s CAN Filter Bank cluster 0x240 FR1 F0R1 Filter bank x register 1 0x0 0x20 read-write 0x00000000 FB Filter bits 0 32 FR2 F0R2 Filter bank x register 2 0x4 0x20 read-write 0x00000000 FB Filter bits 0 32 ADC1_2 ADC common registers ADC_Common 0x50000300 0x0 0x11 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADRDY_MST Master ADC ready 0 1 ADRDY_MST NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 EOSMP_MST End of Sampling phase flag of the master ADC 1 1 EOSMP_MST NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOC_MST End of regular conversion of the master ADC 2 1 EOC_MST NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOS_MST End of regular sequence flag of the master ADC 3 1 EOS_MST NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 OVR_MST Overrun flag of the master ADC 4 1 OVR_MST NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 JEOC_MST End of injected conversion flag of the master ADC 5 1 JEOC_MST NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOS_MST End of injected sequence flag of the master ADC 6 1 JEOS_MST NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 AWD1_MST Analog watchdog 1 flag of the master ADC 7 1 AWD1_MST NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD2_MST Analog watchdog 2 flag of the master ADC 8 1 AWD3_MST Analog watchdog 3 flag of the master ADC 9 1 JQOVF_MST Injected Context Queue Overflow flag of the master ADC 10 1 JQOVF_MST NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 ADRDY_SLV Slave ADC ready 16 1 EOSMP_SLV End of Sampling phase flag of the slave ADC 17 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 OVR_SLV Overrun flag of the slave ADC 20 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 DUAL Dual ADC mode selection 0 5 DUAL Independent Independent mode 0 DualRJ Dual, combined regular simultaneous + injected simultaneous mode 1 DualRA Dual, combined regular simultaneous + alternate trigger mode 2 DualIJ Dual, combined interleaved mode + injected simultaneous mode 3 DualJ Dual, injected simultaneous mode only 5 DualR Dual, regular simultaneous mode only 6 DualI Dual, interleaved mode only 7 DualA Dual, alternate trigger mode only 9 DELAY Delay between 2 sampling phases 8 4 0 15 DMACFG DMA configuration (for dual ADC mode) 13 1 DMACFG OneShot DMA one shot mode selected 0 Circulator DMA circular mode selected 1 MDMA Direct memory access mode for dual ADC mode 14 2 MDMA Disabled MDMA mode disabled 0 Bits12_10 MDMA mode enabled for 12 and 10-bit resolution 2 Bits8_6 MDMA mode enabled for 8 and 6-bit resolution 3 CKMODE ADC clock mode 16 2 CKMODE Asynchronous Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock 0 SyncDiv1 Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck 1 SyncDiv2 Use AHB clock rcc_hclk3 divided by 2 2 SyncDiv4 Use AHB clock rcc_hclk3 divided by 4 3 VREFEN VREFINT enable 22 1 VREFEN Disabled V_REFINT channel disabled 0 Enabled V_REFINT channel enabled 1 TSEN Temperature sensor enable 23 1 TSEN Disabled Temperature sensor channel disabled 0 Enabled Temperature sensor channel enabled 1 VBATEN VBAT enable 24 1 VBATEN Disabled V_BAT channel disabled 0 Enabled V_BAT channel enabled 1 CDR CDR ADC common regular data register for dual mode 0xC 0x20 read-only 0x00000000 RDATA_SLV Regular data of the slave ADC 16 16 RDATA_MST Regular data of the master ADC 0 16 HRTIM_Master High Resolution Timer: Master Timers HRTIM 0x40017400 0x0 0x80 registers HRTIM_MST HRTIM1 master timer interrupt 67 CR CR Master Timer Control Register 0x0 0x20 read-write 0x00000000 BRSTDMA Burst DMA Update 30 2 BRSTDMA Independent Update done independently from the DMA burst transfer completion 0 Completion Update done when the DMA burst transfer is completed 1 Rollover Update done on master timer roll-over following a DMA burst transfer completion 2 MREPU Master Timer Repetition update 29 1 MREPU Disabled Update on repetition disabled 0 Enabled Update on repetition enabled 1 PREEN Preload enable 27 1 PREEN Disabled Preload disabled: the write access is directly done into the active register 0 Enabled Preload enabled: the write access is done into the preload register 1 DACSYNC AC Synchronization 25 2 DACSYNC Disabled No DAC trigger generated 0 DACSync1 Trigger generated on DACSync1 1 DACSync2 Trigger generated on DACSync2 2 DACSync3 Trigger generated on DACSync3 3 5 0x1 A,B,C,D,E T%sCEN Timer %s counter enable 17 1 TACEN Disabled Timer counter disabled 0 Enabled Timer counter enabled 1 MCEN Master Counter enable 16 1 MCEN Disabled Master timer counter disabled 0 Enabled Master timer counter enabled 1 SYNCSRC Synchronization source 14 2 SYNCSRC MasterStart Master timer Start 0 MasterCompare1 Master timer Compare 1 event 1 TimerAStart Timer A start/reset 2 TimerACompare1 Timer A Compare 1 event 3 SYNCOUT Synchronization output 12 2 SYNCOUT Disabled Disabled 0 PositivePulse Positive pulse on SCOUT output (16x f_HRTIM clock cycles) 2 NegativePulse Negative pulse on SCOUT output (16x f_HRTIM clock cycles) 3 SYNCSTRT Synchronization Starts Master 11 1 SYNCSTRT Disabled No effect on the master timer 0 Start A synchroniation input event starts the master timer 1 SYNCRST Synchronization Resets Master 10 1 SYNCRST Disabled No effect on the master timer 0 Reset A synchroniation input event resets the master timer 1 SYNCIN ynchronization input 8 2 SYNCIN Disabled Disabled. HRTIM is not synchronized and runs in standalone mode 0 Internal Internal event: the HRTIM is synchronized with the on-chip timer 2 External External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM 3 HALF Half mode enable 5 1 HALF Disabled Half mode disabled 0 Enabled Half mode enabled 1 RETRIG Master Re-triggerable mode 4 1 RETRIG Disabled The timer is not re-triggerable: a counter reset can be done only if the counter is stopped 0 Enabled The timer is retriggerable: a counter reset is done whatever the counter state 1 CONT Master Continuous mode 3 1 CONT SingleShot The timer operates in single-shot mode and stops when it reaches the MPER value 0 Continuous The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value 1 CKPSC HRTIM Master Clock prescaler 0 3 0 7 ISR ISR Master Timer Interrupt Status Register 0x4 0x20 read-only 0x00000000 UPD Master Update Interrupt Flag 6 1 UPD NoEvent No timer update interrupt occurred 0 Event Timer update interrupt occurred 1 SYNC Sync Input Interrupt Flag 5 1 SYNC NoEvent No sync input interrupt occurred 0 Event Sync input interrupt occurred 1 REP Master Repetition Interrupt Flag 4 1 REP NoEvent No timer repetition interrupt occurred 0 Event Timer repetition interrupt occurred 1 4 0x1 1-4 CMP%s Master Compare %s Interrupt Flag 0 1 CMP1 NoEvent No compare interrupt occurred 0 Event Compare interrupt occurred 1 ICR ICR Master Timer Interrupt Clear Register 0x8 0x20 write-only 0x00000000 4 0x1 1-4 CMP%sC Master Compare %s Interrupt flag clear 0 1 oneToClear CMP1CW Clear Clears associated flag in ISR register 1 UPDC Master update Interrupt flag clear 6 1 oneToClear SYNCC Sync Input Interrupt flag clear 5 1 oneToClear REPC Repetition Interrupt flag clear 4 1 oneToClear DIER DIER4 MDIER4 0xC 0x20 read-write 0x00000000 4 0x1 1-4 CMP%sDE MCMP%sDE 16 1 CMP1DE Disabled DMA request disabled 0 Enabled DMA request enabled 1 UPDDE MUPDDE 22 1 SYNCDE SYNCDE 21 1 REPDE MREPDE 20 1 4 0x1 1-4 CMP%sIE MCMP%sIE 0 1 CMP1IE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 UPDIE MUPDIE 6 1 SYNCIE SYNCIE 5 1 REPIE MREPIE 4 1 CNTR CNTR Master Timer Counter Register 0x10 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 PERR PER Master Timer Period Register 0x14 0x20 read-write 0x0000FFFF PER Master Timer Period value 0 16 0 65535 REPR REP Master Timer Repetition Register 0x18 0x20 read-write 0x00000000 REP Master Timer Repetition counter value 0 8 0 255 CMP1R CMP1R Master Timer Compare 1 Register 0x1C 0x20 read-write 0x00000000 CMP Master Timer Compare 1 value 0 16 0 65535 CMP2R CMP2R Master Timer Compare 2 Register 0x24 CMP3R CMP3R Master Timer Compare 3 Register 0x28 CMP4R CMP4R Master Timer Compare 4 Register 0x2C HRTIM_TIMA High Resolution Timer: TIMA HRTIM 0x40017480 0x0 0x80 registers HRTIM_TIMA HRTIM1 timer A interrupt 68 CR ACR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 UPDGAT Independent Update occurs independently from the DMA burst transfer 0 DMABurst Update occurs when the DMA burst transfer is completed 1 DMABurst_Update Update occurs on the update event following DMA burst transfer completion 2 Input1 Update occurs on a rising edge of HRTIM update enable input 1 3 Input2 Update occurs on a rising edge of HRTIM update enable input 2 4 Input3 Update occurs on a rising edge of HRTIM update enable input 3 5 Input1_Update Update occurs on the update event following a rising edge of HRTIM update enable input 1 6 Input2_Update Update occurs on the update event following a rising edge of HRTIM update enable input 2 7 Input3_Update Update occurs on the update event following a rising edge of HRTIM update enable input 3 8 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 MSTU Disabled Update by master timer disabled 0 Enabled Update by master timer enabled 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TRSTU Disabled Update by timer x reset/roll-over disabled 0 Enabled Update by timer x reset/roll-over enabled 1 TREPU Timer x Repetition update 17 1 TREPU Disabled Update by timer x repetition disabled 0 Enabled Update by timer x repetition enabled 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP4 Standard CMP4 register is always active (standard compare mode) 0 Capture2 CMP4 is recomputed and is active following a capture 2 event 1 Capture2_Compare1 CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match 2 Capture_Compare3 CMP4 is recomputed and is active following a capture event or a Compare 3 match 3 DELCMP2 Delayed CMP2 mode 12 2 DELCMP2 Standard CMP2 register is always active (standard compare mode) 0 Capture1 CMP2 is recomputed and is active following a capture 1 event 1 Capture1_Compare1 CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match 2 Capture1_Compare3 CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match 3 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 PSHPLL Disabled Push-pull mode disabled 0 Enabled Push-pull mode enabled 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR AISR Timerx Interrupt Status Register 0x4 0x20 read-only 0x00000000 O1CPY Output 1 Copy 20 1 O1CPY Inactive Output is inactive 0 Active Output is active 1 O2CPY Output 2 Copy 21 1 O1STAT Output 1 State 18 1 O1STAT Inactive Output was inactive 0 Active Output was active 1 O2STAT Output 2 State 19 1 IPPSTAT Idle Push Pull Status 17 1 IPPSTAT Output1Active Protection occurred when the output 1 was active and output 2 forced inactive 0 Output2Active Protection occurred when the output 2 was active and output 1 forced inactive 1 CPPSTAT Current Push Pull Status 16 1 CPPSTAT Output1Active Signal applied on output 1 and output 2 forced inactive 0 Output2Active Signal applied on output 2 and output 1 forced inactive 1 DLYPRT Delayed Protection Flag 14 1 DLYPRT Inactive Not in delayed idle or balanced idle mode 0 Active Delayed idle or balanced idle mode entry 1 RST Reset Interrupt Flag 13 1 RST NoEvent No TIMx counter reset/roll-over interrupt occurred 0 Event TIMx counter reset/roll-over interrupt occurred 1 RST1 Output 1 Reset Interrupt Flag 10 1 RST1 NoEvent No Tx output reset interrupt occurred 0 Event Tx output reset interrupt occurred 1 RST2 Output 2 Reset Interrupt Flag 12 1 2 0x2 1-2 SET%s Output %s Set Interrupt Flag 9 1 SET1 NoEvent No Tx output set interrupt occurred 0 Event Tx output set interrupt occurred 1 2 0x1 1-2 CPT%s Capture%s Interrupt Flag 7 1 CPT1 NoEvent No timer x capture reset interrupt occurred 0 Event Timer x capture reset interrupt occurred 1 UPD Update Interrupt Flag 6 1 REP Repetition Interrupt Flag 4 1 4 0x1 1-4 CMP%s Compare %s Interrupt Flag 0 1 ICR AICR Timerx Interrupt Clear Register 0x8 0x20 write-only 0x00000000 4 0x1 1-4 CMP%sC Compare %s Interrupt flag Clear 0 1 DLYPRTC Delayed Protection Flag Clear 14 1 RSTC Reset Interrupt flag Clear 13 1 RST2C Output 2 Reset flag Clear 12 1 2 0x2 1-2 SET%sC Output %s Set flag Clear 9 1 RST1C Output 1 Reset flag Clear 10 1 2 0x1 1-2 CPT%sC Capture%s Interrupt flag Clear 7 1 UPDC Update Interrupt flag Clear 6 1 REPC Repetition Interrupt flag Clear 4 1 DIER ADIER5 TIMxDIER5 0xC 0x20 read-write 0x00000000 4 0x1 1-4 CMP%sDE CMP%sDE 16 1 DLYPRTDE DLYPRTDE 30 1 RSTDE RSTDE 29 1 RST2DE RSTx2DE 28 1 2 0x2 1-2 SET%sDE Output %s set DMA request enable 25 1 RST1DE RSTx1DE 26 1 2 0x1 1-2 CPT%sDE CPT%sDE 23 1 UPDDE UPDDE 22 1 REPDE REPDE 20 1 4 0x1 1-4 CMP%sIE CMP%sIE 0 1 DLYPRTIE DLYPRTIE 14 1 RSTIE RSTIE 13 1 RST2IE RSTx2IE 12 1 2 0x2 1-2 SET%sIE Output %s set interrupt enable 9 1 RST1IE RSTx1IE 10 1 2 0x1 1-2 CPT%sIE CPT%sIE 7 1 UPDIE UPDIE 6 1 REPIE REPIE 4 1 CNTR CNTAR Timerx Counter Register 0x10 PERR PERAR Timerx Period Register 0x14 REPR REPAR Timerx Repetition Register 0x18 CMP1R CMP1AR Timerx Compare 1 Register 0x1C CMP1CR CMP1CAR Timerx Compare 1 Compound Register 0x20 0x20 read-write 0x00000000 REP Timerx Repetition value (aliased from HRTIM_REPx register) 16 8 0 255 CMP1 Timerx Compare 1 value 0 16 0 65535 CMP2R CMP2AR Timerx Compare 2 Register 0x24 CMP3R CMP3AR Timerx Compare 3 Register 0x28 CMP4R CMP4AR Timerx Compare 4 Register 0x2C CPT1R CPT1AR Timerx Capture 1 Register 0x30 0x20 read-only 0x00000000 CPT Timerx Capture 1 value 0 16 0 65535 CPT2R CPT2AR Timerx Capture 2 Register 0x34 DTR DTAR Timerx Deadtime Register 0x38 0x20 read-write 0x00000000 DTFLK Deadtime Falling Lock 31 1 DTFLK Unlocked Deadtime falling value and sign is writable 0 Locked Deadtime falling value and sign is read-only 1 DTFSLK Deadtime Falling Sign Lock 30 1 DTFSLK Unlocked Deadtime falling sign is writable 0 Locked Deadtime falling sign is read-only 1 SDTF Sign Deadtime Falling value 25 1 SDTF Positive Positive deadtime on falling edge 0 Negative Negative deadtime on falling edge 1 DTF Deadtime Falling value 16 9 0 511 DTRLK Deadtime Rising Lock 15 1 DTRLK Unlocked Deadtime rising value and sign is writable 0 Locked Deadtime rising value and sign is read-only 1 DTRSLK Deadtime Rising Sign Lock 14 1 DTRSLK Unlocked Deadtime rising sign is writable 0 Locked Deadtime rising sign is read-only 1 DTPRSC Deadtime Prescaler 10 3 0 7 SDTR Sign Deadtime Rising value 9 1 SDTR Positive Positive deadtime on rising edge 0 Negative Negative deadtime on rising edge 1 DTR Deadtime Rising value 0 9 0 511 SET1R SETA1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 UPDATE NoEffect Register update event has no effect 0 SetActive Register update event forces the output to its active state 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 EXTEVNT1 NoEffect External event has no effect 0 SetActive External event forces the output to its active state 1 TIMBCMP1 Timer B Compare 1 12 1 TIMBCMP1 NoEffect Timer event has no effect 0 SetActive Timer event forces the output to its active state 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMDCMP2 Timer D Compare 2 18 1 TIMDCMP1 Timer D Compare 1 17 1 TIMCCMP3 Timer C Compare 3 16 1 TIMCCMP2 Timer C Compare 2 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP2 Timer B Compare 2 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTCMP1 NoEffect Master timer compare event has no effect 0 SetActive Master timer compare event forces the output to its active state 1 MSTPER Master Period 7 1 MSTPER NoEffect Master timer counter roll-over/reset has no effect 0 SetActive Master timer counter roll-over/reset forces the output to its active state 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 CMP1 NoEffect Timer compare event has no effect 0 SetActive Timer compare event forces the output to its active state 1 PER Timer A Period 2 1 PER NoEffect Timer period event has no effect 0 SetActive Timer period event forces the output to its active state 1 RESYNC Timer A resynchronizaton 1 1 RESYNC NoEffect Timer reset event coming solely from software or SYNC input event has no effect 0 SetActive Timer reset event coming solely from software or SYNC input event forces the output to its active state 1 SST Software Set trigger 0 1 SST NoEffect No effect 0 SetActive Force output to its active state 1 RST1R RSTA1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 UPDATE NoEffect Register update event has no effect 0 SetInactive Register update event forces the output to its inactive state 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 EXTEVNT1 NoEffect External event has no effect 0 SetInactive External event forces the output to its inactive state 1 TIMBCMP1 Timer B Compare 1 12 1 TIMBCMP1 NoEffect Timer event has no effect 0 SetInactive Timer event forces the output to its inactive state 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMDCMP2 Timer D Compare 2 18 1 TIMDCMP1 Timer D Compare 1 17 1 TIMCCMP3 Timer C Compare 3 16 1 TIMCCMP2 Timer C Compare 2 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP2 Timer B Compare 2 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTCMP1 NoEffect Master timer compare event has no effect 0 SetInactive Master timer compare event forces the output to its inactive state 1 MSTPER MSTPER 7 1 MSTPER NoEffect Master timer counter roll-over/reset has no effect 0 SetInactive Master timer counter roll-over/reset forces the output to its inactive state 1 4 0x1 1-4 CMP%s CMP%s 3 1 CMP1 NoEffect Timer compare event has no effect 0 SetInactive Timer compare event forces the output to its inactive state 1 PER PER 2 1 PER NoEffect Timer period event has no effect 0 SetInactive Timer period event forces the output to its inactive state 1 RESYNC RESYNC 1 1 RESYNC NoEffect Timer reset event coming solely from software or SYNC input event has no effect 0 SetInactive Timer reset event coming solely from software or SYNC input event forces the output to its inactive state 1 SRT SRT 0 1 SRT NoEffect No effect 0 SetInactive Force output to its inactive state 1 SET2R SETA2R Timerx Output2 Set Register 0x44 RST2R RSTA2R Timerx Output2 Reset Register 0x48 EEFR1 EEFAR1 Timerx External Event Filtering Register 1 0x4C 0x20 read-write 0x00000000 5 0x6 1-5 EE%sFLTR External Event %s filter 1 4 EE1FLTR Disabled No filtering 0 BlankResetToCompare1 Blanking from counter reset/roll-over to Compare 1 1 BlankResetToCompare2 Blanking from counter reset/roll-over to Compare 2 2 BlankResetToCompare3 Blanking from counter reset/roll-over to Compare 3 3 BlankResetToCompare4 Blanking from counter reset/roll-over to Compare 4 4 BlankTIMFLTR1 Blanking from another timing unit: TIMFLTR1 source 5 BlankTIMFLTR2 Blanking from another timing unit: TIMFLTR2 source 6 BlankTIMFLTR3 Blanking from another timing unit: TIMFLTR3 source 7 BlankTIMFLTR4 Blanking from another timing unit: TIMFLTR4 source 8 BlankTIMFLTR5 Blanking from another timing unit: TIMFLTR5 source 9 BlankTIMFLTR6 Blanking from another timing unit: TIMFLTR6 source 10 BlankTIMFLTR7 Blanking from another timing unit: TIMFLTR7 source 11 BlankTIMFLTR8 Blanking from another timing unit: TIMFLTR8 source 12 WindowResetToCompare2 Windowing from counter reset/roll-over to compare 2 13 WindowResetToCompare3 Windowing from counter reset/roll-over to compare 3 14 WindowTIMWIN Windowing from another timing unit: TIMWIN source 15 5 0x6 1-5 EE%sLTCH External Event %s latch 0 1 EE1LTCH Disabled Event is ignored if it happens during a blank, or passed through during a window 0 Enabled Event is latched and delayed till the end of the blanking or windowing period 1 EEFR2 EEFAR2 Timerx External Event Filtering Register 2 0x50 0x20 read-write 0x00000000 5 0x6 6-10 EE%sFLTR External Event %s filter 1 4 EE6FLTR Disabled No filtering 0 BlankResetToCompare1 Blanking from counter reset/roll-over to Compare 1 1 BlankResetToCompare2 Blanking from counter reset/roll-over to Compare 2 2 BlankResetToCompare3 Blanking from counter reset/roll-over to Compare 3 3 BlankResetToCompare4 Blanking from counter reset/roll-over to Compare 4 4 BlankTIMFLTR1 Blanking from another timing unit: TIMFLTR1 source 5 BlankTIMFLTR2 Blanking from another timing unit: TIMFLTR2 source 6 BlankTIMFLTR3 Blanking from another timing unit: TIMFLTR3 source 7 BlankTIMFLTR4 Blanking from another timing unit: TIMFLTR4 source 8 BlankTIMFLTR5 Blanking from another timing unit: TIMFLTR5 source 9 BlankTIMFLTR6 Blanking from another timing unit: TIMFLTR6 source 10 BlankTIMFLTR7 Blanking from another timing unit: TIMFLTR7 source 11 BlankTIMFLTR8 Blanking from another timing unit: TIMFLTR8 source 12 WindowResetToCompare2 Windowing from counter reset/roll-over to compare 2 13 WindowResetToCompare3 Windowing from counter reset/roll-over to compare 3 14 WindowTIMWIN Windowing from another timing unit: TIMWIN source 15 5 0x6 6-10 EE%sLTCH External Event %s latch 0 1 EE6LTCH Disabled Event is ignored if it happens during a blank, or passed through during a window 0 Enabled Event is latched and delayed till the end of the blanking or windowing period 1 RSTR RSTAR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMBCMP1 Timer B Compare 1 19 1 TIMBCMP1 NoEffect Timer Y compare Z event has no effect 0 ResetCounter Timer X counter is reset upon timer Y compare Z event 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMCCMP4 Timer C Compare 4 24 1 TIMCCMP2 Timer C Compare 2 23 1 TIMCCMP1 Timer C Compare 1 22 1 TIMBCMP4 Timer B Compare 4 21 1 TIMBCMP2 Timer B Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 EXTEVNT1 NoEffect External event Z has no effect 0 ResetCounter Timer X counter is reset upon external event Z 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTCMP1 NoEffect Master timer compare Z event has no effect 0 ResetCounter Timer X counter is reset upon master timer compare Z event 1 MSTPER Master timer Period 4 1 MSTPER NoEffect Master timer period event has no effect 0 ResetCounter Timer X counter is reset upon master timer period event 1 CMP2 Timer A compare 2 reset 2 1 CMP2 NoEffect Timer X compare Z event has no effect 0 ResetCounter Timer X counter is reset upon timer X compare Z event 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 UPDT NoEffect Update event has no effect 0 ResetCounter Timer X counter is reset upon update event 1 CHPR CHPAR Timerx Chopper Register 0x58 0x20 read-write 0x00000000 STRTPW STRTPW 7 4 0 15 CARDTY Timerx chopper duty cycle value 4 3 0 7 CARFRQ Timerx carrier frequency value 0 4 0 15 CPT1CR CPT1ACR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TBCMP1 Timer B Compare 1 18 1 TBCMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TB1RST Timer B output 1 Reset 17 1 TB1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TB1SET Timer B output 1 Set 16 1 TB1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2ACR CPT2xCR 0x60 OUTR OUTAR Timerx Output Register 0x64 0x20 read-write 0x00000000 DIDL1 Output 1 Deadtime upon burst mode Idle entry 7 1 DIDL1 Disabled The programmed idle state is applied immediately to the output 0 Enabled Deadtime (inactive level) is inserted on output before entering the idle mode 1 DIDL2 Output 2 Deadtime upon burst mode Idle entry 23 1 CHP1 Output 1 Chopper enable 6 1 CHP1 Disabled Output signal not altered 0 Enabled Output signal is chopped by a carrier signal 1 CHP2 Output 2 Chopper enable 22 1 FAULT1 Output 1 Fault state 4 2 FAULT1 Disabled No action: the output is not affected by the fault input and stays in run mode 0 SetActive Output goes to active state after a fault event 1 SetInactive Output goes to inactive state after a fault event 2 SetHighZ Output goes to high-z state after a fault event 3 FAULT2 Output 2 Fault state 20 2 IDLES1 Output 1 Idle State 3 1 IDLES1 Inactive Output idle state is inactive 0 Active Output idle state is active 1 IDLES2 Output 2 Idle State 19 1 IDLEM1 Output 1 Idle mode 2 1 IDLEM1 NoEffect No action: the output is not affected by the burst mode operation 0 SetIdle The output is in idle state when requested by the burst mode controller 1 IDLEM2 Output 2 Idle mode 18 1 POL1 Output 1 polarity 1 1 POL1 ActiveHigh Positive polarity (output active high) 0 ActiveLow Negative polarity (output active low) 1 POL2 Output 2 polarity 17 1 DLYPRT Delayed Protection 10 3 DLYPRT Output1_EE6 Output 1 delayed idle on external event 6 0 Output2_EE6 Output 2 delayed idle on external event 6 1 Output1_2_EE6 Output 1 and 2 delayed idle on external event 6 2 Balanced_EE6 Balanced idle on external event 6 3 Output1_EE7 Output 1 delayed idle on external event 7 4 Output2_EE7 Output 2 delayed idle on external event 7 5 Output1_2_EE7 Output 1 and 2 delayed idle on external event 7 6 Balanced_EE7 Balanced idle on external event 7 7 DLYPRTEN Delayed Protection Enable 9 1 DLYPRTEN Disabled No action 0 Enabled Delayed protection is enabled, as per DLYPRT bits 1 DTEN Deadtime enable 8 1 DTEN Disabled Output 1 and 2 signals are independent 0 Enabled Deadtime is inserted between output 1 and output 2 1 FLTR FLTAR Timerx Fault Register 0x68 0x20 read-write 0x00000000 FLTLCK Fault sources Lock 31 1 FLTLCK Unlocked FLT1EN..FLT5EN bits are read/write 0 Locked FLT1EN..FLT5EN bits are read only 1 5 0x1 1-5 FLT%sEN Fault %s enable 0 1 FLT1EN Ignored Fault input ignored 0 Active Fault input is active and can disable HRTIM outputs 1 HRTIM_TIMB High Resolution Timer: TIMB HRTIM 0x40017500 0x0 0x80 registers HRTIM_TIMB HRTIM1 timer B interrupt 69 CR BCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR BISR Timerx Interrupt Status Register 0x4 ICR BICR Timerx Interrupt Clear Register 0x8 DIER BDIER5 TIMxDIER5 0xC CNTR CNTR Timerx Counter Register 0x10 PERR PERBR Timerx Period Register 0x14 REPR REPBR Timerx Repetition Register 0x18 CMP1R CMP1BR Timerx Compare 1 Register 0x1C CMP1CR CMP1CBR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2BR Timerx Compare 2 Register 0x24 CMP3R CMP3BR Timerx Compare 3 Register 0x28 CMP4R CMP4BR Timerx Compare 4 Register 0x2C CPT1R CPT1BR Timerx Capture 1 Register 0x30 CPT2R CPT2BR Timerx Capture 2 Register 0x34 DTR DTBR Timerx Deadtime Register 0x38 SET1R SETB1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMDCMP4 Timer D Compare 4 18 1 TIMDCMP3 Timer D Compare 3 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMCCMP3 Timer C Compare 3 15 1 TIMACMP4 Timer A Compare 4 14 1 TIMACMP2 Timer A Compare 2 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTB1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMDCMP4 Timer D Compare 4 18 1 TIMDCMP3 Timer D Compare 3 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMCCMP3 Timer C Compare 3 15 1 TIMACMP4 Timer A Compare 4 14 1 TIMACMP2 Timer A Compare 2 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETB2R Timerx Output2 Set Register 0x44 RST2R RSTB2R Timerx Output2 Reset Register 0x48 EEFR1 EEFBR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFBR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTBR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMCCMP4 Timer C Compare 4 24 1 TIMCCMP2 Timer C Compare 2 23 1 TIMCCMP1 Timer C Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPBR Timerx Chopper Register 0x58 CPT1CR CPT1BCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2BCR CPT2xCR 0x60 OUTR OUTBR Timerx Output Register 0x64 FLTR FLTBR Timerx Fault Register 0x68 HRTIM_TIMC High Resolution Timer: TIMC HRTIM 0x40017580 0x0 0x80 registers HRTIM_TIMC HRTIM1 timer C interrupt 70 CR CCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR CISR Timerx Interrupt Status Register 0x4 ICR CICR Timerx Interrupt Clear Register 0x8 DIER CDIER5 TIMxDIER5 0xC CNTR CNTCR Timerx Counter Register 0x10 PERR PERCR Timerx Period Register 0x14 REPR REPCR Timerx Repetition Register 0x18 CMP1R CMP1CR Timerx Compare 1 Register 0x1C CMP1CR CMP1CCR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2CR Timerx Compare 2 Register 0x24 CMP3R CMP3CR Timerx Compare 3 Register 0x28 CMP4R CMP4CR Timerx Compare 4 Register 0x2C CPT1R CPT1CR Timerx Capture 1 Register 0x30 CPT2R CPT2CR Timerx Capture 2 Register 0x34 DTR DTCR Timerx Deadtime Register 0x38 SET1R SETC1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP2 Timer A Compare 2 12 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMECMP2 Timer E Compare 2 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP2 Timer D Compare 2 16 1 TIMBCMP3 Timer B Compare 3 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP3 Timer A Compare 3 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTC1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP2 Timer A Compare 2 12 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMECMP2 Timer E Compare 2 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP2 Timer D Compare 2 16 1 TIMBCMP3 Timer B Compare 3 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP3 Timer A Compare 3 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETC2R Timerx Output2 Set Register 0x44 RST2R RSTC2R Timerx Output2 Reset Register 0x48 EEFR1 EEFCR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFCR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTCR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPCR Timerx Chopper Register 0x58 CPT1CR CPT1CCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2CCR CPT2xCR 0x60 OUTR OUTCR Timerx Output Register 0x64 FLTR FLTCR Timerx Fault Register 0x68 HRTIM_TIMD High Resolution Timer: TIMD HRTIM 0x40017600 0x0 0x80 registers HRTIM_TIMD HRTIM1 timer D interrupt 71 CR DCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR DISR Timerx Interrupt Status Register 0x4 ICR DICR Timerx Interrupt Clear Register 0x8 DIER DDIER5 TIMxDIER5 0xC CNTR CNTDR Timerx Counter Register 0x10 PERR PERDR Timerx Period Register 0x14 REPR REPDR Timerx Repetition Register 0x18 CMP1R CMP1DR Timerx Compare 1 Register 0x1C CMP1CR CMP1CDR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2DR Timerx Compare 2 Register 0x24 CMP3R CMP3DR Timerx Compare 3 Register 0x28 CMP4R CMP4DR Timerx Compare 4 Register 0x2C CPT1R CPT1DR Timerx Capture 1 Register 0x30 CPT2R CPT2DR Timerx Capture 2 Register 0x34 DTR DTDR Timerx Deadtime Register 0x38 SET1R SETD1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMCCMP4 Timer C Compare 4 18 1 TIMCCMP3 Timer C Compare 3 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTD1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMCCMP4 Timer C Compare 4 18 1 TIMCCMP3 Timer C Compare 3 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETD2R Timerx Output2 Set Register 0x44 RST2R RSTD2R Timerx Output2 Reset Register 0x48 EEFR1 EEFDR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFDR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTDR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPDR Timerx Chopper Register 0x58 CPT1CR CPT1DCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2DCR CPT2xCR 0x60 OUTR OUTDR Timerx Output Register 0x64 FLTR FLTDR Timerx Fault Register 0x68 HRTIM_TIME High Resolution Timer: TIME HRTIM 0x40017680 0x0 0x80 registers HRTIM_TIME HRTIM1 timer E interrupt 72 CR ECR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR EISR Timerx Interrupt Status Register 0x4 ICR EICR Timerx Interrupt Clear Register 0x8 DIER EDIER5 TIMxDIER5 0xC CNTR CNTER Timerx Counter Register 0x10 PERR PERER Timerx Period Register 0x14 REPR REPER Timerx Repetition Register 0x18 CMP1R CMP1ER Timerx Compare 1 Register 0x1C CMP1CR CMP1CER Timerx Compare 1 Compound Register 0x20 CMP2R CMP2ER Timerx Compare 2 Register 0x24 CMP3R CMP3ER Timerx Compare 3 Register 0x28 CMP4R CMP4ER Timerx Compare 4 Register 0x2C CPT1R CPT1ER Timerx Capture 1 Register 0x30 CPT2R CPT2ER Timerx Capture 2 Register 0x34 DTR DTER Timerx Deadtime Register 0x38 SET1R SETE1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP3 Timer A Compare 3 12 1 TIMDCMP4 Timer D Compare 4 20 1 TIMDCMP2 Timer D Compare 2 19 1 TIMDCMP1 Timer D Compare 1 18 1 TIMCCMP2 Timer C Compare 2 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP3 Timer B Compare 3 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTE1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP3 Timer A Compare 3 12 1 TIMDCMP4 Timer D Compare 4 20 1 TIMDCMP2 Timer D Compare 2 19 1 TIMDCMP1 Timer D Compare 1 18 1 TIMCCMP2 Timer C Compare 2 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP3 Timer B Compare 3 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETE2R Timerx Output2 Set Register 0x44 RST2R RSTE2R Timerx Output2 Reset Register 0x48 EEFR1 EEFER1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFER2 Timerx External Event Filtering Register 2 0x50 RSTR RSTER TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMDCMP4 Timer D Compare 4 30 1 TIMDCMP2 Timer D Compare 2 29 1 TIMDCMP1 Timer D Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPER Timerx Chopper Register 0x58 CPT1CR CPT1ECR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TD1RST Timer D output 1 Reset 25 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2ECR CPT2xCR 0x60 OUTR OUTER Timerx Output Register 0x64 FLTR FLTER Timerx Fault Register 0x68 HRTIM_Common High Resolution Timer: Common functions HRTIM 0x40017780 0x0 0x80 registers HRTIM_FLT HRTIM1 fault interrupt 73 CR1 CR1 Control Register 1 0x0 0x20 read-write 0x00000000 4 0x3 1-4 AD%sUSRC ADC Trigger %s Update Source 16 3 AD1USRC Master ADC trigger update from master timer 0 TimerA ADC trigger update from timer A 1 TimerB ADC trigger update from timer B 2 TimerC ADC trigger update from timer C 3 TimerD ADC trigger update from timer D 4 TimerE ADC trigger update from timer E 5 MUDIS Master Update Disable 0 1 MUDIS Enabled Timer update enabled 0 Disabled Timer update disabled 1 5 0x1 A,B,C,D,E T%sUDIS Timer %s Update Disable 1 1 CR2 CR2 Control Register 2 0x4 0x20 read-write 0x00000000 MRST Master Counter software reset 8 1 MRST Reset Reset timer 1 5 0x1 A,B,C,D,E T%sRST Timer %s counter software reset 9 1 MSWU Master Timer Software update 0 1 MSWU Update Force immediate update 1 5 0x1 A,B,C,D,E T%sSWU Timer %s Software Update 1 1 ISR ISR Interrupt Status Register 0x8 0x20 0x00000000 BMPER Burst mode Period Interrupt Flag 17 1 read-only BMPERR NoEvent No burst mode period interrupt occurred 0 Event Burst mode period interrupt occured 1 DLLRDY DLL Ready Interrupt Flag 16 1 read-only DLLRDYR NoEvent No DLL calibration ready interrupt occurred 0 Event DLL calibration ready interrupt occurred 1 SYSFLT System Fault Interrupt Flag 5 1 read-write SYSFLTR read NoEvent No fault interrupt occurred 0 Event Fault interrupt occurred 1 FLT1 Fault 1 Interrupt Flag 0 1 read-only FLT1R NoEvent No fault interrupt occurred 0 Event Fault interrupt occurred 1 FLT5 Fault 5 Interrupt Flag 4 1 read-only FLT4 Fault 4 Interrupt Flag 3 1 read-only FLT3 Fault 3 Interrupt Flag 2 1 read-only FLT2 Fault 2 Interrupt Flag 1 1 read-only ICR ICR Interrupt Clear Register 0xC 0x20 0x00000000 FLT1C Fault 1 Interrupt Flag Clear 0 1 write-only oneToClear FLT1CW Clear Clears associated flag in ISR register 1 BMPERC Burst mode period flag Clear 17 1 write-only oneToClear DLLRDYC DLL Ready Interrupt flag Clear 16 1 write-only oneToClear SYSFLTC System Fault Interrupt Flag Clear 5 1 write-only oneToClear FLT5C Fault 5 Interrupt Flag Clear 4 1 write-only oneToClear FLT4C Fault 4 Interrupt Flag Clear 3 1 write-only oneToClear FLT3C Fault 3 Interrupt Flag Clear 2 1 write-only oneToClear FLT2C Fault 2 Interrupt Flag Clear 1 1 write-only oneToClear IER IER Interrupt Enable Register 0x10 0x20 read-write 0x00000000 BMPERIE Burst mode period Interrupt Enable 17 1 BMPERIE Disabled Burst mode period interrupt disabled 0 Enabled Burst mode period interrupt enabled 1 DLLRDYIE DLL Ready Interrupt Enable 16 1 DLLRDYIE Disabled DLL ready interrupt disabled 0 Enabled DLL Ready interrupt enabled 1 FLT1IE Fault 1 Interrupt Enable 0 1 FLT1IE Disabled Fault interrupt disabled 0 Enabled Fault interrupt enabled 1 SYSFLTIE System Fault Interrupt Enable 5 1 FLT5IE Fault 5 Interrupt Enable 4 1 FLT4IE Fault 4 Interrupt Enable 3 1 FLT3IE Fault 3 Interrupt Enable 2 1 FLT2IE Fault 2 Interrupt Enable 1 1 OENR OENR Output Enable Register 0x14 0x20 read-write 0x00000000 5 0x2 A,B,C,D,E T%s1OEN Timer %s Output 1 Enable 0 1 oneToSet TOENR read Disabled Output disabled 0 Enabled Output enabled 1 TORNW write Enable Enable output 1 5 0x2 A,B,C,D,E T%s2OEN Timer %s Output 2 Enable 1 1 oneToSet read write ODISR ODISR DISR 0x18 0x20 write-only 0x00000000 5 0x2 A,B,C,D,E T%s1ODIS T%s1ODIS 0 1 oneToSet TODIS Disable Disable output 1 5 0x2 A,B,C,D,E T%s2ODIS T%s2ODIS 1 1 oneToSet ODSR ODSR Output Disable Status Register 0x1C 0x20 read-only 0x00000000 5 0x2 A,B,C,D,E T%s1ODS Timer %s Output 1 disable status 0 1 TODS Idle Output disabled in idle state 0 Fault Output disabled in fault state 1 5 0x2 A,B,C,D,E T%s2ODS Timer %s Output 2 disable status 1 1 BMCR BMCR Burst Mode Control Register 0x20 0x20 read-write 0x00000000 BMSTAT Burst Mode Status 31 1 zeroToClear BMSTATR read Normal Normal operation 0 Burst Burst operation ongoing 1 BMSTATW write Cancel Terminate burst mode 0 MTBM Master Timer Burst Mode 16 1 MTBM Normal Counter clock is maintained and timer operates normally 0 Stopped Counter clock is stopped and counter is reset 1 5 0x1 A,B,C,D,E T%sBM Timer %s Burst Mode 17 1 BMPREN Burst Mode Preload Enable 10 1 BMPREN Disabled Preload disabled: the write access is directly done into active registers 0 Enabled Preload enabled: the write access is done into preload registers 1 BMPRSC Burst Mode Prescaler 6 4 BMPRSC Div1 Clock not divided 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 Div16 Division by 16 4 Div32 Division by 32 5 Div64 Division by 64 6 Div128 Division by 128 7 Div256 Division by 256 8 Div512 Division by 512 9 Div1024 Division by 1024 10 Div2048 Division by 2048 11 Div4096 Division by 4096 12 Div8192 Division by 8192 13 Div16384 Division by 16384 14 Div32768 Division by 32768 15 BMCLK Burst Mode Clock source 2 4 BMCLK Master Master timer reset/roll-over 0 TimerA Timer A counter reset/roll-over 1 TimerB Timer B counter reset/roll-over 2 TimerC Timer C counter reset/roll-over 3 TimerD Timer D counter reset/roll-over 4 TimerE Timer E counter reset/roll-over 5 Event1 On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock 6 Event2 On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock 7 Event3 On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock 8 Event4 On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock 9 Clock Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting 10 BMOM Burst Mode operating mode 1 1 BMOM SingleShot Single-shot mode 0 Continuous Continuous operation 1 BME Burst Mode enable 0 1 BME Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 BMTRGR BMTRGR BMTRGR 0x24 0x20 read-write 0x00000000 OCHPEV OCHPEV 31 1 OCHPEV NoEffect Rising edge on an on-chip event has no effect 0 Trigger Rising edge on an on-chip event triggers a burst mode entry 1 EEV7 EEV7 29 1 EEV7 NoEffect External event X has no effect 0 Trigger External event X triggers a burst mode entry 1 EEV8 EEV8 30 1 TAEEV7 TAEEV7 27 1 TAEEV7 NoEffect Timer X period following external event Y has no effect 0 Trigger Timer X period following external event Y triggers a burst mode entry 1 TDEEV8 TDEEV8 28 1 TACMP1 TACMP1 9 1 TACMP1 NoEffect Timer X compare Y event has no effect 0 Trigger Timer X compare Y event triggers a burst mode entry 1 TECMP2 TECMP2 26 1 TECMP1 TECMP1 25 1 TAREP TAREP 8 1 TAREP NoEffect Timer X repetition event has no effect 0 Trigger Timer X repetition event triggers a burst mode entry 1 TEREP TEREP 24 1 TARST TARST 7 1 TARST NoEffect Timer X reset/roll-over event has no effect 0 Trigger Timer X reset/roll-over event triggers a burst mode entry 1 TERST TERST 23 1 TDCMP2 TDCMP2 22 1 TDCMP1 TDCMP1 21 1 TDREP TDREP 20 1 TDRST TDRST 19 1 TCCMP2 TCCMP2 18 1 TCCMP1 TCCMP1 17 1 TCREP TCREP 16 1 TCRST TCRST 15 1 TBCMP2 TBCMP2 14 1 TBCMP1 TBCMP1 13 1 TBREP TBREP 12 1 TBRST TBRST 11 1 TACMP2 TACMP2 10 1 MSTCMP1 MSTCMP1 3 1 MSTCMP1 NoEffect Master timer compare X event has no effect 0 Trigger Master timer compare X event triggers a burst mode entry 1 MSTCMP4 MSTCMP4 6 1 MSTCMP3 MSTCMP3 5 1 MSTCMP2 MSTCMP2 4 1 MSTREP MSTREP 2 1 MSTREP NoEffect Master timer repetition event has no effect 0 Trigger Master timer repetition event triggers a burst mode entry 1 MSTRST MSTRST 1 1 MSTRST NoEffect Master timer reset/roll-over event has no effect 0 Trigger Master timer reset/roll-over event triggers a burst mode entry 1 SW SW 0 1 SW NoEffect No effect 0 Trigger Trigger immediate burst mode operation 1 BMCMPR BMCMPR BMCMPR 0x28 0x20 read-write 0x00000000 BMCMP BMCMP 0 16 0 65535 BMPER BMPER Burst Mode Period Register 0x2C 0x20 read-write 0x00000000 BMPER Burst mode Period 0 16 0 65535 EECR1 EECR1 Timer External Event Control Register 1 0x30 0x20 read-write 0x00000000 5 0x6 1-5 EE%sFAST External Event %s Fast mode 5 1 EE1FAST Resynchronized External event is re-synchronised by the HRTIM logic before acting on outputs 0 Asynchronous External event is acting asynchronously on outputs (low-latency mode) 1 5 0x6 1-5 EE%sSNS External Event %s Sensitivity 3 2 EE1SNS Active On active level defined by EExPOL bit 0 Rising Rising edge 1 Falling Falling edge 2 Both Both edges 3 5 0x6 1-5 EE%sPOL External Event %s Polarity 2 1 EE1POL ActiveHigh External event is active high 0 ActiveLow External event is active low 1 5 0x6 1-5 EE%sSRC External Event %s Source 0 2 EE1SRC Src1 Source 1 0 Src2 Source 2 1 Src3 Source 3 2 Src4 Source 4 3 EECR2 EECR2 Timer External Event Control Register 2 0x34 0x20 read-write 0x00000000 5 0x6 6-10 EE%sSNS External Event %s Sensitivity 3 2 EE6SNS Active On active level defined by EExPOL bit 0 Rising Rising edge 1 Falling Falling edge 2 Both Both edges 3 5 0x6 6-10 EE%sPOL External Event %s Polarity 2 1 EE6POL ActiveHigh External event is active high 0 ActiveLow External event is active low 1 5 0x6 6-10 EE%sSRC External Event %s Source 0 2 EE6SRC Src1 Source 1 0 Src2 Source 2 1 Src3 Source 3 2 Src4 Source 4 3 EECR3 EECR3 Timer External Event Control Register 3 0x38 0x20 read-write 0x00000000 EEVSD EEVSD 30 2 EEVSD Div1 f_EEVS=f_HRTIM 0 Div2 f_EEVS=f_HRTIM/2 1 Div4 f_EEVS=f_HRTIM/4 2 Div8 f_EEVS=f_HRTIM/8 3 5 0x6 6-10 EE%sF EE%sF 0 4 EE6F Disabled Filter disabled 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_EEVS/2, N=6 4 Div2_N8 f_SAMPLING=f_EEVS/2, N=8 5 Div4_N6 f_SAMPLING=f_EEVS/4, N=6 6 Div4_N8 f_SAMPLING=f_EEVS/4, N=8 7 Div8_N6 f_SAMPLING=f_EEVS/8, N=6 8 Div8_N8 f_SAMPLING=f_EEVS/8, N=8 9 Div16_N5 f_SAMPLING=f_EEVS/16, N=5 10 Div16_N6 f_SAMPLING=f_EEVS/16, N=6 11 Div16_N8 f_SAMPLING=f_EEVS/16, N=8 12 Div32_N5 f_SAMPLING=f_EEVS/32, N=5 13 Div32_N6 f_SAMPLING=f_EEVS/32, N=6 14 Div32_N8 f_SAMPLING=f_EEVS/32, N=8 15 ADC1R ADC1R ADC Trigger 1 Register 0x3C 0x20 read-write 0x00000000 MPER ADC trigger 1 on Master Period 4 1 MPER Disabled No generation of ADC trigger on timer period event 0 Enabled Generation of ADC trigger on timer period event 1 EPER ADC trigger 1 on Timer E Period 31 1 AC2 ADC trigger 1 on Timer A compare 2 10 1 AC2 Disabled No generation of ADC trigger on timer compare event 0 Enabled Generation of ADC trigger on timer compare event 1 EC4 ADC trigger 1 on Timer E compare 4 30 1 EC3 ADC trigger 1 on Timer E compare 3 29 1 EC2 ADC trigger 1 on Timer E compare 2 28 1 DPER ADC trigger 1 on Timer D Period 27 1 DC4 ADC trigger 1 on Timer D compare 4 26 1 DC3 ADC trigger 1 on Timer D compare 3 25 1 DC2 ADC trigger 1 on Timer D compare 2 24 1 CPER ADC trigger 1 on Timer C Period 23 1 CC4 ADC trigger 1 on Timer C compare 4 22 1 CC3 ADC trigger 1 on Timer C compare 3 21 1 CC2 ADC trigger 1 on Timer C compare 2 20 1 ARST ADC trigger 1 on Timer A Reset 14 1 ARST Disabled No generation of ADC trigger on timer reset and roll-over 0 Enabled Generation of ADC trigger on timer reset and roll-over 1 BRST ADC trigger 1 on Timer B Reset 19 1 BPER ADC trigger 1 on Timer B Period 18 1 BC4 ADC trigger 1 on Timer B compare 4 17 1 BC3 ADC trigger 1 on Timer B compare 3 16 1 BC2 ADC trigger 1 on Timer B compare 2 15 1 APER ADC trigger 1 on Timer A Period 13 1 AC4 ADC trigger 1 on Timer A compare 4 12 1 AC3 ADC trigger 1 on Timer A compare 3 11 1 5 0x1 1-5 EEV%s ADC trigger 1 on External Event %s 5 1 EEV1 Disabled No generation of ADC trigger on external event 0 Enabled Generation of ADC trigger on external event 1 4 0x1 1-4 MC%s ADC trigger 1 on Master Compare %s 0 1 MC1 Disabled No generation of ADC trigger on master compare event 0 Enabled Generation of ADC trigger on master compare event 1 ADC2R ADC2R ADC Trigger 2 Register 0x40 0x20 read-write 0x00000000 CRST ADC trigger 2 on Timer C Reset 22 1 CRST Disabled No generation of ADC trigger on timer reset and roll-over 0 Enabled Generation of ADC trigger on timer reset and roll-over 1 ERST ADC trigger 2 on Timer E Reset 31 1 AC2 ADC trigger 2 on Timer A compare 2 10 1 AC2 Disabled No generation of ADC trigger on timer compare event 0 Enabled Generation of ADC trigger on timer compare event 1 EC4 ADC trigger 2 on Timer E compare 4 30 1 EC3 ADC trigger 2 on Timer E compare 3 29 1 EC2 ADC trigger 2 on Timer E compare 2 28 1 DRST ADC trigger 2 on Timer D Reset 27 1 MPER ADC trigger 2 on Master Period 4 1 MPER Disabled No generation of ADC trigger on timer period event 0 Enabled Generation of ADC trigger on timer period event 1 DPER ADC trigger 2 on Timer D Period 26 1 DC4 ADC trigger 2 on Timer D compare 4 25 1 DC3 ADC trigger 2 on Timer D compare 3 24 1 DC2 ADC trigger 2 on Timer D compare 2 23 1 CPER ADC trigger 2 on Timer C Period 21 1 CC4 ADC trigger 2 on Timer C compare 4 20 1 CC3 ADC trigger 2 on Timer C compare 3 19 1 CC2 ADC trigger 2 on Timer C compare 2 18 1 BPER ADC trigger 2 on Timer B Period 17 1 BC4 ADC trigger 2 on Timer B compare 4 16 1 BC3 ADC trigger 2 on Timer B compare 3 15 1 BC2 ADC trigger 2 on Timer B compare 2 14 1 APER ADC trigger 2 on Timer A Period 13 1 AC4 ADC trigger 2 on Timer A compare 4 12 1 AC3 ADC trigger 2 on Timer A compare 3 11 1 5 0x1 6-10 EEV%s ADC trigger 2 on External Event %s 5 1 EEV6 Disabled No generation of ADC trigger on external event 0 Enabled Generation of ADC trigger on external event 1 4 0x1 1-4 MC%s ADC trigger 2 on Master Compare %s 0 1 MC1 Disabled No generation of ADC trigger on master compare event 0 Enabled Generation of ADC trigger on master compare event 1 ADC3R ADC3R ADC Trigger 3 Register 0x44 ADC4R ADC4R ADC Trigger 4 Register 0x48 DLLCR DLLCR DLL Control Register 0x4C 0x20 read-write 0x00000000 CALRTE DLL Calibration rate 2 2 CALRTE Clk1048576 1048576*t_HRTIM (6.168 ms for fHRTIM = 170 MHz) 0 Clk131072 131072*t_HRTIM (771 µs for f_HRTIM = 170 MHz) 1 Clk16384 16384*t_HRTIM (96 µs for f_HRTIM = 170 MHz) 2 Clk2048 2048*t_HRTIM (12 µs for f_HRTIM = 170 MHz) 3 CALEN DLL Calibration Enable 1 1 CALEN Disabled Periodic calibration disabled 0 Enabled Calibration is performed periodically, as per CALRTE setting 1 CAL DLL Calibration Start 0 1 CAL Start Calibration start 1 FLTINR1 FLTINR1 HRTIM Fault Input Register 1 0x50 0x20 read-write 0x00000000 FLT1LCK FLT1LCK 7 1 FLT1LCKR read Unlocked Fault bits are read/write 0 Locked Fault bits are read-only 1 FLT1LCKW write Lock Lock corresponding fault bits 1 FLT4LCK FLT4LCK 31 1 read write 4 0x8 1-4 FLT%sF FLT%sF 3 4 FLT1F Disabled No filter, FLTx acts asynchronously 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_HRTIM/2, N=6 4 Div2_N8 f_SAMPLING=f_HRTIM/2, N=8 5 Div4_N6 f_SAMPLING=f_HRTIM/4, N=6 6 Div4_N8 f_SAMPLING=f_HRTIM/4, N=8 7 Div8_N6 f_SAMPLING=f_HRTIM/8, N=6 8 Div8_N8 f_SAMPLING=f_HRTIM/8, N=8 9 Div16_N5 f_SAMPLING=f_HRTIM/16, N=5 10 Div16_N6 f_SAMPLING=f_HRTIM/16, N=6 11 Div16_N8 f_SAMPLING=f_HRTIM/16, N=8 12 Div32_N5 f_SAMPLING=f_HRTIM/32, N=5 13 Div32_N6 f_SAMPLING=f_HRTIM/32, N=6 14 Div32_N8 f_SAMPLING=f_HRTIM/32, N=8 15 4 0x8 1-4 FLT%sSRC Fault %s source 2 1 FLT1SRC Input Fault input is FLTx input pin 0 Internal Fault input is FLTn_Int signal 1 4 0x8 1-4 FLT%sP FLT%sP 1 1 FLT1P ActiveLow Fault input is active low 0 ActiveHigh Fault input is active high 1 4 0x8 1-4 FLT%sE FLT%sE 0 1 FLT1E Disabled Fault input disabled 0 Enabled Fault input enabled 1 FLT3LCK FLT3LCK 23 1 read write FLT2LCK FLT2LCK 15 1 read write FLTINR2 FLTINR2 HRTIM Fault Input Register 2 0x54 0x20 read-write 0x00000000 FLTSD FLTSD 24 2 FLTSD Div1 f_FLTS=f_HRTIM 0 Div2 f_FLTS=f_HRTIM/2 1 Div4 f_FLTS=f_HRTIM/4 2 Div8 f_FLTS=f_HRTIM/8 3 FLT5LCK FLT5LCK 7 1 FLT5LCKR read Unlocked Fault bits are read/write 0 Locked Fault bits are read-only 1 FLT5LCKW write Lock Lock corresponding fault bits 1 1 0x0 5-5 FLT%sF FLT%sF 3 4 FLT5F Disabled No filter, FLTx acts asynchronously 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_HRTIM/2, N=6 4 Div2_N8 f_SAMPLING=f_HRTIM/2, N=8 5 Div4_N6 f_SAMPLING=f_HRTIM/4, N=6 6 Div4_N8 f_SAMPLING=f_HRTIM/4, N=8 7 Div8_N6 f_SAMPLING=f_HRTIM/8, N=6 8 Div8_N8 f_SAMPLING=f_HRTIM/8, N=8 9 Div16_N5 f_SAMPLING=f_HRTIM/16, N=5 10 Div16_N6 f_SAMPLING=f_HRTIM/16, N=6 11 Div16_N8 f_SAMPLING=f_HRTIM/16, N=8 12 Div32_N5 f_SAMPLING=f_HRTIM/32, N=5 13 Div32_N6 f_SAMPLING=f_HRTIM/32, N=6 14 Div32_N8 f_SAMPLING=f_HRTIM/32, N=8 15 1 0x0 5-5 FLT%sSRC Fault %s source 2 1 FLT5SRC Input Fault input is FLTx input pin 0 Internal Fault input is FLTn_Int signal 1 1 0x0 5-5 FLT%sP FLT%sP 1 1 FLT5P ActiveLow Fault input is active low 0 ActiveHigh Fault input is active high 1 1 0x0 5-5 FLT%sE FLT%sE 0 1 FLT5E Disabled Fault input disabled 0 Enabled Fault input enabled 1 BDMUPR BDMUPDR BDMUPDR 0x58 0x20 read-write 0x00000000 MCR MCR 0 1 MCR NotUpdated Register not updated by burst DMA access 0 Updated Register updated by burst DMA access 1 MCMP4 MCMP4 9 1 MCMP3 MCMP3 8 1 MCMP2 MCMP2 7 1 MCMP1 MCMP1 6 1 MREP MREP 5 1 MPER MPER 4 1 MCNT MCNT 3 1 MDIER MDIER 2 1 MICR MICR 1 1 BDTAUPR BDTAUPR Burst DMA Timerx update Register 0x5C 0x20 read-write 0x00000000 CR HRTIM_TIMxCR register update enable 0 1 CR NotUpdated Register not updated by burst DMA access 0 Updated Register updated by burst DMA access 1 FLTR HRTIM_FLTxR register update enable 20 1 OUTR HRTIM_OUTxR register update enable 19 1 CHPR HRTIM_CHPxR register update enable 18 1 RSTR HRTIM_RSTxR register update enable 17 1 EEFR2 HRTIM_EEFxR2 register update enable 16 1 EEFR1 HRTIM_EEFxR1 register update enable 15 1 RST2R HRTIM_RST2xR register update enable 14 1 SET2R HRTIM_SET2xR register update enable 13 1 RST1R HRTIM_RST1xR register update enable 12 1 SET1R HRTIM_SET1xR register update enable 11 1 DTR HRTIM_DTxR register update enable 10 1 CMP4 HRTIM_CMP4xR register update enable 9 1 CMP3 HRTIM_CMP3xR register update enable 8 1 CMP2 HRTIM_CMP2xR register update enable 7 1 CMP1 HRTIM_CMP1xR register update enable 6 1 REP HRTIM_REPxR register update enable 5 1 PER HRTIM_PERxR register update enable 4 1 CNT HRTIM_CNTxR register update enable 3 1 DIER HRTIM_TIMxDIER register update enable 2 1 ICR HRTIM_TIMxICR register update enable 1 1 BDTBUPR BDTBUPR Burst DMA Timerx update Register 0x60 BDTCUPR BDTCUPR Burst DMA Timerx update Register 0x64 BDTDUPR BDTDUPR Burst DMA Timerx update Register 0x68 BDTEUPR BDTEUPR Burst DMA Timerx update Register 0x6C BDMADR BDMADR Burst DMA Data Register 0x70 0x20 read-write 0x00000000 BDMADR Burst DMA Data register 0 32 0 4294967295