STM32F429
1.2
STM32F429
CM4
r1p0
little
false
false
4
false
8
32
0x20
0x00000000
0xFFFFFFFF
RNG
Random number generator
RNG
0x50060800
0x0
0x400
registers
FPU
FPU interrupt
81
FPU
FPU interrupt
81
CR
CR
control register
0x0
0x20
read-write
0x00000000
IE
Interrupt enable
3
1
IE
Disabled
RNG interrupt is disabled
0
Enabled
RNG interrupt is enabled
1
RNGEN
Random number generator
enable
2
1
RNGEN
Disabled
Random number generator is disabled
0
Enabled
Random number generator is enabled
1
SR
SR
status register
0x4
0x20
0x00000000
SEIS
Seed error interrupt
status
6
1
read-write
CEIS
Clock error interrupt
status
5
1
read-write
SECS
Seed error current status
2
1
read-only
CECS
Clock error current status
1
1
read-only
DRDY
Data ready
0
1
read-only
DR
DR
data register
0x8
0x20
read-only
0x00000000
RNDATA
Random data
0
32
HASH
Hash processor
HASH
0x50060400
0x0
0x400
registers
HASH_RNG
Hash and Rng global interrupt
80
HASH_RNG
Hash and Rng global interrupt
80
CR
CR
control register
0x0
0x20
0x00000000
INIT
Initialize message digest
calculation
2
1
write-only
DMAE
DMA enable
3
1
read-write
DATATYPE
Data type selection
4
2
read-write
MODE
Mode selection
6
1
read-write
ALGO0
Algorithm selection
7
1
read-write
NBW
Number of words already
pushed
8
4
read-only
DINNE
DIN not empty
12
1
read-only
MDMAT
Multiple DMA Transfers
13
1
read-write
LKEY
Long key selection
16
1
read-write
ALGO1
ALGO
18
1
read-write
DIN
DIN
data input register
0x4
0x20
read-write
0x00000000
DATAIN
Data input
0
32
STR
STR
start register
0x8
0x20
0x00000000
DCAL
Digest calculation
8
1
write-only
NBLW
Number of valid bits in the last word of
the message
0
5
read-write
5
0x4
0-4
HR%s
HR%s
digest registers
0xC
0x20
read-only
0x00000000
H
H0
0
32
IMR
IMR
interrupt enable register
0x20
0x20
read-write
0x00000000
DCIE
Digest calculation completion interrupt
enable
1
1
DINIE
Data input interrupt
enable
0
1
SR
SR
status register
0x24
0x20
0x00000001
BUSY
Busy bit
3
1
read-only
DMAS
DMA Status
2
1
read-only
DCIS
Digest calculation completion interrupt
status
1
1
read-write
DINIS
Data input interrupt
status
0
1
read-write
54
0x4
0-53
CSR%s
CSR%s
context swap registers
0xF8
0x20
read-write
0x00000000
CSR
CSR0
0
32
8
0x4
0-7
HASH_HR%s
HASH_HR%s
HASH digest register %s
0x310
0x20
read-only
0x00000000
H
H0
0
32
CRYP
Cryptographic processor
CRYP
0x50060000
0x0
0x400
registers
CRYP
CRYP crypto global interrupt
79
CRYP
CRYP crypto global interrupt
79
CR
CR
control register
0x0
0x20
0x00000000
ALGODIR
Algorithm direction
2
1
read-write
ALGOMODE0
Algorithm mode
3
3
read-write
DATATYPE
Data type selection
6
2
read-write
KEYSIZE
Key size selection (AES mode
only)
8
2
read-write
FFLUSH
FIFO flush
14
1
write-only
CRYPEN
Cryptographic processor
enable
15
1
read-write
GCM_CCMPH
GCM_CCMPH
16
2
read-write
ALGOMODE3
ALGOMODE
19
1
read-write
SR
SR
status register
0x4
0x20
read-only
0x00000003
BUSY
Busy bit
4
1
OFFU
Output FIFO full
3
1
OFNE
Output FIFO not empty
2
1
IFNF
Input FIFO not full
1
1
IFEM
Input FIFO empty
0
1
DIN
DIN
data input register
0x8
0x20
read-write
0x00000000
DATAIN
Data input
0
32
DOUT
DOUT
data output register
0xC
0x20
read-only
0x00000000
DATAOUT
Data output
0
32
DMACR
DMACR
DMA control register
0x10
0x20
read-write
0x00000000
DOEN
DMA output enable
1
1
DIEN
DMA input enable
0
1
IMSCR
IMSCR
interrupt mask set/clear
register
0x14
0x20
read-write
0x00000000
OUTIM
Output FIFO service interrupt
mask
1
1
INIM
Input FIFO service interrupt
mask
0
1
RISR
RISR
raw interrupt status register
0x18
0x20
read-only
0x00000001
OUTRIS
Output FIFO service raw interrupt
status
1
1
INRIS
Input FIFO service raw interrupt
status
0
1
MISR
MISR
masked interrupt status
register
0x1C
0x20
read-only
0x00000000
OUTMIS
Output FIFO service masked interrupt
status
1
1
INMIS
Input FIFO service masked interrupt
status
0
1
4
0x8
0-3
KEY%s
Cluster KEY%s, containing K?LR, K?RR
0x20
KLR
K0LR
key registers
0x0
0x20
write-only
0x00000000
b2
b224
0
32
KRR
K0RR
key registers
0x4
0x20
write-only
0x00000000
b
b192
0
32
2
0x8
0-1
INIT%s
Cluster INIT%s, containing IV?LR, IV?RR
0x40
IVLR
IV0LR
initialization vector
registers
0x0
0x20
read-write
0x00000000
IV
IV31
0
32
IVRR
IV0RR
initialization vector
registers
0x4
0x20
read-write
0x00000000
IV
IV63
0
32
8
0x4
0-7
CSGCMCCM%sR
CSGCMCCM%sR
context swap register
0x50
0x20
read-write
0x00000000
CSGCMCCM0R
CSGCMCCM0R
0
32
8
0x4
0-7
CSGCM%sR
CSGCM%sR
context swap register
0x70
0x20
read-write
0x00000000
CSGCMR
CSGCM0R
0
32
DCMI
Digital camera interface
DCMI
0x50050000
0x0
0x400
registers
DCMI
DCMI global interrupt
78
DCMI
DCMI global interrupt
78
CR
CR
control register 1
0x0
0x20
read-write
0x00000000
ENABLE
DCMI enable
14
1
EDM
Extended data mode
10
2
FCRC
Frame capture rate control
8
2
VSPOL
Vertical synchronization
polarity
7
1
HSPOL
Horizontal synchronization
polarity
6
1
PCKPOL
Pixel clock polarity
5
1
ESS
Embedded synchronization
select
4
1
JPEG
JPEG format
3
1
CROP
Crop feature
2
1
CM
Capture mode
1
1
CAPTURE
Capture enable
0
1
SR
SR
status register
0x4
0x20
read-only
0x00000000
FNE
FIFO not empty
2
1
VSYNC
VSYNC
1
1
HSYNC
HSYNC
0
1
RIS
RIS
raw interrupt status register
0x8
0x20
read-only
0x00000000
LINE_RIS
Line raw interrupt status
4
1
VSYNC_RIS
VSYNC raw interrupt status
3
1
ERR_RIS
Synchronization error raw interrupt
status
2
1
OVR_RIS
Overrun raw interrupt
status
1
1
FRAME_RIS
Capture complete raw interrupt
status
0
1
IER
IER
interrupt enable register
0xC
0x20
read-write
0x00000000
LINE_IE
Line interrupt enable
4
1
VSYNC_IE
VSYNC interrupt enable
3
1
ERR_IE
Synchronization error interrupt
enable
2
1
OVR_IE
Overrun interrupt enable
1
1
FRAME_IE
Capture complete interrupt
enable
0
1
MIS
MIS
masked interrupt status
register
0x10
0x20
read-only
0x00000000
LINE_MIS
Line masked interrupt
status
4
1
VSYNC_MIS
VSYNC masked interrupt
status
3
1
ERR_MIS
Synchronization error masked interrupt
status
2
1
OVR_MIS
Overrun masked interrupt
status
1
1
FRAME_MIS
Capture complete masked interrupt
status
0
1
ICR
ICR
interrupt clear register
0x14
0x20
write-only
0x00000000
LINE_ISC
line interrupt status
clear
4
1
VSYNC_ISC
Vertical synch interrupt status
clear
3
1
ERR_ISC
Synchronization error interrupt status
clear
2
1
OVR_ISC
Overrun interrupt status
clear
1
1
FRAME_ISC
Capture complete interrupt status
clear
0
1
ESCR
ESCR
embedded synchronization code
register
0x18
0x20
read-write
0x00000000
FEC
Frame end delimiter code
24
8
LEC
Line end delimiter code
16
8
LSC
Line start delimiter code
8
8
FSC
Frame start delimiter code
0
8
ESUR
ESUR
embedded synchronization unmask
register
0x1C
0x20
read-write
0x00000000
FEU
Frame end delimiter unmask
24
8
LEU
Line end delimiter unmask
16
8
LSU
Line start delimiter
unmask
8
8
FSU
Frame start delimiter
unmask
0
8
CWSTRT
CWSTRT
crop window start
0x20
0x20
read-write
0x00000000
VST
Vertical start line count
16
13
HOFFCNT
Horizontal offset count
0
14
CWSIZE
CWSIZE
crop window size
0x24
0x20
read-write
0x00000000
VLINE
Vertical line count
16
14
CAPCNT
Capture count
0
14
DR
DR
data register
0x28
0x20
read-only
0x00000000
Byte3
Data byte 3
24
8
Byte2
Data byte 2
16
8
Byte1
Data byte 1
8
8
Byte0
Data byte 0
0
8
FMC
Flexible memory controller
FSMC
0xA0000000
0x0
0x400
registers
FMC
FMC global interrupt
48
FMC
FMC global interrupt
48
BCR1
BCR1
SRAM/NOR-Flash chip-select control register
1
0x0
0x20
read-write
0x000030D0
CCLKEN
CCLKEN
20
1
CBURSTRW
CBURSTRW
19
1
CBURSTRW
Disabled
Write operations are always performed in asynchronous mode
0
Enabled
Write operations are performed in synchronous mode
1
ASYNCWAIT
ASYNCWAIT
15
1
ASYNCWAIT
Disabled
Wait signal not used in asynchronous mode
0
Enabled
Wait signal used even in asynchronous mode
1
EXTMOD
EXTMOD
14
1
EXTMOD
Disabled
Values inside the FMC_BWTR are not taken into account
0
Enabled
Values inside the FMC_BWTR are taken into account
1
WAITEN
WAITEN
13
1
WAITEN
Disabled
Values inside the FMC_BWTR are taken into account
0
Enabled
NWAIT signal enabled
1
WREN
WREN
12
1
WREN
Disabled
Write operations disabled for the bank by the FMC
0
Enabled
Write operations enabled for the bank by the FMC
1
WAITCFG
WAITCFG
11
1
WAITCFG
BeforeWaitState
NWAIT signal is active one data cycle before wait state
0
DuringWaitState
NWAIT signal is active during wait state
1
WAITPOL
WAITPOL
9
1
WAITPOL
ActiveLow
NWAIT active low
0
ActiveHigh
NWAIT active high
1
BURSTEN
BURSTEN
8
1
BURSTEN
Disabled
Burst mode disabled
0
Enabled
Burst mode enabled
1
FACCEN
FACCEN
6
1
FACCEN
Disabled
Corresponding NOR Flash memory access is disabled
0
Enabled
Corresponding NOR Flash memory access is enabled
1
MWID
MWID
4
2
MWID
Bits8
Memory data bus width 8 bits
0
Bits16
Memory data bus width 16 bits
1
Bits32
Memory data bus width 32 bits
2
MTYP
MTYP
2
2
MTYP
SRAM
SRAM memory type
0
PSRAM
PSRAM (CRAM) memory type
1
Flash
NOR Flash/OneNAND Flash
2
MUXEN
MUXEN
1
1
MUXEN
Disabled
Address/Data non-multiplexed
0
Enabled
Address/Data multiplexed on databus
1
MBKEN
MBKEN
0
1
MBKEN
Disabled
Corresponding memory bank is disabled
0
Enabled
Corresponding memory bank is enabled
1
WRAPMOD
WRAPMOD
10
1
CPSIZE
CRAM page size
16
3
read-write
CPSIZE
NoBurstSplit
No burst split when crossing page boundary
0
Bytes128
128 bytes CRAM page size
1
Bytes256
256 bytes CRAM page size
2
Bytes512
512 bytes CRAM page size
3
Bytes1024
1024 bytes CRAM page size
4
4
0x8
1-4
BTR%s
BTR%s
SRAM/NOR-Flash chip-select timing register
%s
0x4
0x20
read-write
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ACCMOD
A
Access mode A
0
B
Access mode B
1
C
Access mode C
2
D
Access mode D
3
DATLAT
DATLAT
24
4
0
15
CLKDIV
CLKDIV
20
4
1
15
BUSTURN
BUSTURN
16
4
0
15
DATAST
DATAST
8
8
1
255
ADDHLD
ADDHLD
4
4
1
15
ADDSET
ADDSET
0
4
0
15
3
0x8
2-4
BCR%s
BCR%s
SRAM/NOR-Flash chip-select control register
%s
0x8
0x20
read-write
0x000030D0
CBURSTRW
CBURSTRW
19
1
CBURSTRW
Disabled
Write operations are always performed in asynchronous mode
0
Enabled
Write operations are performed in synchronous mode
1
ASYNCWAIT
ASYNCWAIT
15
1
ASYNCWAIT
Disabled
Wait signal not used in asynchronous mode
0
Enabled
Wait signal used even in asynchronous mode
1
EXTMOD
EXTMOD
14
1
EXTMOD
Disabled
Values inside the FMC_BWTR are not taken into account
0
Enabled
Values inside the FMC_BWTR are taken into account
1
WAITEN
WAITEN
13
1
WAITEN
Disabled
Values inside the FMC_BWTR are taken into account
0
Enabled
NWAIT signal enabled
1
WREN
WREN
12
1
WREN
Disabled
Write operations disabled for the bank by the FMC
0
Enabled
Write operations enabled for the bank by the FMC
1
WAITCFG
WAITCFG
11
1
WAITCFG
BeforeWaitState
NWAIT signal is active one data cycle before wait state
0
DuringWaitState
NWAIT signal is active during wait state
1
WRAPMOD
WRAPMOD
10
1
WAITPOL
WAITPOL
9
1
WAITPOL
ActiveLow
NWAIT active low
0
ActiveHigh
NWAIT active high
1
BURSTEN
BURSTEN
8
1
BURSTEN
Disabled
Burst mode disabled
0
Enabled
Burst mode enabled
1
FACCEN
FACCEN
6
1
FACCEN
Disabled
Corresponding NOR Flash memory access is disabled
0
Enabled
Corresponding NOR Flash memory access is enabled
1
MWID
MWID
4
2
MWID
Bits8
Memory data bus width 8 bits
0
Bits16
Memory data bus width 16 bits
1
Bits32
Memory data bus width 32 bits
2
MTYP
MTYP
2
2
MTYP
SRAM
SRAM memory type
0
PSRAM
PSRAM (CRAM) memory type
1
Flash
NOR Flash/OneNAND Flash
2
MUXEN
MUXEN
1
1
MUXEN
Disabled
Address/Data non-multiplexed
0
Enabled
Address/Data multiplexed on databus
1
MBKEN
MBKEN
0
1
MBKEN
Disabled
Corresponding memory bank is disabled
0
Enabled
Corresponding memory bank is enabled
1
CPSIZE
CRAM page size
16
3
read-write
CPSIZE
NoBurstSplit
No burst split when crossing page boundary
0
Bytes128
128 bytes CRAM page size
1
Bytes256
256 bytes CRAM page size
2
Bytes512
512 bytes CRAM page size
3
Bytes1024
1024 bytes CRAM page size
4
3
0x20
2-4
PCR%s
PCR%s
PC Card/NAND Flash control register
%s
0x60
0x20
read-write
0x00000018
ECCPS
ECCPS
17
3
ECCPS
Bytes256
ECC page size 256 bytes
0
Bytes512
ECC page size 512 bytes
1
Bytes1024
ECC page size 1024 bytes
2
Bytes2048
ECC page size 2048 bytes
3
Bytes4096
ECC page size 4096 bytes
4
Bytes8192
ECC page size 8192 bytes
5
TAR
TAR
13
4
0
15
TCLR
TCLR
9
4
0
15
ECCEN
ECCEN
6
1
ECCEN
Disabled
ECC logic is disabled and reset
0
Enabled
ECC logic is enabled
1
PWID
PWID
4
2
PWID
Bits8
External memory device width 8 bits
0
Bits16
External memory device width 16 bits
1
PTYP
PTYP
3
1
PTYP
NANDFlash
NAND Flash
1
PBKEN
PBKEN
2
1
PBKEN
Disabled
Corresponding memory bank is disabled
0
Enabled
Corresponding memory bank is enabled
1
PWAITEN
PWAITEN
1
1
PWAITEN
Disabled
Wait feature disabled
0
Enabled
Wait feature enabled
1
3
0x20
2-4
SR%s
SR%s
FIFO status and interrupt register
%s
0x64
0x20
0x00000040
FEMPT
FEMPT
6
1
read-only
FEMPT
NotEmpty
FIFO not empty
0
Empty
FIFO empty
1
IFEN
IFEN
5
1
read-write
IFEN
Disabled
Interrupt falling edge detection request disabled
0
Enabled
Interrupt falling edge detection request enabled
1
ILEN
ILEN
4
1
read-write
ILEN
Disabled
Interrupt high-level detection request disabled
0
Enabled
Interrupt high-level detection request enabled
1
IREN
IREN
3
1
read-write
IREN
Disabled
Interrupt rising edge detection request disabled
0
Enabled
Interrupt rising edge detection request enabled
1
IFS
IFS
2
1
read-write
IFS
DidNotOccur
Interrupt falling edge did not occur
0
Occurred
Interrupt falling edge occurred
1
ILS
ILS
1
1
read-write
ILS
DidNotOccur
Interrupt high-level did not occur
0
Occurred
Interrupt high-level occurred
1
IRS
IRS
0
1
read-write
IRS
DidNotOccur
Interrupt rising edge did not occur
0
Occurred
Interrupt rising edge occurred
1
PMEM2
PMEM2
Common memory space timing register
2
0x68
0x20
read-write
0xFCFCFCFC
MEMHIZ
MEMHIZx
24
8
0
254
MEMHOLD
MEMHOLDx
16
8
1
254
MEMWAIT
MEMWAITx
8
8
1
254
MEMSET
MEMSETx
0
8
0
254
PATT2
PATT2
Attribute memory space timing register
2
0x6C
0x20
read-write
0xFCFCFCFC
ATTHIZ
ATTHIZx
24
8
0
254
ATTHOLD
ATTHOLDx
16
8
1
254
ATTWAIT
ATTWAITx
8
8
1
254
ATTSET
ATTSETx
0
8
0
254
ECCR2
ECCR2
ECC result register 2
0x74
0x20
read-only
0x00000000
ECC
ECCx
0
32
0
4294967295
PMEM3
PMEM3
Common memory space timing register
3
0x88
0x20
read-write
0xFCFCFCFC
MEMHIZ
MEMHIZx
24
8
0
254
MEMHOLD
MEMHOLDx
16
8
1
254
MEMWAIT
MEMWAITx
8
8
1
254
MEMSET
MEMSETx
0
8
0
254
PATT3
PATT3
Attribute memory space timing register
3
0x8C
0x20
read-write
0xFCFCFCFC
ATTHIZ
ATTHIZx
24
8
0
254
ATTHOLD
ATTHOLDx
16
8
1
254
ATTWAIT
ATTWAITx
8
8
1
254
ATTSET
ATTSETx
0
8
0
254
ECCR3
ECCR3
ECC result register 3
0x94
0x20
read-only
0x00000000
ECC
ECCx
0
32
0
4294967295
PMEM4
PMEM4
Common memory space timing register
4
0xA8
0x20
read-write
0xFCFCFCFC
MEMHIZ
MEMHIZx
24
8
0
254
MEMHOLD
MEMHOLDx
16
8
1
254
MEMWAIT
MEMWAITx
8
8
1
254
MEMSET
MEMSETx
0
8
0
254
PATT4
PATT4
Attribute memory space timing register
4
0xAC
0x20
read-write
0xFCFCFCFC
ATTHIZ
ATTHIZx
24
8
0
254
ATTHOLD
ATTHOLDx
16
8
1
254
ATTWAIT
ATTWAITx
8
8
1
254
ATTSET
ATTSETx
0
8
0
254
PIO4
PIO4
I/O space timing register 4
0xB0
0x20
read-write
0xFCFCFCFC
IOHIZx
IOHIZx
24
8
IOHOLDx
IOHOLDx
16
8
IOWAITx
IOWAITx
8
8
IOSETx
IOSETx
0
8
4
0x8
1-4
BWTR%s
BWTR%s
SRAM/NOR-Flash write timing registers
%s
0x104
0x20
read-write
0x0FFFFFFF
ACCMOD
ACCMOD
28
2
ACCMOD
A
Access mode A
0
B
Access mode B
1
C
Access mode C
2
D
Access mode D
3
DATLAT
DATLAT
24
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
1
255
ADDHLD
ADDHLD
4
4
1
15
ADDSET
ADDSET
0
4
0
15
BUSTURN
Bus turnaround phase duration
16
4
read-write
0
15
2
0x4
1-2
SDCR%s
SDCR%s
SDRAM Control Register %s
0x140
0x20
read-write
0x000002D0
NC
Number of column address
bits
0
2
NC
Bits8
8 bits
0
Bits9
9 bits
1
Bits10
10 bits
2
Bits11
11 bits
3
NR
Number of row address bits
2
2
NR
Bits11
11 bits
0
Bits12
12 bits
1
Bits13
13 bits
2
MWID
Memory data bus width
4
2
MWID
Bits8
Memory data bus width 8 bits
0
Bits16
Memory data bus width 16 bits
1
Bits32
Memory data bus width 32 bits
2
NB
Number of internal banks
6
1
NB
NB2
Two internal Banks
0
NB4
Four internal Banks
1
CAS
CAS latency
7
2
CAS
Clocks1
1 cycle
1
Clocks2
2 cycles
2
Clocks3
3 cycles
3
WP
Write protection
9
1
WP
Disabled
Write accesses allowed
0
Enabled
Write accesses ignored
1
SDCLK
SDRAM clock configuration
10
2
SDCLK
Disabled
SDCLK clock disabled
0
Div2
SDCLK period = 2 x HCLK period
2
Div3
SDCLK period = 3 x HCLK period
3
RBURST
Burst read
12
1
RBURST
Disabled
Single read requests are not managed as bursts
0
Enabled
Single read requests are always managed as bursts
1
RPIPE
Read pipe
13
2
RPIPE
NoDelay
No clock cycle delay
0
Clocks1
One clock cycle delay
1
Clocks2
Two clock cycles delay
2
2
0x4
1-2
SDTR%s
SDTR%s
SDRAM Timing register %s
0x148
0x20
read-write
0x0FFFFFFF
TMRD
Load Mode Register to
Active
0
4
0
15
TXSR
Exit self-refresh delay
4
4
0
15
TRAS
Self refresh time
8
4
0
15
TRC
Row cycle delay
12
4
0
15
TWR
Recovery delay
16
4
0
15
TRP
Row precharge delay
20
4
0
15
TRCD
Row to column delay
24
4
0
15
SDCMR
SDCMR
SDRAM Command Mode register
0x150
0x20
0x00000000
MODE
Command mode
0
3
write-only
MODE
Normal
Normal Mode
0
ClockConfigurationEnable
Clock Configuration Enable
1
PALL
PALL (All Bank Precharge) command
2
AutoRefreshCommand
Auto-refresh command
3
LoadModeRegister
Load Mode Resgier
4
SelfRefreshCommand
Self-refresh command
5
PowerDownCommand
Power-down command
6
CTB2
Command target bank 2
3
1
write-only
CTB2
NotIssued
Command not issued to SDRAM Bank 1
0
Issued
Command issued to SDRAM Bank 1
1
CTB1
Command target bank 1
4
1
write-only
NRFS
Number of Auto-refresh
5
4
read-write
0
15
MRD
Mode Register definition
9
13
read-write
0
8191
SDRTR
SDRTR
SDRAM Refresh Timer register
0x154
0x20
0x00000000
CRE
Clear Refresh error flag
0
1
write-only
CRE
Clear
Refresh Error Flag is cleared
1
COUNT
Refresh Timer Count
1
13
read-write
0
8191
REIE
RES Interrupt Enable
14
1
read-write
REIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is generated if RE = 1
1
SDSR
SDSR
SDRAM Status register
0x158
0x20
read-only
0x00000000
RE
Refresh error flag
0
1
RE
NoError
No refresh error has been detected
0
Error
A refresh error has been detected
1
MODES1
Status Mode for Bank 1
1
2
MODES1
Normal
Normal Mode
0
SelfRefresh
Self-refresh mode
1
PowerDown
Power-down mode
2
MODES2
Status Mode for Bank 2
3
2
BUSY
Busy status
5
1
BUSY
NotBusy
SDRAM Controller is ready to accept a new request
0
Busy
SDRAM Controller is not ready to accept a new request
1
DBGMCU
Debug support
DBG
0xE0042000
0x0
0x400
registers
IDCODE
IDCODE
IDCODE
0x0
0x20
read-only
0x10006411
DEV_ID
DEV_ID
0
12
REV_ID
REV_ID
16
16
CR
CR
Control Register
0x4
0x20
read-write
0x00000000
DBG_SLEEP
DBG_SLEEP
0
1
DBG_STOP
DBG_STOP
1
1
DBG_STANDBY
DBG_STANDBY
2
1
TRACE_IOEN
TRACE_IOEN
5
1
TRACE_MODE
TRACE_MODE
6
2
APB1_FZ
APB1_FZ
Debug MCU APB1 Freeze registe
0x8
0x20
read-write
0x00000000
DBG_TIM2_STOP
DBG_TIM2_STOP
0
1
DBG_TIM3_STOP
DBG_TIM3 _STOP
1
1
DBG_TIM4_STOP
DBG_TIM4_STOP
2
1
DBG_TIM5_STOP
DBG_TIM5_STOP
3
1
DBG_TIM6_STOP
DBG_TIM6_STOP
4
1
DBG_TIM7_STOP
DBG_TIM7_STOP
5
1
DBG_TIM12_STOP
DBG_TIM12_STOP
6
1
DBG_TIM13_STOP
DBG_TIM13_STOP
7
1
DBG_TIM14_STOP
DBG_TIM14_STOP
8
1
DBG_WWDG_STOP
DBG_WWDG_STOP
11
1
DBG_IWDG_STOP
DBG_IWDEG_STOP
12
1
DBG_J2C1_SMBUS_TIMEOUT
DBG_J2C1_SMBUS_TIMEOUT
21
1
DBG_J2C2_SMBUS_TIMEOUT
DBG_J2C2_SMBUS_TIMEOUT
22
1
DBG_J2C3SMBUS_TIMEOUT
DBG_J2C3SMBUS_TIMEOUT
23
1
DBG_CAN1_STOP
DBG_CAN1_STOP
25
1
DBG_CAN2_STOP
DBG_CAN2_STOP
26
1
APB2_FZ
APB2_FZ
Debug MCU APB2 Freeze registe
0xC
0x20
read-write
0x00000000
DBG_TIM1_STOP
TIM1 counter stopped when core is
halted
0
1
DBG_TIM8_STOP
TIM8 counter stopped when core is
halted
1
1
DBG_TIM9_STOP
TIM9 counter stopped when core is
halted
16
1
DBG_TIM10_STOP
TIM10 counter stopped when core is
halted
17
1
DBG_TIM11_STOP
TIM11 counter stopped when core is
halted
18
1
DMA2
DMA controller
DMA
0x40026400
0x0
0x400
registers
DMA2_Stream0
DMA2 Stream0 global interrupt
56
DMA2_Stream0
DMA2 Stream0 global interrupt
56
DMA2_Stream1
DMA2 Stream1 global interrupt
57
DMA2_Stream1
DMA2 Stream1 global interrupt
57
DMA2_Stream2
DMA2 Stream2 global interrupt
58
DMA2_Stream2
DMA2 Stream2 global interrupt
58
DMA2_Stream3
DMA2 Stream3 global interrupt
59
DMA2_Stream3
DMA2 Stream3 global interrupt
59
DMA2_Stream4
DMA2 Stream4 global interrupt
60
DMA2_Stream4
DMA2 Stream4 global interrupt
60
DMA2_Stream5
DMA2 Stream5 global interrupt
68
DMA2_Stream5
DMA2 Stream5 global interrupt
68
DMA2_Stream6
DMA2 Stream6 global interrupt
69
DMA2_Stream6
DMA2 Stream6 global interrupt
69
DMA2_Stream7
DMA2 Stream7 global interrupt
70
DMA2_Stream7
DMA2 Stream7 global interrupt
70
LISR
LISR
low interrupt status register
0x0
0x20
read-only
0x00000000
TCIF0
Stream x transfer complete interrupt
flag (x = 3..0)
5
1
TCIF0
NotComplete
No transfer complete event on stream x
0
Complete
A transfer complete event occurred on stream x
1
TCIF3
Stream x transfer complete interrupt
flag (x = 3..0)
27
1
HTIF0
Stream x half transfer interrupt flag
(x=3..0)
4
1
HTIF0
NotHalf
No half transfer event on stream x
0
Half
A half transfer event occurred on stream x
1
HTIF3
Stream x half transfer interrupt flag
(x=3..0)
26
1
TEIF0
Stream x transfer error interrupt flag
(x=3..0)
3
1
TEIF0
NoError
No transfer error on stream x
0
Error
A transfer error occurred on stream x
1
TEIF3
Stream x transfer error interrupt flag
(x=3..0)
25
1
DMEIF0
Stream x direct mode error interrupt
flag (x=3..0)
2
1
DMEIF0
NoError
No Direct Mode error on stream x
0
Error
A Direct Mode error occurred on stream x
1
DMEIF3
Stream x direct mode error interrupt
flag (x=3..0)
24
1
FEIF0
Stream x FIFO error interrupt flag
(x=3..0)
0
1
FEIF0
NoError
No FIFO error event on stream x
0
Error
A FIFO error event occurred on stream x
1
FEIF3
Stream x FIFO error interrupt flag
(x=3..0)
22
1
TCIF2
Stream x transfer complete interrupt
flag (x = 3..0)
21
1
HTIF2
Stream x half transfer interrupt flag
(x=3..0)
20
1
TEIF2
Stream x transfer error interrupt flag
(x=3..0)
19
1
DMEIF2
Stream x direct mode error interrupt
flag (x=3..0)
18
1
FEIF2
Stream x FIFO error interrupt flag
(x=3..0)
16
1
TCIF1
Stream x transfer complete interrupt
flag (x = 3..0)
11
1
HTIF1
Stream x half transfer interrupt flag
(x=3..0)
10
1
TEIF1
Stream x transfer error interrupt flag
(x=3..0)
9
1
DMEIF1
Stream x direct mode error interrupt
flag (x=3..0)
8
1
FEIF1
Stream x FIFO error interrupt flag
(x=3..0)
6
1
HISR
HISR
high interrupt status register
0x4
0x20
read-only
0x00000000
TCIF4
Stream x transfer complete interrupt
flag (x=7..4)
5
1
TCIF4
NotComplete
No transfer complete event on stream x
0
Complete
A transfer complete event occurred on stream x
1
TCIF7
Stream x transfer complete interrupt
flag (x=7..4)
27
1
HTIF4
Stream x half transfer interrupt flag
(x=7..4)
4
1
HTIF4
NotHalf
No half transfer event on stream x
0
Half
A half transfer event occurred on stream x
1
HTIF7
Stream x half transfer interrupt flag
(x=7..4)
26
1
TEIF4
Stream x transfer error interrupt flag
(x=7..4)
3
1
TEIF4
NoError
No transfer error on stream x
0
Error
A transfer error occurred on stream x
1
TEIF7
Stream x transfer error interrupt flag
(x=7..4)
25
1
DMEIF4
Stream x direct mode error interrupt
flag (x=7..4)
2
1
DMEIF4
NoError
No Direct Mode error on stream x
0
Error
A Direct Mode error occurred on stream x
1
DMEIF7
Stream x direct mode error interrupt
flag (x=7..4)
24
1
FEIF4
Stream x FIFO error interrupt flag
(x=7..4)
0
1
FEIF4
NoError
No FIFO error event on stream x
0
Error
A FIFO error event occurred on stream x
1
FEIF7
Stream x FIFO error interrupt flag
(x=7..4)
22
1
TCIF6
Stream x transfer complete interrupt
flag (x=7..4)
21
1
HTIF6
Stream x half transfer interrupt flag
(x=7..4)
20
1
TEIF6
Stream x transfer error interrupt flag
(x=7..4)
19
1
DMEIF6
Stream x direct mode error interrupt
flag (x=7..4)
18
1
FEIF6
Stream x FIFO error interrupt flag
(x=7..4)
16
1
TCIF5
Stream x transfer complete interrupt
flag (x=7..4)
11
1
HTIF5
Stream x half transfer interrupt flag
(x=7..4)
10
1
TEIF5
Stream x transfer error interrupt flag
(x=7..4)
9
1
DMEIF5
Stream x direct mode error interrupt
flag (x=7..4)
8
1
FEIF5
Stream x FIFO error interrupt flag
(x=7..4)
6
1
LIFCR
LIFCR
low interrupt flag clear
register
0x8
0x20
write-only
0x00000000
CTCIF0
Stream x clear transfer complete
interrupt flag (x = 3..0)
5
1
CTCIF0
Clear
Clear the corresponding TCIFx flag
1
CTCIF3
Stream x clear transfer complete
interrupt flag (x = 3..0)
27
1
CHTIF0
Stream x clear half transfer interrupt
flag (x = 3..0)
4
1
CHTIF0
Clear
Clear the corresponding HTIFx flag
1
CHTIF3
Stream x clear half transfer interrupt
flag (x = 3..0)
26
1
CTEIF0
Stream x clear transfer error interrupt
flag (x = 3..0)
3
1
CTEIF0
Clear
Clear the corresponding TEIFx flag
1
CTEIF3
Stream x clear transfer error interrupt
flag (x = 3..0)
25
1
CDMEIF0
Stream x clear direct mode error
interrupt flag (x = 3..0)
2
1
CDMEIF0
Clear
Clear the corresponding DMEIFx flag
1
CDMEIF3
Stream x clear direct mode error
interrupt flag (x = 3..0)
24
1
CFEIF0
Stream x clear FIFO error interrupt flag
(x = 3..0)
0
1
CFEIF0
Clear
Clear the corresponding CFEIFx flag
1
CFEIF3
Stream x clear FIFO error interrupt flag
(x = 3..0)
22
1
CTCIF2
Stream x clear transfer complete
interrupt flag (x = 3..0)
21
1
CHTIF2
Stream x clear half transfer interrupt
flag (x = 3..0)
20
1
CTEIF2
Stream x clear transfer error interrupt
flag (x = 3..0)
19
1
CDMEIF2
Stream x clear direct mode error
interrupt flag (x = 3..0)
18
1
CFEIF2
Stream x clear FIFO error interrupt flag
(x = 3..0)
16
1
CTCIF1
Stream x clear transfer complete
interrupt flag (x = 3..0)
11
1
CHTIF1
Stream x clear half transfer interrupt
flag (x = 3..0)
10
1
CTEIF1
Stream x clear transfer error interrupt
flag (x = 3..0)
9
1
CDMEIF1
Stream x clear direct mode error
interrupt flag (x = 3..0)
8
1
CFEIF1
Stream x clear FIFO error interrupt flag
(x = 3..0)
6
1
HIFCR
HIFCR
high interrupt flag clear
register
0xC
0x20
write-only
0x00000000
CTCIF4
Stream x clear transfer complete
interrupt flag (x = 7..4)
5
1
CTCIF4
Clear
Clear the corresponding TCIFx flag
1
CTCIF7
Stream x clear transfer complete
interrupt flag (x = 7..4)
27
1
CHTIF4
Stream x clear half transfer interrupt
flag (x = 7..4)
4
1
CHTIF4
Clear
Clear the corresponding HTIFx flag
1
CHTIF7
Stream x clear half transfer interrupt
flag (x = 7..4)
26
1
CTEIF4
Stream x clear transfer error interrupt
flag (x = 7..4)
3
1
CTEIF4
Clear
Clear the corresponding TEIFx flag
1
CTEIF7
Stream x clear transfer error interrupt
flag (x = 7..4)
25
1
CDMEIF4
Stream x clear direct mode error
interrupt flag (x = 7..4)
2
1
CDMEIF4
Clear
Clear the corresponding DMEIFx flag
1
CDMEIF7
Stream x clear direct mode error
interrupt flag (x = 7..4)
24
1
CFEIF4
Stream x clear FIFO error interrupt flag
(x = 7..4)
0
1
CFEIF4
Clear
Clear the corresponding CFEIFx flag
1
CFEIF7
Stream x clear FIFO error interrupt flag
(x = 7..4)
22
1
CTCIF6
Stream x clear transfer complete
interrupt flag (x = 7..4)
21
1
CHTIF6
Stream x clear half transfer interrupt
flag (x = 7..4)
20
1
CTEIF6
Stream x clear transfer error interrupt
flag (x = 7..4)
19
1
CDMEIF6
Stream x clear direct mode error
interrupt flag (x = 7..4)
18
1
CFEIF6
Stream x clear FIFO error interrupt flag
(x = 7..4)
16
1
CTCIF5
Stream x clear transfer complete
interrupt flag (x = 7..4)
11
1
CHTIF5
Stream x clear half transfer interrupt
flag (x = 7..4)
10
1
CTEIF5
Stream x clear transfer error interrupt
flag (x = 7..4)
9
1
CDMEIF5
Stream x clear direct mode error
interrupt flag (x = 7..4)
8
1
CFEIF5
Stream x clear FIFO error interrupt flag
(x = 7..4)
6
1
8
0x18
0-7
ST%s
Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers
0x10
CR
S0CR
stream x configuration
register
0x0
0x20
read-write
0x00000000
CHSEL
Channel selection
25
3
0
7
PBURST
Peripheral burst transfer
configuration
21
2
PBURST
Single
Single transfer
0
INCR4
Incremental burst of 4 beats
1
INCR8
Incremental burst of 8 beats
2
INCR16
Incremental burst of 16 beats
3
MBURST
Memory burst transfer
configuration
23
2
CT
Current target (only in double buffer
mode)
19
1
CT
Memory0
The current target memory is Memory 0
0
Memory1
The current target memory is Memory 1
1
DBM
Double buffer mode
18
1
DBM
Disabled
No buffer switching at the end of transfer
0
Enabled
Memory target switched at the end of the DMA transfer
1
PL
Priority level
16
2
PL
Low
Low
0
Medium
Medium
1
High
High
2
VeryHigh
Very high
3
PINCOS
Peripheral increment offset
size
15
1
PINCOS
PSIZE
The offset size for the peripheral address calculation is linked to the PSIZE
0
Fixed4
The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)
1
PSIZE
Peripheral data size
11
2
PSIZE
Bits8
Byte (8-bit)
0
Bits16
Half-word (16-bit)
1
Bits32
Word (32-bit)
2
MSIZE
Memory data size
13
2
PINC
Peripheral increment mode
9
1
PINC
Fixed
Address pointer is fixed
0
Incremented
Address pointer is incremented after each data transfer
1
MINC
Memory increment mode
10
1
CIRC
Circular mode
8
1
CIRC
Disabled
Circular mode disabled
0
Enabled
Circular mode enabled
1
DIR
Data transfer direction
6
2
DIR
PeripheralToMemory
Peripheral-to-memory
0
MemoryToPeripheral
Memory-to-peripheral
1
MemoryToMemory
Memory-to-memory
2
PFCTRL
Peripheral flow controller
5
1
PFCTRL
DMA
The DMA is the flow controller
0
Peripheral
The peripheral is the flow controller
1
TCIE
Transfer complete interrupt
enable
4
1
TCIE
Disabled
TC interrupt disabled
0
Enabled
TC interrupt enabled
1
HTIE
Half transfer interrupt
enable
3
1
HTIE
Disabled
HT interrupt disabled
0
Enabled
HT interrupt enabled
1
TEIE
Transfer error interrupt
enable
2
1
TEIE
Disabled
TE interrupt disabled
0
Enabled
TE interrupt enabled
1
DMEIE
Direct mode error interrupt
enable
1
1
DMEIE
Disabled
DME interrupt disabled
0
Enabled
DME interrupt enabled
1
EN
Stream enable / flag stream ready when
read low
0
1
EN
Disabled
Stream disabled
0
Enabled
Stream enabled
1
NDTR
S0NDTR
stream x number of data
register
0x4
0x20
read-write
0x00000000
NDT
Number of data items to
transfer
0
16
0
65535
PAR
S0PAR
stream x peripheral address
register
0x8
0x20
read-write
0x00000000
PA
Peripheral address
0
32
M0AR
S0M0AR
stream x memory 0 address
register
0xC
0x20
read-write
0x00000000
M0A
Memory 0 address
0
32
M1AR
S0M1AR
stream x memory 1 address
register
0x10
0x20
read-write
0x00000000
M1A
Memory 1 address (used in case of Double
buffer mode)
0
32
FCR
S0FCR
stream x FIFO control register
0x14
0x20
0x00000021
FEIE
FIFO error interrupt
enable
7
1
read-write
FEIE
Disabled
FE interrupt disabled
0
Enabled
FE interrupt enabled
1
FS
FIFO status
3
3
read-only
FS
Quarter1
0 < fifo_level < 1/4
0
Quarter2
1/4 <= fifo_level < 1/2
1
Quarter3
1/2 <= fifo_level < 3/4
2
Quarter4
3/4 <= fifo_level < full
3
Empty
FIFO is empty
4
Full
FIFO is full
5
DMDIS
Direct mode disable
2
1
read-write
DMDIS
Enabled
Direct mode is enabled
0
Disabled
Direct mode is disabled
1
FTH
FIFO threshold selection
0
2
read-write
FTH
Quarter
1/4 full FIFO
0
Half
1/2 full FIFO
1
ThreeQuarters
3/4 full FIFO
2
Full
Full FIFO
3
DMA1
0x40026000
DMA1_Stream0
DMA1 Stream0 global interrupt
11
DMA1_Stream0
DMA1 Stream0 global interrupt
11
DMA1_Stream1
DMA1 Stream1 global interrupt
12
DMA1_Stream1
DMA1 Stream1 global interrupt
12
DMA1_Stream2
DMA1 Stream2 global interrupt
13
DMA1_Stream2
DMA1 Stream2 global interrupt
13
DMA1_Stream3
DMA1 Stream3 global interrupt
14
DMA1_Stream3
DMA1 Stream3 global interrupt
14
DMA1_Stream4
DMA1 Stream4 global interrupt
15
DMA1_Stream4
DMA1 Stream4 global interrupt
15
DMA1_Stream5
DMA1 Stream5 global interrupt
16
DMA1_Stream5
DMA1 Stream5 global interrupt
16
DMA1_Stream6
DMA1 Stream6 global interrupt
17
DMA1_Stream6
DMA1 Stream6 global interrupt
17
DMA1_Stream7
DMA1 Stream7 global interrupt
47
DMA1_Stream7
DMA1 Stream7 global interrupt
47
RCC
Reset and clock control
RCC
0x40023800
0x0
0x400
registers
RCC
RCC global interrupt
5
RCC
RCC global interrupt
5
CR
CR
clock control register
0x0
0x20
0x00000083
HSIRDY
Internal high-speed clock ready
flag
1
1
read-only
HSIRDYR
NotReady
Clock not ready
0
Ready
Clock ready
1
PLLI2SRDY
PLLI2S clock ready flag
27
1
read-only
HSION
Internal high-speed clock
enable
0
1
read-write
HSION
Off
Clock Off
0
On
Clock On
1
PLLI2SON
PLLI2S enable
26
1
read-write
PLLRDY
Main PLL (PLL) clock ready
flag
25
1
read-only
PLLON
Main PLL (PLL) enable
24
1
read-write
CSSON
Clock security system
enable
19
1
read-write
CSSON
Off
Clock security system disabled (clock detector OFF)
0
On
Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
1
HSEBYP
HSE clock bypass
18
1
read-write
HSEBYP
NotBypassed
HSE crystal oscillator not bypassed
0
Bypassed
HSE crystal oscillator bypassed with external clock
1
HSERDY
HSE clock ready flag
17
1
read-only
HSEON
HSE clock enable
16
1
read-write
HSICAL
Internal high-speed clock
calibration
8
8
read-only
0
255
HSITRIM
Internal high-speed clock
trimming
3
5
read-write
0
31
PLLSAIRDY
PLLSAI clock ready flag
29
1
read-only
PLLSAION
PLLSAI enable
28
1
read-write
PLLCFGR
PLLCFGR
PLL configuration register
0x4
0x20
read-write
0x24003010
PLLSRC
Main PLL(PLL) and audio PLL (PLLI2S)
entry clock source
22
1
PLLSRC
HSI
HSI clock selected as PLL and PLLI2S clock entry
0
HSE
HSE oscillator clock selected as PLL and PLLI2S clock entry
1
PLLM
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
0
6
2
63
PLLN
Main PLL (PLL) multiplication factor for
VCO
6
9
50
432
PLLP
Main PLL (PLL) division factor for main
system clock
16
2
PLLP
Div2
PLLP=2
0
Div4
PLLP=4
1
Div6
PLLP=6
2
Div8
PLLP=8
3
PLLQ
Main PLL (PLL) division factor for USB
OTG FS, SDIO and random number generator
clocks
24
4
2
15
CFGR
CFGR
clock configuration register
0x8
0x20
0x00000000
MCO2
Microcontroller clock output
2
30
2
read-write
MCO2
SYSCLK
System clock (SYSCLK) selected
0
PLLI2S
PLLI2S clock selected
1
HSE
HSE oscillator clock selected
2
PLL
PLL clock selected
3
MCO1PRE
MCO1 prescaler
24
3
read-write
MCO1PRE
Div1
No division
0
Div2
Division by 2
4
Div3
Division by 3
5
Div4
Division by 4
6
Div5
Division by 5
7
MCO2PRE
MCO2 prescaler
27
3
read-write
I2SSRC
I2S clock selection
23
1
read-write
I2SSRC
PLLI2S
PLLI2S clock used as I2S clock source
0
CKIN
External clock mapped on the I2S_CKIN pin used as I2S clock source
1
MCO1
Microcontroller clock output
1
21
2
read-write
MCO1
HSI
HSI clock selected
0
LSE
LSE oscillator selected
1
HSE
HSE oscillator clock selected
2
PLL
PLL clock selected
3
RTCPRE
HSE division factor for RTC
clock
16
5
read-write
0
31
PPRE1
APB Low speed prescaler
(APB1)
10
3
read-write
PPRE1
Div1
HCLK not divided
0
Div2
HCLK divided by 2
4
Div4
HCLK divided by 4
5
Div8
HCLK divided by 8
6
Div16
HCLK divided by 16
7
PPRE2
APB high-speed prescaler
(APB2)
13
3
read-write
HPRE
AHB prescaler
4
4
read-write
HPRE
Div1
SYSCLK not divided
0
Div2
SYSCLK divided by 2
8
Div4
SYSCLK divided by 4
9
Div8
SYSCLK divided by 8
10
Div16
SYSCLK divided by 16
11
Div64
SYSCLK divided by 64
12
Div128
SYSCLK divided by 128
13
Div256
SYSCLK divided by 256
14
Div512
SYSCLK divided by 512
15
SW
System clock switch
0
2
SW
HSI
HSI selected as system clock
0
HSE
HSE selected as system clock
1
PLL
PLL selected as system clock
2
SWS
System clock switch status
2
2
SWSR
read
HSI
HSI oscillator used as system clock
0
HSE
HSE oscillator used as system clock
1
PLL
PLL used as system clock
2
CIR
CIR
clock interrupt register
0xC
0x20
0x00000000
CSSC
Clock security system interrupt
clear
23
1
write-only
CSSCW
Clear
Clear CSSF flag
1
LSIRDYC
LSI ready interrupt clear
16
1
write-only
LSIRDYCW
Clear
Clear interrupt flag
1
PLLI2SRDYC
PLLI2S ready interrupt
clear
21
1
write-only
PLLRDYC
Main PLL(PLL) ready interrupt
clear
20
1
write-only
HSERDYC
HSE ready interrupt clear
19
1
write-only
HSIRDYC
HSI ready interrupt clear
18
1
write-only
LSERDYC
LSE ready interrupt clear
17
1
write-only
LSIRDYIE
LSI ready interrupt enable
8
1
read-write
LSIRDYIE
Disabled
Interrupt disabled
0
Enabled
Interrupt enabled
1
PLLI2SRDYIE
PLLI2S ready interrupt
enable
13
1
read-write
PLLRDYIE
Main PLL (PLL) ready interrupt
enable
12
1
read-write
HSERDYIE
HSE ready interrupt enable
11
1
read-write
HSIRDYIE
HSI ready interrupt enable
10
1
read-write
LSERDYIE
LSE ready interrupt enable
9
1
read-write
CSSF
Clock security system interrupt
flag
7
1
read-only
CSSFR
NotInterrupted
No clock security interrupt caused by HSE clock failure
0
Interrupted
Clock security interrupt caused by HSE clock failure
1
LSIRDYF
LSI ready interrupt flag
0
1
read-only
LSIRDYFR
NotInterrupted
No clock ready interrupt
0
Interrupted
Clock ready interrupt
1
PLLI2SRDYF
PLLI2S ready interrupt
flag
5
1
read-only
PLLRDYF
Main PLL (PLL) ready interrupt
flag
4
1
read-only
HSERDYF
HSE ready interrupt flag
3
1
read-only
HSIRDYF
HSI ready interrupt flag
2
1
read-only
LSERDYF
LSE ready interrupt flag
1
1
read-only
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x10
0x20
read-write
0x00000000
GPIOARST
IO port A reset
0
1
GPIOARST
Reset
Reset the selected module
1
OTGHSRST
USB OTG HS module reset
29
1
ETHMACRST
Ethernet MAC reset
25
1
DMA2RST
DMA2 reset
22
1
DMA1RST
DMA2 reset
21
1
CRCRST
CRC reset
12
1
GPIOIRST
IO port I reset
8
1
GPIOHRST
IO port H reset
7
1
GPIOGRST
IO port G reset
6
1
GPIOFRST
IO port F reset
5
1
GPIOERST
IO port E reset
4
1
GPIODRST
IO port D reset
3
1
GPIOCRST
IO port C reset
2
1
GPIOBRST
IO port B reset
1
1
DMA2DRST
DMA2D reset
23
1
GPIOJRST
IO port J reset
9
1
GPIOKRST
IO port K reset
10
1
AHB2RSTR
AHB2RSTR
AHB2 peripheral reset register
0x14
0x20
read-write
0x00000000
DCMIRST
Camera interface reset
0
1
DCMIRST
Reset
Reset the selected module
1
OTGFSRST
USB OTG FS module reset
7
1
RNGRST
Random number generator module
reset
6
1
HSAHRST
Hash module reset
5
1
CRYPRST
Cryptographic module reset
4
1
AHB3RSTR
AHB3RSTR
AHB3 peripheral reset register
0x18
0x20
read-write
0x00000000
FMCRST
Flexible memory controller module
reset
0
1
FMCRST
Reset
Reset the selected module
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x20
0x20
read-write
0x00000000
TIM2RST
TIM2 reset
0
1
TIM2RST
Reset
Reset the selected module
1
TIM3RST
TIM3 reset
1
1
TIM4RST
TIM4 reset
2
1
TIM5RST
TIM5 reset
3
1
TIM6RST
TIM6 reset
4
1
TIM7RST
TIM7 reset
5
1
TIM12RST
TIM12 reset
6
1
TIM13RST
TIM13 reset
7
1
TIM14RST
TIM14 reset
8
1
WWDGRST
Window watchdog reset
11
1
SPI2RST
SPI 2 reset
14
1
SPI3RST
SPI 3 reset
15
1
USART2RST
USART 2 reset
17
1
USART3RST
USART 3 reset
18
1
UART4RST
USART 4 reset
19
1
UART5RST
USART 5 reset
20
1
I2C1RST
I2C 1 reset
21
1
I2C2RST
I2C 2 reset
22
1
I2C3RST
I2C3 reset
23
1
CAN1RST
CAN1 reset
25
1
CAN2RST
CAN2 reset
26
1
PWRRST
Power interface reset
28
1
DACRST
DAC reset
29
1
UART7RST
UART7 reset
30
1
UART8RST
UART8 reset
31
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x24
0x20
read-write
0x00000000
TIM1RST
TIM1 reset
0
1
TIM1RST
Reset
Reset the selected module
1
TIM8RST
TIM8 reset
1
1
USART1RST
USART1 reset
4
1
USART6RST
USART6 reset
5
1
ADCRST
ADC interface reset (common to all
ADCs)
8
1
SDIORST
SDIO reset
11
1
SPI1RST
SPI 1 reset
12
1
SYSCFGRST
System configuration controller
reset
14
1
TIM9RST
TIM9 reset
16
1
TIM10RST
TIM10 reset
17
1
TIM11RST
TIM11 reset
18
1
SPI6RST
SPI6 reset
21
1
SAI1RST
SAI1 reset
22
1
LTDCRST
LTDC reset
26
1
SPI4RST
SPI4 reset
13
1
SPI5RST
SPI5 reset
20
1
AHB1ENR
AHB1ENR
AHB1 peripheral clock register
0x30
0x20
read-write
0x00100000
GPIOAEN
IO port A clock enable
0
1
GPIOAEN
Disabled
The selected clock is disabled
0
Enabled
The selected clock is enabled
1
OTGHSULPIEN
USB OTG HSULPI clock
enable
30
1
OTGHSEN
USB OTG HS clock enable
29
1
ETHMACPTPEN
Ethernet PTP clock enable
28
1
ETHMACRXEN
Ethernet Reception clock
enable
27
1
ETHMACTXEN
Ethernet Transmission clock
enable
26
1
ETHMACEN
Ethernet MAC clock enable
25
1
DMA2EN
DMA2 clock enable
22
1
DMA1EN
DMA1 clock enable
21
1
CCMDATARAMEN
CCM data RAM clock enable
20
1
BKPSRAMEN
Backup SRAM interface clock
enable
18
1
CRCEN
CRC clock enable
12
1
GPIOIEN
IO port I clock enable
8
1
GPIOHEN
IO port H clock enable
7
1
GPIOGEN
IO port G clock enable
6
1
GPIOFEN
IO port F clock enable
5
1
GPIOEEN
IO port E clock enable
4
1
GPIODEN
IO port D clock enable
3
1
GPIOCEN
IO port C clock enable
2
1
GPIOBEN
IO port B clock enable
1
1
DMA2DEN
DMA2D clock enable
23
1
GPIOJEN
IO port J clock enable
9
1
GPIOKEN
IO port K clock enable
10
1
AHB2ENR
AHB2ENR
AHB2 peripheral clock enable
register
0x34
0x20
read-write
0x00000000
DCMIEN
Camera interface enable
0
1
DCMIEN
Disabled
The selected clock is disabled
0
Enabled
The selected clock is enabled
1
OTGFSEN
USB OTG FS clock enable
7
1
RNGEN
Random number generator clock
enable
6
1
HASHEN
Hash modules clock enable
5
1
CRYPEN
Cryptographic modules clock
enable
4
1
AHB3ENR
AHB3ENR
AHB3 peripheral clock enable
register
0x38
0x20
read-write
0x00000000
FMCEN
Flexible memory controller module clock
enable
0
1
FMCEN
Disabled
The selected clock is disabled
0
Enabled
The selected clock is enabled
1
APB1ENR
APB1ENR
APB1 peripheral clock enable
register
0x40
0x20
read-write
0x00000000
TIM2EN
TIM2 clock enable
0
1
TIM2EN
Disabled
The selected clock is disabled
0
Enabled
The selected clock is enabled
1
TIM3EN
TIM3 clock enable
1
1
TIM4EN
TIM4 clock enable
2
1
TIM5EN
TIM5 clock enable
3
1
TIM6EN
TIM6 clock enable
4
1
TIM7EN
TIM7 clock enable
5
1
TIM12EN
TIM12 clock enable
6
1
TIM13EN
TIM13 clock enable
7
1
TIM14EN
TIM14 clock enable
8
1
WWDGEN
Window watchdog clock
enable
11
1
SPI2EN
SPI2 clock enable
14
1
SPI3EN
SPI3 clock enable
15
1
USART2EN
USART 2 clock enable
17
1
USART3EN
USART3 clock enable
18
1
UART4EN
UART4 clock enable
19
1
UART5EN
UART5 clock enable
20
1
I2C1EN
I2C1 clock enable
21
1
I2C2EN
I2C2 clock enable
22
1
I2C3EN
I2C3 clock enable
23
1
CAN1EN
CAN 1 clock enable
25
1
CAN2EN
CAN 2 clock enable
26
1
PWREN
Power interface clock
enable
28
1
DACEN
DAC interface clock enable
29
1
UART7EN
UART7 clock enable
30
1
UART8EN
UART8 clock enable
31
1
APB2ENR
APB2ENR
APB2 peripheral clock enable
register
0x44
0x20
read-write
0x00000000
TIM1EN
TIM1 clock enable
0
1
TIM1EN
Disabled
The selected clock is disabled
0
Enabled
The selected clock is enabled
1
TIM8EN
TIM8 clock enable
1
1
USART1EN
USART1 clock enable
4
1
USART6EN
USART6 clock enable
5
1
ADC1EN
ADC1 clock enable
8
1
ADC2EN
ADC2 clock enable
9
1
ADC3EN
ADC3 clock enable
10
1
SDIOEN
SDIO clock enable
11
1
SPI1EN
SPI1 clock enable
12
1
SYSCFGEN
System configuration controller clock
enable
14
1
TIM9EN
TIM9 clock enable
16
1
TIM10EN
TIM10 clock enable
17
1
TIM11EN
TIM11 clock enable
18
1
SPI6EN
SPI6 clock enable
21
1
SAI1EN
SAI1 clock enable
22
1
LTDCEN
LTDC clock enable
26
1
SPI4EN
SPI4 clock enable
13
1
SPI5EN
SPI5 clock enable
20
1
AHB1LPENR
AHB1LPENR
AHB1 peripheral clock enable in low power
mode register
0x50
0x20
read-write
0x7E6791FF
GPIOALPEN
IO port A clock enable during sleep
mode
0
1
GPIOALPEN
DisabledInSleep
Selected module is disabled during Sleep mode
0
EnabledInSleep
Selected module is enabled during Sleep mode
1
GPIOBLPEN
IO port B clock enable during Sleep
mode
1
1
GPIOCLPEN
IO port C clock enable during Sleep
mode
2
1
GPIODLPEN
IO port D clock enable during Sleep
mode
3
1
GPIOELPEN
IO port E clock enable during Sleep
mode
4
1
GPIOFLPEN
IO port F clock enable during Sleep
mode
5
1
GPIOGLPEN
IO port G clock enable during Sleep
mode
6
1
GPIOHLPEN
IO port H clock enable during Sleep
mode
7
1
GPIOILPEN
IO port I clock enable during Sleep
mode
8
1
CRCLPEN
CRC clock enable during Sleep
mode
12
1
FLITFLPEN
Flash interface clock enable during
Sleep mode
15
1
SRAM1LPEN
SRAM 1interface clock enable during
Sleep mode
16
1
SRAM2LPEN
SRAM 2 interface clock enable during
Sleep mode
17
1
BKPSRAMLPEN
Backup SRAM interface clock enable
during Sleep mode
18
1
DMA1LPEN
DMA1 clock enable during Sleep
mode
21
1
DMA2LPEN
DMA2 clock enable during Sleep
mode
22
1
ETHMACLPEN
Ethernet MAC clock enable during Sleep
mode
25
1
ETHMACTXLPEN
Ethernet transmission clock enable
during Sleep mode
26
1
ETHMACRXLPEN
Ethernet reception clock enable during
Sleep mode
27
1
ETHMACPTPLPEN
Ethernet PTP clock enable during Sleep
mode
28
1
OTGHSLPEN
USB OTG HS clock enable during Sleep
mode
29
1
OTGHSULPILPEN
USB OTG HS ULPI clock enable during
Sleep mode
30
1
SRAM3LPEN
SRAM3 interface clock enable during Sleep mode
19
1
DMA2DLPEN
DMA2D clock enable during Sleep mode
23
1
GPIOJLPEN
IO port J clock enable during Sleep mode
9
1
GPIOKLPEN
IO port K clock enable during Sleep mode
10
1
AHB2LPENR
AHB2LPENR
AHB2 peripheral clock enable in low power
mode register
0x54
0x20
read-write
0x000000F1
DCMILPEN
Camera interface enable during Sleep
mode
0
1
DCMILPEN
DisabledInSleep
Selected module is disabled during Sleep mode
0
EnabledInSleep
Selected module is enabled during Sleep mode
1
OTGFSLPEN
USB OTG FS clock enable during Sleep
mode
7
1
RNGLPEN
Random number generator clock enable
during Sleep mode
6
1
HASHLPEN
Hash modules clock enable during Sleep
mode
5
1
CRYPLPEN
Cryptography modules clock enable during
Sleep mode
4
1
AHB3LPENR
AHB3LPENR
AHB3 peripheral clock enable in low power
mode register
0x58
0x20
read-write
0x00000001
FMCLPEN
Flexible memory controller module clock
enable during Sleep mode
0
1
FMCLPEN
DisabledInSleep
Selected module is disabled during Sleep mode
0
EnabledInSleep
Selected module is enabled during Sleep mode
1
APB1LPENR
APB1LPENR
APB1 peripheral clock enable in low power
mode register
0x60
0x20
read-write
0x36FEC9FF
TIM2LPEN
TIM2 clock enable during Sleep
mode
0
1
TIM2LPEN
DisabledInSleep
Selected module is disabled during Sleep mode
0
EnabledInSleep
Selected module is enabled during Sleep mode
1
TIM3LPEN
TIM3 clock enable during Sleep
mode
1
1
TIM4LPEN
TIM4 clock enable during Sleep
mode
2
1
TIM5LPEN
TIM5 clock enable during Sleep
mode
3
1
TIM6LPEN
TIM6 clock enable during Sleep
mode
4
1
TIM7LPEN
TIM7 clock enable during Sleep
mode
5
1
TIM12LPEN
TIM12 clock enable during Sleep
mode
6
1
TIM13LPEN
TIM13 clock enable during Sleep
mode
7
1
TIM14LPEN
TIM14 clock enable during Sleep
mode
8
1
WWDGLPEN
Window watchdog clock enable during
Sleep mode
11
1
SPI2LPEN
SPI2 clock enable during Sleep
mode
14
1
SPI3LPEN
SPI3 clock enable during Sleep
mode
15
1
USART2LPEN
USART2 clock enable during Sleep
mode
17
1
USART3LPEN
USART3 clock enable during Sleep
mode
18
1
UART4LPEN
UART4 clock enable during Sleep
mode
19
1
UART5LPEN
UART5 clock enable during Sleep
mode
20
1
I2C1LPEN
I2C1 clock enable during Sleep
mode
21
1
I2C2LPEN
I2C2 clock enable during Sleep
mode
22
1
I2C3LPEN
I2C3 clock enable during Sleep
mode
23
1
CAN1LPEN
CAN 1 clock enable during Sleep
mode
25
1
CAN2LPEN
CAN 2 clock enable during Sleep
mode
26
1
PWRLPEN
Power interface clock enable during
Sleep mode
28
1
DACLPEN
DAC interface clock enable during Sleep
mode
29
1
UART7LPEN
UART7 clock enable during Sleep mode
30
1
UART8LPEN
UART8 clock enable during Sleep mode
31
1
APB2LPENR
APB2LPENR
APB2 peripheral clock enabled in low power
mode register
0x64
0x20
read-write
0x00075F33
TIM1LPEN
TIM1 clock enable during Sleep
mode
0
1
TIM1LPEN
DisabledInSleep
Selected module is disabled during Sleep mode
0
EnabledInSleep
Selected module is enabled during Sleep mode
1
TIM8LPEN
TIM8 clock enable during Sleep
mode
1
1
USART1LPEN
USART1 clock enable during Sleep
mode
4
1
USART6LPEN
USART6 clock enable during Sleep
mode
5
1
ADC1LPEN
ADC1 clock enable during Sleep
mode
8
1
ADC2LPEN
ADC2 clock enable during Sleep
mode
9
1
ADC3LPEN
ADC 3 clock enable during Sleep
mode
10
1
SDIOLPEN
SDIO clock enable during Sleep
mode
11
1
SPI1LPEN
SPI 1 clock enable during Sleep
mode
12
1
SYSCFGLPEN
System configuration controller clock
enable during Sleep mode
14
1
TIM9LPEN
TIM9 clock enable during sleep
mode
16
1
TIM10LPEN
TIM10 clock enable during Sleep
mode
17
1
TIM11LPEN
TIM11 clock enable during Sleep
mode
18
1
SPI6LPEN
SPI6 clock enable during Sleep mode
21
1
SAI1LPEN
SAI1 clock enable during Sleep mode
22
1
LTDCLPEN
LTDC clock enable during Sleep mode
26
1
SPI4LPEN
SPI4 clock enable during Sleep mode
13
1
SPI5LPEN
SPI5 clock enable during Sleep mode
20
1
BDCR
BDCR
Backup domain control register
0x70
0x20
0x00000000
BDRST
Backup domain software
reset
16
1
read-write
BDRST
Disabled
Reset not activated
0
Enabled
Reset the entire RTC domain
1
RTCEN
RTC clock enable
15
1
read-write
RTCEN
Disabled
RTC clock disabled
0
Enabled
RTC clock enabled
1
LSEBYP
External low-speed oscillator
bypass
2
1
read-write
LSEBYP
NotBypassed
LSE crystal oscillator not bypassed
0
Bypassed
LSE crystal oscillator bypassed with external clock
1
LSERDY
External low-speed oscillator
ready
1
1
read-only
LSERDYR
NotReady
LSE oscillator not ready
0
Ready
LSE oscillator ready
1
LSEON
External low-speed oscillator
enable
0
1
read-write
LSEON
Off
LSE oscillator Off
0
On
LSE oscillator On
1
RTCSEL
RTC clock source selection
8
2
RTCSEL
NoClock
No clock
0
LSE
LSE oscillator clock used as RTC clock
1
LSI
LSI oscillator clock used as RTC clock
2
HSE
HSE oscillator clock divided by a prescaler used as RTC clock
3
CSR
CSR
clock control & status
register
0x74
0x20
0x0E000000
BORRSTF
BOR reset flag
25
1
read-write
BORRSTFR
read
NoReset
No reset has occured
0
Reset
A reset has occured
1
LPWRRSTF
Low-power reset flag
31
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
WDGRSTF
Independent watchdog reset
flag
29
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
PADRSTF
PIN reset flag
26
1
read-write
RMVF
Remove reset flag
24
1
read-write
RMVFW
write
Clear
Clears the reset flag
1
LSIRDY
Internal low-speed oscillator
ready
1
1
read-only
LSIRDYR
NotReady
LSI oscillator not ready
0
Ready
LSI oscillator ready
1
LSION
Internal low-speed oscillator
enable
0
1
read-write
LSION
Off
LSI oscillator Off
0
On
LSI oscillator On
1
SSCGR
SSCGR
spread spectrum clock generation
register
0x80
0x20
read-write
0x00000000
SSCGEN
Spread spectrum modulation
enable
31
1
SSCGEN
Disabled
Spread spectrum modulation disabled
0
Enabled
Spread spectrum modulation enabled
1
SPREADSEL
Spread Select
30
1
SPREADSEL
Center
Center spread
0
Down
Down spread
1
INCSTEP
Incrementation step
13
15
0
32767
MODPER
Modulation period
0
13
0
8191
PLLI2SCFGR
PLLI2SCFGR
PLLI2S configuration register
0x84
0x20
read-write
0x20003000
PLLI2SR
PLLI2S division factor for I2S
clocks
28
3
2
7
PLLI2SQ
PLLI2S division factor for SAI1
clock
24
4
2
15
PLLI2SN
PLLI2S multiplication factor for
VCO
6
9
50
432
DCKCFGR
DCKCFGR
RCC Dedicated Clock Configuration
Register
0x8C
0x20
read-write
0x00000000
PLLI2SDIVQ
PLLI2S division factor for SAI1
clock
0
5
PLLI2SDIVQ
Div1
PLLI2SDIVQ = /1
0
Div2
PLLI2SDIVQ = /2
1
Div3
PLLI2SDIVQ = /3
2
Div4
PLLI2SDIVQ = /4
3
Div5
PLLI2SDIVQ = /5
4
Div6
PLLI2SDIVQ = /6
5
Div7
PLLI2SDIVQ = /7
6
Div8
PLLI2SDIVQ = /8
7
Div9
PLLI2SDIVQ = /9
8
Div10
PLLI2SDIVQ = /10
9
Div11
PLLI2SDIVQ = /11
10
Div12
PLLI2SDIVQ = /12
11
Div13
PLLI2SDIVQ = /13
12
Div14
PLLI2SDIVQ = /14
13
Div15
PLLI2SDIVQ = /15
14
Div16
PLLI2SDIVQ = /16
15
Div17
PLLI2SDIVQ = /17
16
Div18
PLLI2SDIVQ = /18
17
Div19
PLLI2SDIVQ = /19
18
Div20
PLLI2SDIVQ = /20
19
Div21
PLLI2SDIVQ = /21
20
Div22
PLLI2SDIVQ = /22
21
Div23
PLLI2SDIVQ = /23
22
Div24
PLLI2SDIVQ = /24
23
Div25
PLLI2SDIVQ = /25
24
Div26
PLLI2SDIVQ = /26
25
Div27
PLLI2SDIVQ = /27
26
Div28
PLLI2SDIVQ = /28
27
Div29
PLLI2SDIVQ = /29
28
Div30
PLLI2SDIVQ = /30
29
Div31
PLLI2SDIVQ = /31
30
Div32
PLLI2SDIVQ = /32
31
PLLSAIDIVQ
PLLSAI division factor for SAI1
clock
8
5
PLLSAIDIVQ
Div1
PLLSAIDIVQ = /1
0
Div2
PLLSAIDIVQ = /2
1
Div3
PLLSAIDIVQ = /3
2
Div4
PLLSAIDIVQ = /4
3
Div5
PLLSAIDIVQ = /5
4
Div6
PLLSAIDIVQ = /6
5
Div7
PLLSAIDIVQ = /7
6
Div8
PLLSAIDIVQ = /8
7
Div9
PLLSAIDIVQ = /9
8
Div10
PLLSAIDIVQ = /10
9
Div11
PLLSAIDIVQ = /11
10
Div12
PLLSAIDIVQ = /12
11
Div13
PLLSAIDIVQ = /13
12
Div14
PLLSAIDIVQ = /14
13
Div15
PLLSAIDIVQ = /15
14
Div16
PLLSAIDIVQ = /16
15
Div17
PLLSAIDIVQ = /17
16
Div18
PLLSAIDIVQ = /18
17
Div19
PLLSAIDIVQ = /19
18
Div20
PLLSAIDIVQ = /20
19
Div21
PLLSAIDIVQ = /21
20
Div22
PLLSAIDIVQ = /22
21
Div23
PLLSAIDIVQ = /23
22
Div24
PLLSAIDIVQ = /24
23
Div25
PLLSAIDIVQ = /25
24
Div26
PLLSAIDIVQ = /26
25
Div27
PLLSAIDIVQ = /27
26
Div28
PLLSAIDIVQ = /28
27
Div29
PLLSAIDIVQ = /29
28
Div30
PLLSAIDIVQ = /30
29
Div31
PLLSAIDIVQ = /31
30
Div32
PLLSAIDIVQ = /32
31
PLLSAIDIVR
division factor for
LCD_CLK
16
2
PLLSAIDIVR
Div2
PLLSAIDIVR = /2
0
Div4
PLLSAIDIVR = /4
1
Div8
PLLSAIDIVR = /8
2
Div16
PLLSAIDIVR = /16
3
SAI1ASRC
SAI1-A clock source
selection
20
2
SAI1ASRC
PLLSAI
SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
0
PLLI2S
SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
1
I2S_CKIN
SAI1-A clock frequency = Alternate function input frequency
2
SAI1BSRC
SAI1-B clock source
selection
22
2
SAI1BSRC
PLLSAI
SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
0
PLLI2S
SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
1
I2S_CKIN
SAI1-B clock frequency = Alternate function input frequency
2
TIMPRE
Timers clocks prescalers
selection
24
1
TIMPRE
Mul1Or2
If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx
0
Mul1Or4
If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx
1
PLLSAICFGR
PLLSAICFGR
RCC PLL configuration register
0x88
0x20
read-write
0x24003000
PLLSAIR
PLLSAI division factor for LCD
clock
28
3
2
7
PLLSAIQ
PLLSAI division factor for SAI1
clock
24
4
2
15
PLLSAIN
PLLSAI division factor for
VCO
6
9
50
432
GPIOK
General-purpose I/Os
GPIO
0x40022800
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0x00000000
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x00000000
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x00000000
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
GPIO alternate function low
register
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
GPIOJ
0x40022400
GPIOI
0x40022000
GPIOH
0x40021C00
GPIOG
0x40021800
GPIOF
0x40021400
GPIOE
0x40021000
GPIOD
0x40020C00
GPIOC
0x40020800
GPIOB
General-purpose I/Os
GPIO
0x40020400
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0x00000280
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x000000C0
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x00000100
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
GPIO alternate function low
register
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
GPIOA
General-purpose I/Os
GPIO
0x40020000
0x0
0x400
registers
MODER
MODER
GPIO port mode register
0x0
0x20
read-write
0xA8000000
16
0x2
0-15
MODER%s
Port x configuration pin %s
0
2
MODER0
Input
Input mode (reset state)
0
Output
General purpose output mode
1
Alternate
Alternate function mode
2
Analog
Analog mode
3
OTYPER
OTYPER
GPIO port output type register
0x4
0x20
read-write
0x00000000
16
0x1
0-15
OT%s
Port x configuration pin %s
0
1
OT0
PushPull
Output push-pull (reset state)
0
OpenDrain
Output open-drain
1
OSPEEDR
OSPEEDR
GPIO port output speed
register
0x8
0x20
read-write
0x00000000
16
0x2
0-15
OSPEEDR%s
Port x configuration pin %s
0
2
OSPEEDR0
LowSpeed
Low speed
0
MediumSpeed
Medium speed
1
HighSpeed
High speed
2
VeryHighSpeed
Very high speed
3
PUPDR
PUPDR
GPIO port pull-up/pull-down
register
0xC
0x20
read-write
0x64000000
16
0x2
0-15
PUPDR%s
Port x configuration pin %s
0
2
PUPDR0
Floating
No pull-up, pull-down
0
PullUp
Pull-up
1
PullDown
Pull-down
2
IDR
IDR
GPIO port input data register
0x10
0x20
read-only
0x00000000
16
0x1
0-15
IDR%s
Port input data pin %s
0
1
IDR0
Low
Input is logic low
0
High
Input is logic high
1
ODR
ODR
GPIO port output data register
0x14
0x20
read-write
0x00000000
16
0x1
0-15
ODR%s
Port output data pin %s
0
1
ODR0
Low
Set output to logic low
0
High
Set output to logic high
1
BSRR
BSRR
GPIO port bit set/reset
register
0x18
0x20
write-only
0x00000000
16
0x1
0-15
BR%s
Port x reset pin %s
16
1
BR0W
Reset
Resets the corresponding ODRx bit
1
16
0x1
0-15
BS%s
Port x set pin %s
0
1
BS0W
Set
Sets the corresponding ODRx bit
1
LCKR
LCKR
GPIO port configuration lock
register
0x1C
0x20
read-write
0x00000000
LCKK
Port x lock bit y (y=
0..15)
16
1
LCKK
NotActive
Port configuration lock key not active
0
Active
Port configuration lock key active
1
16
0x1
0-15
LCK%s
Port x lock pin %s
0
1
LCK0
Unlocked
Port configuration not locked
0
Locked
Port configuration locked
1
AFRL
AFRL
GPIO alternate function low
register
0x20
0x20
read-write
0x00000000
8
0x4
L0,L1,L2,L3,L4,L5,L6,L7
AFR%s
Alternate function selection for port x
bit y (y = 0..7)
0
4
AFRL0
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
AFRH
AFRH
GPIO alternate function high
register
0x24
0x20
read-write
0x00000000
8
0x4
H8,H9,H10,H11,H12,H13,H14,H15
AFR%s
Alternate function selection for port x
bit y (y = 8..15)
0
4
AFRH8
AF0
AF0
0
AF1
AF1
1
AF2
AF2
2
AF3
AF3
3
AF4
AF4
4
AF5
AF5
5
AF6
AF6
6
AF7
AF7
7
AF8
AF8
8
AF9
AF9
9
AF10
AF10
10
AF11
AF11
11
AF12
AF12
12
AF13
AF13
13
AF14
AF14
14
AF15
AF15
15
SYSCFG
System configuration controller
SYSCFG
0x40013800
0x0
0x400
registers
MEMRM
MEMRM
memory remap register
0x0
0x20
read-write
0x00000000
MEM_MODE
Memory mapping selection
0
3
FB_MODE
Flash bank mode selection
8
1
SWP_FMC
FMC memory mapping swap
10
2
PMC
PMC
peripheral mode configuration
register
0x4
0x20
read-write
0x00000000
MII_RMII_SEL
Ethernet PHY interface
selection
23
1
ADC1DC2
ADC1DC2
16
1
ADC2DC2
ADC2DC2
17
1
ADC3DC2
ADC3DC2
18
1
EXTICR1
EXTICR1
external interrupt configuration register
1
0x8
0x20
read-write
0x00000000
EXTI3
EXTI x configuration (x = 0 to
3)
12
4
EXTI2
EXTI x configuration (x = 0 to
3)
8
4
EXTI1
EXTI x configuration (x = 0 to
3)
4
4
EXTI0
EXTI x configuration (x = 0 to
3)
0
4
EXTICR2
EXTICR2
external interrupt configuration register
2
0xC
0x20
read-write
0x00000000
EXTI7
EXTI x configuration (x = 4 to
7)
12
4
EXTI6
EXTI x configuration (x = 4 to
7)
8
4
EXTI5
EXTI x configuration (x = 4 to
7)
4
4
EXTI4
EXTI x configuration (x = 4 to
7)
0
4
EXTICR3
EXTICR3
external interrupt configuration register
3
0x10
0x20
read-write
0x00000000
EXTI11
EXTI x configuration (x = 8 to
11)
12
4
EXTI10
EXTI10
8
4
EXTI9
EXTI x configuration (x = 8 to
11)
4
4
EXTI8
EXTI x configuration (x = 8 to
11)
0
4
EXTICR4
EXTICR4
external interrupt configuration register
4
0x14
0x20
read-write
0x00000000
EXTI15
EXTI x configuration (x = 12 to
15)
12
4
EXTI14
EXTI x configuration (x = 12 to
15)
8
4
EXTI13
EXTI x configuration (x = 12 to
15)
4
4
EXTI12
EXTI x configuration (x = 12 to
15)
0
4
CMPCR
CMPCR
Compensation cell control
register
0x20
0x20
read-only
0x00000000
READY
READY
8
1
CMP_PD
Compensation cell
power-down
0
1
SPI1
Serial peripheral interface
SPI
0x40013000
0x0
0x400
registers
SPI1
SPI1 global interrupt
35
SPI1
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
BIDIMODE
Bidirectional data mode
enable
15
1
BIDIMODE
Unidirectional
2-line unidirectional data mode selected
0
Bidirectional
1-line bidirectional data mode selected
1
BIDIOE
Output enable in bidirectional
mode
14
1
BIDIOE
OutputDisabled
Output disabled (receive-only mode)
0
OutputEnabled
Output enabled (transmit-only mode)
1
CRCEN
Hardware CRC calculation
enable
13
1
CRCEN
Disabled
CRC calculation disabled
0
Enabled
CRC calculation enabled
1
CRCNEXT
CRC transfer next
12
1
CRCNEXT
TxBuffer
Next transmit value is from Tx buffer
0
CRC
Next transmit value is from Tx CRC register
1
DFF
Data frame format
11
1
DFF
EightBit
8-bit data frame format is selected for transmission/reception
0
SixteenBit
16-bit data frame format is selected for transmission/reception
1
RXONLY
Receive only
10
1
RXONLY
FullDuplex
Full duplex (Transmit and receive)
0
OutputDisabled
Output disabled (Receive-only mode)
1
SSM
Software slave management
9
1
SSM
Disabled
Software slave management disabled
0
Enabled
Software slave management enabled
1
SSI
Internal slave select
8
1
SSI
SlaveSelected
0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
0
SlaveNotSelected
1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1
LSBFIRST
Frame format
7
1
LSBFIRST
MSBFirst
Data is transmitted/received with the MSB first
0
LSBFirst
Data is transmitted/received with the LSB first
1
SPE
SPI enable
6
1
SPE
Disabled
Peripheral disabled
0
Enabled
Peripheral enabled
1
BR
Baud rate control
3
3
BR
Div2
f_PCLK / 2
0
Div4
f_PCLK / 4
1
Div8
f_PCLK / 8
2
Div16
f_PCLK / 16
3
Div32
f_PCLK / 32
4
Div64
f_PCLK / 64
5
Div128
f_PCLK / 128
6
Div256
f_PCLK / 256
7
MSTR
Master selection
2
1
MSTR
Slave
Slave configuration
0
Master
Master configuration
1
CPOL
Clock polarity
1
1
CPOL
IdleLow
CK to 0 when idle
0
IdleHigh
CK to 1 when idle
1
CPHA
Clock phase
0
1
CPHA
FirstEdge
The first clock transition is the first data capture edge
0
SecondEdge
The second clock transition is the first data capture edge
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TXEIE
Tx buffer empty interrupt
enable
7
1
TXEIE
Masked
TXE interrupt masked
0
NotMasked
TXE interrupt not masked
1
RXNEIE
RX buffer not empty interrupt
enable
6
1
RXNEIE
Masked
RXE interrupt masked
0
NotMasked
RXE interrupt not masked
1
ERRIE
Error interrupt enable
5
1
ERRIE
Masked
Error interrupt masked
0
NotMasked
Error interrupt not masked
1
FRF
Frame format
4
1
FRF
Motorola
SPI Motorola mode
0
TI
SPI TI mode
1
SSOE
SS output enable
2
1
SSOE
Disabled
SS output is disabled in master mode
0
Enabled
SS output is enabled in master mode
1
TXDMAEN
Tx buffer DMA enable
1
1
TXDMAEN
Disabled
Tx buffer DMA disabled
0
Enabled
Tx buffer DMA enabled
1
RXDMAEN
Rx buffer DMA enable
0
1
RXDMAEN
Disabled
Rx buffer DMA disabled
0
Enabled
Rx buffer DMA enabled
1
SR
SR
status register
0x8
0x20
0x00000002
FRE
TI frame format error
8
1
read-only
FRER
NoError
No frame format error
0
Error
A frame format error occurred
1
BSY
Busy flag
7
1
read-only
BSYR
NotBusy
SPI not busy
0
Busy
SPI busy
1
OVR
Overrun flag
6
1
read-only
OVRR
NoOverrun
No overrun occurred
0
Overrun
Overrun occurred
1
MODF
Mode fault
5
1
read-only
MODFR
NoFault
No mode fault occurred
0
Fault
Mode fault occurred
1
CRCERR
CRC error flag
4
1
read-write
zeroToClear
CRCERRR
read
Match
CRC value received matches the SPIx_RXCRCR value
0
NoMatch
CRC value received does not match the SPIx_RXCRCR value
1
CRCERRW
write
Clear
Clear flag
0
UDR
Underrun flag
3
1
read-only
UDRR
NoUnderrun
No underrun occurred
0
Underrun
Underrun occurred
1
CHSIDE
Channel side
2
1
read-only
CHSIDE
Left
Channel left has to be transmitted or has been received
0
Right
Channel right has to be transmitted or has been received
1
TXE
Transmit buffer empty
1
1
read-only
TXE
NotEmpty
Tx buffer not empty
0
Empty
Tx buffer empty
1
RXNE
Receive buffer not empty
0
1
read-only
RXNE
Empty
Rx buffer empty
0
NotEmpty
Rx buffer not empty
1
DR
DR
data register
0xC
0x20
read-write
0x00000000
DR
Data register
0
16
0
65535
CRCPR
CRCPR
CRC polynomial register
0x10
0x20
read-write
0x00000007
CRCPOLY
CRC polynomial register
0
16
0
65535
RXCRCR
RXCRCR
RX CRC register
0x14
0x20
read-only
0x00000000
RxCRC
Rx CRC register
0
16
0
65535
TXCRCR
TXCRCR
TX CRC register
0x18
0x20
read-only
0x00000000
TxCRC
Tx CRC register
0
16
0
65535
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
0x20
read-write
0x00000000
I2SMOD
I2S mode selection
11
1
I2SMOD
SPIMode
SPI mode is selected
0
I2SMode
I2S mode is selected
1
I2SE
I2S Enable
10
1
I2SE
Disabled
I2S peripheral is disabled
0
Enabled
I2S peripheral is enabled
1
I2SCFG
I2S configuration mode
8
2
I2SCFG
SlaveTx
Slave - transmit
0
SlaveRx
Slave - receive
1
MasterTx
Master - transmit
2
MasterRx
Master - receive
3
PCMSYNC
PCM frame synchronization
7
1
PCMSYNC
Short
Short frame synchronisation
0
Long
Long frame synchronisation
1
I2SSTD
I2S standard selection
4
2
I2SSTD
Philips
I2S Philips standard
0
MSB
MSB justified standard
1
LSB
LSB justified standard
2
PCM
PCM standard
3
CKPOL
Steady state clock
polarity
3
1
CKPOL
IdleLow
I2S clock inactive state is low level
0
IdleHigh
I2S clock inactive state is high level
1
DATLEN
Data length to be
transferred
1
2
DATLEN
SixteenBit
16-bit data length
0
TwentyFourBit
24-bit data length
1
ThirtyTwoBit
32-bit data length
2
CHLEN
Channel length (number of bits per audio
channel)
0
1
CHLEN
SixteenBit
16-bit wide
0
ThirtyTwoBit
32-bit wide
1
I2SPR
I2SPR
I2S prescaler register
0x20
0x20
read-write
0x0000000A
MCKOE
Master clock output enable
9
1
MCKOE
Disabled
Master clock output is disabled
0
Enabled
Master clock output is enabled
1
ODD
Odd factor for the
prescaler
8
1
ODD
Even
Real divider value is I2SDIV * 2
0
Odd
Real divider value is (I2SDIV * 2) + 1
1
I2SDIV
I2S Linear prescaler
0
8
2
255
SPI2
0x40003800
SPI2
SPI2 global interrupt
36
SPI2
SPI2 global interrupt
36
SPI3
0x40003C00
SPI3
SPI3 global interrupt
51
SPI3
SPI3 global interrupt
51
I2S2ext
0x40003400
I2S3ext
0x40004000
SPI4
0x40013400
SPI4
SPI 4 global interrupt
84
SPI4
SPI 4 global interrupt
84
SPI5
0x40015000
SPI5
SPI 5 global interrupt
85
SPI5
SPI 5 global interrupt
85
SPI6
0x40015400
SPI6
SPI 6 global interrupt
86
SPI6
SPI 6 global interrupt
86
SDIO
Secure digital input/output
interface
SDIO
0x40012C00
0x0
0x400
registers
SDIO
SDIO global interrupt
49
SDIO
SDIO global interrupt
49
POWER
POWER
power control register
0x0
0x20
read-write
0x00000000
PWRCTRL
PWRCTRL
0
2
PWRCTRL
PowerOff
Power off
0
PowerOn
Power on
3
CLKCR
CLKCR
SDI clock control register
0x4
0x20
read-write
0x00000000
HWFC_EN
HW Flow Control enable
14
1
HWFC_EN
Disabled
HW Flow Control is disabled
0
Enabled
HW Flow Control is enabled
1
NEGEDGE
SDIO_CK dephasing selection
bit
13
1
NEGEDGE
Rising
SDIO_CK generated on the rising edge
0
Falling
SDIO_CK generated on the falling edge
1
WIDBUS
Wide bus mode enable bit
11
2
WIDBUS
BusWidth1
1 lane wide bus
0
BusWidth4
4 lane wide bus
1
BusWidth8
8 lane wide bus
2
BYPASS
Clock divider bypass enable
bit
10
1
BYPASS
Disabled
SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal.
0
Enabled
SDIOCLK directly drives the SDIO_CK output signal
1
PWRSAV
Power saving configuration
bit
9
1
PWRSAV
Enabled
SDIO_CK clock is always enabled
0
Disabled
SDIO_CK is only enabled when the bus is active
1
CLKEN
Clock enable bit
8
1
CLKEN
Disabled
Disable clock
0
Enabled
Enable clock
1
CLKDIV
Clock divide factor
0
8
0
255
ARG
ARG
argument register
0x8
0x20
read-write
0x00000000
CMDARG
Command argument
0
32
0
4294967295
CMD
CMD
command register
0xC
0x20
read-write
0x00000000
CE_ATACMD
CE-ATA command
14
1
CE_ATACMD
Disabled
CE-ATA command disabled
0
Enabled
CE-ATA command enabled
1
nIEN
not Interrupt Enable
13
1
nIEN
Disabled
Interrupts to the CE-ATA not disabled
0
Enabled
Interrupt to the CE-ATA are disabled
1
ENCMDcompl
Enable CMD completion
12
1
ENCMDcompl
Disabled
Command complete signal disabled
0
Enabled
Command complete signal enabled
1
SDIOSuspend
SD I/O suspend command
11
1
SDIOSuspend
Disabled
Next command is not a SDIO suspend command
0
Enabled
Next command send is a SDIO suspend command
1
CPSMEN
Command path state machine (CPSM) Enable
bit
10
1
CPSMEN
Disabled
Command path state machine disabled
0
Enabled
Command path state machine enabled
1
WAITPEND
CPSM Waits for ends of data transfer
(CmdPend internal signal).
9
1
WAITPEND
Disabled
Don't wait for data end
0
Enabled
Wait for end of data transfer signal before sending command
1
WAITINT
CPSM waits for interrupt
request
8
1
WAITINT
Disabled
Don't wait for interrupt request
0
Enabled
Wait for interrupt request
1
WAITRESP
Wait for response bits
6
2
WAITRESP
NoResponse
No response
0
ShortResponse
Short response
1
NoResponse2
No reponse
2
LongResponse
Long reponse
3
CMDINDEX
Command index
0
6
0
63
RESPCMD
RESPCMD
command response register
0x10
0x20
read-only
0x00000000
RESPCMD
Response command index
0
6
0
63
4
0x4
1-4
RESP%s
RESP%s
SDIO response %s register
0x14
0x20
read-only
0x00000000
CARDSTATUS
Status of a card, which is part of the received response
0
32
0
4294967295
DTIMER
DTIMER
data timer register
0x24
0x20
read-write
0x00000000
DATATIME
Data timeout period
0
32
0
4294967295
DLEN
DLEN
data length register
0x28
0x20
read-write
0x00000000
DATALENGTH
Data length value
0
25
0
33554431
DCTRL
DCTRL
data control register
0x2C
0x20
read-write
0x00000000
SDIOEN
SD I/O enable functions
11
1
SDIOEN
Disabled
SDIO operations disabled
0
Enabled
SDIO operations enabled
1
RWMOD
Read wait mode
10
1
RWMOD
D2
Read wait control stopping using SDIO_D2
0
Ck
Read wait control using SDIO_CK
1
RWSTOP
Read wait stop
9
1
RWSTOP
Disabled
Read wait in progress if RWSTART is enabled
0
Enabled
Enable for read wait stop if RWSTART is enabled
1
RWSTART
Read wait start
8
1
RWSTART
Disabled
Don't start read wait operation
0
Enabled
Read wait operation starts
1
DBLOCKSIZE
Data block size
4
4
0
15
DMAEN
DMA enable bit
3
1
DMAEN
Disabled
Dma disabled
0
Enabled
Dma enabled
1
DTMODE
Data transfer mode selection 1: Stream
or SDIO multibyte data transfer.
2
1
DTMODE
BlockMode
Bloack data transfer
0
StreamMode
Stream or SDIO multibyte data transfer
1
DTDIR
Data transfer direction
selection
1
1
DTDIR
ControllerToCard
From controller to card
0
CardToController
From card to controller
1
DTEN
DTEN
0
1
DTEN
Disabled
Disabled
0
Enabled
Start transfer
1
DCOUNT
DCOUNT
data counter register
0x30
0x20
read-only
0x00000000
DATACOUNT
Data count value
0
25
0
33554431
STA
STA
status register
0x34
0x20
read-only
0x00000000
CEATAEND
CE-ATA command completion signal
received for CMD61
23
1
CEATAEND
NotReceived
Completion signal not received
0
Received
CE-ATA command completion signal received for CMD61
1
SDIOIT
SDIO interrupt received
22
1
SDIOIT
NotReceived
SDIO interrupt not receieved
0
Received
SDIO interrupt received
1
RXDAVL
Data available in receive
FIFO
21
1
RXDAVL
NotAvailable
Data not available in receive FIFO
0
Available
Data available in receive FIFO
1
TXDAVL
Data available in transmit
FIFO
20
1
TXDAVL
NotAvailable
Data not available in transmit FIFO
0
Available
Data available in transmit FIFO
1
RXFIFOE
Receive FIFO empty
19
1
RXFIFOE
NotEmpty
Receive FIFO not empty
0
Empty
Receive FIFO empty
1
TXFIFOE
Transmit FIFO empty
18
1
TXFIFOE
NotEmpty
Transmit FIFO not empty
0
Empty
Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.
1
RXFIFOF
Receive FIFO full
17
1
RXFIFOF
NotFull
Transmit FIFO not full
0
Full
Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.
1
TXFIFOF
Transmit FIFO full
16
1
TXFIFOF
NotFull
Transmit FIFO not full
0
Full
Transmit FIFO full
1
RXFIFOHF
Receive FIFO half full: there are at
least 8 words in the FIFO
15
1
RXFIFOHF
NotHalfFull
Receive FIFO not half full
0
HalfFull
Receive FIFO half full. At least 8 words in the FIFO
1
TXFIFOHE
Transmit FIFO half empty: at least 8
words can be written into the FIFO
14
1
TXFIFOHE
NotHalfEmpty
Transmit FIFO not half empty
0
HalfEmpty
Transmit FIFO half empty. At least 8 words can be written into the FIFO
1
RXACT
Data receive in progress
13
1
RXACT
NotInProgress
Data receive not in progress
0
InProgress
Data receive in progress
1
TXACT
Data transmit in progress
12
1
TXACT
NotInProgress
Data transmit is not in progress
0
InProgress
Data transmit in progress
1
CMDACT
Command transfer in
progress
11
1
CMDACT
NotInProgress
Command transfer not in progress
0
InProgress
Command tranfer in progress
1
DBCKEND
Data block sent/received (CRC check
passed)
10
1
DBCKEND
NotTransferred
Data block not sent/received (CRC check failed)
0
Transferred
Data block sent/received (CRC check passed)
1
STBITERR
Start bit not detected on all data
signals in wide bus mode
9
1
STBITERR
Detected
No start bit detected error
0
NotDetected
Start bit not detected error
1
DATAEND
Data end (data counter, SDIDCOUNT, is
zero)
8
1
DATAEND
NotDone
Not done
0
Done
Data end (DCOUNT, is zero)
1
CMDSENT
Command sent (no response
required)
7
1
CMDSENT
NotSent
Command not sent
0
Sent
Command sent (no response required)
1
CMDREND
Command response received (CRC check
passed)
6
1
CMDREND
NotDone
Command not done
0
Done
Command response received (CRC check passed)
1
RXOVERR
Received FIFO overrun
error
5
1
RXOVERR
NoOverrun
No FIFO overrun error
0
Overrun
Receive FIFO overrun error
1
TXUNDERR
Transmit FIFO underrun
error
4
1
TXUNDERR
NoUnderrun
No transmit FIFO underrun error
0
Underrun
Transmit FIFO underrun error
1
DTIMEOUT
Data timeout
3
1
DTIMEOUT
NoTimeout
No data timeout
0
Timeout
Data timeout
1
CTIMEOUT
Command response timeout
2
1
CTIMEOUT
NoTimeout
No Command timeout
0
Timeout
Command timeout
1
DCRCFAIL
Data block sent/received (CRC check
failed)
1
1
DCRCFAIL
NotFailed
No Data block sent/received crc check fail
0
Failed
Data block sent/received crc failed
1
CCRCFAIL
Command response received (CRC check
failed)
0
1
CCRCFAIL
NotFailed
Command response received, crc check passed
0
Failed
Command response received, crc check failed
1
ICR
ICR
interrupt clear register
0x38
0x20
read-write
0x00000000
CCRCFAILC
CCRCFAIL flag clear bit
0
1
CCRCFAILCW
write
Clear
Clear flag
1
CEATAENDC
CEATAEND flag clear bit
23
1
SDIOITC
SDIOIT flag clear bit
22
1
DBCKENDC
DBCKEND flag clear bit
10
1
STBITERRC
STBITERR flag clear bit
9
1
DATAENDC
DATAEND flag clear bit
8
1
CMDSENTC
CMDSENT flag clear bit
7
1
CMDRENDC
CMDREND flag clear bit
6
1
RXOVERRC
RXOVERR flag clear bit
5
1
TXUNDERRC
TXUNDERR flag clear bit
4
1
DTIMEOUTC
DTIMEOUT flag clear bit
3
1
CTIMEOUTC
CTIMEOUT flag clear bit
2
1
DCRCFAILC
DCRCFAIL flag clear bit
1
1
MASK
MASK
mask register
0x3C
0x20
read-write
0x00000000
CCRCFAILIE
Command CRC fail interrupt
enable
0
1
CCRCFAILIE
Disabled
Interrupt disabled
0
Enabled
Interrupt enabled
1
CEATAENDIE
CE-ATA command completion signal
received interrupt enable
23
1
SDIOITIE
SDIO mode interrupt received interrupt
enable
22
1
RXDAVLIE
Data available in Rx FIFO interrupt
enable
21
1
TXDAVLIE
Data available in Tx FIFO interrupt
enable
20
1
RXFIFOEIE
Rx FIFO empty interrupt
enable
19
1
TXFIFOEIE
Tx FIFO empty interrupt
enable
18
1
RXFIFOFIE
Rx FIFO full interrupt
enable
17
1
TXFIFOFIE
Tx FIFO full interrupt
enable
16
1
RXFIFOHFIE
Rx FIFO half full interrupt
enable
15
1
TXFIFOHEIE
Tx FIFO half empty interrupt
enable
14
1
RXACTIE
Data receive acting interrupt
enable
13
1
TXACTIE
Data transmit acting interrupt
enable
12
1
CMDACTIE
Command acting interrupt
enable
11
1
DBCKENDIE
Data block end interrupt
enable
10
1
STBITERRIE
Start bit error interrupt
enable
9
1
DATAENDIE
Data end interrupt enable
8
1
CMDSENTIE
Command sent interrupt
enable
7
1
CMDRENDIE
Command response received interrupt
enable
6
1
RXOVERRIE
Rx FIFO overrun error interrupt
enable
5
1
TXUNDERRIE
Tx FIFO underrun error interrupt
enable
4
1
DTIMEOUTIE
Data timeout interrupt
enable
3
1
CTIMEOUTIE
Command timeout interrupt
enable
2
1
DCRCFAILIE
Data CRC fail interrupt
enable
1
1
FIFOCNT
FIFOCNT
FIFO counter register
0x48
0x20
read-only
0x00000000
FIFOCOUNT
Remaining number of words to be written
to or read from the FIFO.
0
24
0
16777215
FIFO
FIFO
data FIFO register
0x80
0x20
read-write
0x00000000
FIFOData
Receive and transmit FIFO
data
0
32
0
4294967295
ADC1
Analog-to-digital converter
ADC
0x40012000
0x0
0x51
registers
SR
SR
status register
0x0
0x20
read-write
0x00000000
OVR
Overrun
5
1
zeroToClear
OVRR
read
NoOverrun
No overrun occurred
0
Overrun
Overrun occurred
1
OVRW
write
Clear
Clear flag
0
STRT
Regular channel start flag
4
1
zeroToClear
STRTR
read
NotStarted
No regular channel conversion started
0
Started
Regular channel conversion has started
1
STRTW
write
Clear
Clear flag
0
JSTRT
Injected channel start
flag
3
1
zeroToClear
JSTRTR
read
NotStarted
No injected channel conversion started
0
Started
Injected channel conversion has started
1
JSTRTW
write
Clear
Clear flag
0
JEOC
Injected channel end of
conversion
2
1
zeroToClear
JEOCR
read
NotComplete
Conversion is not complete
0
Complete
Conversion complete
1
JEOCW
write
Clear
Clear flag
0
EOC
Regular channel end of
conversion
1
1
zeroToClear
EOCR
read
NotComplete
Conversion is not complete
0
Complete
Conversion complete
1
EOCW
write
Clear
Clear flag
0
AWD
Analog watchdog flag
0
1
zeroToClear
AWDR
read
NoEvent
No analog watchdog event occurred
0
Event
Analog watchdog event occurred
1
AWDW
write
Clear
Clear flag
0
CR1
CR1
control register 1
0x4
0x20
read-write
0x00000000
OVRIE
Overrun interrupt enable
26
1
OVRIE
Disabled
Overrun interrupt disabled
0
Enabled
Overrun interrupt enabled
1
RES
Resolution
24
2
RES
TwelveBit
12-bit (15 ADCCLK cycles)
0
TenBit
10-bit (13 ADCCLK cycles)
1
EightBit
8-bit (11 ADCCLK cycles)
2
SixBit
6-bit (9 ADCCLK cycles)
3
AWDEN
Analog watchdog enable on regular
channels
23
1
AWDEN
Disabled
Analog watchdog disabled on regular channels
0
Enabled
Analog watchdog enabled on regular channels
1
JAWDEN
Analog watchdog enable on injected
channels
22
1
JAWDEN
Disabled
Analog watchdog disabled on injected channels
0
Enabled
Analog watchdog enabled on injected channels
1
DISCNUM
Discontinuous mode channel
count
13
3
0
7
JDISCEN
Discontinuous mode on injected
channels
12
1
JDISCEN
Disabled
Discontinuous mode on injected channels disabled
0
Enabled
Discontinuous mode on injected channels enabled
1
DISCEN
Discontinuous mode on regular
channels
11
1
DISCEN
Disabled
Discontinuous mode on regular channels disabled
0
Enabled
Discontinuous mode on regular channels enabled
1
JAUTO
Automatic injected group
conversion
10
1
JAUTO
Disabled
Automatic injected group conversion disabled
0
Enabled
Automatic injected group conversion enabled
1
AWDSGL
Enable the watchdog on a single channel
in scan mode
9
1
AWDSGL
AllChannels
Analog watchdog enabled on all channels
0
SingleChannel
Analog watchdog enabled on a single channel
1
SCAN
Scan mode
8
1
SCAN
Disabled
Scan mode disabled
0
Enabled
Scan mode enabled
1
JEOCIE
Interrupt enable for injected
channels
7
1
JEOCIE
Disabled
JEOC interrupt disabled
0
Enabled
JEOC interrupt enabled
1
AWDIE
Analog watchdog interrupt
enable
6
1
AWDIE
Disabled
Analogue watchdog interrupt disabled
0
Enabled
Analogue watchdog interrupt enabled
1
EOCIE
Interrupt enable for EOC
5
1
EOCIE
Disabled
EOC interrupt disabled
0
Enabled
EOC interrupt enabled
1
AWDCH
Analog watchdog channel select
bits
0
5
0
18
CR2
CR2
control register 2
0x8
0x20
read-write
0x00000000
SWSTART
Start conversion of regular
channels
30
1
SWSTARTW
write
Start
Starts conversion of regular channels
1
EXTEN
External trigger enable for regular
channels
28
2
EXTEN
Disabled
Trigger detection disabled
0
RisingEdge
Trigger detection on the rising edge
1
FallingEdge
Trigger detection on the falling edge
2
BothEdges
Trigger detection on both the rising and falling edges
3
EXTSEL
External event select for regular
group
24
4
EXTSEL
TIM1CC1
Timer 1 CC1 event
0
TIM1CC2
Timer 1 CC2 event
1
TIM1CC3
Timer 1 CC3 event
2
TIM2CC2
Timer 2 CC2 event
3
TIM2CC3
Timer 2 CC3 event
4
TIM2CC4
Timer 2 CC4 event
5
TIM2TRGO
Timer 2 TRGO event
6
TIM3CC1
Timer 3 CC1 event
7
TIM3TRGO
Timer 3 TRGO event
8
TIM4CC4
Timer 4 CC4 event
9
TIM5CC1
Timer 5 CC1 event
10
TIM5CC2
Timer 5 CC2 event
11
TIM5CC3
Timer 5 CC3 event
12
TIM8CC1
Timer 8 CC1 event
13
TIM8TRGO
Timer 8 TRGO event
14
EXTI11
EXTI line 11
15
JSWSTART
Start conversion of injected
channels
22
1
JSWSTARTW
write
Start
Starts conversion of injected channels
1
JEXTEN
External trigger enable for injected
channels
20
2
JEXTEN
Disabled
Trigger detection disabled
0
RisingEdge
Trigger detection on the rising edge
1
FallingEdge
Trigger detection on the falling edge
2
BothEdges
Trigger detection on both the rising and falling edges
3
JEXTSEL
External event select for injected
group
16
4
JEXTSEL
TIM1CC4
Timer 1 CC4 event
0
TIM1TRGO
Timer 1 TRGO event
1
TIM2CC1
Timer 2 CC1 event
2
TIM2TRGO
Timer 2 TRGO event
3
TIM3CC2
Timer 3 CC2 event
4
TIM3CC4
Timer 3 CC4 event
5
TIM4CC1
Timer 4 CC1 event
6
TIM4CC2
Timer 4 CC2 event
7
TIM4CC3
Timer 4 CC3 event
8
TIM4TRGO
Timer 4 TRGO event
9
TIM5CC4
Timer 5 CC4 event
10
TIM5TRGO
Timer 5 TRGO event
11
TIM8CC2
Timer 8 CC2 event
12
TIM8CC3
Timer 8 CC3 event
13
TIM8CC4
Timer 8 CC4 event
14
EXTI15
EXTI line 15
15
ALIGN
Data alignment
11
1
ALIGN
Right
Right alignment
0
Left
Left alignment
1
EOCS
End of conversion
selection
10
1
EOCS
EachSequence
The EOC bit is set at the end of each sequence of regular conversions
0
EachConversion
The EOC bit is set at the end of each regular conversion
1
DDS
DMA disable selection (for single ADC
mode)
9
1
DDS
Single
No new DMA request is issued after the last transfer
0
Continuous
DMA requests are issued as long as data are converted and DMA=1
1
DMA
Direct memory access mode (for single
ADC mode)
8
1
DMA
Disabled
DMA mode disabled
0
Enabled
DMA mode enabled
1
CONT
Continuous conversion
1
1
CONT
Single
Single conversion mode
0
Continuous
Continuous conversion mode
1
ADON
A/D Converter ON / OFF
0
1
ADON
Disabled
Disable ADC conversion and go to power down mode
0
Enabled
Enable ADC
1
SMPR1
SMPR1
sample time register 1
0xC
0x20
read-write
0x00000000
SMP10
Channel 10 sampling time selection
0
3
SMP10
Cycles3
3 cycles
0
Cycles15
15 cycles
1
Cycles28
28 cycles
2
Cycles56
56 cycles
3
Cycles84
84 cycles
4
Cycles112
112 cycles
5
Cycles144
144 cycles
6
Cycles480
480 cycles
7
SMP18
Channel 18 sampling time selection
24
3
SMP17
Channel 17 sampling time selection
21
3
SMP16
Channel 16 sampling time selection
18
3
SMP15
Channel 15 sampling time selection
15
3
SMP14
Channel 14 sampling time selection
12
3
SMP13
Channel 13 sampling time selection
9
3
SMP12
Channel 12 sampling time selection
6
3
SMP11
Channel 11 sampling time selection
3
3
SMPR2
SMPR2
sample time register 2
0x10
0x20
read-write
0x00000000
SMP0
Channel 0 sampling time selection
0
3
SMP0
Cycles3
3 cycles
0
Cycles15
15 cycles
1
Cycles28
28 cycles
2
Cycles56
56 cycles
3
Cycles84
84 cycles
4
Cycles112
112 cycles
5
Cycles144
144 cycles
6
Cycles480
480 cycles
7
SMP9
Channel 9 sampling time selection
27
3
SMP8
Channel 8 sampling time selection
24
3
SMP7
Channel 7 sampling time selection
21
3
SMP6
Channel 6 sampling time selection
18
3
SMP5
Channel 5 sampling time selection
15
3
SMP4
Channel 4 sampling time selection
12
3
SMP3
Channel 3 sampling time selection
9
3
SMP2
Channel 2 sampling time selection
6
3
SMP1
Channel 1 sampling time selection
3
3
4
0x4
1-4
JOFR%s
JOFR%s
injected channel data offset register
x
0x14
0x20
read-write
0x00000000
JOFFSET
Data offset for injected channel
x
0
12
0
4095
HTR
HTR
watchdog higher threshold
register
0x24
0x20
read-write
0x00000FFF
HT
Analog watchdog higher
threshold
0
12
0
4095
LTR
LTR
watchdog lower threshold
register
0x28
0x20
read-write
0x00000000
LT
Analog watchdog lower
threshold
0
12
0
4095
SQR1
SQR1
regular sequence register 1
0x2C
0x20
read-write
0x00000000
L
Regular channel sequence
length
20
4
0
15
SQ16
16th conversion in regular
sequence
15
5
0
18
SQ15
15th conversion in regular
sequence
10
5
0
18
SQ14
14th conversion in regular
sequence
5
5
0
18
SQ13
13th conversion in regular
sequence
0
5
0
18
SQR2
SQR2
regular sequence register 2
0x30
0x20
read-write
0x00000000
SQ12
12th conversion in regular
sequence
25
5
0
18
SQ11
11th conversion in regular
sequence
20
5
0
18
SQ10
10th conversion in regular
sequence
15
5
0
18
SQ9
9th conversion in regular
sequence
10
5
0
18
SQ8
8th conversion in regular
sequence
5
5
0
18
SQ7
7th conversion in regular
sequence
0
5
0
18
SQR3
SQR3
regular sequence register 3
0x34
0x20
read-write
0x00000000
SQ6
6th conversion in regular
sequence
25
5
0
18
SQ5
5th conversion in regular
sequence
20
5
0
18
SQ4
4th conversion in regular
sequence
15
5
0
18
SQ3
3rd conversion in regular
sequence
10
5
0
18
SQ2
2nd conversion in regular
sequence
5
5
0
18
SQ1
1st conversion in regular
sequence
0
5
0
18
JSQR
JSQR
injected sequence register
0x38
0x20
read-write
0x00000000
JL
Injected sequence length
20
2
0
3
JSQ4
4th conversion in injected
sequence
15
5
0
18
JSQ3
3rd conversion in injected
sequence
10
5
0
18
JSQ2
2nd conversion in injected
sequence
5
5
0
18
JSQ1
1st conversion in injected
sequence
0
5
0
18
4
0x4
1-4
JDR%s
JDR%s
injected data register x
0x3C
0x20
read-only
0x00000000
JDATA
Injected data
0
16
DR
DR
regular data register
0x4C
0x20
read-only
0x00000000
DATA
Regular data
0
16
ADC2
0x40012100
ADC
ADC2 global interrupts
18
ADC
ADC2 global interrupts
18
ADC3
0x40012200
USART1
Universal synchronous asynchronous receiver
transmitter
USART
0x40011000
0x0
0x400
registers
USART1
USART1 global interrupt
37
USART1
USART1 global interrupt
37
SR
SR
Status register
0x0
0x20
0x00C00000
CTS
CTS flag
9
1
read-write
LBD
LIN break detection flag
8
1
read-write
TXE
Transmit data register
empty
7
1
read-only
TC
Transmission complete
6
1
read-write
RXNE
Read data register not
empty
5
1
read-write
IDLE
IDLE line detected
4
1
read-only
ORE
Overrun error
3
1
read-only
NF
Noise detected flag
2
1
read-only
FE
Framing error
1
1
read-only
PE
Parity error
0
1
read-only
DR
DR
Data register
0x4
0x20
read-write
0x00000000
DR
Data value
0
9
0
511
BRR
BRR
Baud rate register
0x8
0x20
read-write
0x00000000
DIV_Mantissa
mantissa of USARTDIV
4
12
0
4095
DIV_Fraction
fraction of USARTDIV
0
4
0
15
CR1
CR1
Control register 1
0xC
0x20
read-write
0x00000000
OVER8
Oversampling mode
15
1
OVER8
Oversample16
Oversampling by 16
0
Oversample8
Oversampling by 8
1
UE
USART enable
13
1
UE
Disabled
USART prescaler and outputs disabled
0
Enabled
USART enabled
1
M
Word length
12
1
M
M8
8 data bits
0
M9
9 data bits
1
WAKE
Wakeup method
11
1
WAKE
IdleLine
USART wakeup on idle line
0
AddressMark
USART wakeup on address mark
1
PCE
Parity control enable
10
1
PCE
Disabled
Parity control disabled
0
Enabled
Parity control enabled
1
PS
Parity selection
9
1
PS
Even
Even parity
0
Odd
Odd parity
1
PEIE
PE interrupt enable
8
1
PEIE
Disabled
PE interrupt disabled
0
Enabled
PE interrupt enabled
1
TXEIE
TXE interrupt enable
7
1
TXEIE
Disabled
TXE interrupt disabled
0
Enabled
TXE interrupt enabled
1
TCIE
Transmission complete interrupt
enable
6
1
TCIE
Disabled
TC interrupt disabled
0
Enabled
TC interrupt enabled
1
RXNEIE
RXNE interrupt enable
5
1
RXNEIE
Disabled
RXNE interrupt disabled
0
Enabled
RXNE interrupt enabled
1
IDLEIE
IDLE interrupt enable
4
1
IDLEIE
Disabled
IDLE interrupt disabled
0
Enabled
IDLE interrupt enabled
1
TE
Transmitter enable
3
1
TE
Disabled
Transmitter disabled
0
Enabled
Transmitter enabled
1
RE
Receiver enable
2
1
RE
Disabled
Receiver disabled
0
Enabled
Receiver enabled
1
RWU
Receiver wakeup
1
1
RWU
Active
Receiver in active mode
0
Mute
Receiver in mute mode
1
SBK
Send break
0
1
SBK
NoBreak
No break character is transmitted
0
Break
Break character transmitted
1
CR2
CR2
Control register 2
0x10
0x20
read-write
0x00000000
LINEN
LIN mode enable
14
1
LINEN
Disabled
LIN mode disabled
0
Enabled
LIN mode enabled
1
STOP
STOP bits
12
2
STOP
Stop1
1 stop bit
0
Stop0p5
0.5 stop bits
1
Stop2
2 stop bits
2
Stop1p5
1.5 stop bits
3
CLKEN
Clock enable
11
1
CLKEN
Disabled
CK pin disabled
0
Enabled
CK pin enabled
1
CPOL
Clock polarity
10
1
CPOL
Low
Steady low value on CK pin outside transmission window
0
High
Steady high value on CK pin outside transmission window
1
CPHA
Clock phase
9
1
CPHA
First
The first clock transition is the first data capture edge
0
Second
The second clock transition is the first data capture edge
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt
enable
6
1
LBDIE
Disabled
LIN break detection interrupt disabled
0
Enabled
LIN break detection interrupt enabled
1
LBDL
lin break detection length
5
1
LBDL
LBDL10
10-bit break detection
0
LBDL11
11-bit break detection
1
ADD
Address of the USART node
0
4
0
15
CR3
CR3
Control register 3
0x14
0x20
read-write
0x00000000
ONEBIT
One sample bit method
enable
11
1
ONEBIT
Sample3
Three sample bit method
0
Sample1
One sample bit method
1
CTSIE
CTS interrupt enable
10
1
CTSIE
Disabled
CTS interrupt disabled
0
Enabled
CTS interrupt enabled
1
CTSE
CTS enable
9
1
CTSE
Disabled
CTS hardware flow control disabled
0
Enabled
CTS hardware flow control enabled
1
RTSE
RTS enable
8
1
RTSE
Disabled
RTS hardware flow control disabled
0
Enabled
RTS hardware flow control enabled
1
DMAT
DMA enable transmitter
7
1
DMAT
Disabled
DMA mode is disabled for transmission
0
Enabled
DMA mode is enabled for transmission
1
DMAR
DMA enable receiver
6
1
DMAR
Disabled
DMA mode is disabled for reception
0
Enabled
DMA mode is enabled for reception
1
SCEN
Smartcard mode enable
5
1
SCEN
Disabled
Smartcard mode disabled
0
Enabled
Smartcard mode enabled
1
NACK
Smartcard NACK enable
4
1
NACK
Disabled
NACK transmission in case of parity error is disabled
0
Enabled
NACK transmission during parity error is enabled
1
HDSEL
Half-duplex selection
3
1
HDSEL
FullDuplex
Half duplex mode is not selected
0
HalfDuplex
Half duplex mode is selected
1
IRLP
IrDA low-power
2
1
IRLP
Normal
Normal mode
0
LowPower
Low-power mode
1
IREN
IrDA mode enable
1
1
IREN
Disabled
IrDA disabled
0
Enabled
IrDA enabled
1
EIE
Error interrupt enable
0
1
EIE
Disabled
Error interrupt disabled
0
Enabled
Error interrupt enabled
1
GTPR
GTPR
Guard time and prescaler
register
0x18
0x20
read-write
0x00000000
GT
Guard time value
8
8
PSC
Prescaler value
0
8
USART6
0x40011400
USART6
USART6 global interrupt
71
USART6
USART6 global interrupt
71
USART2
0x40004400
USART2
USART2 global interrupt
38
USART2
USART2 global interrupt
38
USART3
0x40004800
USART3
USART3 global interrupt
39
USART3
USART3 global interrupt
39
UART4
Universal synchronous asynchronous receiver
transmitter
USART
0x40004C00
0x0
0x400
registers
UART4
UART4 global interrupt
52
UART4
UART4 global interrupt
52
SR
SR
Status register
0x0
0x20
0x00C00000
LBD
LIN break detection flag
8
1
read-write
TXE
Transmit data register
empty
7
1
read-only
TC
Transmission complete
6
1
read-write
RXNE
Read data register not
empty
5
1
read-write
IDLE
IDLE line detected
4
1
read-only
ORE
Overrun error
3
1
read-only
NF
Noise detected flag
2
1
read-only
FE
Framing error
1
1
read-only
PE
Parity error
0
1
read-only
DR
DR
Data register
0x4
0x20
read-write
0x00000000
DR
Data value
0
9
0
511
BRR
BRR
Baud rate register
0x8
0x20
read-write
0x00000000
DIV_Mantissa
mantissa of USARTDIV
4
12
0
4095
DIV_Fraction
fraction of USARTDIV
0
4
0
15
CR1
CR1
Control register 1
0xC
0x20
read-write
0x00000000
OVER8
Oversampling mode
15
1
OVER8
Oversample16
Oversampling by 16
0
Oversample8
Oversampling by 8
1
UE
USART enable
13
1
UE
Disabled
USART prescaler and outputs disabled
0
Enabled
USART enabled
1
M
Word length
12
1
M
M8
8 data bits
0
M9
9 data bits
1
WAKE
Wakeup method
11
1
WAKE
IdleLine
USART wakeup on idle line
0
AddressMark
USART wakeup on address mark
1
PCE
Parity control enable
10
1
PCE
Disabled
Parity control disabled
0
Enabled
Parity control enabled
1
PS
Parity selection
9
1
PS
Even
Even parity
0
Odd
Odd parity
1
PEIE
PE interrupt enable
8
1
PEIE
Disabled
PE interrupt disabled
0
Enabled
PE interrupt enabled
1
TXEIE
TXE interrupt enable
7
1
TXEIE
Disabled
TXE interrupt disabled
0
Enabled
TXE interrupt enabled
1
TCIE
Transmission complete interrupt
enable
6
1
TCIE
Disabled
TC interrupt disabled
0
Enabled
TC interrupt enabled
1
RXNEIE
RXNE interrupt enable
5
1
RXNEIE
Disabled
RXNE interrupt disabled
0
Enabled
RXNE interrupt enabled
1
IDLEIE
IDLE interrupt enable
4
1
IDLEIE
Disabled
IDLE interrupt disabled
0
Enabled
IDLE interrupt enabled
1
TE
Transmitter enable
3
1
TE
Disabled
Transmitter disabled
0
Enabled
Transmitter enabled
1
RE
Receiver enable
2
1
RE
Disabled
Receiver disabled
0
Enabled
Receiver enabled
1
RWU
Receiver wakeup
1
1
RWU
Active
Receiver in active mode
0
Mute
Receiver in mute mode
1
SBK
Send break
0
1
SBK
NoBreak
No break character is transmitted
0
Break
Break character transmitted
1
CR2
CR2
Control register 2
0x10
0x20
read-write
0x00000000
LINEN
LIN mode enable
14
1
LINEN
Disabled
LIN mode disabled
0
Enabled
LIN mode enabled
1
STOP
STOP bits
12
2
STOP
Stop1
1 stop bit
0
Stop2
2 stop bits
2
LBDIE
LIN break detection interrupt
enable
6
1
LBDIE
Disabled
LIN break detection interrupt disabled
0
Enabled
LIN break detection interrupt enabled
1
LBDL
lin break detection length
5
1
LBDL
LBDL10
10-bit break detection
0
LBDL11
11-bit break detection
1
ADD
Address of the USART node
0
4
0
15
CR3
CR3
Control register 3
0x14
0x20
read-write
0x00000000
ONEBIT
One sample bit method
enable
11
1
ONEBIT
Sample3
Three sample bit method
0
Sample1
One sample bit method
1
DMAT
DMA enable transmitter
7
1
DMAT
Disabled
DMA mode is disabled for transmission
0
Enabled
DMA mode is enabled for transmission
1
DMAR
DMA enable receiver
6
1
DMAR
Disabled
DMA mode is disabled for reception
0
Enabled
DMA mode is enabled for reception
1
HDSEL
Half-duplex selection
3
1
HDSEL
FullDuplex
Half duplex mode is not selected
0
HalfDuplex
Half duplex mode is selected
1
IRLP
IrDA low-power
2
1
IRLP
Normal
Normal mode
0
LowPower
Low-power mode
1
IREN
IrDA mode enable
1
1
IREN
Disabled
IrDA disabled
0
Enabled
IrDA enabled
1
EIE
Error interrupt enable
0
1
EIE
Disabled
Error interrupt disabled
0
Enabled
Error interrupt enabled
1
GTPR
Guard Time and Prescaler Register
0x18
read-write
PSC
IrDA Low-Power pulse width peripheral clock prescaler
0
8
UART7
0x40007800
UART7
UART 7 global interrupt
82
UART7
UART 7 global interrupt
82
UART8
0x40007C00
UART8
UART 8 global interrupt
83
UART8
UART 8 global interrupt
83
DAC
Digital-to-analog converter
DAC
0x40007400
0x0
0x400
registers
TIM6_DAC
TIM6 global interrupt, DAC1 and DAC2 underrun
error interrupt
54
TIM6_DAC
TIM6 global interrupt, DAC1 and DAC2 underrun
error interrupt
54
CR
CR
control register
0x0
0x20
read-write
0x00000000
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt
enable
13
1
DMAUDRIE1
Disabled
DAC channel X DMA Underrun Interrupt disabled
0
Enabled
DAC channel X DMA Underrun Interrupt enabled
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt
enable
29
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN1
Disabled
DAC channel X DMA mode disabled
0
Enabled
DAC channel X DMA mode enabled
1
DMAEN2
DAC channel2 DMA enable
28
1
MAMP2
DAC channel2 mask/amplitude
selector
24
4
0
15
WAVE1
DAC channel1 noise/triangle wave
generation enable
6
2
WAVE1
Disabled
Wave generation disabled
0
Noise
Noise wave generation enabled
1
Triangle
Triangle wave generation enabled
2
WAVE2
DAC channel2 noise/triangle wave
generation enable
22
2
TSEL1
DAC channel1 trigger
selection
3
3
TSEL1
TIM6_TRGO
Timer 6 TRGO event
0
TIM8_TRGO
Timer 8 TRGO event
1
TIM7_TRGO
Timer 7 TRGO event
2
TIM5_TRGO
Timer 5 TRGO event
3
TIM2_TRGO
Timer 2 TRGO event
4
TIM4_TRGO
Timer 4 TRGO event
5
EXTI9
EXTI line9
6
SOFTWARE
Software trigger
7
TSEL2
DAC channel2 trigger
selection
19
3
TEN1
DAC channel1 trigger
enable
2
1
TEN1
Disabled
DAC channel X trigger disabled
0
Enabled
DAC channel X trigger enabled
1
TEN2
DAC channel2 trigger
enable
18
1
BOFF1
DAC channel1 output buffer
disable
1
1
BOFF1
Enabled
DAC channel X output buffer enabled
0
Disabled
DAC channel X output buffer disabled
1
BOFF2
DAC channel2 output buffer
disable
17
1
EN1
DAC channel1 enable
0
1
EN1
Disabled
DAC channel X disabled
0
Enabled
DAC channel X enabled
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude
selector
8
4
0
15
SWTRIGR
SWTRIGR
software trigger register
0x4
0x20
write-only
0x00000000
SWTRIG1
DAC channel1 software
trigger
0
1
SWTRIG1
Disabled
DAC channel X software trigger disabled
0
Enabled
DAC channel X software trigger enabled
1
SWTRIG2
DAC channel2 software
trigger
1
1
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding
register
0x8
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit right-aligned
data
0
12
0
4095
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding
register
0xC
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 12-bit left-aligned
data
4
12
0
4095
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding
register
0x10
0x20
read-write
0x00000000
DACC1DHR
DAC channel1 8-bit right-aligned
data
0
8
0
255
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding
register
0x14
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit right-aligned
data
0
12
0
4095
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding
register
0x18
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit left-aligned
data
4
12
0
4095
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding
register
0x1C
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 8-bit right-aligned
data
0
8
0
255
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding
register
0x20
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit right-aligned
data
16
12
0
4095
DACC1DHR
DAC channel1 12-bit right-aligned
data
0
12
0
4095
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding
register
0x24
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 12-bit left-aligned
data
20
12
0
4095
DACC1DHR
DAC channel1 12-bit left-aligned
data
4
12
0
4095
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding
register
0x28
0x20
read-write
0x00000000
DACC2DHR
DAC channel2 8-bit right-aligned
data
8
8
0
255
DACC1DHR
DAC channel1 8-bit right-aligned
data
0
8
0
255
DOR1
DOR1
channel1 data output register
0x2C
0x20
read-only
0x00000000
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
0x20
read-only
0x00000000
DACC2DOR
DAC channel2 data output
0
12
SR
SR
status register
0x34
0x20
read-write
0x00000000
DMAUDR1
DAC channel1 DMA underrun
flag
13
1
DMAUDR1
NoUnderrun
No DMA underrun error condition occurred for DAC channel X
0
Underrun
DMA underrun error condition occurred for DAC channel X
1
DMAUDR2
DAC channel2 DMA underrun
flag
29
1
PWR
Power control
PWR
0x40007000
0x0
0x400
registers
PVD
PVD through EXTI line detection
interrupt
1
PVD
PVD through EXTI line detection
interrupt
1
CR
CR
power control register
0x0
0x20
read-write
0x0000C000
LPDS
Low-power deep sleep
0
1
PDDS
Power down deepsleep
1
1
CWUF
Clear wakeup flag
2
1
CSBF
Clear standby flag
3
1
PVDE
Power voltage detector
enable
4
1
PLS
PVD level selection
5
3
DBP
Disable backup domain write
protection
8
1
FPDS
Flash power down in Stop
mode
9
1
LPLVDS
Low-Power Regulator Low Voltage in
deepsleep
10
1
MRLVDS
Main regulator low voltage in deepsleep
mode
11
1
VOS
Regulator voltage scaling output
selection
14
2
ODEN
Over-drive enable
16
1
ODSWEN
Over-drive switching
enabled
17
1
UDEN
Under-drive enable in stop
mode
18
2
CSR
CSR
power control/status register
0x4
0x20
0x00000000
WUF
Wakeup flag
0
1
read-only
SBF
Standby flag
1
1
read-only
PVDO
PVD output
2
1
read-only
BRR
Backup regulator ready
3
1
read-only
EWUP
Enable WKUP pin
8
1
read-write
BRE
Backup regulator enable
9
1
read-write
VOSRDY
Regulator voltage scaling output
selection ready bit
14
1
read-write
ODRDY
Over-drive mode ready
16
1
read-only
ODSWRDY
Over-drive mode switching
ready
17
1
read-only
UDRDY
Under-drive ready flag
18
2
read-write
IWDG
Independent watchdog
IWDG
0x40003000
0x0
0x400
registers
KR
KR
Key register
0x0
0x20
write-only
0x00000000
KEY
Key value (write only, read
0000h)
0
16
KEY
Enable
Enable access to PR, RLR and WINR registers (0x5555)
21845
Reset
Reset the watchdog value (0xAAAA)
43690
Start
Start the watchdog (0xCCCC)
52428
PR
PR
Prescaler register
0x4
0x20
read-write
0x00000000
PR
Prescaler divider
0
3
PR
DivideBy4
Divider /4
0
DivideBy8
Divider /8
1
DivideBy16
Divider /16
2
DivideBy32
Divider /32
3
DivideBy64
Divider /64
4
DivideBy128
Divider /128
5
DivideBy256
Divider /256
6
RLR
RLR
Reload register
0x8
0x20
read-write
0x00000FFF
RL
Watchdog counter reload
value
0
12
0
4095
SR
SR
Status register
0xC
0x20
read-only
0x00000000
RVU
Watchdog counter reload value
update
1
1
PVU
Watchdog prescaler value
update
0
1
WWDG
Window watchdog
WWDG
0x40002C00
0x0
0x400
registers
WWDG
Window Watchdog interrupt
0
WWDG
Window Watchdog interrupt
0
CR
CR
Control register
0x0
0x20
read-write
0x0000007F
WDGA
Activation bit
7
1
WDGA
Disabled
Watchdog disabled
0
Enabled
Watchdog enabled
1
T
7-bit counter (MSB to LSB)
0
7
0
127
CFR
CFR
Configuration register
0x4
0x20
read-write
0x0000007F
EWI
Early wakeup interrupt
9
1
EWIW
write
Enable
interrupt occurs whenever the counter reaches the value 0x40
1
W
7-bit window value
0
7
0
127
WDGTB
Timer base
7
2
WDGTB
Div1
Counter clock (PCLK1 div 4096) div 1
0
Div2
Counter clock (PCLK1 div 4096) div 2
1
Div4
Counter clock (PCLK1 div 4096) div 4
2
Div8
Counter clock (PCLK1 div 4096) div 8
3
SR
SR
Status register
0x8
0x20
read-write
0x00000000
EWIF
Early wakeup interrupt
flag
0
1
zeroToClear
EWIFR
read
Finished
The EWI Interrupt Service Routine has been serviced
0
Pending
The EWI Interrupt Service Routine has been triggered
1
EWIFW
write
Finished
The EWI Interrupt Service Routine has been serviced
0
RTC
Real-time clock
RTC
0x40002800
0x0
0x400
registers
RTC_WKUP
RTC Wakeup interrupt through the EXTI
line
3
RTC_WKUP
RTC Wakeup interrupt through the EXTI
line
3
RTC_Alarm
RTC Alarms (A and B) through EXTI line
interrupt
41
RTC_Alarm
RTC Alarms (A and B) through EXTI line
interrupt
41
TR
TR
time register
0x0
0x20
read-write
0x00000000
PM
AM/PM notation
22
1
PM
AM
AM or 24-hour format
0
PM
PM
1
HT
Hour tens in BCD format
20
2
0
3
HU
Hour units in BCD format
16
4
0
15
MNT
Minute tens in BCD format
12
3
0
7
MNU
Minute units in BCD format
8
4
0
15
ST
Second tens in BCD format
4
3
0
7
SU
Second units in BCD format
0
4
0
15
DR
DR
date register
0x4
0x20
read-write
0x00002101
YT
Year tens in BCD format
20
4
0
15
YU
Year units in BCD format
16
4
0
15
WDU
Week day units
13
3
1
7
MT
Month tens in BCD format
12
1
MT
Zero
Month tens is 0
0
One
Month tens is 1
1
MU
Month units in BCD format
8
4
0
15
DT
Date tens in BCD format
4
2
0
3
DU
Date units in BCD format
0
4
0
15
CR
CR
control register
0x8
0x20
read-write
0x00000000
COE
Calibration output enable
23
1
COE
Disabled
Calibration output disabled
0
Enabled
Calibration output enabled
1
OSEL
Output selection
21
2
OSEL
Disabled
Output disabled
0
AlarmA
Alarm A output enabled
1
AlarmB
Alarm B output enabled
2
Wakeup
Wakeup output enabled
3
POL
Output polarity
20
1
POL
High
The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
0
Low
The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1
BKP
Backup
18
1
BKP
DST_Not_Changed
Daylight Saving Time change has not been performed
0
DST_Changed
Daylight Saving Time change has been performed
1
SUB1H
Subtract 1 hour (winter time
change)
17
1
SUB1HW
write
Sub1
Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
1
ADD1H
Add 1 hour (summer time
change)
16
1
ADD1HW
write
Add1
Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
1
TSIE
Time-stamp interrupt
enable
15
1
TSIE
Disabled
Time-stamp Interrupt disabled
0
Enabled
Time-stamp Interrupt enabled
1
WUTIE
Wakeup timer interrupt
enable
14
1
WUTIE
Disabled
Wakeup timer interrupt disabled
0
Enabled
Wakeup timer interrupt enabled
1
ALRBIE
Alarm B interrupt enable
13
1
ALRBIE
Disabled
Alarm B Interrupt disabled
0
Enabled
Alarm B Interrupt enabled
1
ALRAIE
Alarm A interrupt enable
12
1
ALRAIE
Disabled
Alarm A interrupt disabled
0
Enabled
Alarm A interrupt enabled
1
TSE
Time stamp enable
11
1
TSE
Disabled
Timestamp disabled
0
Enabled
Timestamp enabled
1
WUTE
Wakeup timer enable
10
1
WUTE
Disabled
Wakeup timer disabled
0
Enabled
Wakeup timer enabled
1
ALRBE
Alarm B enable
9
1
ALRBE
Disabled
Alarm B disabled
0
Enabled
Alarm B enabled
1
ALRAE
Alarm A enable
8
1
ALRAE
Disabled
Alarm A disabled
0
Enabled
Alarm A enabled
1
DCE
Coarse digital calibration
enable
7
1
FMT
Hour format
6
1
FMT
Twenty_Four_Hour
24 hour/day format
0
AM_PM
AM/PM hour format
1
REFCKON
Reference clock detection enable (50 or
60 Hz)
4
1
REFCKON
Disabled
RTC_REFIN detection disabled
0
Enabled
RTC_REFIN detection enabled
1
TSEDGE
Time-stamp event active
edge
3
1
TSEDGE
RisingEdge
RTC_TS input rising edge generates a time-stamp event
0
FallingEdge
RTC_TS input falling edge generates a time-stamp event
1
WUCKSEL
Wakeup clock selection
0
3
WUCKSEL
Div16
RTC/16 clock is selected
0
Div8
RTC/8 clock is selected
1
Div4
RTC/4 clock is selected
2
Div2
RTC/2 clock is selected
3
ClockSpare
ck_spre (usually 1 Hz) clock is selected
4
ClockSpareWithOffset
ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
6
BYPSHAD
Bypass the shadow registers
5
1
read-write
BYPSHAD
ShadowReg
Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
0
BypassShadowReg
Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
1
COSEL
Calibration output selection
19
1
read-write
COSEL
CalFreq_512Hz
Calibration output is 512 Hz (with default prescaler setting)
0
CalFreq_1Hz
Calibration output is 1 Hz (with default prescaler setting)
1
ISR
ISR
initialization and status
register
0xC
0x20
0x00000007
ALRAWF
Alarm A write flag
0
1
read-only
ALRAWFR
UpdateNotAllowed
Alarm update not allowed
0
UpdateAllowed
Alarm update allowed
1
ALRBWF
Alarm B write flag
1
1
read-only
WUTWF
Wakeup timer write flag
2
1
read-only
WUTWFR
UpdateNotAllowed
Wakeup timer configuration update not allowed
0
UpdateAllowed
Wakeup timer configuration update allowed
1
SHPF
Shift operation pending
3
1
read-write
SHPFR
read
NoShiftPending
No shift operation is pending
0
ShiftPending
A shift operation is pending
1
INITS
Initialization status flag
4
1
read-only
INITSR
NotInitalized
Calendar has not been initialized
0
Initalized
Calendar has been initialized
1
RSF
Registers synchronization
flag
5
1
read-write
zeroToClear
RSFR
read
NotSynced
Calendar shadow registers not yet synchronized
0
Synced
Calendar shadow registers synchronized
1
RSFW
write
Clear
This flag is cleared by software by writing 0
0
INITF
Initialization flag
6
1
read-only
INITFR
NotAllowed
Calendar registers update is not allowed
0
Allowed
Calendar registers update is allowed
1
INIT
Initialization mode
7
1
read-write
INIT
FreeRunningMode
Free running mode
0
InitMode
Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
1
ALRAF
Alarm A flag
8
1
read-write
zeroToClear
ALRAFR
read
Match
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
1
ALRAFW
write
Clear
This flag is cleared by software by writing 0
0
ALRBF
Alarm B flag
9
1
read-write
zeroToClear
ALRBFR
read
Match
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)
1
ALRBFW
write
Clear
This flag is cleared by software by writing 0
0
WUTF
Wakeup timer flag
10
1
read-write
zeroToClear
WUTFR
read
Zero
This flag is set by hardware when the wakeup auto-reload counter reaches 0
1
WUTFW
write
Clear
This flag is cleared by software by writing 0
0
TSF
Time-stamp flag
11
1
read-write
zeroToClear
TSFR
read
TimestampEvent
This flag is set by hardware when a time-stamp event occurs
1
TSFW
write
Clear
This flag is cleared by software by writing 0
0
TSOVF
Time-stamp overflow flag
12
1
read-write
zeroToClear
TSOVFR
read
Overflow
This flag is set by hardware when a time-stamp event occurs while TSF is already set
1
TSOVFW
write
Clear
This flag is cleared by software by writing 0
0
TAMP1F
Tamper detection flag
13
1
read-write
zeroToClear
TAMP1FR
read
Tampered
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
1
TAMP1FW
write
Clear
Flag cleared by software writing 0
0
TAMP2F
TAMPER2 detection flag
14
1
read-write
zeroToClear
read
write
RECALPF
Recalibration pending Flag
16
1
read-only
RECALPFR
Pending
The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
1
PRER
PRER
prescaler register
0x10
0x20
read-write
0x007F00FF
PREDIV_A
Asynchronous prescaler
factor
16
7
0
127
PREDIV_S
Synchronous prescaler
factor
0
15
0
32767
WUTR
WUTR
wakeup timer register
0x14
0x20
read-write
0x0000FFFF
WUT
Wakeup auto-reload value
bits
0
16
0
65535
CALIBR
CALIBR
calibration register
0x18
0x20
read-write
0x00000000
DCS
Digital calibration sign
7
1
DC
Digital calibration
0
5
2
0x4
A,B
ALRM%sR
ALRM%sR
Alarm %s register
0x1C
0x20
read-write
0x00000000
MSK1
Alarm seconds mask
7
1
MSK1
Mask
Alarm set if the date/day match
0
NotMask
Date/day don’t care in Alarm comparison
1
MSK4
Alarm date mask
31
1
WDSEL
Week day selection
30
1
WDSEL
DateUnits
DU[3:0] represents the date units
0
WeekDay
DU[3:0] represents the week day. DT[1:0] is don’t care.
1
DT
Date tens in BCD format
28
2
0
3
DU
Date units or day in BCD format
24
4
0
15
MSK3
Alarm hours mask
23
1
PM
AM/PM notation
22
1
PM
AM
AM or 24-hour format
0
PM
PM
1
HT
Hour tens in BCD format
20
2
0
3
HU
Hour units in BCD format
16
4
0
15
MSK2
Alarm minutes mask
15
1
MNT
Minute tens in BCD format
12
3
0
7
MNU
Minute units in BCD format
8
4
0
15
ST
Second tens in BCD format
4
3
0
7
SU
Second units in BCD format
0
4
0
15
WPR
WPR
write protection register
0x24
0x20
write-only
0x00000000
KEY
Write protection key
0
8
0
255
SSR
SSR
sub second register
0x28
0x20
read-only
0x00000000
SS
Sub second value
0
16
0
65535
SHIFTR
SHIFTR
shift control register
0x2C
0x20
write-only
0x00000000
ADD1S
Add one second
31
1
ADD1SW
Add1
Add one second to the clock/calendar
1
SUBFS
Subtract a fraction of a
second
0
15
0
32767
TSTR
TSTR
time stamp time register
0x30
TSDR
TSDR
time stamp date register
0x34
TSSSR
TSSSR
timestamp sub second register
0x38
CALR
CALR
calibration register
0x3C
0x20
read-write
0x00000000
CALP
Increase frequency of RTC by 488.5
ppm
15
1
CALP
NoChange
No RTCCLK pulses are added
0
IncreaseFreq
One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
1
CALW8
Use an 8-second calibration cycle
period
14
1
CALW8
Eight_Second
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
1
CALW16
Use a 16-second calibration cycle
period
13
1
CALW16
Sixteen_Second
When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
1
CALM
Calibration minus
0
9
0
511
TAFCR
TAFCR
tamper and alternate function configuration
register
0x40
0x20
read-write
0x00000000
ALARMOUTTYPE
AFO_ALARM output type
18
1
TSINSEL
TIMESTAMP mapping
17
1
TAMP1INSEL
TAMPER1 mapping
16
1
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMPPRCH
Tamper precharge duration
13
2
TAMPFLT
Tamper filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPTS
Activate timestamp on tamper detection
event
7
1
TAMP2TRG
Active level for tamper 2
4
1
TAMP2E
Tamper 2 detection enable
3
1
TAMPIE
Tamper interrupt enable
2
1
TAMP1TRG
Active level for tamper 1
1
1
TAMP1E
Tamper 1 detection enable
0
1
2
0x4
A,B
ALRM%sSSR
ALRM%sSSR
Alarm %s sub-second register
0x44
0x20
read-write
0x00000000
MASKSS
Mask the most-significant bits starting
at this bit
24
4
0
15
SS
Sub seconds value
0
15
0
32767
20
0x4
0-19
BKP%sR
BKP%sR
backup register
0x50
0x20
read-write
0x00000000
BKP
BKP
0
32
0
4294967295
UART5
0x40005000
UART5
UART5 global interrupt
53
UART5
UART5 global interrupt
53
ADC_Common
Common ADC registers
ADC_Common
0x40012300
0x0
0xD
registers
CSR
CSR
ADC Common status register
0x0
0x20
read-only
0x00000000
OVR1
Overrun flag of ADC 1
5
1
OVR1
NoOverrun
No overrun occurred
0
Overrun
Overrun occurred
1
OVR3
Overrun flag of ADC3
21
1
STRT1
Regular channel Start flag of ADC
1
4
1
STRT1
NotStarted
No regular channel conversion started
0
Started
Regular channel conversion has started
1
STRT3
Regular channel Start flag of ADC
3
20
1
JSTRT1
Injected channel Start flag of ADC
1
3
1
JSTRT1
NotStarted
No injected channel conversion started
0
Started
Injected channel conversion has started
1
JSTRT3
Injected channel Start flag of ADC
3
19
1
JEOC1
Injected channel end of conversion of
ADC 1
2
1
JEOC1
NotComplete
Conversion is not complete
0
Complete
Conversion complete
1
JEOC3
Injected channel end of conversion of
ADC 3
18
1
EOC1
End of conversion of ADC 1
1
1
EOC1
NotComplete
Conversion is not complete
0
Complete
Conversion complete
1
EOC3
End of conversion of ADC 3
17
1
AWD1
Analog watchdog flag of ADC
1
0
1
AWD1
NoEvent
No analog watchdog event occurred
0
Event
Analog watchdog event occurred
1
AWD3
Analog watchdog flag of ADC
3
16
1
OVR2
Overrun flag of ADC 2
13
1
STRT2
Regular channel Start flag of ADC
2
12
1
JSTRT2
Injected channel Start flag of ADC
2
11
1
JEOC2
Injected channel end of conversion of
ADC 2
10
1
EOC2
End of conversion of ADC 2
9
1
AWD2
Analog watchdog flag of ADC
2
8
1
CCR
CCR
ADC common control register
0x4
0x20
read-write
0x00000000
TSVREFE
Temperature sensor and VREFINT
enable
23
1
TSVREFE
Disabled
Temperature sensor and V_REFINT channel disabled
0
Enabled
Temperature sensor and V_REFINT channel enabled
1
VBATE
VBAT enable
22
1
VBATE
Disabled
V_BAT channel disabled
0
Enabled
V_BAT channel enabled
1
ADCPRE
ADC prescaler
16
2
ADCPRE
Div2
PCLK2 divided by 2
0
Div4
PCLK2 divided by 4
1
Div6
PCLK2 divided by 6
2
Div8
PCLK2 divided by 8
3
DMA
Direct memory access mode for multi ADC
mode
14
2
DMA
Disabled
DMA mode disabled
0
Mode1
DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
1
Mode2
DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
2
Mode3
DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
3
DDS
DMA disable selection for multi-ADC
mode
13
1
DDS
Single
No new DMA request is issued after the last transfer
0
Continuous
DMA requests are issued as long as data are converted and DMA=01, 10 or 11
1
DELAY
Delay between 2 sampling
phases
8
4
0
15
MULTI
Multi ADC mode selection
0
5
MULTI
Independent
All the ADCs independent: independent mode
0
DualRJ
Dual ADC1 and ADC2, combined regular and injected simultaneous mode
1
DualRA
Dual ADC1 and ADC2, combined regular and alternate trigger mode
2
DualJ
Dual ADC1 and ADC2, injected simultaneous mode only
5
DualR
Dual ADC1 and ADC2, regular simultaneous mode only
6
DualI
Dual ADC1 and ADC2, interleaved mode only
7
DualA
Dual ADC1 and ADC2, alternate trigger mode only
9
TripleRJ
Triple ADC, regular and injected simultaneous mode
17
TripleRA
Triple ADC, regular and alternate trigger mode
18
TripleJ
Triple ADC, injected simultaneous mode only
21
TripleR
Triple ADC, regular simultaneous mode only
22
TripleI
Triple ADC, interleaved mode only
23
TripleA
Triple ADC, alternate trigger mode only
24
CDR
CDR
ADC common regular data register for dual
and triple modes
0x8
0x20
read-only
0x00000000
DATA2
2nd data item of a pair of regular
conversions
16
16
DATA1
1st data item of a pair of regular
conversions
0
16
TIM1
Advanced-timers
TIM
0x40010000
0x0
0x400
registers
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global
interrupt
24
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global
interrupt
24
TIM1_UP_TIM10
TIM1 Update interrupt and TIM10 global
interrupt
25
TIM1_UP_TIM10
TIM1 Update interrupt and TIM10 global
interrupt
25
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation interrupts and
TIM11 global interrupt
26
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation interrupts and
TIM11 global interrupt
26
TIM1_CC
TIM1 Capture Compare interrupt
27
TIM1_CC
TIM1 Capture Compare interrupt
27
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
4
0x2
1-4
OIS%s
Output Idle state (OC%s output)
8
1
OIS1
Reset
OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
0
Set
OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
1
3
0x2
1-3
OIS%sN
Output Idle state (OC%sN output)
9
1
OIS1N
Reset
OCxN=0 after a dead-time when MOE=0
0
Set
OCxN=1 after a dead-time when MOE=0
1
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
CCUS
Capture/compare control update
selection
2
1
CCPC
Capture/compare preloaded
control
0
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
COMDE
COM DMA request enable
13
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
BIE
Break interrupt enable
7
1
COMIE
COM interrupt enable
5
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
BIF
Break interrupt flag
7
1
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
COMIF
COM interrupt flag
5
1
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
BG
Break generation
7
1
TG
Trigger generation
6
1
TGW
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
COMG
Capture/Compare control update
generation
5
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output
mode)
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
3
0x4
1-3
CC%sNP
Capture/Compare %s output Polarity
3
1
3
0x4
1-3
CC%sNE
Capture/Compare %s complementary output enable
2
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
counter value
0
16
0
65535
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
0
65535
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
0
65535
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
RCR
RCR
repetition counter register
0x30
0x20
read-write
0x00000000
REP
Repetition counter value
0
8
BDTR
BDTR
break and dead-time register
0x44
0x20
read-write
0x00000000
MOE
Main output enable
15
1
MOE
DisabledIdle
OC/OCN are disabled or forced idle depending on OSSI
0
Enabled
OC/OCN are enabled if CCxE/CCxNE are set
1
AOE
Automatic output enable
14
1
AOE
Manual
MOE can be set only by software
0
Automatic
MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
1
BKP
Break polarity
13
1
BKP
ActiveLow
Break input BRKx is active low
0
ActiveHigh
Break input BRKx is active high
1
BKE
Break enable
12
1
BKE
Disabled
Break function x disabled
0
Enabled
Break function x disabled
1
OSSR
Off-state selection for Run
mode
11
1
OSSR
Disabled
When inactive, OC/OCN outputs are disabled
0
IdleLevel
When inactive, OC/OCN outputs are enabled with their inactive level
1
OSSI
Off-state selection for Idle
mode
10
1
OSSI
Disabled
When inactive, OC/OCN outputs are disabled
0
IdleLevel
When inactive, OC/OCN outputs are forced to idle level
1
LOCK
Lock configuration
8
2
LOCK
Off
No bit is write protected
0
Level1
Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
1
Level2
LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
2
Level3
LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
3
DTG
Dead-time generator setup
0
8
0
255
TIM8
TIM
0x40010400
TIM8_BRK_TIM12
TIM8 Break interrupt and TIM12 global
interrupt
43
TIM8_BRK_TIM12
TIM8 Break interrupt and TIM12 global
interrupt
43
TIM8_CC
TIM8 Capture Compare interrupt
46
TIM8_CC
TIM8 Capture Compare interrupt
46
TIM2
General purpose timers
TIM
0x40000000
0x0
0x400
registers
TIM2
TIM2 global interrupt
28
TIM2
TIM2 global interrupt
28
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
TG
Trigger generation
6
1
TGW
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output
mode)
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sNP
Capture/Compare %s output Polarity
3
1
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
Counter value
0
32
0
4294967295
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
32
0
4294967295
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
32
0
4294967295
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
OR
OR
TIM5 option register
0x50
0x20
read-write
0x00000000
ITR1_RMP
Timer Input 4 remap
10
2
ITR1_RMP
TIM8_TRGOUT
TIM8 trigger output is connected to TIM2_ITR1 input
0
PTP
Ethernet PTP clock is connected to TIM2_ITR1 input
1
OTG_FS_SOF
OTG FS SOF is connected to the TIM2_ITR1 input
2
OTG_HS_SOF
OTG HS SOF is connected to the TIM2_ITR1 input
3
TIM3
General purpose timers
TIM
0x40000400
0x0
0x400
registers
TIM3
TIM3 global interrupt
29
TIM3
TIM3 global interrupt
29
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
TG
Trigger generation
6
1
TGW
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output
mode)
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sNP
Capture/Compare %s output Polarity
3
1
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
Counter value
0
16
0
65535
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
0
65535
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
0
65535
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
TIM4
TIM
0x40000800
TIM4
TIM4 global interrupt
30
TIM4
TIM4 global interrupt
30
TIM5
General-purpose-timers
TIM
0x40000C00
0x0
0x400
registers
TIM5
TIM5 global interrupt
50
TIM5
TIM5 global interrupt
50
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
CMS
Center-aligned mode
selection
5
2
CMS
EdgeAligned
The counter counts up or down depending on the direction bit
0
CenterAligned1
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
1
CenterAligned2
The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
2
CenterAligned3
The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
3
DIR
Direction
4
1
DIR
Up
Counter used as upcounter
0
Down
Counter used as downcounter
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
TI1S
TI1 selection
7
1
TI1S
Normal
The TIMx_CH1 pin is connected to TI1 input
0
XOR
The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
1
MMS
Master mode selection
4
3
MMS
Reset
The UG bit from the TIMx_EGR register is used as trigger output
0
Enable
The counter enable signal, CNT_EN, is used as trigger output
1
Update
The update event is selected as trigger output
2
ComparePulse
The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
3
CompareOC1
OC1REF signal is used as trigger output
4
CompareOC2
OC2REF signal is used as trigger output
5
CompareOC3
OC3REF signal is used as trigger output
6
CompareOC4
OC4REF signal is used as trigger output
7
CCDS
Capture/compare DMA
selection
3
1
CCDS
OnCompare
CCx DMA request sent when CCx event occurs
0
OnUpdate
CCx DMA request sent when update event occurs
1
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
ETP
External trigger polarity
15
1
ETP
NotInverted
ETR is noninverted, active at high level or rising edge
0
Inverted
ETR is inverted, active at low level or falling edge
1
ECE
External clock enable
14
1
ECE
Disabled
External clock mode 2 disabled
0
Enabled
External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1
ETPS
External trigger prescaler
12
2
ETPS
Div1
Prescaler OFF
0
Div2
ETRP frequency divided by 2
1
Div4
ETRP frequency divided by 4
2
Div8
ETRP frequency divided by 8
3
ETF
External trigger filter
8
4
ETF
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
MSM
Master/Slave mode
7
1
MSM
NoSync
No action
0
Sync
The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
1
TS
Trigger selection
4
3
TS
ITR0
Internal Trigger 0 (ITR0)
0
ITR1
Internal Trigger 1 (ITR1)
1
ITR2
Internal Trigger 2 (ITR2)
2
TI1F_ED
TI1 Edge Detector (TI1F_ED)
4
TI1FP1
Filtered Timer Input 1 (TI1FP1)
5
TI2FP2
Filtered Timer Input 2 (TI2FP2)
6
ETRF
External Trigger input (ETRF)
7
SMS
Slave mode selection
0
3
SMS
Disabled
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0
Encoder_Mode_1
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
1
Encoder_Mode_2
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
2
Encoder_Mode_3
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
3
Reset_Mode
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
4
Gated_Mode
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
5
Trigger_Mode
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
6
Ext_Clock_Mode
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
7
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TDE
Trigger DMA request enable
14
1
TDE
Disabled
Trigger DMA request disabled
0
Enabled
Trigger DMA request enabled
1
4
0x1
1-4
CC%sDE
Capture/Compare %s DMA request enable
9
1
CC1DE
Disabled
CCx DMA request disabled
0
Enabled
CCx DMA request enabled
1
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
TIE
Trigger interrupt enable
6
1
TIE
Disabled
Trigger interrupt disabled
0
Enabled
Trigger interrupt enabled
1
4
0x1
1-4
CC%sIE
Capture/Compare %s interrupt enable
1
1
CC1IE
Disabled
CCx interrupt disabled
0
Enabled
CCx interrupt enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
4
0x1
1-4
CC%sOF
Capture/Compare %s overcapture flag
9
1
zeroToClear
CC1OFR
read
Overcapture
The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
1
CC1OFW
write
Clear
Clear flag
0
TIF
Trigger interrupt flag
6
1
zeroToClear
TIFR
read
NoTrigger
No trigger event occurred
0
Trigger
Trigger interrupt pending
1
TIFW
write
Clear
Clear flag
0
4
0x1
1-4
CC%sIF
Capture/compare %s interrupt flag
1
1
zeroToClear
CC1IFR
read
Match
If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1
CC1IFW
write
Clear
Clear flag
0
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
TG
Trigger generation
6
1
TGW
Trigger
The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1
4
0x1
1-4
CC%sG
Capture/compare %s generation
1
1
CC1GW
Trigger
If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sCE
Output compare %s clear enable
7
1
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
OC1PE
Disabled
Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
0
Enabled
Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
Output
CC1 channel is configured as output
0
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
4
IC1F
NoFilter
No filter, sampling is done at fDTS
0
FCK_INT_N2
fSAMPLING=fCK_INT, N=2
1
FCK_INT_N4
fSAMPLING=fCK_INT, N=4
2
FCK_INT_N8
fSAMPLING=fCK_INT, N=8
3
FDTS_Div2_N6
fSAMPLING=fDTS/2, N=6
4
FDTS_Div2_N8
fSAMPLING=fDTS/2, N=8
5
FDTS_Div4_N6
fSAMPLING=fDTS/4, N=6
6
FDTS_Div4_N8
fSAMPLING=fDTS/4, N=8
7
FDTS_Div8_N6
fSAMPLING=fDTS/8, N=6
8
FDTS_Div8_N8
fSAMPLING=fDTS/8, N=8
9
FDTS_Div16_N5
fSAMPLING=fDTS/16, N=5
10
FDTS_Div16_N6
fSAMPLING=fDTS/16, N=6
11
FDTS_Div16_N8
fSAMPLING=fDTS/16, N=8
12
FDTS_Div32_N5
fSAMPLING=fDTS/32, N=5
13
FDTS_Div32_N6
fSAMPLING=fDTS/32, N=6
14
FDTS_Div32_N8
fSAMPLING=fDTS/32, N=8
15
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CC1S
TI1
CC1 channel is configured as input, IC1 is mapped on TI1
1
TI2
CC1 channel is configured as input, IC1 is mapped on TI2
2
TRC
CC1 channel is configured as input, IC1 is mapped on TRC
3
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output
mode)
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
OC%sCE
Output compare %s clear enable
7
1
2
0x8
3-4
OC%sM
Output compare %s mode
4
3
OC3M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
3-4
OC%sPE
Output compare %s preload enable
3
1
OC3PE
Disabled
Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
0
Enabled
Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1
2
0x8
3-4
OC%sFE
Output compare %s fast enable
2
1
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
Output
CC3 channel is configured as output
0
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input
mode)
CCMR2_Output
0x1C
0x20
read-write
0x00000000
2
0x8
3-4
IC%sF
Input capture %s filter
4
4
0
15
2
0x8
3-4
IC%sPSC
Input capture %s prescaler
2
2
0
3
2
0x8
3-4
CC%sS
Capture/Compare %s selection
0
2
CC3S
TI3
CC3 channel is configured as input, IC3 is mapped on TI3
1
TI4
CC3 channel is configured as input, IC3 is mapped on TI4
2
TRC
CC3 channel is configured as input, IC3 is mapped on TRC
3
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
4
0x4
1-4
CC%sNP
Capture/Compare %s output Polarity
3
1
4
0x4
1-4
CC%sP
Capture/Compare %s output Polarity
1
1
4
0x4
1-4
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
Counter value
0
32
0
4294967295
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
32
0
4294967295
4
0x4
1-4
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
32
0
4294967295
DCR
DCR
DMA control register
0x48
0x20
read-write
0x00000000
DBL
DMA burst length
8
5
0
18
DBA
DMA base address
0
5
0
31
DMAR
DMAR
DMA address for full transfer
0x4C
0x20
read-write
0x00000000
DMAB
DMA register for burst
accesses
0
16
OR
OR
TIM5 option register
0x50
0x20
read-write
0x00000000
IT4_RMP
Timer Input 4 remap
6
2
TIM9
General purpose timers
TIM
0x40014000
0x0
0x400
registers
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
MMS
Master mode selection
4
3
SMCR
SMCR
slave mode control register
0x8
0x20
read-write
0x00000000
MSM
Master/Slave mode
7
1
TS
Trigger selection
4
3
SMS
Slave mode selection
0
3
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
TIE
Trigger interrupt enable
6
1
2
0x1
1-2
CC%sIE
Capture/Compare %s interrupt enable
1
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
2
0x1
1-2
CC%sOF
Capture/Compare %s overcapture flag
9
1
TIF
Trigger interrupt flag
6
1
2
0x1
1-2
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
TG
Trigger generation
6
1
2
0x1
1-2
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
2
0x8
1-2
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
2
0x8
1-2
OC%sPE
Output compare %s preload enable
3
1
2
0x8
1-2
OC%sFE
Output compare %s fast enable
2
1
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
2
0x8
1-2
IC%sF
Input capture %s filter
4
3
2
0x8
1-2
IC%sPSC
Input capture %s prescaler
2
2
2
0x8
1-2
CC%sS
Capture/Compare %s selection
0
2
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
2
0x4
1-2
CC%sNP
Capture/Compare %s output Polarity
3
1
2
0x4
1-2
CC%sP
Capture/Compare %s output Polarity
1
1
2
0x4
1-2
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
counter value
0
16
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
2
0x4
1-2
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
TIM12
TIM
0x40001800
TIM10
General-purpose-timers
TIM
0x40014400
0x0
0x400
registers
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
1
0x0
1-1
CC%sIE
Capture/Compare %s interrupt enable
1
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
1
0x0
1-1
CC%sOF
Capture/Compare %s overcapture flag
9
1
1
0x0
1-1
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
1
0x0
1-1
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
1
0x0
1-1
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
1
0x0
1-1
OC%sPE
Output compare %s preload enable
3
1
1
0x0
1-1
OC%sFE
Output compare %s fast enable
2
1
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
1
0x0
1-1
IC%sF
Input capture %s filter
4
4
1
0x0
1-1
IC%sPSC
Input capture %s prescaler
2
2
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
1
0x0
1-1
CC%sNP
Capture/Compare %s output Polarity
3
1
1
0x0
1-1
CC%sP
Capture/Compare %s output Polarity
1
1
1
0x0
1-1
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
counter value
0
16
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
1
0x4
1-1
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
TIM13
TIM
0x40001C00
TIM8_UP_TIM13
TIM8 Update interrupt and TIM13 global
interrupt
44
TIM8_UP_TIM13
TIM8 Update interrupt and TIM13 global
interrupt
44
TIM8_UP_TIM13
TIM8 Update interrupt and TIM13 global
interrupt
44
TIM8_UP_TIM13
TIM8 Update interrupt and TIM13 global
interrupt
44
TIM14
TIM
0x40002000
TIM8_TRG_COM_TIM14
TIM8 Trigger and Commutation interrupts and
TIM14 global interrupt
45
TIM8_TRG_COM_TIM14
TIM8 Trigger and Commutation interrupts and
TIM14 global interrupt
45
TIM11
General-purpose-timers
TIM
0x40014800
0x0
0x400
registers
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
CKD
Clock division
8
2
CKD
Div1
t_DTS = t_CK_INT
0
Div2
t_DTS = 2 × t_CK_INT
1
Div4
t_DTS = 4 × t_CK_INT
2
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
1
0x0
1-1
CC%sIE
Capture/Compare %s interrupt enable
1
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
1
0x0
1-1
CC%sOF
Capture/Compare %s overcapture flag
9
1
1
0x0
1-1
CC%sIF
Capture/compare %s interrupt flag
1
1
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
1
0x0
1-1
CC%sG
Capture/compare %s generation
1
1
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output
mode)
0x18
0x20
read-write
0x00000000
1
0x0
1-1
OC%sM
Output compare %s mode
4
3
OC1M
Frozen
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
0
ActiveOnMatch
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1
InactiveOnMatch
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
2
Toggle
OCyREF toggles when TIMx_CNT=TIMx_CCRy
3
ForceInactive
OCyREF is forced low
4
ForceActive
OCyREF is forced high
5
PwmMode1
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
6
PwmMode2
Inversely to PwmMode1
7
1
0x0
1-1
OC%sPE
Output compare %s preload enable
3
1
1
0x0
1-1
OC%sFE
Output compare %s fast enable
2
1
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input
mode)
CCMR1_Output
0x18
0x20
read-write
0x00000000
1
0x0
1-1
IC%sF
Input capture %s filter
4
4
1
0x0
1-1
IC%sPSC
Input capture %s prescaler
2
2
1
0x0
1-1
CC%sS
Capture/Compare %s selection
0
2
CCER
CCER
capture/compare enable
register
0x20
0x20
read-write
0x00000000
1
0x0
1-1
CC%sNP
Capture/Compare %s output Polarity
3
1
1
0x0
1-1
CC%sP
Capture/Compare %s output Polarity
1
1
1
0x0
1-1
CC%sE
Capture/Compare %s output enable
0
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
counter value
0
16
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Auto-reload value
0
16
1
0x4
1-1
CCR%s
CCR%s
capture/compare register
0x34
0x20
read-write
0x00000000
CCR
Capture/Compare value
0
16
OR
OR
option register
0x50
0x20
read-write
0x00000000
RMP
Input 1 remapping
capability
0
2
TIM6
Basic timers
TIM
0x40001000
0x0
0x400
registers
CR1
CR1
control register 1
0x0
0x20
read-write
0x00000000
ARPE
Auto-reload preload enable
7
1
ARPE
Disabled
TIMx_APRR register is not buffered
0
Enabled
TIMx_APRR register is buffered
1
OPM
One-pulse mode
3
1
OPM
Disabled
Counter is not stopped at update event
0
Enabled
Counter stops counting at the next update event (clearing the CEN bit)
1
URS
Update request source
2
1
URS
AnyEvent
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
0
CounterOnly
Only counter overflow/underflow generates an update interrupt or DMA request
1
UDIS
Update disable
1
1
UDIS
Enabled
Update event enabled
0
Disabled
Update event disabled
1
CEN
Counter enable
0
1
CEN
Disabled
Counter disabled
0
Enabled
Counter enabled
1
CR2
CR2
control register 2
0x4
0x20
read-write
0x00000000
MMS
Master mode selection
4
3
MMS
Reset
Use UG bit from TIMx_EGR register
0
Enable
Use CNT bit from TIMx_CEN register
1
Update
Use the update event
2
DIER
DIER
DMA/Interrupt enable register
0xC
0x20
read-write
0x00000000
UDE
Update DMA request enable
8
1
UDE
Disabled
Update DMA request disabled
0
Enabled
Update DMA request enabled
1
UIE
Update interrupt enable
0
1
UIE
Disabled
Update interrupt disabled
0
Enabled
Update interrupt enabled
1
SR
SR
status register
0x10
0x20
read-write
0x00000000
UIF
Update interrupt flag
0
1
zeroToClear
UIFR
read
NoUpdateOccurred
No update occurred
0
UpdatePending
Update interrupt pending
1
UIFW
write
Clear
Clear flag
0
EGR
EGR
event generation register
0x14
0x20
write-only
0x00000000
UG
Update generation
0
1
UG
Update
Re-initializes the timer counter and generates an update of the registers.
1
CNT
CNT
counter
0x24
0x20
read-write
0x00000000
CNT
Low counter value
0
16
0
65535
PSC
PSC
prescaler
0x28
0x20
read-write
0x00000000
PSC
Prescaler value
0
16
0
65535
ARR
ARR
auto-reload register
0x2C
0x20
read-write
0x00000000
ARR
Low Auto-reload value
0
16
0
65535
TIM7
TIM
0x40001400
TIM7
TIM7 global interrupt
55
TIM7
TIM7 global interrupt
55
Ethernet_MAC
Ethernet: media access control
(MAC)
Ethernet
0x40028000
0x0
0x61
registers
ETH
Ethernet global interrupt
61
ETH
Ethernet global interrupt
61
ETH_WKUP
Ethernet Wakeup through EXTI line
interrupt
62
ETH_WKUP
Ethernet Wakeup through EXTI line
interrupt
62
MACCR
MACCR
Ethernet MAC configuration
register
0x0
0x20
read-write
0x00008000
RE
Receiver enable
2
1
RE
Disabled
MAC receive state machine is disabled after the completion of the reception of the current frame
0
Enabled
MAC receive state machine is enabled
1
TE
Transmitter enable
3
1
TE
Disabled
MAC transmit state machine is disabled after completion of the transmission of the current frame
0
Enabled
MAC transmit state machine is enabled
1
DC
Deferral check
4
1
DC
Disabled
MAC defers until CRS signal goes inactive
0
Enabled
Deferral check function enabled
1
BL
Back-off limit
5
2
BL
BL10
For retransmission n, wait up to 2^min(n, 10) time slots
0
BL8
For retransmission n, wait up to 2^min(n, 8) time slots
1
BL4
For retransmission n, wait up to 2^min(n, 4) time slots
2
BL1
For retransmission n, wait up to 2^min(n, 1) time slots
3
APCS
Automatic pad/CRC stripping
7
1
APCS
Disabled
MAC passes all incoming frames unmodified
0
Strip
MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes
1
RD
Retry disable
9
1
RD
Enabled
MAC attempts retries based on the settings of BL
0
Disabled
MAC attempts only 1 transmission
1
IPCO
IPv4 checksum offload
10
1
IPCO
Disabled
IPv4 checksum offload disabled
0
Offload
IPv4 checksums are checked in received frames
1
DM
Duplex mode
11
1
DM
HalfDuplex
MAC operates in half-duplex mode
0
FullDuplex
MAC operates in full-duplex mode
1
LM
Loopback mode
12
1
LM
Normal
Normal mode
0
Loopback
MAC operates in loopback mode at the MII
1
ROD
Receive own disable
13
1
ROD
Enabled
MAC receives all packets from PHY while transmitting
0
Disabled
MAC disables reception of frames in half-duplex mode
1
FES
Fast Ethernet speed
14
1
FES
FES10
10 Mbit/s
0
FES100
100 Mbit/s
1
CSD
Carrier sense disable
16
1
CSD
Enabled
Errors generated due to loss of carrier
0
Disabled
No error generated due to loss of carrier
1
IFG
Interframe gap
17
3
IFG
IFG96
96 bit times
0
IFG88
88 bit times
1
IFG80
80 bit times
2
IFG72
72 bit times
3
IFG64
64 bit times
4
IFG56
56 bit times
5
IFG48
48 bit times
6
IFG40
40 bit times
7
JD
Jabber disable
22
1
JD
Enabled
Jabber enabled, transmit frames up to 2048 bytes
0
Disabled
Jabber disabled, transmit frames up to 16384 bytes
1
WD
Watchdog disable
23
1
WD
Enabled
Watchdog enabled, receive frames limited to 2048 bytes
0
Disabled
Watchdog disabled, receive frames may be up to to 16384 bytes
1
CSTF
CRC stripping for type frames
25
1
CSTF
Disabled
CRC not stripped
0
Enabled
CRC stripped
1
MACFFR
MACFFR
Ethernet MAC frame filter
register
0x4
0x20
read-write
0x00000000
PM
Promiscuous mode
0
1
PM
Disabled
Normal address filtering
0
Enabled
Address filters pass all incoming frames regardless of their destination or source address
1
HU
Hash unicast
1
1
HU
Perfect
MAC performs a perfect destination address filtering for unicast frames
0
Hash
MAC performs destination address filtering of received unicast frames according to the hash table
1
HM
Hash multicast
2
1
HM
Perfect
MAC performs a perfect destination address filtering for multicast frames
0
Hash
MAC performs destination address filtering of received multicast frames according to the hash table
1
DAIF
Destination address unique filtering
3
1
DAIF
Normal
Normal filtering of frames
0
Invert
Address check block operates in inverse filtering mode for the DA address comparison
1
PAM
Pass all multicast
4
1
PAM
Disabled
Filtering of multicast frames depends on HM
0
Enabled
All received frames with a multicast destination address are passed
1
BFD
Broadcast frames disable
5
1
BFD
Enabled
Address filters pass all received broadcast frames
0
Disabled
Address filters filter all incoming broadcast frames
1
PCF
Pass control frames
6
2
PCF
PreventAll
MAC prevents all control frames from reaching the application
0
ForwardAllExceptPause
MAC forwards all control frames to application except Pause
1
ForwardAll
MAC forwards all control frames to application even if they fail the address filter
2
ForwardAllFiltered
MAC forwards control frames that pass the address filter
3
SAIF
Source address inverse filtering
8
1
SAIF
Normal
Source address filter operates normally
0
Invert
Source address filter operation inverted
1
SAF
Source address filter
9
1
SAF
Disabled
Source address ignored
0
Enabled
MAC drops frames that fail the source address filter
1
HPF
Hash or perfect filter
10
1
HPF
HashOnly
If HM or HU is set, only frames that match the Hash filter are passed
0
HashOrPerfect
If HM or HU is set, frames that match either the perfect filter or the hash filter are passed
1
RA
Receive all
31
1
RA
Disabled
MAC receiver passes on to the application only those frames that have passed the SA/DA address file
0
Enabled
MAC receiver passes oll received frames on to the application
1
MACHTHR
MACHTHR
Ethernet MAC hash table high
register
0x8
0x20
read-write
0x00000000
HTH
Upper 32 bits of hash table
0
32
0
4294967295
MACHTLR
MACHTLR
Ethernet MAC hash table low
register
0xC
0x20
read-write
0x00000000
HTL
Lower 32 bits of hash table
0
32
0
4294967295
MACMIIAR
MACMIIAR
Ethernet MAC MII address
register
0x10
0x20
read-write
0x00000000
MB
MII busy
0
1
MB
Busy
This bit is set to 1 by the application to indicate that a read or write access is in progress
1
MW
MII write
1
1
MW
Read
Read operation
0
Write
Write operation
1
CR
Clock range
2
3
CR
CR_60_100
60-100MHz HCLK/42
0
CR_100_150
100-150 MHz HCLK/62
1
CR_20_35
20-35MHz HCLK/16
2
CR_35_60
35-60MHz HCLK/16
3
CR_150_168
150-168MHz HCLK/102
4
MR
MII register - select the desired MII register in the PHY device
6
5
0
31
PA
PHY address - select which of possible 32 PHYs is being accessed
11
5
0
31
MACMIIDR
MACMIIDR
Ethernet MAC MII data register
0x14
0x20
read-write
0x00000000
MD
MII data read from/written to the PHY
0
16
0
65535
MACFCR
MACFCR
Ethernet MAC flow control
register
0x18
0x20
read-write
0x00000000
FCB
Flow control busy/back pressure activate
0
1
FCB
DisableBackPressure
In half duplex only, deasserts back pressure
0
PauseOrBackPressure
In full duplex, initiate a Pause control frame. In half duplex, assert back pressure
1
TFCE
Transmit flow control enable
1
1
TFCE
Disabled
In full duplex, flow control is disabled. In half duplex, back pressure is disabled
0
Enabled
In full duplex, flow control is enabled. In half duplex, back pressure is enabled
1
RFCE
Receive flow control enable
2
1
RFCE
Disabled
Pause frames are not decoded
0
Enabled
MAC decodes received Pause frames and disables its transmitted for a specified time
1
UPFD
Unicast pause frame detect
3
1
UPFD
Disabled
MAC detects only a Pause frame with the multicast address specified in the 802.3x standard
0
Enabled
MAC additionally detects Pause frames with the station's unicast address
1
PLT
Pause low threshold
4
2
PLT
PLT4
Pause time minus 4 slot times
0
PLT28
Pause time minus 28 slot times
1
PLT144
Pause time minus 144 slot times
2
PLT256
Pause time minus 256 slot times
3
ZQPD
Zero-quanta pause disable
7
1
ZQPD
Enabled
Normal operation with automatic zero-quanta pause control frame generation
0
Disabled
Automatic generation of zero-quanta pause control frames is disabled
1
PT
Pause time
16
16
0
65535
MACVLANTR
MACVLANTR
Ethernet MAC VLAN tag register
0x1C
0x20
read-write
0x00000000
VLANTI
VLAN tag identifier (for receive frames)
0
16
0
65535
VLANTC
12-bit VLAN tag comparison
16
1
VLANTC
VLANTC16
Full 16 bit VLAN identifiers are used for comparison and filtering
0
VLANTC12
12 bit VLAN identifies are used for comparison and filtering
1
MACPMTCSR
MACPMTCSR
Ethernet MAC PMT control and status
register
0x2C
0x20
read-write
0x00000000
PD
Power down
0
1
PD
Enabled
All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received
1
MPE
Magic packet enable
1
1
MPE
Disabled
No power management event generated due to Magic Packet reception
0
Enabled
Enable generation of a power management event due to Magic Packet reception
1
WFE
Wakeup frame enable
2
1
WFE
Disabled
No power management event generated due to wakeup frame reception
0
Enabled
Enable generation of a power management event due to wakeup frame reception
1
MPR
Magic packet received
5
1
WFR
Wakeup frame received
6
1
GU
Global unicast
9
1
GU
Disabled
Normal operation
0
Enabled
Any unicast packet filtered by the MAC address recognition may be a wakeup frame
1
WFFRPR
Wakeup frame filter register pointer reset
31
1
WFFRPR
Reset
Reset wakeup frame filter register point to 0b000. Automatically cleared
1
MACDBGR
MACDBGR
Ethernet MAC debug register
0x34
0x20
read-only
0x00000000
TFF
Tx FIFO full
25
1
TFNE
Tx FIFO not empty
24
1
TFWA
Tx FIFO write active
22
1
TFRS
Tx FIFO read status
20
2
MTP
MAC transmitter in pause
19
1
MTFCS
MAC transmit frame controller status
17
2
MMTEA
MAC MII transmit engine active
16
1
RFFL
Rx FIFO fill level
8
2
RFRCS
Rx FIFO read controller status
5
2
RFWRA
Rx FIFO write controller active
4
1
MSFRWCS
MAC small FIFO read/write controllers status
1
2
MMRPEA
MAC MII receive protocol engine active
0
1
MACSR
MACSR
Ethernet MAC interrupt status
register
0x38
0x20
0x00000000
PMTS
PMT status
3
1
read-only
MMCS
MMC status
4
1
read-only
MMCRS
MMC receive status
5
1
read-only
MMCTS
MMC transmit status
6
1
read-only
TSTS
Time stamp trigger status
9
1
read-write
MACIMR
MACIMR
Ethernet MAC interrupt mask
register
0x3C
0x20
read-write
0x00000000
PMTIM
PMT interrupt mask
3
1
PMTIM
Unmasked
PMT Status interrupt generation enabled
0
Masked
PMT Status interrupt generation disabled
1
TSTIM
Time stamp trigger interrupt mask
9
1
TSTIM
Unmasked
Time stamp interrupt generation enabled
0
Masked
Time stamp interrupt generation disabled
1
MACA0HR
MACA0HR
Ethernet MAC address 0 high
register
0x40
0x20
0x0010FFFF
MACA0H
MAC address0 high
0
16
read-write
0
65535
MO
Always 1
31
1
read-only
MACA0LR
MACA0LR
Ethernet MAC address 0 low
register
0x44
0x20
read-write
0xFFFFFFFF
MACA0L
0
0
32
0
4294967295
MACA1HR
MACA1HR
Ethernet MAC address 1 high
register
0x48
0x20
read-write
0x0000FFFF
MACA1H
MACA1H
0
16
0
65535
MBC
MBC
24
6
0
63
SA
SA
30
1
SA
Destination
This address is used for comparison with DA fields of the received frame
0
Source
This address is used for comparison with SA fields of received frames
1
AE
AE
31
1
AE
Disabled
Address filters ignore this address
0
Enabled
Address filters use this address
1
MACA1LR
MACA1LR
Ethernet MAC address1 low
register
0x4C
0x20
read-write
0xFFFFFFFF
MACA1L
MACA1LR
0
32
0
4294967295
MACA2HR
MACA2HR
Ethernet MAC address 2 high
register
0x50
0x20
read-write
0x0000FFFF
MACA2H
MAC2AH
0
16
0
65535
MBC
MBC
24
6
0
63
SA
SA
30
1
SA
Destination
This address is used for comparison with DA fields of the received frame
0
Source
This address is used for comparison with SA fields of received frames
1
AE
AE
31
1
AE
Disabled
Address filters ignore this address
0
Enabled
Address filters use this address
1
MACA2LR
MACA2LR
Ethernet MAC address 2 low
register
0x54
0x20
read-write
0xFFFFFFFF
MACA2L
MACA2L
0
32
0
4294967295
MACA3HR
MACA3HR
Ethernet MAC address 3 high
register
0x58
0x20
read-write
0x0000FFFF
MACA3H
MACA3H
0
16
0
65535
MBC
MBC
24
6
0
63
SA
SA
30
1
SA
Destination
This address is used for comparison with DA fields of the received frame
0
Source
This address is used for comparison with SA fields of received frames
1
AE
AE
31
1
AE
Disabled
Address filters ignore this address
0
Enabled
Address filters use this address
1
MACA3LR
MACA3LR
Ethernet MAC address 3 low
register
0x5C
0x20
read-write
0xFFFFFFFF
MACA3L
MBCA3L
0
32
0
4294967295
Ethernet_MMC
Ethernet: MAC management counters
Ethernet
0x40028100
0x0
0x400
registers
MMCCR
MMCCR
Ethernet MMC control register
0x0
0x20
read-write
0x00000000
CR
Counter reset
0
1
CR
Reset
Reset all counters. Cleared automatically
1
CSR
Counter stop rollover
1
1
CSR
Disabled
Counters roll over to zero after reaching the maximum value
0
Enabled
Counters do not roll over to zero after reaching the maximum value
1
ROR
Reset on read
2
1
ROR
Disabled
MMC counters do not reset on read
0
Enabled
MMC counters reset to zero after read
1
MCF
MMC counter freeze
3
1
MCF
Unfrozen
All MMC counters update normally
0
Frozen
All MMC counters frozen to their current value
1
MCP
MMC counter preset
4
1
MCP
Preset
MMC counters will be preset to almost full or almost half. Cleared automatically
1
MCFHP
MMC counter Full-Half preset
5
1
MCFHP
AlmostHalf
When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0
0
AlmostFull
When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0
1
MMCRIR
MMCRIR
Ethernet MMC receive interrupt
register
0x4
0x20
read-write
0x00000000
RFCES
Received frames CRC error status
5
1
RFAES
Received frames alignment error status
6
1
RGUFS
Received good Unicast frames status
17
1
MMCTIR
MMCTIR
Ethernet MMC transmit interrupt
register
0x8
0x20
read-only
0x00000000
TGFSCS
Transmitted good frames single collision status
14
1
TGFMSCS
Transmitted good frames more than single collision status
15
1
TGFS
Transmitted good frames status
21
1
MMCRIMR
MMCRIMR
Ethernet MMC receive interrupt mask
register
0xC
0x20
read-write
0x00000000
RFCEM
Received frame CRC error mask
5
1
RFCEM
Unmasked
Received-crc-error counter half-full interrupt enabled
0
Masked
Received-crc-error counter half-full interrupt disabled
1
RFAEM
Received frames alignment error mask
6
1
RFAEM
Unmasked
Received-alignment-error counter half-full interrupt enabled
0
Masked
Received-alignment-error counter half-full interrupt disabled
1
RGUFM
Received good Unicast frames mask
17
1
RGUFM
Unmasked
Received-good-unicast counter half-full interrupt enabled
0
Masked
Received-good-unicast counter half-full interrupt disabled
1
MMCTIMR
MMCTIMR
Ethernet MMC transmit interrupt mask
register
0x10
0x20
read-write
0x00000000
TGFSCM
Transmitted good frames single collision mask
14
1
TGFSCM
Unmasked
Transmitted-good-single-collision half-full interrupt enabled
0
Masked
Transmitted-good-single-collision half-full interrupt disabled
1
TGFMSCM
Transmitted good frames more than single collision mask
15
1
TGFMSCM
Unmasked
Transmitted-good-multiple-collision half-full interrupt enabled
0
Masked
Transmitted-good-multiple-collision half-full interrupt disabled
1
TGFM
Transmitted good frames mask
21
1
TGFM
Unmasked
Transmitted-good counter half-full interrupt enabled
0
Masked
Transmitted-good counter half-full interrupt disabled
1
MMCTGFSCCR
MMCTGFSCCR
Ethernet MMC transmitted good frames after a
single collision counter
0x4C
0x20
read-only
0x00000000
TGFSCC
Transmitted good frames single collision counter
0
32
MMCTGFMSCCR
MMCTGFMSCCR
Ethernet MMC transmitted good frames after
more than a single collision
0x50
0x20
read-only
0x00000000
TGFMSCC
TGFMSCC
0
32
MMCTGFCR
MMCTGFCR
Ethernet MMC transmitted good frames counter
register
0x68
0x20
read-only
0x00000000
TGFC
HTL
0
32
MMCRFCECR
MMCRFCECR
Ethernet MMC received frames with CRC error
counter register
0x94
0x20
read-only
0x00000000
RFCFC
RFCFC
0
32
MMCRFAECR
MMCRFAECR
Ethernet MMC received frames with alignment
error counter register
0x98
0x20
read-only
0x00000000
RFAEC
RFAEC
0
32
MMCRGUFCR
MMCRGUFCR
MMC received good unicast frames counter
register
0xC4
0x20
read-only
0x00000000
RGUFC
RGUFC
0
32
Ethernet_PTP
Ethernet: Precision time protocol
Ethernet
0x40028700
0x0
0x400
registers
PTPTSCR
PTPTSCR
Ethernet PTP time stamp control
register
0x0
0x20
read-write
0x00002000
TSE
TSE
0
1
TSFCU
TSFCU
1
1
TSPTPPSV2E
TSPTPPSV2E
10
1
TSSPTPOEFE
TSSPTPOEFE
11
1
TSSIPV6FE
TSSIPV6FE
12
1
TSSIPV4FE
TSSIPV4FE
13
1
TSSEME
TSSEME
14
1
TSSMRME
TSSMRME
15
1
TSCNT
TSCNT
16
2
TSPFFMAE
TSPFFMAE
18
1
TSSTI
TSSTI
2
1
TSSTU
TSSTU
3
1
TSITE
TSITE
4
1
TTSARU
TTSARU
5
1
TSSARFE
TSSARFE
8
1
TSSSR
TSSSR
9
1
PTPSSIR
PTPSSIR
Ethernet PTP subsecond increment
register
0x4
0x20
read-write
0x00000000
STSSI
STSSI
0
8
PTPTSHR
PTPTSHR
Ethernet PTP time stamp high
register
0x8
0x20
read-only
0x00000000
STS
STS
0
32
PTPTSLR
PTPTSLR
Ethernet PTP time stamp low
register
0xC
0x20
read-only
0x00000000
STSS
STSS
0
31
STPNS
STPNS
31
1
PTPTSHUR
PTPTSHUR
Ethernet PTP time stamp high update
register
0x10
0x20
read-write
0x00000000
TSUS
TSUS
0
32
PTPTSLUR
PTPTSLUR
Ethernet PTP time stamp low update
register
0x14
0x20
read-write
0x00000000
TSUSS
TSUSS
0
31
TSUPNS
TSUSS
31
1
PTPTSAR
PTPTSAR
Ethernet PTP time stamp addend
register
0x18
0x20
read-write
0x00000000
TSA
TSA
0
32
PTPTTHR
PTPTTHR
Ethernet PTP target time high
register
0x1C
0x20
read-write
0x00000000
TTSH
0
0
32
PTPTTLR
PTPTTLR
Ethernet PTP target time low
register
0x20
0x20
read-write
0x00000000
TTSL
TTSL
0
32
PTPTSSR
PTPTSSR
Ethernet PTP time stamp status
register
0x28
0x20
read-only
0x00000000
TSSO
TSSO
0
1
TSTTR
TSTTR
1
1
PTPPPSCR
PTPPPSCR
Ethernet PTP PPS control
register
0x2C
0x20
read-only
0x00000000
PPSFREQ
PPS frequency selection
0
4
read-write
PPSFREQ
Hz_1
1 Hz with a pulse width of 125 ms for binary rollover and of 100 ms for digital rollover
0
Hz_2
2 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
1
Hz_4
4 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
2
Hz_8
8 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
3
Hz_16
16 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
4
Hz_32
32 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
5
Hz_64
64 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
6
Hz_128
128 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
7
Hz_256
256 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
8
Hz_512
512 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
9
Hz_1024
1024 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
10
Hz_2048
2048 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
11
Hz_4096
4096 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
12
Hz_8192
8192 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
13
Hz_16384
16384 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
14
Hz_32768
32768 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
15
Ethernet_DMA
Ethernet: DMA controller operation
Ethernet
0x40029000
0x0
0x400
registers
DMABMR
DMABMR
Ethernet DMA bus mode register
0x0
0x20
read-write
0x00002101
SR
Software reset
0
1
SR
Reset
Reset all MAC subsystem internal registers and logic. Cleared automatically
1
DA
DMA arbitration
1
1
DA
RoundRobin
Round-robin with Rx:Tx priority given by PM
0
RxPriority
Rx has priority over Tx
1
DSL
Descriptor skip length
2
5
0
31
EDFE
Enhanced descriptor format enable
7
1
EDFE
Disabled
Normal descriptor format
0
Enabled
Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload
1
PBL
Programmable burst length
8
6
PBL
PBL1
Maximum of 1 beat per DMA transaction
1
PBL2
Maximum of 2 beats per DMA transaction
2
PBL4
Maximum of 4 beats per DMA transaction
4
PBL8
Maximum of 8 beats per DMA transaction
8
PBL16
Maximum of 16 beats per DMA transaction
16
PBL32
Maximum of 32 beats per DMA transaction
32
PM
Rx-Tx priority ratio
14
2
PM
OneToOne
RxDMA priority over TxDMA is 1:1
0
TwoToOne
RxDMA priority over TxDMA is 2:1
1
ThreeToOne
RxDMA priority over TxDMA is 3:1
2
FourToOne
RxDMA priority over TxDMA is 4:1
3
FB
Fixed burst
16
1
FB
Variable
AHB uses SINGLE and INCR burst transfers
0
Fixed
AHB uses only fixed burst transfers
1
RDP
Rx DMA PBL
17
6
RDP
RDP1
1 beat per RxDMA transaction
1
RDP2
2 beats per RxDMA transaction
2
RDP4
4 beats per RxDMA transaction
4
RDP8
8 beats per RxDMA transaction
8
RDP16
16 beats per RxDMA transaction
16
RDP32
32 beats per RxDMA transaction
32
USP
Use separate PBL
23
1
USP
Combined
PBL value used for both Rx and Tx DMA
0
Separate
RxDMA uses RDP value, TxDMA uses PBL value
1
FPM
4xPBL mode
24
1
FPM
x1
PBL values used as-is
0
x4
PBL values multiplied by 4
1
AAB
Address-aligned beats
25
1
AAB
Unaligned
Bursts are not aligned
0
Aligned
Align bursts to start address LS bits. First burst alignment depends on FB bit
1
MB
Mixed burst
26
1
MB
Normal
Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below
0
Mixed
If FB is low, start all bursts greater than 16 with INCR (undefined burst)
1
DMATPDR
DMATPDR
Ethernet DMA transmit poll demand
register
0x4
0x20
read-write
0x00000000
TPD
Transmit poll demand
0
32
TPD
Poll
Poll the transmit descriptor list
0
DMARPDR
DMARPDR
EHERNET DMA receive poll demand
register
0x8
0x20
read-write
0x00000000
RPD
Receive poll demand
0
32
RPD
Poll
Poll the receive descriptor list
0
DMARDLAR
DMARDLAR
Ethernet DMA receive descriptor list address
register
0xC
0x20
read-write
0x00000000
SRL
Start of receive list
0
32
DMATDLAR
DMATDLAR
Ethernet DMA transmit descriptor list
address register
0x10
0x20
read-write
0x00000000
STL
Start of transmit list
0
32
DMASR
DMASR
Ethernet DMA status register
0x14
0x20
0x00000000
TS
Transmit status
0
1
read-write
TPSS
Transmit process stopped status
1
1
read-write
TBUS
Transmit buffer unavailable status
2
1
read-write
TJTS
Transmit jabber timeout status
3
1
read-write
ROS
Receive overflow status
4
1
read-write
TUS
Transmit underflow status
5
1
read-write
RS
Receive status
6
1
read-write
RBUS
Receive buffer unavailable status
7
1
read-write
RPSS
Receive process stopped status
8
1
read-write
PWTS
PWTS
9
1
read-write
ETS
Early transmit status
10
1
read-write
FBES
Fatal bus error status
13
1
read-write
ERS
Early receive status
14
1
read-write
AIS
Abnormal interrupt summary
15
1
read-write
NIS
Normal interrupt summary
16
1
read-write
RPS
Receive process state
17
3
read-only
RPS
Stopped
Stopped, reset or Stop Receive command issued
0
RunningFetching
Running, fetching receive transfer descriptor
1
RunningWaiting
Running, waiting for receive packet
3
Suspended
Suspended, receive descriptor unavailable
4
RunningWriting
Running, writing data to host memory buffer
7
TPS
Transmit process state
20
3
read-only
TPS
Stopped
Stopped, Reset or Stop Transmit command issued
0
RunningFetching
Running, fetching transmit transfer descriptor
1
RunningWaiting
Running, waiting for status
2
RunningReading
Running, reading data from host memory buffer
3
Suspended
Suspended, transmit descriptor unavailable or transmit buffer underflow
6
Running
Running, closing transmit descriptor
7
EBS
Error bits status
23
3
read-only
MMCS
MMC status
27
1
read-only
PMTS
PMT status
28
1
read-only
TSTS
Time stamp trigger status
29
1
read-only
DMAOMR
DMAOMR
Ethernet DMA operation mode
register
0x18
0x20
read-write
0x00000000
SR
Start/stop receive
1
1
SR
Stopped
Reception is stopped after transfer of the current frame
0
Started
Reception is placed in the Running state
1
OSF
Operate on second frame
2
1
RTC
Receive threshold control
3
2
RTC
RTC64
64 bytes
0
RTC32
32 bytes
1
RTC96
96 bytes
2
RTC128
128 bytes
3
FUGF
Forward undersized good frames
6
1
FUGF
Drop
Rx FIFO drops all frames of less than 64 bytes
0
Forward
Rx FIFO forwards undersized frames
1
FEF
Forward error frames
7
1
FEF
Drop
Rx FIFO drops frames with error status
0
Forward
All frames except runt error frames are forwarded to the DMA
1
ST
Start/stop transmission
13
1
ST
Stopped
Transmission is placed in the Stopped state
0
Started
Transmission is placed in Running state
1
TTC
Transmit threshold control
14
3
TTC
TTC64
64 bytes
0
TTC128
128 bytes
1
TTC192
192 bytes
2
TTC256
256 bytes
3
TTC40
40 bytes
4
TTC32
32 bytes
5
TTC24
24 bytes
6
TTC16
16 bytes
7
FTF
Flush transmit FIFO
20
1
FTF
Flush
Transmit FIFO controller logic is reset to its default values. Cleared automatically
1
TSF
Transmit store and forward
21
1
TSF
CutThrough
Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold
0
StoreForward
Transmission starts when a full frame is in the Tx FIFO
1
DFRF
Disable flushing of received frames
24
1
RSF
Receive store and forward
25
1
RSF
CutThrough
Rx FIFO operates in cut-through mode, subject to RTC bits
0
StoreForward
Frames are read from Rx FIFO after complete frame has been written
1
DTCEFD
Dropping of TCP/IP checksum error frames disable
26
1
DTCEFD
Enabled
Drop frames with errors only in the receive checksum offload engine
0
Disabled
Do not drop frames that only have errors in the receive checksum offload engine
1
DMAIER
DMAIER
Ethernet DMA interrupt enable
register
0x1C
0x20
read-write
0x00000000
TIE
Transmit interrupt enable
0
1
TPSIE
Transmit process stopped interrupt enable
1
1
TBUIE
Transmit buffer unavailable interrupt enable
2
1
TJTIE
Transmit jabber timeout interrupt enable
3
1
ROIE
Receive overflow interrupt enable
4
1
TUIE
Transmit underflow interrupt enable
5
1
RIE
Receive interrupt enable
6
1
RBUIE
Receive buffer unavailable interrupt enable
7
1
RPSIE
Receive process stopped interrupt enable
8
1
RWTIE
Receive watchdog timeout interrupt enable
9
1
ETIE
Early transmit interrupt enable
10
1
FBEIE
Fatal bus error interrupt enable
13
1
ERIE
Early receive interrupt enable
14
1
AISE
Abnormal interrupt summary enable
15
1
NISE
Normal interrupt summary enable
16
1
DMAMFBOCR
DMAMFBOCR
Ethernet DMA missed frame and buffer
overflow counter register
0x20
0x20
read-write
0x00000000
MFC
Missed frames by the controller
0
16
OMFC
Overflow bit for missed frame counter
16
1
MFA
Missed frames by the application
17
11
OFOC
Overflow bit for FIFO overflow counter
28
1
DMARSWTR
DMARSWTR
Ethernet DMA receive status watchdog timer
register
0x24
0x20
read-write
0x00000000
RSWTC
Receive status watchdog timer count
0
8
0
255
DMACHTDR
DMACHTDR
Ethernet DMA current host transmit
descriptor register
0x48
0x20
read-only
0x00000000
HTDAP
Host transmit descriptor address pointer
0
32
DMACHRDR
DMACHRDR
Ethernet DMA current host receive descriptor
register
0x4C
0x20
read-only
0x00000000
HRDAP
Host receive descriptor address pointer
0
32
DMACHTBAR
DMACHTBAR
Ethernet DMA current host transmit buffer
address register
0x50
0x20
read-only
0x00000000
HTBAP
Host transmit buffer address pointer
0
32
DMACHRBAR
DMACHRBAR
Ethernet DMA current host receive buffer
address register
0x54
0x20
read-only
0x00000000
HRBAP
Host receive buffer address pointer
0
32
CRC
Cryptographic processor
CRC
0x40023000
0x0
0x400
registers
DR
DR
Data register
0x0
0x20
read-write
0xFFFFFFFF
DR
Data Register
0
32
0
4294967295
IDR
IDR
Independent Data register
0x4
0x20
read-write
0x00000000
IDR
Independent Data register
0
8
0
255
CR
CR
Control register
0x8
0x20
write-only
0x00000000
RESET
Control regidter
0
1
RESETW
Reset
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
1
OTG_FS_GLOBAL
USB on the go full speed
USB_OTG_FS
0x50000000
0x0
0x400
registers
OTG_FS_WKUP
USB On-The-Go FS Wakeup through EXTI line
interrupt
42
OTG_FS_WKUP
USB On-The-Go FS Wakeup through EXTI line
interrupt
42
OTG_FS
USB On The Go FS global
interrupt
67
OTG_FS
USB On The Go FS global
interrupt
67
GOTGCTL
GOTGCTL
OTG_FS control and status register
(OTG_FS_GOTGCTL)
0x0
0x20
0x00000800
SRQSCS
Session request success
0
1
read-only
SRQ
Session request
1
1
read-write
HNGSCS
Host negotiation success
8
1
read-only
HNPRQ
HNP request
9
1
read-write
HSHNPEN
Host set HNP enable
10
1
read-write
DHNPEN
Device HNP enabled
11
1
read-write
CIDSTS
Connector ID status
16
1
read-only
DBCT
Long/short debounce time
17
1
read-only
ASVLD
A-session valid
18
1
read-only
BSVLD
B-session valid
19
1
read-only
GOTGINT
GOTGINT
OTG_FS interrupt register
(OTG_FS_GOTGINT)
0x4
0x20
read-write
0x00000000
SEDET
Session end detected
2
1
SRSSCHG
Session request success status
change
8
1
HNSSCHG
Host negotiation success status
change
9
1
HNGDET
Host negotiation detected
17
1
ADTOCHG
A-device timeout change
18
1
DBCDNE
Debounce done
19
1
GAHBCFG
GAHBCFG
OTG_FS AHB configuration register
(OTG_FS_GAHBCFG)
0x8
0x20
read-write
0x00000000
GINT
Global interrupt mask
0
1
TXFELVL
TxFIFO empty level
7
1
PTXFELVL
Periodic TxFIFO empty
level
8
1
GUSBCFG
GUSBCFG
OTG_FS USB configuration register
(OTG_FS_GUSBCFG)
0xC
0x20
0x00000A00
TOCAL
FS timeout calibration
0
3
read-write
PHYSEL
Full Speed serial transceiver
select
6
1
write-only
SRPCAP
SRP-capable
8
1
read-write
HNPCAP
HNP-capable
9
1
read-write
TRDT
USB turnaround time
10
4
read-write
FHMOD
Force host mode
29
1
read-write
FDMOD
Force device mode
30
1
read-write
CTXPKT
Corrupt Tx packet
31
1
read-write
GRSTCTL
GRSTCTL
OTG_FS reset register
(OTG_FS_GRSTCTL)
0x10
0x20
0x20000000
CSRST
Core soft reset
0
1
read-write
HSRST
HCLK soft reset
1
1
read-write
FCRST
Host frame counter reset
2
1
read-write
RXFFLSH
RxFIFO flush
4
1
read-write
TXFFLSH
TxFIFO flush
5
1
read-write
TXFNUM
TxFIFO number
6
5
read-write
AHBIDL
AHB master idle
31
1
read-only
GINTSTS
GINTSTS
OTG_FS core interrupt register
(OTG_FS_GINTSTS)
0x14
0x20
0x04000020
CMOD
Current mode of operation
0
1
read-only
MMIS
Mode mismatch interrupt
1
1
read-write
OTGINT
OTG interrupt
2
1
read-only
SOF
Start of frame
3
1
read-write
RXFLVL
RxFIFO non-empty
4
1
read-only
NPTXFE
Non-periodic TxFIFO empty
5
1
read-only
GINAKEFF
Global IN non-periodic NAK
effective
6
1
read-only
GOUTNAKEFF
Global OUT NAK effective
7
1
read-only
ESUSP
Early suspend
10
1
read-write
USBSUSP
USB suspend
11
1
read-write
USBRST
USB reset
12
1
read-write
ENUMDNE
Enumeration done
13
1
read-write
ISOODRP
Isochronous OUT packet dropped
interrupt
14
1
read-write
EOPF
End of periodic frame
interrupt
15
1
read-write
IEPINT
IN endpoint interrupt
18
1
read-only
OEPINT
OUT endpoint interrupt
19
1
read-only
IISOIXFR
Incomplete isochronous IN
transfer
20
1
read-write
IPXFR_INCOMPISOOUT
Incomplete periodic transfer(Host
mode)/Incomplete isochronous OUT transfer(Device
mode)
21
1
read-write
HPRTINT
Host port interrupt
24
1
read-only
HCINT
Host channels interrupt
25
1
read-only
PTXFE
Periodic TxFIFO empty
26
1
read-only
CIDSCHG
Connector ID status change
28
1
read-write
DISCINT
Disconnect detected
interrupt
29
1
read-write
SRQINT
Session request/new session detected
interrupt
30
1
read-write
WKUPINT
Resume/remote wakeup detected
interrupt
31
1
read-write
GINTMSK
GINTMSK
OTG_FS interrupt mask register
(OTG_FS_GINTMSK)
0x18
0x20
0x00000000
MMISM
Mode mismatch interrupt
mask
1
1
read-write
OTGINT
OTG interrupt mask
2
1
read-write
SOFM
Start of frame mask
3
1
read-write
RXFLVLM
Receive FIFO non-empty
mask
4
1
read-write
NPTXFEM
Non-periodic TxFIFO empty
mask
5
1
read-write
GINAKEFFM
Global non-periodic IN NAK effective
mask
6
1
read-write
GONAKEFFM
Global OUT NAK effective
mask
7
1
read-write
ESUSPM
Early suspend mask
10
1
read-write
USBSUSPM
USB suspend mask
11
1
read-write
USBRST
USB reset mask
12
1
read-write
ENUMDNEM
Enumeration done mask
13
1
read-write
ISOODRPM
Isochronous OUT packet dropped interrupt
mask
14
1
read-write
EOPFM
End of periodic frame interrupt
mask
15
1
read-write
EPMISM
Endpoint mismatch interrupt
mask
17
1
read-write
IEPINT
IN endpoints interrupt
mask
18
1
read-write
OEPINT
OUT endpoints interrupt
mask
19
1
read-write
IISOIXFRM
Incomplete isochronous IN transfer
mask
20
1
read-write
IPXFRM_IISOOXFRM
Incomplete periodic transfer mask(Host
mode)/Incomplete isochronous OUT transfer mask(Device
mode)
21
1
read-write
PRTIM
Host port interrupt mask
24
1
read-write
HCIM
Host channels interrupt
mask
25
1
read-write
PTXFEM
Periodic TxFIFO empty mask
26
1
read-write
CIDSCHGM
Connector ID status change
mask
28
1
read-write
DISCINT
Disconnect detected interrupt
mask
29
1
read-write
SRQIM
Session request/new session detected
interrupt mask
30
1
read-write
WUIM
Resume/remote wakeup detected interrupt
mask
31
1
read-write
GRXSTSR_Device
GRXSTSR_Device
OTG_FS Receive status debug read(Device
mode)
0x1C
0x20
read-only
0x00000000
EPNUM
Endpoint number
0
4
BCNT
Byte count
4
11
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
FRMNUM
Frame number
21
4
GRXSTSR_Host
GRXSTSR_Host
OTG status debug read (host mode)
GRXSTSR_Device
0x1C
0x20
read-only
0x00000000
CHNUM
Channel number
0
4
BCNT
Byte count
4
11
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
GRXFSIZ
GRXFSIZ
OTG_FS Receive FIFO size register
(OTG_FS_GRXFSIZ)
0x24
0x20
read-write
0x00000200
RXFD
RxFIFO depth
0
16
DIEPTXF0
DIEPTXF0
OTG_FS non-periodic transmit FIFO size
register (Device mode)
0x28
0x20
read-write
0x00000200
TX0FSA
Endpoint 0 transmit RAM start
address
0
16
TX0FD
Endpoint 0 TxFIFO depth
16
16
HNPTXFSIZ
HNPTXFSIZ
OTG_FS non-periodic transmit FIFO size
register (Host mode)
DIEPTXF0
0x28
0x20
read-write
0x00000200
NPTXFSA
Non-periodic transmit RAM start
address
0
16
NPTXFD
Non-periodic TxFIFO depth
16
16
GNPTXSTS
GNPTXSTS
OTG_FS non-periodic transmit FIFO/queue
status register (OTG_FS_GNPTXSTS)
0x2C
0x20
read-only
0x00080200
NPTXFSAV
Non-periodic TxFIFO space
available
0
16
NPTQXSAV
Non-periodic transmit request queue
space available
16
8
NPTXQTOP
Top of the non-periodic transmit request
queue
24
7
GCCFG
GCCFG
OTG_FS general core configuration register
(OTG_FS_GCCFG)
0x38
0x20
read-write
0x00000000
PWRDWN
Power down
16
1
VBUSASEN
Enable the VBUS sensing
device
18
1
VBUSBSEN
Enable the VBUS sensing
device
19
1
SOFOUTEN
SOF output enable
20
1
NOVBUSSENS
Vbus sensing disable option
21
1
CID
CID
core ID register
0x3C
0x20
read-write
0x00001000
PRODUCT_ID
Product ID field
0
32
HPTXFSIZ
HPTXFSIZ
OTG_FS Host periodic transmit FIFO size
register (OTG_FS_HPTXFSIZ)
0x100
0x20
read-write
0x02000600
PTXSA
Host periodic TxFIFO start
address
0
16
PTXFSIZ
Host periodic TxFIFO depth
16
16
5
0x4
1-5
DIEPTXF%s
DIEPTXF%s
OTF_FS device IN endpoint transmit FIFO size register
0x104
0x20
read-write
0x02000400
INEPTXSA
IN endpoint FIFO2 transmit RAM start
address
0
16
INEPTXFD
IN endpoint TxFIFO depth
16
16
GRXSTSP_Device
OTG status read and pop (device mode)
0x20
0x20
read-only
0x00000000
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
DPID
Data PID
15
2
BCNT
Byte count
4
11
EPNUM
Endpoint number
0
4
GRXSTSP_Host
OTG status read and pop (host mode)
GRXSTSP_Device
0x20
0x20
read-only
0x00000000
PKTSTS
Packet status
17
4
DPID
Data PID
15
2
BCNT
Byte count
4
11
CHNUM
Channel number
0
4
OTG_FS_HOST
USB on the go full speed
USB_OTG_FS
0x50000400
0x0
0x400
registers
HCFG
HCFG
OTG_FS host configuration register
(OTG_FS_HCFG)
0x0
0x20
0x00000000
FSLSPCS
FS/LS PHY clock select
0
2
read-write
FSLSS
FS- and LS-only support
2
1
read-write
HFIR
HFIR
OTG_FS Host frame interval
register
0x4
0x20
read-write
0x0000EA60
FRIVL
Frame interval
0
16
HFNUM
HFNUM
OTG_FS host frame number/frame time
remaining register (OTG_FS_HFNUM)
0x8
0x20
read-only
0x00003FFF
FRNUM
Frame number
0
16
FTREM
Frame time remaining
16
16
HPTXSTS
HPTXSTS
OTG_FS_Host periodic transmit FIFO/queue
status register (OTG_FS_HPTXSTS)
0x10
0x20
0x00080100
PTXFSAVL
Periodic transmit data FIFO space
available
0
16
read-write
PTXQSAV
Periodic transmit request queue space
available
16
8
read-only
PTXQTOP
Top of the periodic transmit request
queue
24
8
read-only
HAINT
HAINT
OTG_FS Host all channels interrupt
register
0x14
0x20
read-only
0x00000000
HAINT
Channel interrupts
0
16
HAINTMSK
HAINTMSK
OTG_FS host all channels interrupt mask
register
0x18
0x20
read-write
0x00000000
HAINTM
Channel interrupt mask
0
16
HPRT
HPRT
OTG_FS host port control and status register
(OTG_FS_HPRT)
0x40
0x20
0x00000000
PCSTS
Port connect status
0
1
read-only
PCDET
Port connect detected
1
1
read-write
PENA
Port enable
2
1
read-write
PENCHNG
Port enable/disable change
3
1
read-write
POCA
Port overcurrent active
4
1
read-only
POCCHNG
Port overcurrent change
5
1
read-write
PRES
Port resume
6
1
read-write
PSUSP
Port suspend
7
1
read-write
PRST
Port reset
8
1
read-write
PLSTS
Port line status
10
2
read-only
PPWR
Port power
12
1
read-write
PTCTL
Port test control
13
4
read-write
PSPD
Port speed
17
2
read-only
12
0x20
0-11
HC%s
Host channel
0x100
CHAR
HCCHAR0
OTG_FS host channel-0 characteristics
register (OTG_FS_HCCHAR0)
0x0
0x20
read-write
0x00000000
MPSIZ
Maximum packet size
0
11
EPNUM
Endpoint number
11
4
EPDIR
Endpoint direction
15
1
LSDEV
Low-speed device
17
1
EPTYP
Endpoint type
18
2
MCNT
Multicount
20
2
DAD
Device address
22
7
ODDFRM
Odd frame
29
1
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
INT
HCINT0
OTG_FS host channel-0 interrupt register
(OTG_FS_HCINT0)
0x8
0x20
read-write
0x00000000
XFRC
Transfer completed
0
1
CHH
Channel halted
1
1
STALL
STALL response received
interrupt
3
1
NAK
NAK response received
interrupt
4
1
ACK
ACK response received/transmitted
interrupt
5
1
TXERR
Transaction error
7
1
BBERR
Babble error
8
1
FRMOR
Frame overrun
9
1
DTERR
Data toggle error
10
1
INTMSK
HCINTMSK0
OTG_FS host channel-0 mask register
(OTG_FS_HCINTMSK0)
0xC
0x20
read-write
0x00000000
XFRCM
Transfer completed mask
0
1
CHHM
Channel halted mask
1
1
STALLM
STALL response received interrupt
mask
3
1
NAKM
NAK response received interrupt
mask
4
1
ACKM
ACK response received/transmitted
interrupt mask
5
1
NYET
response received interrupt
mask
6
1
TXERRM
Transaction error mask
7
1
BBERRM
Babble error mask
8
1
FRMORM
Frame overrun mask
9
1
DTERRM
Data toggle error mask
10
1
TSIZ
HCTSIZ0
OTG_FS host channel-0 transfer size
register
0x10
0x20
read-write
0x00000000
XFRSIZ
Transfer size
0
19
PKTCNT
Packet count
19
10
DPID
Data PID
29
2
OTG_FS_DEVICE
USB on the go full speed
USB_OTG_FS
0x50000800
0x0
0x400
registers
DCFG
DCFG
OTG_FS device configuration register
(OTG_FS_DCFG)
0x0
0x20
read-write
0x02200000
DSPD
Device speed
0
2
NZLSOHSK
Non-zero-length status OUT
handshake
2
1
DAD
Device address
4
7
PFIVL
Periodic frame interval
11
2
DCTL
DCTL
OTG_FS device control register
(OTG_FS_DCTL)
0x4
0x20
0x00000000
RWUSIG
Remote wakeup signaling
0
1
read-write
SDIS
Soft disconnect
1
1
read-write
GINSTS
Global IN NAK status
2
1
read-only
GONSTS
Global OUT NAK status
3
1
read-only
TCTL
Test control
4
3
read-write
SGINAK
Set global IN NAK
7
1
read-write
CGINAK
Clear global IN NAK
8
1
read-write
SGONAK
Set global OUT NAK
9
1
read-write
CGONAK
Clear global OUT NAK
10
1
read-write
POPRGDNE
Power-on programming done
11
1
read-write
DSTS
DSTS
OTG_FS device status register
(OTG_FS_DSTS)
0x8
0x20
read-only
0x00000010
SUSPSTS
Suspend status
0
1
ENUMSPD
Enumerated speed
1
2
EERR
Erratic error
3
1
FNSOF
Frame number of the received
SOF
8
14
DIEPMSK
DIEPMSK
OTG_FS device IN endpoint common interrupt
mask register (OTG_FS_DIEPMSK)
0x10
0x20
read-write
0x00000000
XFRCM
Transfer completed interrupt
mask
0
1
EPDM
Endpoint disabled interrupt
mask
1
1
TOM
Timeout condition mask (Non-isochronous
endpoints)
3
1
ITTXFEMSK
IN token received when TxFIFO empty
mask
4
1
INEPNMM
IN token received with EP mismatch
mask
5
1
INEPNEM
IN endpoint NAK effective
mask
6
1
DOEPMSK
DOEPMSK
OTG_FS device OUT endpoint common interrupt
mask register (OTG_FS_DOEPMSK)
0x14
0x20
read-write
0x00000000
XFRCM
Transfer completed interrupt
mask
0
1
EPDM
Endpoint disabled interrupt
mask
1
1
STUPM
SETUP phase done mask
3
1
OTEPDM
OUT token received when endpoint
disabled mask
4
1
DAINT
DAINT
OTG_FS device all endpoints interrupt
register (OTG_FS_DAINT)
0x18
0x20
read-only
0x00000000
IEPINT
IN endpoint interrupt bits
0
16
OEPINT
OUT endpoint interrupt
bits
16
16
DAINTMSK
DAINTMSK
OTG_FS all endpoints interrupt mask register
(OTG_FS_DAINTMSK)
0x1C
0x20
read-write
0x00000000
IEPM
IN EP interrupt mask bits
0
16
OEPM
OUT EP interrupt mask bits
16
16
DVBUSDIS
DVBUSDIS
OTG_FS device VBUS discharge time
register
0x28
0x20
read-write
0x000017D7
VBUSDT
Device VBUS discharge time
0
16
DVBUSPULSE
DVBUSPULSE
OTG_FS device VBUS pulsing time
register
0x2C
0x20
read-write
0x000005B8
DVBUSP
Device VBUS pulsing time
0
12
DIEPEMPMSK
DIEPEMPMSK
OTG_FS device IN endpoint FIFO empty
interrupt mask register
0x34
0x20
read-write
0x00000000
INEPTXFEM
IN EP Tx FIFO empty interrupt mask
bits
0
16
DIEP0
Device IN endpoint 0
0x100
CTL
DIEPCTL0
OTG_FS device control IN endpoint 0 control
register (OTG_FS_DIEPCTL0)
0x0
0x20
0x00000000
MPSIZ
Maximum packet size
0
2
read-write
USBAEP
USB active endpoint
15
1
read-only
NAKSTS
NAK status
17
1
read-only
EPTYP
Endpoint type
18
2
read-only
STALL
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
CNAK
Clear NAK
26
1
write-only
SNAK
Set NAK
27
1
write-only
EPDIS
Endpoint disable
30
1
read-only
EPENA
Endpoint enable
31
1
read-write
INT
DIEPINT0
device endpoint-x interrupt
register
0x8
0x20
0x00000080
TXFE
TXFE
7
1
read-only
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
EPDISD
EPDISD
1
1
read-write
XFRC
XFRC
0
1
read-write
TSIZ
DIEPTSIZ0
device endpoint-0 transfer size
register
0x10
0x20
read-write
0x00000000
PKTCNT
Packet count
19
2
XFRSIZ
Transfer size
0
7
TXFSTS
DTXFSTS0
OTG_FS device IN endpoint transmit FIFO
status register
0x18
0x20
read-only
0x00000000
INEPTFSAV
IN endpoint TxFIFO space
available
0
16
5
0x20
1-5
DIEP%s
Device IN endpoint X
0x120
CTL
DIEPCTL1
OTG device endpoint-1 control
register
0x0
0x20
0x00000000
EPENA
EPENA
31
1
read-write
EPDIS
EPDIS
30
1
read-write
SODDFRM_SD1PID
SODDFRM/SD1PID
29
1
write-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
CNAK
CNAK
26
1
write-only
TXFNUM
TXFNUM
22
4
read-write
STALL
STALL handshake
21
1
read-write
EPTYP
EPTYP
18
2
read-write
NAKSTS
NAKSTS
17
1
read-only
EONUM_DPID
EONUM/DPID
16
1
read-only
USBAEP
USBAEP
15
1
read-write
MPSIZ
MPSIZ
0
11
read-write
INT
DIEPINT1
device endpoint-1 interrupt
register
0x8
0x20
0x00000080
TXFE
TXFE
7
1
read-only
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
EPDISD
EPDISD
1
1
read-write
XFRC
XFRC
0
1
read-write
TSIZ
DIEPTSIZ1
device endpoint-1 transfer size
register
0x10
0x20
read-write
0x00000000
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
TXFSTS
DTXFSTS1
OTG_FS device IN endpoint transmit FIFO
status register
0x18
0x20
read-only
0x00000000
INEPTFSAV
IN endpoint TxFIFO space
available
0
16
DOEP0
Device OUT endpoint 0
0x300
CTL
DOEPCTL0
device endpoint-0 control
register
0x0
0x20
0x00008000
EPENA
EPENA
31
1
read-write
EPDIS
EPDIS
30
1
read-only
SNAK
SNAK
27
1
write-only
CNAK
CNAK
26
1
write-only
STALL
STALL handshake
21
1
read-write
SNPM
SNPM
20
1
read-write
EPTYP
EPTYP
18
2
read-only
NAKSTS
NAKSTS
17
1
read-only
USBAEP
USBAEP
15
1
read-only
MPSIZ
MPSIZ
0
2
read-only
INT
DOEPINT0
device endpoint-0 interrupt
register
0x8
0x20
read-write
0x00000080
B2BSTUP
B2BSTUP
6
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
EPDISD
EPDISD
1
1
XFRC
XFRC
0
1
TSIZ
DOEPTSIZ0
device OUT endpoint-0 transfer size
register
0x10
0x20
read-write
0x00000000
STUPCNT
SETUP packet count
29
2
PKTCNT
Packet count
19
1
XFRSIZ
Transfer size
0
7
5
0x20
1-5
DOEP%s
Device IN endpoint X
0x320
CTL
DOEPCTL1
device endpoint-1 control
register
0x0
0x20
0x00000000
EPENA
EPENA
31
1
read-write
EPDIS
EPDIS
30
1
read-write
SODDFRM
SODDFRM
29
1
write-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
CNAK
CNAK
26
1
write-only
STALL
STALL handshake
21
1
read-write
SNPM
SNPM
20
1
read-write
EPTYP
EPTYP
18
2
read-write
NAKSTS
NAKSTS
17
1
read-only
EONUM_DPID
EONUM/DPID
16
1
read-only
USBAEP
USBAEP
15
1
read-write
MPSIZ
MPSIZ
0
11
read-write
INT
DOEPINT1
device endpoint-1 interrupt
register
0x8
0x20
read-write
0x00000080
B2BSTUP
B2BSTUP
6
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
EPDISD
EPDISD
1
1
XFRC
XFRC
0
1
TSIZ
DOEPTSIZ1
device OUT endpoint-1 transfer size
register
0x10
0x20
read-write
0x00000000
RXDPID_STUPCNT
Received data PID/SETUP packet
count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
OTG_FS_PWRCLK
USB on the go full speed
USB_OTG_FS
0x50000E00
0x0
0x400
registers
PCGCCTL
PCGCCTL
OTG_FS power and clock gating control
register (OTG_FS_PCGCCTL)
0x0
0x20
read-write
0x00000000
STPPCLK
Stop PHY clock
0
1
GATEHCLK
Gate HCLK
1
1
PHYSUSP
PHY Suspended
4
1
CAN1
Controller area network
CAN
0x40006400
0x0
0x400
registers
CAN1_TX
CAN1 TX interrupts
19
CAN1_TX
CAN1 TX interrupts
19
CAN1_RX0
CAN1 RX0 interrupts
20
CAN1_RX0
CAN1 RX0 interrupts
20
CAN1_RX1
CAN1 RX1 interrupts
21
CAN1_RX1
CAN1 RX1 interrupts
21
CAN1_SCE
CAN1 SCE interrupt
22
CAN1_SCE
CAN1 SCE interrupt
22
MCR
MCR
master control register
0x0
0x20
read-write
0x00010002
DBF
DBF
16
1
RESET
RESET
15
1
TTCM
TTCM
7
1
ABOM
ABOM
6
1
AWUM
AWUM
5
1
NART
NART
4
1
RFLM
RFLM
3
1
TXFP
TXFP
2
1
SLEEP
SLEEP
1
1
INRQ
INRQ
0
1
MSR
MSR
master status register
0x4
0x20
0x00000C02
RX
RX
11
1
read-only
SAMP
SAMP
10
1
read-only
RXM
RXM
9
1
read-only
TXM
TXM
8
1
read-only
SLAKI
SLAKI
4
1
read-write
WKUI
WKUI
3
1
read-write
ERRI
ERRI
2
1
read-write
SLAK
SLAK
1
1
read-only
INAK
INAK
0
1
read-only
TSR
TSR
transmit status register
0x8
0x20
0x1C000000
3
0x1
0-2
LOW%s
Lowest priority flag for mailbox
%s
29
1
read-only
3
0x1
0-2
TME%s
Lowest priority flag for mailbox
%s
26
1
read-only
CODE
CODE
24
2
read-only
ABRQ2
ABRQ2
23
1
read-write
TERR2
TERR2
19
1
read-write
ALST2
ALST2
18
1
read-write
TXOK2
TXOK2
17
1
read-write
RQCP2
RQCP2
16
1
read-write
ABRQ1
ABRQ1
15
1
read-write
TERR1
TERR1
11
1
read-write
ALST1
ALST1
10
1
read-write
TXOK1
TXOK1
9
1
read-write
RQCP1
RQCP1
8
1
read-write
ABRQ0
ABRQ0
7
1
read-write
TERR0
TERR0
3
1
read-write
ALST0
ALST0
2
1
read-write
TXOK0
TXOK0
1
1
read-write
RQCP0
RQCP0
0
1
read-write
2
0x4
0-1
RF%sR
RF%sR
receive FIFO %s register
0xC
0x20
0x00000000
RFOM
RFOM0
5
1
read-write
RFOM0W
write
Release
Set by software to release the output mailbox of the FIFO
1
FOVR
FOVR0
4
1
read-write
FOVR0R
read
NoOverrun
No FIFO x overrun
0
Overrun
FIFO x overrun
1
FOVR0W
write
Clear
Clear flag
1
FULL
FULL0
3
1
read-write
FULL0R
read
NotFull
FIFO x is not full
0
Full
FIFO x is full
1
FULL0W
write
Clear
Clear flag
1
FMP
FMP0
0
2
read-only
IER
IER
interrupt enable register
0x14
0x20
read-write
0x00000000
SLKIE
SLKIE
17
1
SLKIE
Disabled
No interrupt when SLAKI bit is set
0
Enabled
Interrupt generated when SLAKI bit is set
1
WKUIE
WKUIE
16
1
WKUIE
Disabled
No interrupt when WKUI is set
0
Enabled
Interrupt generated when WKUI bit is set
1
ERRIE
ERRIE
15
1
ERRIE
Disabled
No interrupt will be generated when an error condition is pending in the CAN_ESR
0
Enabled
An interrupt will be generation when an error condition is pending in the CAN_ESR
1
LECIE
LECIE
11
1
LECIE
Disabled
ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
0
Enabled
ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
1
BOFIE
BOFIE
10
1
BOFIE
Disabled
ERRI bit will not be set when BOFF is set
0
Enabled
ERRI bit will be set when BOFF is set
1
EPVIE
EPVIE
9
1
EPVIE
Disabled
ERRI bit will not be set when EPVF is set
0
Enabled
ERRI bit will be set when EPVF is set
1
EWGIE
EWGIE
8
1
EWGIE
Disabled
ERRI bit will not be set when EWGF is set
0
Enabled
ERRI bit will be set when EWGF is set
1
FOVIE1
FOVIE1
6
1
FOVIE1
Disabled
No interrupt when FOVR is set
0
Enabled
Interrupt generation when FOVR is set
1
FFIE1
FFIE1
5
1
FFIE1
Disabled
No interrupt when FULL bit is set
0
Enabled
Interrupt generated when FULL bit is set
1
FMPIE1
FMPIE1
4
1
FMPIE1
Disabled
No interrupt generated when state of FMP[1:0] bits are not 00b
0
Enabled
Interrupt generated when state of FMP[1:0] bits are not 00b
1
FOVIE0
FOVIE0
3
1
FOVIE0
Disabled
No interrupt when FOVR bit is set
0
Enabled
Interrupt generated when FOVR bit is set
1
FFIE0
FFIE0
2
1
FFIE0
Disabled
No interrupt when FULL bit is set
0
Enabled
Interrupt generated when FULL bit is set
1
FMPIE0
FMPIE0
1
1
FMPIE0
Disabled
No interrupt generated when state of FMP[1:0] bits are not 00
0
Enabled
Interrupt generated when state of FMP[1:0] bits are not 00b
1
TMEIE
TMEIE
0
1
TMEIE
Disabled
No interrupt when RQCPx bit is set
0
Enabled
Interrupt generated when RQCPx bit is set
1
ESR
ESR
interrupt enable register
0x18
0x20
0x00000000
REC
REC
24
8
read-only
TEC
TEC
16
8
read-only
LEC
LEC
4
3
read-write
LEC
NoError
No Error
0
Stuff
Stuff Error
1
Form
Form Error
2
Ack
Acknowledgment Error
3
BitRecessive
Bit recessive Error
4
BitDominant
Bit dominant Error
5
Crc
CRC Error
6
Custom
Set by software
7
BOFF
BOFF
2
1
read-only
EPVF
EPVF
1
1
read-only
EWGF
EWGF
0
1
read-only
BTR
BTR
bit timing register
0x1C
0x20
read-write
0x00000000
SILM
SILM
31
1
SILM
Normal
Normal operation
0
Silent
Silent Mode
1
LBKM
LBKM
30
1
LBKM
Disabled
Loop Back Mode disabled
0
Enabled
Loop Back Mode enabled
1
SJW
SJW
24
2
TS2
TS2
20
3
TS1
TS1
16
4
BRP
BRP
0
10
3
0x10
0-2
TX%s
CAN Transmit cluster
0x180
TIR
TI0R
TX mailbox identifier register
0x0
0x20
read-write
0x00000000
STID
STID
21
11
EXID
EXID
3
18
IDE
IDE
2
1
IDE
Standard
Standard identifier
0
Extended
Extended identifier
1
RTR
RTR
1
1
RTR
Data
Data frame
0
Remote
Remote frame
1
TXRQ
TXRQ
0
1
TDTR
TDT0R
mailbox data length control and time stamp
register
0x4
0x20
read-write
0x00000000
TIME
TIME
16
16
TGT
TGT
8
1
DLC
DLC
0
4
0
8
TDLR
TDL0R
mailbox data low register
0x8
0x20
read-write
0x00000000
4
0x8
0-3
DATA%s
DATA%s
0
8
TDHR
TDH0R
mailbox data high register
0xC
0x20
read-write
0x00000000
4
0x8
4-7
DATA%s
DATA%s
0
8
2
0x10
0-1
RX%s
CAN Receive cluster
0x1B0
RIR
RI0R
receive FIFO mailbox identifier
register
0x0
0x20
read-only
0x00000000
STID
STID
21
11
EXID
EXID
3
18
IDE
IDE
2
1
IDE
Standard
Standard identifier
0
Extended
Extended identifier
1
RTR
RTR
1
1
RTR
Data
Data frame
0
Remote
Remote frame
1
RDTR
RDT0R
mailbox data high register
0x4
0x20
read-only
0x00000000
TIME
TIME
16
16
FMI
FMI
8
8
DLC
DLC
0
4
0
8
RDLR
RDL0R
mailbox data high register
0x8
0x20
read-only
0x00000000
4
0x8
0-3
DATA%s
DATA%s
0
8
RDHR
RDH0R
receive FIFO mailbox data high
register
0xC
0x20
read-only
0x00000000
4
0x8
4-7
DATA%s
DATA%s
0
8
FMR
FMR
filter master register
0x200
0x20
read-write
0x2A1C0E01
CAN2SB
CAN2SB
8
6
FINIT
FINIT
0
1
FM1R
FM1R
filter mode register
0x204
0x20
read-write
0x00000000
28
0x1
0-27
FBM%s
Filter mode
0
1
FS1R
FS1R
filter scale register
0x20C
0x20
read-write
0x00000000
28
0x1
0-27
FSC%s
Filter scale configuration
0
1
FFA1R
FFA1R
filter FIFO assignment
register
0x214
0x20
read-write
0x00000000
28
0x1
0-27
FFA%s
Filter FIFO assignment for filter %s
0
1
FA1R
FA1R
filter activation register
0x21C
0x20
read-write
0x00000000
28
0x1
0-27
FACT%s
Filter active
0
1
28
0x8
0-27
FB%s
CAN Filter Bank cluster
0x240
FR1
F0R1
Filter bank x register 1
0x0
0x20
read-write
0x00000000
FB
Filter bits
0
32
FR2
F0R2
Filter bank x register 2
0x4
0x20
read-write
0x00000000
FB
Filter bits
0
32
CAN2
0x40006800
CAN2_TX
CAN2 TX interrupts
63
CAN2_TX
CAN2 TX interrupts
63
CAN2_RX0
CAN2 RX0 interrupts
64
CAN2_RX0
CAN2 RX0 interrupts
64
CAN2_RX1
CAN2 RX1 interrupts
65
CAN2_RX1
CAN2 RX1 interrupts
65
CAN2_SCE
CAN2 SCE interrupt
66
CAN2_SCE
CAN2 SCE interrupt
66
NVIC
Nested Vectored Interrupt
Controller
NVIC
0xE000E100
0x0
0x355
registers
ISER0
ISER0
Interrupt Set-Enable Register
0x0
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x4
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ISER2
ISER2
Interrupt Set-Enable Register
0x8
0x20
read-write
0x00000000
SETENA
SETENA
0
32
ICER0
ICER0
Interrupt Clear-Enable
Register
0x80
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable
Register
0x84
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ICER2
ICER2
Interrupt Clear-Enable
Register
0x88
0x20
read-write
0x00000000
CLRENA
CLRENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x104
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ISPR2
ISPR2
Interrupt Set-Pending Register
0x108
0x20
read-write
0x00000000
SETPEND
SETPEND
0
32
ICPR0
ICPR0
Interrupt Clear-Pending
Register
0x180
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending
Register
0x184
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
ICPR2
ICPR2
Interrupt Clear-Pending
Register
0x188
0x20
read-write
0x00000000
CLRPEND
CLRPEND
0
32
IABR0
IABR0
Interrupt Active Bit Register
0x200
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IABR2
IABR2
Interrupt Active Bit Register
0x208
0x20
read-only
0x00000000
ACTIVE
ACTIVE
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x324
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x328
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x32C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x330
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x334
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x338
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR15
IPR15
Interrupt Priority Register
0x33C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR16
IPR16
Interrupt Priority Register
0x340
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR17
IPR17
Interrupt Priority Register
0x344
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR18
IPR18
Interrupt Priority Register
0x348
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR19
IPR19
Interrupt Priority Register
0x34C
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR20
IPR20
Interrupt Priority Register
0x350
0x20
read-write
0x00000000
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
FLASH
FLASH
FLASH
0x40023C00
0x0
0x400
registers
FLASH
Flash global interrupt
4
FLASH
Flash global interrupt
4
ACR
ACR
Flash access control register
0x0
0x20
0x00000000
LATENCY
Latency
0
4
read-write
LATENCY
WS0
0 wait states
0
WS1
1 wait states
1
WS2
2 wait states
2
WS3
3 wait states
3
WS4
4 wait states
4
WS5
5 wait states
5
WS6
6 wait states
6
WS7
7 wait states
7
WS8
8 wait states
8
WS9
9 wait states
9
WS10
10 wait states
10
WS11
11 wait states
11
WS12
12 wait states
12
WS13
13 wait states
13
WS14
14 wait states
14
WS15
15 wait states
15
PRFTEN
Prefetch enable
8
1
read-write
PRFTEN
Disabled
Prefetch is disabled
0
Enabled
Prefetch is enabled
1
ICEN
Instruction cache enable
9
1
read-write
ICEN
Disabled
Instruction cache is disabled
0
Enabled
Instruction cache is enabled
1
DCEN
Data cache enable
10
1
read-write
DCEN
Disabled
Data cache is disabled
0
Enabled
Data cache is enabled
1
ICRST
Instruction cache reset
11
1
write-only
ICRST
NotReset
Instruction cache is not reset
0
Reset
Instruction cache is reset
1
DCRST
Data cache reset
12
1
read-write
DCRST
NotReset
Data cache is not reset
0
Reset
Data cache is reset
1
KEYR
KEYR
Flash key register
0x4
0x20
write-only
0x00000000
KEY
FPEC key
0
32
0
4294967295
OPTKEYR
OPTKEYR
Flash option key register
0x8
0x20
write-only
0x00000000
OPTKEY
Option byte key
0
32
0
4294967295
SR
SR
Status register
0xC
0x20
0x00000000
EOP
End of operation
0
1
read-write
oneToClear
EOPW
write
Clear
Clear error flag
1
OPERR
Operation error
1
1
read-write
oneToClear
OPERRW
write
Clear
Clear error flag
1
WRPERR
Write protection error
4
1
read-write
oneToClear
WRPERRW
write
Clear
Clear error flag
1
PGAERR
Programming alignment
error
5
1
read-write
oneToClear
PGAERRW
write
Clear
Clear error flag
1
PGPERR
Programming parallelism
error
6
1
read-write
oneToClear
PGPERRW
write
Clear
Clear error flag
1
PGSERR
Programming sequence error
7
1
read-write
oneToClear
PGSERRW
write
Clear
Clear error flag
1
BSY
Busy
16
1
read-only
BSYR
NotBusy
no Flash memory operation ongoing
0
Busy
Flash memory operation ongoing
1
CR
CR
Control register
0x10
0x20
read-write
0x80000000
PG
Programming
0
1
PG
Program
Flash programming activated
1
SER
Sector Erase
1
1
SER
SectorErase
Erase activated for selected sector
1
MER
Mass Erase of sectors 0 to
11
2
1
MER
MassErase
Erase activated for all user sectors
1
SNB
Sector number
3
5
0
11
PSIZE
Program size
8
2
PSIZE
PSIZE8
Program x8
0
PSIZE16
Program x16
1
PSIZE32
Program x32
2
PSIZE64
Program x64
3
MER1
Mass Erase of sectors 12 to
23
15
1
STRT
Start
16
1
STRT
Start
Trigger an erase operation
1
EOPIE
End of operation interrupt
enable
24
1
EOPIE
Disabled
End of operation interrupt disabled
0
Enabled
End of operation interrupt enabled
1
ERRIE
Error interrupt enable
25
1
ERRIE
Disabled
Error interrupt generation disabled
0
Enabled
Error interrupt generation enabled
1
LOCK
Lock
31
1
LOCK
Unlocked
FLASH_CR register is unlocked
0
Locked
FLASH_CR register is locked
1
OPTCR
OPTCR
Flash option control register
0x14
0x20
read-write
0x0FFFAAED
OPTLOCK
Option lock
0
1
OPTSTRT
Option start
1
1
BOR_LEV
BOR reset Level
2
2
WDG_SW
WDG_SW User option bytes
5
1
nRST_STOP
nRST_STOP User option
bytes
6
1
nRST_STDBY
nRST_STDBY User option
bytes
7
1
RDP
Read protect
8
8
nWRP
Not write protect
16
12
OPTCR1
OPTCR1
Flash option control register
1
0x18
0x20
read-write
0x0FFF0000
nWRP
Not write protect
16
12
EXTI
External interrupt/event
controller
EXTI
0x40013C00
0x0
0x400
registers
TAMP_STAMP
Tamper and TimeStamp interrupts through the
EXTI line
2
TAMP_STAMP
Tamper and TimeStamp interrupts through the
EXTI line
2
EXTI0
EXTI Line0 interrupt
6
EXTI0
EXTI Line0 interrupt
6
EXTI1
EXTI Line1 interrupt
7
EXTI1
EXTI Line1 interrupt
7
EXTI2
EXTI Line2 interrupt
8
EXTI2
EXTI Line2 interrupt
8
EXTI3
EXTI Line3 interrupt
9
EXTI3
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI4
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI15_10
EXTI Line[15:10] interrupts
40
EXTI15_10
EXTI Line[15:10] interrupts
40
IMR
IMR
Interrupt mask register
(EXTI_IMR)
0x0
0x20
read-write
0x00000000
MR0
Interrupt Mask on line 0
0
1
MR0
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR1
Interrupt Mask on line 1
1
1
MR2
Interrupt Mask on line 2
2
1
MR3
Interrupt Mask on line 3
3
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR18
Interrupt Mask on line 18
18
1
MR19
Interrupt Mask on line 19
19
1
MR20
Interrupt Mask on line 20
20
1
MR21
Interrupt Mask on line 21
21
1
MR22
Interrupt Mask on line 22
22
1
EMR
EMR
Event mask register (EXTI_EMR)
0x4
0x20
read-write
0x00000000
MR0
Event Mask on line 0
0
1
MR0
Masked
Interrupt request line is masked
0
Unmasked
Interrupt request line is unmasked
1
MR1
Event Mask on line 1
1
1
MR2
Event Mask on line 2
2
1
MR3
Event Mask on line 3
3
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR18
Event Mask on line 18
18
1
MR19
Event Mask on line 19
19
1
MR20
Event Mask on line 20
20
1
MR21
Event Mask on line 21
21
1
MR22
Event Mask on line 22
22
1
RTSR
RTSR
Rising Trigger selection register
(EXTI_RTSR)
0x8
0x20
read-write
0x00000000
TR0
Rising trigger event configuration of
line 0
0
1
TR0
Disabled
Rising edge trigger is disabled
0
Enabled
Rising edge trigger is enabled
1
TR1
Rising trigger event configuration of
line 1
1
1
TR2
Rising trigger event configuration of
line 2
2
1
TR3
Rising trigger event configuration of
line 3
3
1
TR4
Rising trigger event configuration of
line 4
4
1
TR5
Rising trigger event configuration of
line 5
5
1
TR6
Rising trigger event configuration of
line 6
6
1
TR7
Rising trigger event configuration of
line 7
7
1
TR8
Rising trigger event configuration of
line 8
8
1
TR9
Rising trigger event configuration of
line 9
9
1
TR10
Rising trigger event configuration of
line 10
10
1
TR11
Rising trigger event configuration of
line 11
11
1
TR12
Rising trigger event configuration of
line 12
12
1
TR13
Rising trigger event configuration of
line 13
13
1
TR14
Rising trigger event configuration of
line 14
14
1
TR15
Rising trigger event configuration of
line 15
15
1
TR16
Rising trigger event configuration of
line 16
16
1
TR17
Rising trigger event configuration of
line 17
17
1
TR18
Rising trigger event configuration of
line 18
18
1
TR19
Rising trigger event configuration of
line 19
19
1
TR20
Rising trigger event configuration of
line 20
20
1
TR21
Rising trigger event configuration of
line 21
21
1
TR22
Rising trigger event configuration of
line 22
22
1
FTSR
FTSR
Falling Trigger selection register
(EXTI_FTSR)
0xC
0x20
read-write
0x00000000
TR0
Falling trigger event configuration of
line 0
0
1
TR0
Disabled
Falling edge trigger is disabled
0
Enabled
Falling edge trigger is enabled
1
TR1
Falling trigger event configuration of
line 1
1
1
TR2
Falling trigger event configuration of
line 2
2
1
TR3
Falling trigger event configuration of
line 3
3
1
TR4
Falling trigger event configuration of
line 4
4
1
TR5
Falling trigger event configuration of
line 5
5
1
TR6
Falling trigger event configuration of
line 6
6
1
TR7
Falling trigger event configuration of
line 7
7
1
TR8
Falling trigger event configuration of
line 8
8
1
TR9
Falling trigger event configuration of
line 9
9
1
TR10
Falling trigger event configuration of
line 10
10
1
TR11
Falling trigger event configuration of
line 11
11
1
TR12
Falling trigger event configuration of
line 12
12
1
TR13
Falling trigger event configuration of
line 13
13
1
TR14
Falling trigger event configuration of
line 14
14
1
TR15
Falling trigger event configuration of
line 15
15
1
TR16
Falling trigger event configuration of
line 16
16
1
TR17
Falling trigger event configuration of
line 17
17
1
TR18
Falling trigger event configuration of
line 18
18
1
TR19
Falling trigger event configuration of
line 19
19
1
TR20
Falling trigger event configuration of
line 20
20
1
TR21
Falling trigger event configuration of
line 21
21
1
TR22
Falling trigger event configuration of
line 22
22
1
SWIER
SWIER
Software interrupt event register
(EXTI_SWIER)
0x10
0x20
read-write
0x00000000
SWIER0
Software Interrupt on line
0
0
1
SWIER0W
write
Pend
Generates an interrupt request
1
SWIER1
Software Interrupt on line
1
1
1
SWIER2
Software Interrupt on line
2
2
1
SWIER3
Software Interrupt on line
3
3
1
SWIER4
Software Interrupt on line
4
4
1
SWIER5
Software Interrupt on line
5
5
1
SWIER6
Software Interrupt on line
6
6
1
SWIER7
Software Interrupt on line
7
7
1
SWIER8
Software Interrupt on line
8
8
1
SWIER9
Software Interrupt on line
9
9
1
SWIER10
Software Interrupt on line
10
10
1
SWIER11
Software Interrupt on line
11
11
1
SWIER12
Software Interrupt on line
12
12
1
SWIER13
Software Interrupt on line
13
13
1
SWIER14
Software Interrupt on line
14
14
1
SWIER15
Software Interrupt on line
15
15
1
SWIER16
Software Interrupt on line
16
16
1
SWIER17
Software Interrupt on line
17
17
1
SWIER18
Software Interrupt on line
18
18
1
SWIER19
Software Interrupt on line
19
19
1
SWIER20
Software Interrupt on line
20
20
1
SWIER21
Software Interrupt on line
21
21
1
SWIER22
Software Interrupt on line
22
22
1
PR
PR
Pending register (EXTI_PR)
0x14
0x20
read-write
0x00000000
PR0
Pending bit 0
0
1
oneToClear
PR0R
read
NotPending
No trigger request occurred
0
Pending
Selected trigger request occurred
1
PR0W
write
Clear
Clears pending bit
1
PR1
Pending bit 1
1
1
oneToClear
read
write
PR2
Pending bit 2
2
1
oneToClear
read
write
PR3
Pending bit 3
3
1
oneToClear
read
write
PR4
Pending bit 4
4
1
oneToClear
read
write
PR5
Pending bit 5
5
1
oneToClear
read
write
PR6
Pending bit 6
6
1
oneToClear
read
write
PR7
Pending bit 7
7
1
oneToClear
read
write
PR8
Pending bit 8
8
1
oneToClear
read
write
PR9
Pending bit 9
9
1
oneToClear
read
write
PR10
Pending bit 10
10
1
oneToClear
read
write
PR11
Pending bit 11
11
1
oneToClear
read
write
PR12
Pending bit 12
12
1
oneToClear
read
write
PR13
Pending bit 13
13
1
oneToClear
read
write
PR14
Pending bit 14
14
1
oneToClear
read
write
PR15
Pending bit 15
15
1
oneToClear
read
write
PR16
Pending bit 16
16
1
oneToClear
read
write
PR17
Pending bit 17
17
1
oneToClear
read
write
PR18
Pending bit 18
18
1
oneToClear
read
write
PR19
Pending bit 19
19
1
oneToClear
read
write
PR20
Pending bit 20
20
1
oneToClear
read
write
PR21
Pending bit 21
21
1
oneToClear
read
write
PR22
Pending bit 22
22
1
oneToClear
read
write
OTG_HS_GLOBAL
USB on the go high speed
USB_OTG_HS
0x40040000
0x0
0x400
registers
OTG_HS_EP1_OUT
USB On The Go HS End Point 1 Out global
interrupt
74
OTG_HS_EP1_OUT
USB On The Go HS End Point 1 Out global
interrupt
74
OTG_HS_EP1_IN
USB On The Go HS End Point 1 In global
interrupt
75
OTG_HS_EP1_IN
USB On The Go HS End Point 1 In global
interrupt
75
OTG_HS_WKUP
USB On The Go HS Wakeup through EXTI
interrupt
76
OTG_HS_WKUP
USB On The Go HS Wakeup through EXTI
interrupt
76
OTG_HS
USB On The Go HS global
interrupt
77
OTG_HS
USB On The Go HS global
interrupt
77
GOTGCTL
GOTGCTL
OTG_HS control and status
register
0x0
0x20
0x00000800
SRQSCS
Session request success
0
1
read-only
SRQ
Session request
1
1
read-write
HNGSCS
Host negotiation success
8
1
read-only
HNPRQ
HNP request
9
1
read-write
HSHNPEN
Host set HNP enable
10
1
read-write
DHNPEN
Device HNP enabled
11
1
read-write
CIDSTS
Connector ID status
16
1
read-only
DBCT
Long/short debounce time
17
1
read-only
ASVLD
A-session valid
18
1
read-only
BSVLD
B-session valid
19
1
read-only
GOTGINT
GOTGINT
OTG_HS interrupt register
0x4
0x20
read-write
0x00000000
SEDET
Session end detected
2
1
SRSSCHG
Session request success status
change
8
1
HNSSCHG
Host negotiation success status
change
9
1
HNGDET
Host negotiation detected
17
1
ADTOCHG
A-device timeout change
18
1
DBCDNE
Debounce done
19
1
GAHBCFG
GAHBCFG
OTG_HS AHB configuration
register
0x8
0x20
read-write
0x00000000
GINT
Global interrupt mask
0
1
HBSTLEN
Burst length/type
1
4
DMAEN
DMA enable
5
1
TXFELVL
TxFIFO empty level
7
1
PTXFELVL
Periodic TxFIFO empty
level
8
1
GUSBCFG
GUSBCFG
OTG_HS USB configuration
register
0xC
0x20
0x00000A00
TOCAL
FS timeout calibration
0
3
read-write
PHYSEL
USB 2.0 high-speed ULPI PHY or USB 1.1
full-speed serial transceiver select
6
1
write-only
SRPCAP
SRP-capable
8
1
read-write
HNPCAP
HNP-capable
9
1
read-write
TRDT
USB turnaround time
10
4
read-write
PHYLPCS
PHY Low-power clock select
15
1
read-write
ULPIFSLS
ULPI FS/LS select
17
1
read-write
ULPIAR
ULPI Auto-resume
18
1
read-write
ULPICSM
ULPI Clock SuspendM
19
1
read-write
ULPIEVBUSD
ULPI External VBUS Drive
20
1
read-write
ULPIEVBUSI
ULPI external VBUS
indicator
21
1
read-write
TSDPS
TermSel DLine pulsing
selection
22
1
read-write
PCCI
Indicator complement
23
1
read-write
PTCI
Indicator pass through
24
1
read-write
ULPIIPD
ULPI interface protect
disable
25
1
read-write
FHMOD
Forced host mode
29
1
read-write
FDMOD
Forced peripheral mode
30
1
read-write
CTXPKT
Corrupt Tx packet
31
1
read-write
GRSTCTL
GRSTCTL
OTG_HS reset register
0x10
0x20
0x20000000
CSRST
Core soft reset
0
1
read-write
HSRST
HCLK soft reset
1
1
read-write
FCRST
Host frame counter reset
2
1
read-write
RXFFLSH
RxFIFO flush
4
1
read-write
TXFFLSH
TxFIFO flush
5
1
read-write
TXFNUM
TxFIFO number
6
5
read-write
DMAREQ
DMA request signal
30
1
read-only
AHBIDL
AHB master idle
31
1
read-only
GINTSTS
GINTSTS
OTG_HS core interrupt register
0x14
0x20
0x04000020
CMOD
Current mode of operation
0
1
read-only
MMIS
Mode mismatch interrupt
1
1
read-write
OTGINT
OTG interrupt
2
1
read-only
SOF
Start of frame
3
1
read-write
RXFLVL
RxFIFO nonempty
4
1
read-only
NPTXFE
Nonperiodic TxFIFO empty
5
1
read-only
GINAKEFF
Global IN nonperiodic NAK
effective
6
1
read-only
BOUTNAKEFF
Global OUT NAK effective
7
1
read-only
ESUSP
Early suspend
10
1
read-write
USBSUSP
USB suspend
11
1
read-write
USBRST
USB reset
12
1
read-write
ENUMDNE
Enumeration done
13
1
read-write
ISOODRP
Isochronous OUT packet dropped
interrupt
14
1
read-write
EOPF
End of periodic frame
interrupt
15
1
read-write
IEPINT
IN endpoint interrupt
18
1
read-only
OEPINT
OUT endpoint interrupt
19
1
read-only
IISOIXFR
Incomplete isochronous IN
transfer
20
1
read-write
PXFR_INCOMPISOOUT
Incomplete periodic
transfer
21
1
read-write
DATAFSUSP
Data fetch suspended
22
1
read-write
HPRTINT
Host port interrupt
24
1
read-only
HCINT
Host channels interrupt
25
1
read-only
PTXFE
Periodic TxFIFO empty
26
1
read-only
CIDSCHG
Connector ID status change
28
1
read-write
DISCINT
Disconnect detected
interrupt
29
1
read-write
SRQINT
Session request/new session detected
interrupt
30
1
read-write
WKUINT
Resume/remote wakeup detected
interrupt
31
1
read-write
GINTMSK
GINTMSK
OTG_HS interrupt mask register
0x18
0x20
0x00000000
MMISM
Mode mismatch interrupt
mask
1
1
read-write
OTGINT
OTG interrupt mask
2
1
read-write
SOFM
Start of frame mask
3
1
read-write
RXFLVLM
Receive FIFO nonempty mask
4
1
read-write
NPTXFEM
Nonperiodic TxFIFO empty
mask
5
1
read-write
GINAKEFFM
Global nonperiodic IN NAK effective
mask
6
1
read-write
GONAKEFFM
Global OUT NAK effective
mask
7
1
read-write
ESUSPM
Early suspend mask
10
1
read-write
USBSUSPM
USB suspend mask
11
1
read-write
USBRST
USB reset mask
12
1
read-write
ENUMDNEM
Enumeration done mask
13
1
read-write
ISOODRPM
Isochronous OUT packet dropped interrupt
mask
14
1
read-write
EOPFM
End of periodic frame interrupt
mask
15
1
read-write
EPMISM
Endpoint mismatch interrupt
mask
17
1
read-write
IEPINT
IN endpoints interrupt
mask
18
1
read-write
OEPINT
OUT endpoints interrupt
mask
19
1
read-write
IISOIXFRM
Incomplete isochronous IN transfer
mask
20
1
read-write
PXFRM_IISOOXFRM
Incomplete periodic transfer
mask
21
1
read-write
FSUSPM
Data fetch suspended mask
22
1
read-write
PRTIM
Host port interrupt mask
24
1
read-only
HCIM
Host channels interrupt
mask
25
1
read-write
PTXFEM
Periodic TxFIFO empty mask
26
1
read-write
CIDSCHGM
Connector ID status change
mask
28
1
read-write
DISCINT
Disconnect detected interrupt
mask
29
1
read-write
SRQIM
Session request/new session detected
interrupt mask
30
1
read-write
WUIM
Resume/remote wakeup detected interrupt
mask
31
1
read-write
GRXSTSR_Host
GRXSTSR_Host
OTG_HS Receive status debug read register
(host mode)
0x1C
0x20
read-only
0x00000000
CHNUM
Channel number
0
4
BCNT
Byte count
4
11
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
GRXSTSP_Host
GRXSTSP_Host
OTG_HS status read and pop register (host
mode)
0x20
0x20
read-only
0x00000000
CHNUM
Channel number
0
4
BCNT
Byte count
4
11
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
GRXFSIZ
GRXFSIZ
OTG_HS Receive FIFO size
register
0x24
0x20
read-write
0x00000200
RXFD
RxFIFO depth
0
16
HNPTXFSIZ
HNPTXFSIZ
OTG_HS nonperiodic transmit FIFO size
register (host mode)
0x28
0x20
read-write
0x00000200
NPTXFSA
Nonperiodic transmit RAM start
address
0
16
NPTXFD
Nonperiodic TxFIFO depth
16
16
DIEPTXF0
DIEPTXF0
Endpoint 0 transmit FIFO size (peripheral
mode)
HNPTXFSIZ
0x28
0x20
read-write
0x00000200
TX0FSA
Endpoint 0 transmit RAM start
address
0
16
TX0FD
Endpoint 0 TxFIFO depth
16
16
HNPTXSTS
GNPTXSTS
OTG_HS nonperiodic transmit FIFO/queue
status register
0x2C
0x20
read-only
0x00080200
NPTXFSAV
Nonperiodic TxFIFO space
available
0
16
NPTQXSAV
Nonperiodic transmit request queue space
available
16
8
NPTXQTOP
Top of the nonperiodic transmit request
queue
24
7
GCCFG
GCCFG
OTG_HS general core configuration
register
0x38
0x20
read-write
0x00000000
PWRDWN
Power down
16
1
I2CPADEN
Enable I2C bus connection for the
external I2C PHY interface
17
1
VBUSASEN
Enable the VBUS sensing
device
18
1
VBUSBSEN
Enable the VBUS sensing
device
19
1
SOFOUTEN
SOF output enable
20
1
NOVBUSSENS
VBUS sensing disable
option
21
1
CID
CID
OTG_HS core ID register
0x3C
0x20
read-write
0x00001200
PRODUCT_ID
Product ID field
0
32
HPTXFSIZ
HPTXFSIZ
OTG_HS Host periodic transmit FIFO size
register
0x100
0x20
read-write
0x02000600
PTXSA
Host periodic TxFIFO start
address
0
16
PTXFD
Host periodic TxFIFO depth
16
16
5
0x4
1-5
DIEPTXF%s
DIEPTXF%s
OTG_HS device IN endpoint transmit FIFO size
register
0x104
0x20
read-write
0x02000400
INEPTXSA
IN endpoint FIFOx transmit RAM start
address
0
16
INEPTXFD
IN endpoint TxFIFO depth
16
16
GRXSTSR_Device
GRXSTSR_Peripheral
OTG_HS Receive status debug read register
(peripheral mode mode)
GRXSTSR_Host
0x1C
0x20
read-only
0x00000000
EPNUM
Endpoint number
0
4
BCNT
Byte count
4
11
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
FRMNUM
Frame number
21
4
GRXSTSP_Device
GRXSTSP_Peripheral
OTG_HS status read and pop register
(peripheral mode)
GRXSTSP_Host
0x20
0x20
read-only
0x00000000
EPNUM
Endpoint number
0
4
BCNT
Byte count
4
11
DPID
Data PID
15
2
PKTSTS
Packet status
17
4
FRMNUM
Frame number
21
4
OTG_HS_HOST
USB on the go high speed
USB_OTG_HS
0x40040400
0x0
0x400
registers
HCFG
HCFG
OTG_HS host configuration
register
0x0
0x20
0x00000000
FSLSPCS
FS/LS PHY clock select
0
2
read-write
FSLSS
FS- and LS-only support
2
1
read-only
HFIR
HFIR
OTG_HS Host frame interval
register
0x4
0x20
read-write
0x0000EA60
FRIVL
Frame interval
0
16
HFNUM
HFNUM
OTG_HS host frame number/frame time
remaining register
0x8
0x20
read-only
0x00003FFF
FRNUM
Frame number
0
16
FTREM
Frame time remaining
16
16
HPTXSTS
HPTXSTS
OTG_HS_Host periodic transmit FIFO/queue
status register
0x10
0x20
0x00080100
PTXFSAVL
Periodic transmit data FIFO space
available
0
16
read-write
PTXQSAV
Periodic transmit request queue space
available
16
8
read-only
PTXQTOP
Top of the periodic transmit request
queue
24
8
read-only
HAINT
HAINT
OTG_HS Host all channels interrupt
register
0x14
0x20
read-only
0x00000000
HAINT
Channel interrupts
0
16
HAINTMSK
HAINTMSK
OTG_HS host all channels interrupt mask
register
0x18
0x20
read-write
0x00000000
HAINTM
Channel interrupt mask
0
16
HPRT
HPRT
OTG_HS host port control and status
register
0x40
0x20
0x00000000
PCSTS
Port connect status
0
1
read-only
PCDET
Port connect detected
1
1
read-write
PENA
Port enable
2
1
read-write
PENCHNG
Port enable/disable change
3
1
read-write
POCA
Port overcurrent active
4
1
read-only
POCCHNG
Port overcurrent change
5
1
read-write
PRES
Port resume
6
1
read-write
PSUSP
Port suspend
7
1
read-write
PRST
Port reset
8
1
read-write
PLSTS
Port line status
10
2
read-only
PPWR
Port power
12
1
read-write
PTCTL
Port test control
13
4
read-write
PSPD
Port speed
17
2
read-only
12
0x20
0-11
HC%s
Host channel
0x100
CHAR
HCCHAR0
OTG_HS host channel-0 characteristics
register
0x0
0x20
read-write
0x00000000
MPSIZ
Maximum packet size
0
11
EPNUM
Endpoint number
11
4
EPDIR
Endpoint direction
15
1
LSDEV
Low-speed device
17
1
EPTYP
Endpoint type
18
2
MC
Multi Count (MC) / Error Count
(EC)
20
2
DAD
Device address
22
7
ODDFRM
Odd frame
29
1
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
SPLT
HCSPLT0
OTG_HS host channel-0 split control
register
0x4
0x20
read-write
0x00000000
PRTADDR
Port address
0
7
HUBADDR
Hub address
7
7
XACTPOS
XACTPOS
14
2
COMPLSPLT
Do complete split
16
1
SPLITEN
Split enable
31
1
INT
HCINT0
OTG_HS host channel-11 interrupt
register
0x8
0x20
read-write
0x00000000
XFRC
Transfer completed
0
1
CHH
Channel halted
1
1
AHBERR
AHB error
2
1
STALL
STALL response received
interrupt
3
1
NAK
NAK response received
interrupt
4
1
ACK
ACK response received/transmitted
interrupt
5
1
NYET
Response received
interrupt
6
1
TXERR
Transaction error
7
1
BBERR
Babble error
8
1
FRMOR
Frame overrun
9
1
DTERR
Data toggle error
10
1
INTMSK
HCINTMSK0
OTG_HS host channel-11 interrupt mask
register
0xC
0x20
read-write
0x00000000
XFRCM
Transfer completed mask
0
1
CHHM
Channel halted mask
1
1
AHBERR
AHB error
2
1
STALLM
STALL response received interrupt
mask
3
1
NAKM
NAK response received interrupt
mask
4
1
ACKM
ACK response received/transmitted
interrupt mask
5
1
NYET
response received interrupt
mask
6
1
TXERRM
Transaction error mask
7
1
BBERRM
Babble error mask
8
1
FRMORM
Frame overrun mask
9
1
DTERRM
Data toggle error mask
10
1
TSIZ
HCTSIZ0
OTG_HS host channel-11 transfer size
register
0x10
0x20
read-write
0x00000000
XFRSIZ
Transfer size
0
19
PKTCNT
Packet count
19
10
DPID
Data PID
29
2
DMA
HCDMA0
OTG_HS host channel-0 DMA address
register
0x14
0x20
read-write
0x00000000
DMAADDR
DMA address
0
32
OTG_HS_DEVICE
USB on the go high speed
USB_OTG_HS
0x40040800
0x0
0x400
registers
DCFG
DCFG
OTG_HS device configuration
register
0x0
0x20
read-write
0x02200000
DSPD
Device speed
0
2
NZLSOHSK
Nonzero-length status OUT
handshake
2
1
DAD
Device address
4
7
PFIVL
Periodic (micro)frame
interval
11
2
PERSCHIVL
Periodic scheduling
interval
24
2
DCTL
DCTL
OTG_HS device control register
0x4
0x20
0x00000000
RWUSIG
Remote wakeup signaling
0
1
read-write
SDIS
Soft disconnect
1
1
read-write
GINSTS
Global IN NAK status
2
1
read-only
GONSTS
Global OUT NAK status
3
1
read-only
TCTL
Test control
4
3
read-write
SGINAK
Set global IN NAK
7
1
write-only
CGINAK
Clear global IN NAK
8
1
write-only
SGONAK
Set global OUT NAK
9
1
write-only
CGONAK
Clear global OUT NAK
10
1
write-only
POPRGDNE
Power-on programming done
11
1
read-write
DSTS
DSTS
OTG_HS device status register
0x8
0x20
read-only
0x00000010
SUSPSTS
Suspend status
0
1
ENUMSPD
Enumerated speed
1
2
EERR
Erratic error
3
1
FNSOF
Frame number of the received
SOF
8
14
DIEPMSK
DIEPMSK
OTG_HS device IN endpoint common interrupt
mask register
0x10
0x20
read-write
0x00000000
XFRCM
Transfer completed interrupt
mask
0
1
EPDM
Endpoint disabled interrupt
mask
1
1
TOM
Timeout condition mask (nonisochronous
endpoints)
3
1
ITTXFEMSK
IN token received when TxFIFO empty
mask
4
1
INEPNMM
IN token received with EP mismatch
mask
5
1
INEPNEM
IN endpoint NAK effective
mask
6
1
TXFURM
FIFO underrun mask
8
1
BIM
BNA interrupt mask
9
1
DOEPMSK
DOEPMSK
OTG_HS device OUT endpoint common interrupt
mask register
0x14
0x20
read-write
0x00000000
XFRCM
Transfer completed interrupt
mask
0
1
EPDM
Endpoint disabled interrupt
mask
1
1
STUPM
SETUP phase done mask
3
1
OTEPDM
OUT token received when endpoint
disabled mask
4
1
B2BSTUP
Back-to-back SETUP packets received
mask
6
1
OPEM
OUT packet error mask
8
1
BOIM
BNA interrupt mask
9
1
DAINT
DAINT
OTG_HS device all endpoints interrupt
register
0x18
0x20
read-only
0x00000000
IEPINT
IN endpoint interrupt bits
0
16
OEPINT
OUT endpoint interrupt
bits
16
16
DAINTMSK
DAINTMSK
OTG_HS all endpoints interrupt mask
register
0x1C
0x20
read-write
0x00000000
IEPM
IN EP interrupt mask bits
0
16
OEPM
OUT EP interrupt mask bits
16
16
DVBUSDIS
DVBUSDIS
OTG_HS device VBUS discharge time
register
0x28
0x20
read-write
0x000017D7
VBUSDT
Device VBUS discharge time
0
16
DVBUSPULSE
DVBUSPULSE
OTG_HS device VBUS pulsing time
register
0x2C
0x20
read-write
0x000005B8
DVBUSP
Device VBUS pulsing time
0
12
DTHRCTL
DTHRCTL
OTG_HS Device threshold control
register
0x30
0x20
read-write
0x00000000
NONISOTHREN
Nonisochronous IN endpoints threshold
enable
0
1
ISOTHREN
ISO IN endpoint threshold
enable
1
1
TXTHRLEN
Transmit threshold length
2
9
RXTHREN
Receive threshold enable
16
1
RXTHRLEN
Receive threshold length
17
9
ARPEN
Arbiter parking enable
27
1
DIEPEMPMSK
DIEPEMPMSK
OTG_HS device IN endpoint FIFO empty
interrupt mask register
0x34
0x20
read-write
0x00000000
INEPTXFEM
IN EP Tx FIFO empty interrupt mask
bits
0
16
DEACHINT
DEACHINT
OTG_HS device each endpoint interrupt
register
0x38
0x20
read-write
0x00000000
IEP1INT
IN endpoint 1interrupt bit
1
1
OEP1INT
OUT endpoint 1 interrupt
bit
17
1
DEACHINTMSK
DEACHINTMSK
OTG_HS device each endpoint interrupt
register mask
0x3C
0x20
read-write
0x00000000
IEP1INTM
IN Endpoint 1 interrupt mask
bit
1
1
OEP1INTM
OUT Endpoint 1 interrupt mask
bit
17
1
DIEPEACHMSK1
DIEPEACHMSK1
OTG_HS device each in endpoint-1 interrupt
register
0x44
0x20
read-write
0x00000000
XFRCM
Transfer completed interrupt
mask
0
1
EPDM
Endpoint disabled interrupt
mask
1
1
TOM
Timeout condition mask (nonisochronous
endpoints)
3
1
ITTXFEMSK
IN token received when TxFIFO empty
mask
4
1
INEPNMM
IN token received with EP mismatch
mask
5
1
INEPNEM
IN endpoint NAK effective
mask
6
1
TXFURM
FIFO underrun mask
8
1
BIM
BNA interrupt mask
9
1
NAKM
NAK interrupt mask
13
1
DOEPEACHMSK1
DOEPEACHMSK1
OTG_HS device each OUT endpoint-1 interrupt
register
0x84
0x20
read-write
0x00000000
XFRCM
Transfer completed interrupt
mask
0
1
EPDM
Endpoint disabled interrupt
mask
1
1
TOM
Timeout condition mask
3
1
ITTXFEMSK
IN token received when TxFIFO empty
mask
4
1
INEPNMM
IN token received with EP mismatch
mask
5
1
INEPNEM
IN endpoint NAK effective
mask
6
1
TXFURM
OUT packet error mask
8
1
BIM
BNA interrupt mask
9
1
BERRM
Bubble error interrupt
mask
12
1
NAKM
NAK interrupt mask
13
1
NYETM
NYET interrupt mask
14
1
DIEP0
Device IN endpoint 0
0x100
CTL
DIEPCTL0
OTG device endpoint-0 control
register
0x0
0x20
0x00000000
MPSIZ
Maximum packet size
0
11
read-write
USBAEP
USB active endpoint
15
1
read-write
EONUM_DPID
Even/odd frame
16
1
read-only
NAKSTS
NAK status
17
1
read-only
EPTYP
Endpoint type
18
2
read-write
STALL
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
CNAK
Clear NAK
26
1
write-only
SNAK
Set NAK
27
1
write-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SODDFRM
Set odd frame
29
1
write-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
INT
DIEPINT0
OTG device endpoint-0 interrupt
register
0x8
0x20
0x00000080
XFRC
Transfer completed
interrupt
0
1
read-write
EPDISD
Endpoint disabled
interrupt
1
1
read-write
TOC
Timeout condition
3
1
read-write
ITTXFE
IN token received when TxFIFO is
empty
4
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
BNA
Buffer not available
interrupt
9
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
BERR
Babble error interrupt
12
1
read-write
NAK
NAK interrupt
13
1
read-write
TSIZ
DIEPTSIZ0
OTG_HS device IN endpoint 0 transfer size
register
0x10
0x20
read-write
0x00000000
XFRSIZ
Transfer size
0
7
PKTCNT
Packet count
19
2
DMA
OTG_HS device endpoint-0 DMA address register
0x14
0x20
read-write
0x00000000
DMAADDR
DMA address
0
32
TXFSTS
DTXFSTS0
OTG_HS device IN endpoint transmit FIFO
status register
0x18
0x20
read-only
0x00000000
INEPTFSAV
IN endpoint TxFIFO space
avail
0
16
5
0x20
1-5
DIEP%s
Device IN endpoint X
0x120
CTL
DIEPCTL1
OTG device endpoint-1 control
register
0x0
0x20
0x00000000
MPSIZ
Maximum packet size
0
11
read-write
USBAEP
USB active endpoint
15
1
read-write
EONUM_DPID
Even/odd frame
16
1
read-only
NAKSTS
NAK status
17
1
read-only
EPTYP
Endpoint type
18
2
read-write
STALL
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
CNAK
Clear NAK
26
1
write-only
SNAK
Set NAK
27
1
write-only
SD0PID_SEVNFRM
Set DATA0 PID
28
1
write-only
SODDFRM
Set odd frame
29
1
write-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
INT
DIEPINT1
OTG device endpoint-1 interrupt
register
0x8
0x20
0x00000000
XFRC
Transfer completed
interrupt
0
1
read-write
EPDISD
Endpoint disabled
interrupt
1
1
read-write
TOC
Timeout condition
3
1
read-write
ITTXFE
IN token received when TxFIFO is
empty
4
1
read-write
INEPNE
IN endpoint NAK effective
6
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
TXFIFOUDRN
Transmit Fifo Underrun
8
1
read-write
BNA
Buffer not available
interrupt
9
1
read-write
PKTDRPSTS
Packet dropped status
11
1
read-write
BERR
Babble error interrupt
12
1
read-write
NAK
NAK interrupt
13
1
read-write
TSIZ
DIEPTSIZ1
OTG_HS device endpoint transfer size
register
0x10
0x20
read-write
0x00000000
XFRSIZ
Transfer size
0
19
PKTCNT
Packet count
19
10
MCNT
Multi count
29
2
DMA
DIEPDMA1
OTG_HS device endpoint-1 DMA address
register
0x14
0x20
read-write
0x00000000
DMAADDR
DMA address
0
32
TXFSTS
DTXFSTS1
OTG_HS device IN endpoint transmit FIFO
status register
0x18
0x20
read-only
0x00000000
INEPTFSAV
IN endpoint TxFIFO space
avail
0
16
DOEP0
Device OUT endpoint 0
0x300
CTL
DOEPCTL0
OTG_HS device control OUT endpoint 0 control
register
0x0
0x20
0x00008000
MPSIZ
Maximum packet size
0
2
read-only
USBAEP
USB active endpoint
15
1
read-only
NAKSTS
NAK status
17
1
read-only
EPTYP
Endpoint type
18
2
read-only
SNPM
Snoop mode
20
1
read-write
STALL
STALL handshake
21
1
read-write
CNAK
Clear NAK
26
1
write-only
SNAK
Set NAK
27
1
write-only
EPDIS
Endpoint disable
30
1
read-only
EPENA
Endpoint enable
31
1
read-write
INT
DOEPINT0
OTG_HS device endpoint-0 interrupt
register
0x8
0x20
read-write
0x00000080
XFRC
Transfer completed
interrupt
0
1
EPDISD
Endpoint disabled
interrupt
1
1
STUP
SETUP phase done
3
1
OTEPDIS
OUT token received when endpoint
disabled
4
1
B2BSTUP
Back-to-back SETUP packets
received
6
1
NYET
NYET interrupt
14
1
TSIZ
DOEPTSIZ0
OTG_HS device endpoint-1 transfer size
register
0x10
0x20
read-write
0x00000000
XFRSIZ
Transfer size
0
7
PKTCNT
Packet count
19
1
STUPCNT
SETUP packet count
29
2
DMA
OTG_HS device endpoint-0 DMA address register
0x14
0x20
read-write
0x00000000
DMAADDR
DMA address
0
32
5
0x20
1-5
DOEP%s
Device IN endpoint X
0x320
CTL
DOEPCTL1
OTG device endpoint-1 control
register
0x0
0x20
0x00000000
MPSIZ
Maximum packet size
0
11
read-write
USBAEP
USB active endpoint
15
1
read-write
EONUM_DPID
Even odd frame/Endpoint data
PID
16
1
read-only
NAKSTS
NAK status
17
1
read-only
EPTYP
Endpoint type
18
2
read-write
SNPM
Snoop mode
20
1
read-write
STALL
STALL handshake
21
1
read-write
CNAK
Clear NAK
26
1
write-only
SNAK
Set NAK
27
1
write-only
SD0PID_SEVNFRM
Set DATA0 PID/Set even
frame
28
1
write-only
SODDFRM
Set odd frame
29
1
write-only
EPDIS
Endpoint disable
30
1
read-write
EPENA
Endpoint enable
31
1
read-write
INT
DOEPINT1
OTG_HS device endpoint-1 interrupt
register
0x8
0x20
read-write
0x00000000
XFRC
Transfer completed
interrupt
0
1
EPDISD
Endpoint disabled
interrupt
1
1
STUP
SETUP phase done
3
1
OTEPDIS
OUT token received when endpoint
disabled
4
1
B2BSTUP
Back-to-back SETUP packets
received
6
1
NYET
NYET interrupt
14
1
DMA
OTG_HS device endpoint-1 DMA address register
0x14
0x20
read-write
0x00000000
DMAADDR
DMA address
0
32
TSIZ
DOEPTSIZ1
OTG_HS device endpoint-2 transfer size
register
0x10
0x20
read-write
0x00000000
XFRSIZ
Transfer size
0
19
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet
count
29
2
OTG_HS_PWRCLK
USB on the go high speed
USB_OTG_HS
0x40040E00
0x0
0x3F200
registers
PCGCCTL
PCGCCTL
Power and clock gating control
register
0x0
0x20
read-write
0x00000000
STPPCLK
Stop PHY clock
0
1
GATEHCLK
Gate HCLK
1
1
PHYSUSP
PHY suspended
4
1
LTDC
LCD-TFT Controller
LTDC
0x40016800
0x0
0x400
registers
LCD_TFT
LTDC global interrupt
88
LCD_TFT
LTDC global interrupt
88
LCD_TFT_1
LTDC global error interrupt
89
LCD_TFT_1
LTDC global error interrupt
89
SSCR
SSCR
Synchronization Size Configuration
Register
0x8
0x20
read-write
0x00000000
HSW
Horizontal Synchronization Width (in
units of pixel clock period)
16
12
0
4095
VSH
Vertical Synchronization Height (in
units of horizontal scan line)
0
11
0
2047
BPCR
BPCR
Back Porch Configuration
Register
0xC
0x20
read-write
0x00000000
AHBP
Accumulated Horizontal back porch (in
units of pixel clock period)
16
12
0
4095
AVBP
Accumulated Vertical back porch (in
units of horizontal scan line)
0
11
0
2047
AWCR
AWCR
Active Width Configuration
Register
0x10
0x20
read-write
0x00000000
AAW
Accumulated Active Width (in units of pixel clock period)
16
12
0
4095
AAH
Accumulated Active Height (in units of
horizontal scan line)
0
11
0
2047
TWCR
TWCR
Total Width Configuration
Register
0x14
0x20
read-write
0x00000000
TOTALW
Total Width (in units of pixel clock
period)
16
12
0
4095
TOTALH
Total Height (in units of horizontal
scan line)
0
11
0
2047
GCR
GCR
Global Control Register
0x18
0x20
0x00002220
HSPOL
Horizontal Synchronization
Polarity
31
1
read-write
HSPOL
ActiveLow
Horizontal synchronization polarity is active low
0
ActiveHigh
Horizontal synchronization polarity is active high
1
VSPOL
Vertical Synchronization
Polarity
30
1
read-write
VSPOL
ActiveLow
Vertical synchronization polarity is active low
0
ActiveHigh
Vertical synchronization polarity is active high
1
DEPOL
Data Enable Polarity
29
1
read-write
DEPOL
ActiveLow
Data enable polarity is active low
0
ActiveHigh
Data enable polarity is active high
1
PCPOL
Pixel Clock Polarity
28
1
read-write
PCPOL
RisingEdge
Pixel clock on rising edge
0
FallingEdge
Pixel clock on falling edge
1
DEN
Dither Enable
16
1
read-write
DEN
Disabled
Dither disabled
0
Enabled
Dither enabled
1
DRW
Dither Red Width
12
3
read-only
DGW
Dither Green Width
8
3
read-only
DBW
Dither Blue Width
4
3
read-only
LTDCEN
LCD-TFT controller enable
bit
0
1
read-write
LTDCEN
Disabled
LCD-TFT controller disabled
0
Enabled
LCD-TFT controller enabled
1
SRCR
SRCR
Shadow Reload Configuration
Register
0x24
0x20
read-write
0x00000000
VBR
Vertical Blanking Reload
1
1
VBR
NoEffect
This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
0
Reload
The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).
1
IMR
Immediate Reload
0
1
IMR
NoEffect
This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
0
Reload
The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload
1
BCCR
BCCR
Background Color Configuration
Register
0x2C
0x20
read-write
0x00000000
BCBLUE
Background color blue value
0
8
0
255
BCGREEN
Background color green value
8
8
0
255
BCRED
Background color red value
16
8
0
255
IER
IER
Interrupt Enable Register
0x34
0x20
read-write
0x00000000
RRIE
Register Reload interrupt
enable
3
1
RRIE
Disabled
Register reload interrupt disabled
0
Enabled
Register reload interrupt enabled
1
TERRIE
Transfer Error Interrupt
Enable
2
1
TERRIE
Disabled
Transfer error interrupt disabled
0
Enabled
Transfer error interrupt enabled
1
FUIE
FIFO Underrun Interrupt
Enable
1
1
FUIE
Disabled
FIFO underrun interrupt disabled
0
Enabled
FIFO underrun interrupt enabled
1
LIE
Line Interrupt Enable
0
1
LIE
Disabled
Line interrupt disabled
0
Enabled
Line interrupt enabled
1
ISR
ISR
Interrupt Status Register
0x38
0x20
read-only
0x00000000
RRIF
Register Reload Interrupt
Flag
3
1
RRIF
NoReload
No register reload
0
Reload
Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)
1
TERRIF
Transfer Error interrupt
flag
2
1
TERRIF
NoError
No transfer error
0
Error
Transfer error interrupt generated when a bus error occurs
1
FUIF
FIFO Underrun Interrupt
flag
1
1
FUIF
NoUnderrun
No FIFO underrun
0
Underrun
FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO
1
LIF
Line Interrupt flag
0
1
LIF
NotReached
Programmed line not reached
0
Reached
Line interrupt generated when a programmed line is reached
1
ICR
ICR
Interrupt Clear Register
0x3C
0x20
write-only
0x00000000
CRRIF
Clears Register Reload Interrupt
Flag
3
1
oneToClear
CRRIFW
Clear
Clears the RRIF flag in the ISR register
1
CTERRIF
Clears the Transfer Error Interrupt
Flag
2
1
oneToClear
CTERRIFW
Clear
Clears the TERRIF flag in the ISR register
1
CFUIF
Clears the FIFO Underrun Interrupt
flag
1
1
oneToClear
CFUIFW
Clear
Clears the FUIF flag in the ISR register
1
CLIF
Clears the Line Interrupt
Flag
0
1
oneToClear
CLIFW
Clear
Clears the LIF flag in the ISR register
1
LIPCR
LIPCR
Line Interrupt Position Configuration
Register
0x40
0x20
read-write
0x00000000
LIPOS
Line Interrupt Position
0
11
0
2047
CPSR
CPSR
Current Position Status
Register
0x44
0x20
read-only
0x00000000
CXPOS
Current X Position
16
16
CYPOS
Current Y Position
0
16
CDSR
CDSR
Current Display Status
Register
0x48
0x20
read-only
0x0000000F
HSYNCS
Horizontal Synchronization display
Status
3
1
HSYNCS
NotActive
Currently not in HSYNC phase
0
Active
Currently in HSYNC phase
1
VSYNCS
Vertical Synchronization display
Status
2
1
VSYNCS
NotActive
Currently not in VSYNC phase
0
Active
Currently in VSYNC phase
1
HDES
Horizontal Data Enable display
Status
1
1
HDES
NotActive
Currently not in horizontal Data Enable phase
0
Active
Currently in horizontal Data Enable phase
1
VDES
Vertical Data Enable display
Status
0
1
VDES
NotActive
Currently not in vertical Data Enable phase
0
Active
Currently in vertical Data Enable phase
1
2
0x80
1-2
LAYER%s
Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR
0x84
CR
L1CR
Layerx Control Register
0x0
0x20
read-write
0x00000000
CLUTEN
Color Look-Up Table Enable
4
1
CLUTEN
Disabled
Color look-up table disabled
0
Enabled
Color look-up table enabled
1
COLKEN
Color Keying Enable
1
1
COLKEN
Disabled
Color keying disabled
0
Enabled
Color keying enabled
1
LEN
Layer Enable
0
1
LEN
Disabled
Layer disabled
0
Enabled
Layer enabled
1
WHPCR
L1WHPCR
Layerx Window Horizontal Position
Configuration Register
0x4
0x20
read-write
0x00000000
WHSPPOS
Window Horizontal Stop
Position
16
12
0
4095
WHSTPOS
Window Horizontal Start
Position
0
12
0
4095
WVPCR
L1WVPCR
Layerx Window Vertical Position
Configuration Register
0x8
0x20
read-write
0x00000000
WVSPPOS
Window Vertical Stop
Position
16
11
0
2047
WVSTPOS
Window Vertical Start
Position
0
11
0
2047
CKCR
L1CKCR
Layerx Color Keying Configuration
Register
0xC
0x20
read-write
0x00000000
CKRED
Color Key Red value
16
8
0
255
CKGREEN
Color Key Green value
8
8
0
255
CKBLUE
Color Key Blue value
0
8
0
255
PFCR
L1PFCR
Layerx Pixel Format Configuration
Register
0x10
0x20
read-write
0x00000000
PF
Pixel Format
0
3
PF
ARGB8888
ARGB8888
0
RGB888
RGB888
1
RGB565
RGB565
2
ARGB1555
ARGB1555
3
ARGB4444
ARGB4444
4
L8
L8 (8-bit luminance)
5
AL44
AL44 (4-bit alpha, 4-bit luminance)
6
AL88
AL88 (8-bit alpha, 8-bit luminance)
7
CACR
L1CACR
Layerx Constant Alpha Configuration
Register
0x14
0x20
read-write
0x00000000
CONSTA
Constant Alpha
0
8
0
255
DCCR
L1DCCR
Layerx Default Color Configuration
Register
0x18
0x20
read-write
0x00000000
DCALPHA
Default Color Alpha
24
8
0
255
DCRED
Default Color Red
16
8
0
255
DCGREEN
Default Color Green
8
8
0
255
DCBLUE
Default Color Blue
0
8
0
255
BFCR
L1BFCR
Layerx Blending Factors Configuration
Register
0x1C
0x20
read-write
0x00000607
BF1
Blending Factor 1
8
3
BF1
Constant
BF1 = constant alpha
4
Pixel
BF1 = pixel alpha * constant alpha
6
BF2
Blending Factor 2
0
3
BF2
Constant
BF2 = 1 - constant alpha
5
Pixel
BF2 = 1 - pixel alpha * constant alpha
7
CFBAR
L1CFBAR
Layerx Color Frame Buffer Address
Register
0x28
0x20
read-write
0x00000000
CFBADD
Color Frame Buffer Start
Address
0
32
0
4294967295
CFBLR
L1CFBLR
Layerx Color Frame Buffer Length
Register
0x2C
0x20
read-write
0x00000000
CFBP
Color Frame Buffer Pitch in
bytes
16
13
0
8191
CFBLL
Color Frame Buffer Line
Length
0
13
0
8191
CFBLNR
L1CFBLNR
Layerx ColorFrame Buffer Line Number
Register
0x30
0x20
read-write
0x00000000
CFBLNBR
Frame Buffer Line Number
0
11
0
2047
CLUTWR
L1CLUTWR
Layerx CLUT Write Register
0x40
0x20
write-only
0x00000000
CLUTADD
CLUT Address
24
8
0
255
RED
Red value
16
8
0
255
GREEN
Green value
8
8
0
255
BLUE
Blue value
0
8
0
255
SAI
Serial audio interface
SAI
0x40015800
0x0
0x400
registers
SAI1
SAI1 global interrupt
87
SAI1
SAI1 global interrupt
87
2
0x20
A,B
CH%s
Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR
0x4
CR1
ACR1
AConfiguration register 1
0x0
0x20
read-write
0x00000040
MCKDIV
Master clock divider
20
4
NODIV
No divider
19
1
NODIV
MasterClock
MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
0
NoDiv
MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
1
DMAEN
DMA enable
17
1
DMAEN
Disabled
DMA disabled
0
Enabled
DMA enabled
1
SAIEN
Audio block A enable
16
1
SAIEN
Disabled
SAI audio block disabled
0
Enabled
SAI audio block enabled
1
OUTDRIV
Output drive
13
1
OUTDRIV
OnStart
Audio block output driven when SAIEN is set
0
Immediately
Audio block output driven immediately after the setting of this bit
1
MONO
Mono mode
12
1
MONO
Stereo
Stereo mode
0
Mono
Mono mode
1
SYNCEN
Synchronization enable
10
2
SYNCEN
Asynchronous
audio sub-block in asynchronous mode
0
Internal
audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
1
External
audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
2
CKSTR
Clock strobing edge
9
1
CKSTR
FallingEdge
Data strobing edge is falling edge of SCK
0
RisingEdge
Data strobing edge is rising edge of SCK
1
LSBFIRST
Least significant bit
first
8
1
LSBFIRST
MsbFirst
Data are transferred with MSB first
0
LsbFirst
Data are transferred with LSB first
1
DS
Data size
5
3
DS
Bit8
8 bits
2
Bit10
10 bits
3
Bit16
16 bits
4
Bit20
20 bits
5
Bit24
24 bits
6
Bit32
32 bits
7
PRTCFG
Protocol configuration
2
2
PRTCFG
Free
Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
0
Spdif
SPDIF protocol
1
Ac97
AC’97 protocol
2
MODE
Audio block mode
0
2
MODE
MasterTx
Master transmitter
0
MasterRx
Master receiver
1
SlaveTx
Slave transmitter
2
SlaveRx
Slave receiver
3
CR2
ACR2
AConfiguration register 2
0x4
0x20
read-write
0x00000000
COMP
Companding mode
14
2
read-write
COMP
NoCompanding
No companding algorithm
0
MuLaw
μ-Law algorithm
2
ALaw
A-Law algorithm
3
CPL
Complement bit
13
1
read-write
CPL
OnesComplement
1’s complement representation
0
TwosComplement
2’s complement representation
1
MUTECNT
Mute counter
7
6
read-write
MUTEVAL
Mute value
6
1
read-write
MUTEVAL
SendZero
Bit value 0 is sent during the mute mode
0
SendLast
Last values are sent during the mute mode
1
MUTE
Mute
5
1
read-write
MUTE
Disabled
No mute mode
0
Enabled
Mute mode enabled
1
TRIS
Tristate management on data
line
4
1
read-write
FFLUSH
FIFO flush
3
1
write-only
FFLUSH
NoFlush
No FIFO flush
0
Flush
FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
1
FTH
FIFO threshold
0
3
read-write
FTH
Empty
FIFO empty
0
Quarter1
1⁄4 FIFO
1
Quarter2
1⁄2 FIFO
2
Quarter3
3⁄4 FIFO
3
Full
FIFO full
4
FRCR
AFRCR
AFRCR
0x8
0x20
read-write
0x00000007
FSOFF
Frame synchronization
offset
18
1
read-write
FSOFF
OnFirst
FS is asserted on the first bit of the slot 0
0
BeforeFirst
FS is asserted one bit before the first bit of the slot 0
1
FSPOL
Frame synchronization
polarity
17
1
read-write
FSPOL
FallingEdge
FS is active low (falling edge)
0
RisingEdge
FS is active high (rising edge)
1
FSDEF
Frame synchronization
definition
16
1
read-write
FSALL
Frame synchronization active level
length
8
7
read-write
FRL
Frame length
0
8
read-write
SLOTR
ASLOTR
ASlot register
0xC
0x20
read-write
0x00000000
SLOTEN
Slot enable
16
16
SLOTEN
Inactive
Inactive slot
0
Active
Active slot
1
NBSLOT
Number of slots in an audio
frame
8
4
SLOTSZ
Slot size
6
2
SLOTSZ
DataSize
The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
0
Bit16
16-bit
1
Bit32
32-bit
2
FBOFF
First bit offset
0
5
IM
AIM
AInterrupt mask register2
0x10
0x20
read-write
0x00000000
LFSDETIE
Late frame synchronization detection
interrupt enable
6
1
LFSDETIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
AFSDETIE
Anticipated frame synchronization
detection interrupt enable
5
1
AFSDETIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
CNRDYIE
Codec not ready interrupt
enable
4
1
CNRDYIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
FREQIE
FIFO request interrupt
enable
3
1
FREQIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
WCKCFGIE
Wrong clock configuration interrupt
enable
2
1
WCKCFGIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
MUTEDETIE
Mute detection interrupt
enable
1
1
MUTEDETIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
OVRUDRIE
Overrun/underrun interrupt
enable
0
1
OVRUDRIE
Disabled
Interrupt is disabled
0
Enabled
Interrupt is enabled
1
SR
ASR
AStatus register
0x14
0x20
read-only
0x00000008
FLVL
FIFO level threshold
16
3
FLVLR
Empty
FIFO empty
0
Quarter1
FIFO <= 1⁄4 but not empty
1
Quarter2
1⁄4 < FIFO <= 1⁄2
2
Quarter3
1⁄2 < FIFO <= 3⁄4
3
Quarter4
3⁄4 < FIFO but not full
4
Full
FIFO full
5
LFSDET
Late frame synchronization
detection
6
1
LFSDETR
NoError
No error
0
NoSync
Frame synchronization signal is not present at the right time
1
AFSDET
Anticipated frame synchronization
detection
5
1
AFSDETR
NoError
No error
0
EarlySync
Frame synchronization signal is detected earlier than expected
1
CNRDY
Codec not ready
4
1
CNRDYR
Ready
External AC’97 Codec is ready
0
NotReady
External AC’97 Codec is not ready
1
FREQ
FIFO request
3
1
FREQR
NoRequest
No FIFO request
0
Request
FIFO request to read or to write the SAI_xDR
1
WCKCFG
Wrong clock configuration flag. This bit
is read only.
2
1
WCKCFGR
Correct
Clock configuration is correct
0
Wrong
Clock configuration does not respect the rule concerning the frame length specification
1
MUTEDET
Mute detection
1
1
MUTEDETR
NoMute
No MUTE detection on the SD input line
0
Mute
MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
1
OVRUDR
Overrun / underrun
0
1
OVRUDRR
NoError
No overrun/underrun error
0
Overrun
Overrun/underrun error detection
1
CLRFR
ACLRFR
AClear flag register
0x18
0x20
write-only
0x00000000
CLFSDET
Clear late frame synchronization
detection flag
6
1
CLFSDETW
Clear
Clears the LFSDET flag
1
CAFSDET
Clear anticipated frame synchronization
detection flag.
5
1
CAFSDETW
Clear
Clears the AFSDET flag
1
CCNRDY
Clear codec not ready flag
4
1
CCNRDYW
Clear
Clears the CNRDY flag
1
CWCKCFG
Clear wrong clock configuration
flag
2
1
CWCKCFGW
Clear
Clears the WCKCFG flag
1
CMUTEDET
Mute detection flag
1
1
CMUTEDETW
Clear
Clears the MUTEDET flag
1
COVRUDR
Clear overrun / underrun
0
1
COVRUDRW
Clear
Clears the OVRUDR flag
1
DR
ADR
AData register
0x1C
0x20
read-write
0x00000000
DATA
Data
0
32
DMA2D
DMA2D controller
DMA2D
0x4002B000
0x0
0xC00
registers
DMA2D
DMA2D global interrupt
90
DMA2D
DMA2D global interrupt
90
CR
CR
control register
0x0
0x20
read-write
0x00000000
MODE
DMA2D mode
16
2
CEIE
Configuration Error Interrupt
Enable
13
1
CTCIE
CLUT transfer complete interrupt
enable
12
1
CAEIE
CLUT access error interrupt
enable
11
1
TWIE
Transfer watermark interrupt
enable
10
1
TCIE
Transfer complete interrupt
enable
9
1
TEIE
Transfer error interrupt
enable
8
1
ABORT
Abort
2
1
SUSP
Suspend
1
1
START
Start
0
1
ISR
ISR
Interrupt Status Register
0x4
0x20
read-only
0x00000000
CEIF
Configuration error interrupt
flag
5
1
CTCIF
CLUT transfer complete interrupt
flag
4
1
CAEIF
CLUT access error interrupt
flag
3
1
TWIF
Transfer watermark interrupt
flag
2
1
TCIF
Transfer complete interrupt
flag
1
1
TEIF
Transfer error interrupt
flag
0
1
IFCR
IFCR
interrupt flag clear register
0x8
0x20
read-write
0x00000000
CCEIF
Clear configuration error interrupt
flag
5
1
CCTCIF
Clear CLUT transfer complete interrupt
flag
4
1
CAECIF
Clear CLUT access error interrupt
flag
3
1
CTWIF
Clear transfer watermark interrupt
flag
2
1
CTCIF
Clear transfer complete interrupt
flag
1
1
CTEIF
Clear Transfer error interrupt
flag
0
1
FGMAR
FGMAR
foreground memory address
register
0xC
0x20
read-write
0x00000000
MA
Memory address
0
32
FGOR
FGOR
foreground offset register
0x10
0x20
read-write
0x00000000
LO
Line offset
0
14
BGMAR
BGMAR
background memory address
register
0x14
0x20
read-write
0x00000000
MA
Memory address
0
32
BGOR
BGOR
background offset register
0x18
0x20
read-write
0x00000000
LO
Line offset
0
14
FGPFCCR
FGPFCCR
foreground PFC control
register
0x1C
0x20
read-write
0x00000000
ALPHA
Alpha value
24
8
AM
Alpha mode
16
2
CS
CLUT size
8
8
START
Start
5
1
CCM
CLUT color mode
4
1
CM
Color mode
0
4
FGCOLR
FGCOLR
foreground color register
0x20
0x20
read-write
0x00000000
RED
Red Value
16
8
GREEN
Green Value
8
8
BLUE
Blue Value
0
8
BGPFCCR
BGPFCCR
background PFC control
register
0x24
0x20
read-write
0x00000000
ALPHA
Alpha value
24
8
AM
Alpha mode
16
2
CS
CLUT size
8
8
START
Start
5
1
CCM
CLUT Color mode
4
1
CM
Color mode
0
4
BGCOLR
BGCOLR
background color register
0x28
0x20
read-write
0x00000000
RED
Red Value
16
8
GREEN
Green Value
8
8
BLUE
Blue Value
0
8
FGCMAR
FGCMAR
foreground CLUT memory address
register
0x2C
0x20
read-write
0x00000000
MA
Memory Address
0
32
BGCMAR
BGCMAR
background CLUT memory address
register
0x30
0x20
read-write
0x00000000
MA
Memory address
0
32
OPFCCR
OPFCCR
output PFC control register
0x34
0x20
read-write
0x00000000
CM
Color mode
0
3
OCOLR
OCOLR
output color register
0x38
0x20
read-write
0x00000000
APLHA
Alpha Channel Value
24
8
RED
Red Value
16
8
GREEN
Green Value
8
8
BLUE
Blue Value
0
8
OMAR
OMAR
output memory address register
0x3C
0x20
read-write
0x00000000
MA
Memory Address
0
32
OOR
OOR
output offset register
0x40
0x20
read-write
0x00000000
LO
Line Offset
0
14
NLR
NLR
number of line register
0x44
0x20
read-write
0x00000000
PL
Pixel per lines
16
14
NL
Number of lines
0
16
LWR
LWR
line watermark register
0x48
0x20
read-write
0x00000000
LW
Line watermark
0
16
AMTCR
AMTCR
AHB master timer configuration
register
0x4C
0x20
read-write
0x00000000
DT
Dead Time
8
8
EN
Enable
0
1
FGCLUT
FGCLUT
FGCLUT
0x400
0x20
read-write
0x00000000
APLHA
APLHA
24
8
RED
RED
16
8
GREEN
GREEN
8
8
BLUE
BLUE
0
8
BGCLUT
BGCLUT
BGCLUT
0x800
0x20
read-write
0x00000000
APLHA
APLHA
24
8
RED
RED
16
8
GREEN
GREEN
8
8
BLUE
BLUE
0
8
I2C1
Inter-integrated circuit
I2C
0x40005400
0x0
0x400
registers
I2C1_EV
I2C1 event interrupt
31
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
I2C1_ER
I2C1 error interrupt
32
CR1
CR1
Control register 1
0x0
0x20
read-write
0x00000000
SWRST
Software reset
15
1
SWRST
NotReset
I2C peripheral not under reset
0
Reset
I2C peripheral under reset
1
ALERT
SMBus alert
13
1
ALERT
Release
SMBA pin released high
0
Drive
SMBA pin driven low
1
PEC
Packet error checking
12
1
PEC
Disabled
No PEC transfer
0
Enabled
PEC transfer
1
POS
Acknowledge/PEC Position (for data
reception)
11
1
POS
Current
ACK bit controls the (N)ACK of the current byte being received
0
Next
ACK bit controls the (N)ACK of the next byte to be received
1
ACK
Acknowledge enable
10
1
ACK
NAK
No acknowledge returned
0
ACK
Acknowledge returned after a byte is received
1
STOP
Stop generation
9
1
STOP
NoStop
No Stop generation
0
Stop
In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte
1
START
Start generation
8
1
START
NoStart
No Start generation
0
Start
In master mode: repeated start generation, in slave mode: start generation when bus is free
1
NOSTRETCH
Clock stretching disable (Slave
mode)
7
1
NOSTRETCH
Enabled
Clock stretching enabled
0
Disabled
Clock stretching disabled
1
ENGC
General call enable
6
1
ENGC
Disabled
General call disabled
0
Enabled
General call enabled
1
ENPEC
PEC enable
5
1
ENPEC
Disabled
PEC calculation disabled
0
Enabled
PEC calculation enabled
1
ENARP
ARP enable
4
1
ENARP
Disabled
ARP disabled
0
Enabled
ARP enabled
1
SMBTYPE
SMBus type
3
1
SMBTYPE
Device
SMBus Device
0
Host
SMBus Host
1
SMBUS
SMBus mode
1
1
SMBUS
I2C
I2C Mode
0
SMBus
SMBus
1
PE
Peripheral enable
0
1
PE
Disabled
Peripheral disabled
0
Enabled
Peripheral enabled
1
CR2
CR2
Control register 2
0x4
0x20
read-write
0x00000000
LAST
DMA last transfer
12
1
LAST
NotLast
Next DMA EOT is not the last transfer
0
Last
Next DMA EOT is the last transfer
1
DMAEN
DMA requests enable
11
1
DMAEN
Disabled
DMA requests disabled
0
Enabled
DMA request enabled when TxE=1 or RxNE=1
1
ITBUFEN
Buffer interrupt enable
10
1
ITBUFEN
Disabled
TxE=1 or RxNE=1 does not generate any interrupt
0
Enabled
TxE=1 or RxNE=1 generates Event interrupt
1
ITEVTEN
Event interrupt enable
9
1
ITEVTEN
Disabled
Event interrupt disabled
0
Enabled
Event interrupt enabled
1
ITERREN
Error interrupt enable
8
1
ITERREN
Disabled
Error interrupt disabled
0
Enabled
Error interrupt enabled
1
FREQ
Peripheral clock frequency
0
6
2
50
OAR1
OAR1
Own address register 1
0x8
0x20
read-write
0x00000000
ADDMODE
Addressing mode (slave
mode)
15
1
ADDMODE
ADD7
7-bit slave address
0
ADD10
10-bit slave address
1
ADD
Interface address
0
10
0
1023
OAR2
OAR2
Own address register 2
0xC
0x20
read-write
0x00000000
ADD2
Interface address
1
7
0
127
ENDUAL
Dual addressing mode
enable
0
1
ENDUAL
Single
Single addressing mode
0
Dual
Dual addressing mode
1
DR
DR
Data register
0x10
0x20
read-write
0x00000000
DR
8-bit data register
0
8
0
255
SR1
SR1
Status register 1
0x14
0x20
0x00000000
SMBALERT
SMBus alert
15
1
read-write
zeroToClear
SMBALERTR
read
NoAlert
No SMBALERT occured
0
Alert
SMBALERT occurred
1
SMBALERTW
write
Clear
Clear flag
0
TIMEOUT
Timeout or Tlow error
14
1
read-write
zeroToClear
TIMEOUTR
read
NoTimeout
No Timeout error
0
Timeout
SCL remained LOW for 25 ms
1
TIMEOUTW
write
Clear
Clear flag
0
PECERR
PEC Error in reception
12
1
read-write
zeroToClear
PECERRR
read
NoError
no PEC error: receiver returns ACK after PEC reception (if ACK=1)
0
Error
PEC error: receiver returns NACK after PEC reception (whatever ACK)
1
PECERRW
write
Clear
Clear flag
0
OVR
Overrun/Underrun
11
1
read-write
zeroToClear
OVRR
read
NoOverrun
No overrun/underrun occured
0
Overrun
Overrun/underrun occured
1
OVRW
write
Clear
Clear flag
0
AF
Acknowledge failure
10
1
read-write
zeroToClear
AFR
read
NoFailure
No acknowledge failure
0
Failure
Acknowledge failure
1
AFW
write
Clear
Clear flag
0
ARLO
Arbitration lost (master
mode)
9
1
read-write
zeroToClear
ARLOR
read
NoLost
No Arbitration Lost detected
0
Lost
Arbitration Lost detected
1
ARLOW
write
Clear
Clear flag
0
BERR
Bus error
8
1
read-write
zeroToClear
BERRR
read
NoError
No misplaced Start or Stop condition
0
Error
Misplaced Start or Stop condition
1
BERRW
write
Clear
Clear flag
0
TxE
Data register empty
(transmitters)
7
1
read-only
TxE
NotEmpty
Data register not empty
0
Empty
Data register empty
1
RxNE
Data register not empty
(receivers)
6
1
read-only
RxNE
Empty
Data register empty
0
NotEmpty
Data register not empty
1
STOPF
Stop detection (slave
mode)
4
1
read-only
STOPF
NoStop
No Stop condition detected
0
Stop
Stop condition detected
1
ADD10
10-bit header sent (Master
mode)
3
1
read-only
BTF
Byte transfer finished
2
1
read-only
BTF
NotFinished
Data byte transfer not done
0
Finished
Data byte transfer successful
1
ADDR
Address sent (master mode)/matched
(slave mode)
1
1
read-only
ADDR
NotMatch
Adress mismatched or not received
0
Match
Received slave address matched with one of the enabled slave addresses
1
SB
Start bit (Master mode)
0
1
read-only
SB
NoStart
No Start condition
0
Start
Start condition generated
1
SR2
SR2
Status register 2
0x18
0x20
read-only
0x00000000
PEC
acket error checking
register
8
8
DUALF
Dual flag (Slave mode)
7
1
SMBHOST
SMBus host header (Slave
mode)
6
1
SMBDEFAULT
SMBus device default address (Slave
mode)
5
1
GENCALL
General call address (Slave
mode)
4
1
TRA
Transmitter/receiver
2
1
BUSY
Bus busy
1
1
MSL
Master/slave
0
1
CCR
CCR
Clock control register
0x1C
0x20
read-write
0x00000000
F_S
I2C master mode selection
15
1
F_S
Standard
Standard mode I2C
0
Fast
Fast mode I2C
1
DUTY
Fast mode duty cycle
14
1
DUTY
Duty2_1
Duty cycle t_low/t_high = 2/1
0
Duty16_9
Duty cycle t_low/t_high = 16/9
1
CCR
Clock control register in Fast/Standard
mode (Master mode)
0
12
1
4095
TRISE
TRISE
TRISE register
0x20
0x20
read-write
0x00000002
TRISE
Maximum rise time in Fast/Standard mode
(Master mode)
0
6
0
63
FLTR
FLTR
I2C FLTR register
0x24
0x20
read-write
0x00000000
DNF
Digital noise filter
0
4
DNF
NoFilter
Digital filter disabled
0
Filter1
Digital filter enabled and filtering capability up to 1 tI2CCLK
1
Filter2
Digital filter enabled and filtering capability up to 2 tI2CCLK
2
Filter3
Digital filter enabled and filtering capability up to 3 tI2CCLK
3
Filter4
Digital filter enabled and filtering capability up to 4 tI2CCLK
4
Filter5
Digital filter enabled and filtering capability up to 5 tI2CCLK
5
Filter6
Digital filter enabled and filtering capability up to 6 tI2CCLK
6
Filter7
Digital filter enabled and filtering capability up to 7 tI2CCLK
7
Filter8
Digital filter enabled and filtering capability up to 8 tI2CCLK
8
Filter9
Digital filter enabled and filtering capability up to 9 tI2CCLK
9
Filter10
Digital filter enabled and filtering capability up to 10 tI2CCLK
10
Filter11
Digital filter enabled and filtering capability up to 11 tI2CCLK
11
Filter12
Digital filter enabled and filtering capability up to 12 tI2CCLK
12
Filter13
Digital filter enabled and filtering capability up to 13 tI2CCLK
13
Filter14
Digital filter enabled and filtering capability up to 14 tI2CCLK
14
Filter15
Digital filter enabled and filtering capability up to 15 tI2CCLK
15
ANOFF
Analog noise filter OFF
4
1
ANOFF
Enabled
Analog noise filter enabled
0
Disabled
Analog noise filter disabled
1
I2C3
0x40005C00
I2C3_EV
I2C3 event interrupt
72
I2C3_EV
I2C3 event interrupt
72
I2C3_ER
I2C3 error interrupt
73
I2C3_ER
I2C3 error interrupt
73
I2C2
0x40005800
I2C2_EV
I2C2 event interrupt
33
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
I2C2_ER
I2C2 error interrupt
34
FPU
Floting point unit
FPU
0xE000EF34
0x0
0xD
registers
FPU
Floating point unit interrupt
81
FPCCR
FPCCR
Floating-point context control
register
0x0
0x20
read-write
0x00000000
LSPACT
LSPACT
0
1
USER
USER
1
1
THREAD
THREAD
3
1
HFRDY
HFRDY
4
1
MMRDY
MMRDY
5
1
BFRDY
BFRDY
6
1
MONRDY
MONRDY
8
1
LSPEN
LSPEN
30
1
ASPEN
ASPEN
31
1
FPCAR
FPCAR
Floating-point context address
register
0x4
0x20
read-write
0x00000000
ADDRESS
Location of unpopulated
floating-point
3
29
FPSCR
FPSCR
Floating-point status control
register
0x8
0x20
read-write
0x00000000
IOC
Invalid operation cumulative exception
bit
0
1
DZC
Division by zero cumulative exception
bit.
1
1
OFC
Overflow cumulative exception
bit
2
1
UFC
Underflow cumulative exception
bit
3
1
IXC
Inexact cumulative exception
bit
4
1
IDC
Input denormal cumulative exception
bit.
7
1
RMode
Rounding Mode control
field
22
2
FZ
Flush-to-zero mode control
bit:
24
1
DN
Default NaN mode control
bit
25
1
AHP
Alternative half-precision control
bit
26
1
V
Overflow condition code
flag
28
1
C
Carry condition code flag
29
1
Z
Zero condition code flag
30
1
N
Negative condition code
flag
31
1
MPU
Memory protection unit
MPU
0xE000ED90
0x0
0x15
registers
TYPER
TYPER
MPU type register
0x0
0x20
read-only
0x00000800
SEPARATE
Separate flag
0
1
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction
regions
16
8
CTRL
CTRL
MPU control register
0x4
0x20
read-only
0x00000000
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard
fault
1
1
PRIVDEFENA
Enable priviliged software access to
default memory map
2
1
RNR
RNR
MPU region number register
0x8
0x20
read-write
0x00000000
REGION
MPU region
0
8
RBAR
RBAR
MPU region base address
register
0xC
0x20
read-write
0x00000000
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
ADDR
Region base address field
5
27
RASR
RASR
MPU region attribute and size
register
0x10
0x20
read-write
0x00000000
ENABLE
Region enable bit.
0
1
SIZE
Size of the MPU protection
region
1
5
SRD
Subregion disable bits
8
8
B
memory attribute
16
1
C
memory attribute
17
1
S
Shareable memory attribute
18
1
TEX
memory attribute
19
3
AP
Access permission
24
3
XN
Instruction access disable
bit
28
1
STK
SysTick timer
STK
0xE000E010
0x0
0x11
registers
CTRL
CTRL
SysTick control and status
register
0x0
0x20
read-write
0x00000000
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request
enable
1
1
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
LOAD
LOAD
SysTick reload value register
0x4
0x20
read-write
0x00000000
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
0x20
read-write
0x00000000
CURRENT
Current counter value
0
24
CALIB
CALIB
SysTick calibration value
register
0xC
0x20
read-write
0x00000000
TENMS
Calibration value
0
24
SKEW
SKEW flag: Indicates whether the TENMS
value is exact
30
1
NOREF
NOREF flag. Reads as zero
31
1
SCB
System control block
SCB
0xE000ED00
0x0
0x41
registers
CPUID
CPUID
CPUID base register
0x0
0x20
read-only
0x410FC241
Revision
Revision number
0
4
PartNo
Part number of the
processor
4
12
Constant
Reads as 0xF
16
4
Variant
Variant number
20
4
Implementer
Implementer code
24
8
ICSR
ICSR
Interrupt control and state
register
0x4
0x20
read-write
0x00000000
VECTACTIVE
Active vector
0
9
RETTOBASE
Return to base level
11
1
VECTPENDING
Pending vector
12
7
ISRPENDING
Interrupt pending flag
22
1
PENDSTCLR
SysTick exception clear-pending
bit
25
1
PENDSTSET
SysTick exception set-pending
bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
NMIPENDSET
NMI set-pending bit.
31
1
VTOR
VTOR
Vector table offset register
0x8
0x20
read-write
0x00000000
TBLOFF
Vector table base offset
field
9
21
AIRCR
AIRCR
Application interrupt and reset control
register
0xC
0x20
read-write
0x00000000
VECTRESET
VECTRESET
0
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
SYSRESETREQ
SYSRESETREQ
2
1
PRIGROUP
PRIGROUP
8
3
ENDIANESS
ENDIANESS
15
1
VECTKEYSTAT
Register key
16
16
SCR
SCR
System control register
0x10
0x20
read-write
0x00000000
SLEEPONEXIT
SLEEPONEXIT
1
1
SLEEPDEEP
SLEEPDEEP
2
1
SEVEONPEND
Send Event on Pending bit
4
1
CCR
CCR
Configuration and control
register
0x14
0x20
read-write
0x00000000
NONBASETHRDENA
Configures how the processor enters
Thread mode
0
1
USERSETMPEND
USERSETMPEND
1
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
DIV_0_TRP
DIV_0_TRP
4
1
BFHFNMIGN
BFHFNMIGN
8
1
STKALIGN
STKALIGN
9
1
SHPR1
SHPR1
System handler priority
registers
0x18
0x20
read-write
0x00000000
PRI_4
Priority of system handler
4
0
8
PRI_5
Priority of system handler
5
8
8
PRI_6
Priority of system handler
6
16
8
SHPR2
SHPR2
System handler priority
registers
0x1C
0x20
read-write
0x00000000
PRI_11
Priority of system handler
11
24
8
SHPR3
SHPR3
System handler priority
registers
0x20
0x20
read-write
0x00000000
PRI_14
Priority of system handler
14
16
8
PRI_15
Priority of system handler
15
24
8
SHCRS
SHCRS
System handler control and state
register
0x24
0x20
read-write
0x00000000
MEMFAULTACT
Memory management fault exception active
bit
0
1
BUSFAULTACT
Bus fault exception active
bit
1
1
USGFAULTACT
Usage fault exception active
bit
3
1
SVCALLACT
SVC call active bit
7
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active
bit
10
1
SYSTICKACT
SysTick exception active
bit
11
1
USGFAULTPENDED
Usage fault exception pending
bit
12
1
MEMFAULTPENDED
Memory management fault exception
pending bit
13
1
BUSFAULTPENDED
Bus fault exception pending
bit
14
1
SVCALLPENDED
SVC call pending bit
15
1
MEMFAULTENA
Memory management fault enable
bit
16
1
BUSFAULTENA
Bus fault enable bit
17
1
USGFAULTENA
Usage fault enable bit
18
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status
register
0x28
0x20
read-write
0x00000000
IACCVIOL
Instruction access violation
flag
1
1
MUNSTKERR
Memory manager fault on unstacking for a
return from exception
3
1
MSTKERR
Memory manager fault on stacking for
exception entry.
4
1
MLSPERR
MLSPERR
5
1
MMARVALID
Memory Management Fault Address Register
(MMAR) valid flag
7
1
IBUSERR
Instruction bus error
8
1
PRECISERR
Precise data bus error
9
1
IMPRECISERR
Imprecise data bus error
10
1
UNSTKERR
Bus fault on unstacking for a return
from exception
11
1
STKERR
Bus fault on stacking for exception
entry
12
1
LSPERR
Bus fault on floating-point lazy state
preservation
13
1
BFARVALID
Bus Fault Address Register (BFAR) valid
flag
15
1
UNDEFINSTR
Undefined instruction usage
fault
16
1
INVSTATE
Invalid state usage fault
17
1
INVPC
Invalid PC load usage
fault
18
1
NOCP
No coprocessor usage
fault.
19
1
UNALIGNED
Unaligned access usage
fault
24
1
DIVBYZERO
Divide by zero usage fault
25
1
HFSR
HFSR
Hard fault status register
0x2C
0x20
read-write
0x00000000
VECTTBL
Vector table hard fault
1
1
FORCED
Forced hard fault
30
1
DEBUG_VT
Reserved for Debug use
31
1
MMFAR
MMFAR
Memory management fault address
register
0x34
0x20
read-write
0x00000000
MMFAR
Memory management fault
address
0
32
BFAR
BFAR
Bus fault address register
0x38
0x20
read-write
0x00000000
BFAR
Bus fault address
0
32
AFSR
AFSR
Auxiliary fault status
register
0x3C
0x20
read-write
0x00000000
IMPDEF
Implementation defined
0
32
NVIC_STIR
Nested vectored interrupt
controller
NVIC
0xE000EF00
0x0
0x5
registers
STIR
STIR
Software trigger interrupt
register
0x0
0x20
read-write
0x00000000
INTID
Software generated interrupt
ID
0
9
FPU_CPACR
Floating point unit CPACR
FPU
0xE000ED88
0x0
0x5
registers
CPACR
CPACR
Coprocessor access control
register
0x0
0x20
read-write
0x00000000
CP
CP
20
4
SCB_ACTRL
System control block ACTLR
SCB
0xE000E008
0x0
0x5
registers
ACTRL
ACTRL
Auxiliary control register
0x0
0x20
read-write
0x00000000
DISMCYCINT
DISMCYCINT
0
1
DISDEFWBUF
DISDEFWBUF
1
1
DISFOLD
DISFOLD
2
1
DISFPCA
DISFPCA
8
1
DISOOFP
DISOOFP
9
1