Registers In BDMA 0x58025400

RegisterOffset STM32H735 STM32H743 STM32H743 STM32H757_CM4 STM32H757_CM7 STM32H753 STM32H753 STM32H7B3 STM32H7R STM32H7S
BDMA_ISR0x0000
ISR0x0000
BDMA_IFCR0x0004
IFCR0x0004
BDMA_CCR00x0008
CH0_CR0x0008
BDMA_CNDTR00x000C
CH0_NDTR0x000C
BDMA_CPAR00x0010
CH0_PAR0x0010
BDMA_CM0AR00x0014
CH0_M0AR0x0014
BDMA_CM1AR00x0018
CH0_M1AR0x0018
BDMA_CCR10x001C
CH1_CR0x001C
BDMA_CNDTR10x0020
CH1_NDTR0x0020
BDMA_CPAR10x0024
CH1_PAR0x0024
BDMA_CM0AR10x0028
CH1_M0AR0x0028
BDMA_CM1AR10x002C
CH1_M1AR0x002C
BDMA_CCR20x0030
CH2_CR0x0030
BDMA_CNDTR20x0034
CH2_NDTR0x0034
BDMA_CPAR20x0038
CH2_PAR0x0038
BDMA_CM0AR20x003C
CH2_M0AR0x003C
BDMA_CM1AR20x0040
CH2_M1AR0x0040
BDMA_CCR30x0044
CH3_CR0x0044
BDMA_CNDTR30x0048
CH3_NDTR0x0048
BDMA_CPAR30x004C
CH3_PAR0x004C
BDMA_CM0AR30x0050
CH3_M0AR0x0050
BDMA_CM1AR30x0054
CH3_M1AR0x0054
BDMA_CCR40x0058
CH4_CR0x0058
BDMA_CNDTR40x005C
CH4_NDTR0x005C
BDMA_CPAR40x0060
CH4_PAR0x0060
BDMA_CM0AR40x0064
CH4_M0AR0x0064
BDMA_CM1AR40x0068
CH4_M1AR0x0068
BDMA_CCR50x006C
CH5_CR0x006C
BDMA_CNDTR50x0070
CH5_NDTR0x0070
BDMA_CPAR50x0074
CH5_PAR0x0074
BDMA_CM0AR50x0078
CH5_M0AR0x0078
BDMA_CM1AR50x007C
CH5_M1AR0x007C
BDMA_CCR60x0080
CH6_CR0x0080
BDMA_CNDTR60x0084
CH6_NDTR0x0084
BDMA_CPAR60x0088
CH6_PAR0x0088
BDMA_CM0AR60x008C
CH6_M0AR0x008C
BDMA_CM1AR60x0090
CH6_M1AR0x0090
BDMA_CCR70x0094
CH7_CR0x0094
BDMA_CNDTR70x0098
CH7_NDTR0x0098
BDMA_CPAR70x009C
CH7_PAR0x009C
BDMA_CM0AR70x00A0
CH7_M0AR0x00A0
BDMA_CM1AR70x00A4
CH7_M1AR0x00A4