STM32H750 2.7 STM32H750 CM7 r0p1 little true true 4 false 8 32 0x20 0x00000000 0xFFFFFFFF COMP1 COMP1 COMP 0x58003800 0x0 0x400 registers COMP COMP1 and COMP2 137 COMP1_SR COMP1_SR Comparator status register 0x0 0x20 read-only 0x00000000 C1VAL COMP channel 1 output status bit 0 1 C2VAL COMP channel 2 output status bit 1 1 C1IF COMP channel 1 Interrupt Flag 16 1 C2IF COMP channel 2 Interrupt Flag 17 1 COMP1_ICFR COMP1_ICFR Comparator interrupt clear flag register 0x4 0x20 write-only 0x00000000 CC1IF Clear COMP channel 1 Interrupt Flag 16 1 CC2IF Clear COMP channel 2 Interrupt Flag 17 1 COMP1_OR COMP1_OR Comparator option register 0x8 0x20 read-write 0x00000000 AFOP Selection of source for alternate function of output ports 0 11 OR Option Register 11 21 COMP1_CFGR1 COMP1_CFGR1 Comparator configuration register 1 0xC 0x20 read-write 0x00000000 EN COMP channel 1 enable bit 0 1 BRGEN Scaler bridge enable 1 1 SCALEN Voltage scaler enable bit 2 1 POLARITY COMP channel 1 polarity selection bit 3 1 ITEN COMP channel 1 interrupt enable 6 1 HYST COMP channel 1 hysteresis selection bits 8 2 PWRMODE Power Mode of the COMP channel 1 12 2 INMSEL COMP channel 1 inverting input selection field 16 3 INPSEL COMP channel 1 non-inverting input selection bit 20 1 BLANKING COMP channel 1 blanking source selection bits 24 4 LOCK Lock bit 31 1 COMP1_CFGR2 COMP1_CFGR2 Comparator configuration register 2 0x10 0x20 read-write 0x00000000 EN COMP channel 1 enable bit 0 1 BRGEN Scaler bridge enable 1 1 SCALEN Voltage scaler enable bit 2 1 POLARITY COMP channel 1 polarity selection bit 3 1 WINMODE Window comparator mode selection bit 4 1 ITEN COMP channel 1 interrupt enable 6 1 HYST COMP channel 1 hysteresis selection bits 8 2 PWRMODE Power Mode of the COMP channel 1 12 2 INMSEL COMP channel 1 inverting input selection field 16 3 INPSEL COMP channel 1 non-inverting input selection bit 20 1 BLANKING COMP channel 1 blanking source selection bits 24 4 LOCK Lock bit 31 1 CRS CRS CRS 0x40008400 0x0 0x400 registers CRS Clock Recovery System globa 144 CR CR CRS control register 0x0 0x20 0x00002000 SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCOKIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 SYNCWARNIE SYNC warning interrupt enable 1 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write CEN Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 5 1 read-write CEN Disabled Frequency error counter disabled 0 Enabled Frequency error counter enabled 1 AUTOTRIMEN Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. 6 1 read-write AUTOTRIMEN Disabled Automatic trimming disabled 0 Enabled Automatic trimming enabled 1 SWSYNC Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 7 1 read-only SWSYNC Sync A software sync is generated 1 TRIM HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. 8 6 read-write 0 63 CFGR CFGR This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. 0x4 0x20 read-write 0x2022BB7F RELOAD Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. 0 16 0 65535 FELIM Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. 16 8 0 255 SYNCDIV SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 24 3 SYNCDIV Div1 SYNC not divided 0 Div2 SYNC divided by 2 1 Div4 SYNC divided by 4 2 Div8 SYNC divided by 8 3 Div16 SYNC divided by 16 4 Div32 SYNC divided by 32 5 Div64 SYNC divided by 64 6 Div128 SYNC divided by 128 7 SYNCSRC SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. 28 2 SYNCSRC GPIO_AF GPIO AF (crs_sync_in_1) selected as SYNC signal source 0 LSE LSE (crs_sync_in_2) selected as SYNC signal source 1 USB_SOF USB SOF (crs_sync_in_3) selected as SYNC signal source 2 SYNCPOL SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 31 1 SYNCPOL RisingEdge SYNC active on rising edge 0 FallingEdge SYNC active on falling edge 1 ISR ISR CRS interrupt and status register 0x8 0x20 read-only 0x00000000 SYNCOKF SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 1 SYNCOKF NotSignaled Signal not set 0 Signaled Signal set 1 SYNCWARNF SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 1 1 ERRF Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 2 1 ESYNCF Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 3 1 SYNCERR SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 8 1 SYNCMISS SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 9 1 TRIMOVF Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 10 1 FEDIR Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 15 1 FEDIR UpCounting Error in up-counting direction 0 DownCounting Error in down-counting direction 1 FECAP Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. 16 16 0 65535 ICR ICR CRS interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 0 1 SYNCOKC Clear Clear flag 1 SYNCWARNC SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. 1 1 ERRC Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. 2 1 ESYNCC Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. 3 1 DAC DAC DAC 0x40007400 0x0 0x400 registers CR CR DAC control register 0x0 0x20 read-write 0x00000000 2 0x10 1-2 EN%s DAC channel%s enable 0 1 EN1 Disabled DAC Channel X disabled 0 Enabled DAC Channel X enabled 1 2 0x10 1-2 TEN%s DAC channel%s trigger enable 1 1 TEN1 Disabled DAC Channel X trigger disabled 0 Enabled DAC Channel X trigger enabled 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL1 Swtrig Software trigger 0 Tim1Trgo Timer 1 TRGO event 1 Tim2Trgo Timer 2 TRGO event 2 Tim4Trgo Timer 4 TRGO event 3 Tim5Trgo Timer 5 TRGO event 4 Tim6Trgo Timer 6 TRGO event 5 Tim7Trgo Timer 7 TRGO event 6 Tim8Trgo Timer 8 TRGO event 7 Tim15Trgo Timer 15 TRGO event 8 Hrtim1Dac1 hrtim1_dactrg1 9 Hrtim1Dac2 hrtim1_dactrg2 10 Lptim1Out LPTIM1 OUT event 11 Lptim2Out LPTIM2 OUT event 12 Exti9 EXTI line 9 13 2 0x10 1-2 WAVE%s DAC channel%s noise/triangle wave generation enable 6 2 WAVE1 Disabled Wave generation disabled 0 Noise Noise wave generation enabled 1 Triangle Triangle wave generation enabled true 2 0x10 1-2 MAMP%s DAC channel%s mask/amplitude selector 8 4 MAMP1 Amp1 Unmask bit0 of LFSR/ triangle amplitude equal to 1 0 Amp3 Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 1 Amp7 Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 2 Amp15 Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 3 Amp31 Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 4 Amp63 Unmask bits[5:0] of LFSR/ triangle amplitude equal 63 5 Amp127 Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 6 Amp255 Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 7 Amp511 Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 8 Amp1023 Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 9 Amp2047 Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 10 Amp4095 Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 true 2 0x10 1-2 DMAEN%s DAC channel%s DMA enable 12 1 DMAEN1 Disabled DAC Channel X DMA mode disabled 0 Enabled DAC Channel X DMA mode enabled 1 2 0x10 1-2 DMAUDRIE%s DAC channel%s DMA Underrun Interrupt enable 13 1 DMAUDRIE1 Disabled DAC channel X DMA Underrun Interrupt disabled 0 Enabled DAC channel X DMA Underrun Interrupt enabled 1 2 0x10 1-2 CEN%s DAC channel%s calibration enable 14 1 CEN1 Normal DAC Channel X Normal operating mode 0 Calibration DAC Channel X calibration mode 1 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 SWTRGR SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 2 0x1 1-2 SWTRIG%s DAC channel%s software trigger 0 1 SWTRIG1 NoTrigger No trigger 0 Trigger Trigger 1 2 0xC 1-2 DHR12R%s DHR12R%s channel%s 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 0 4095 2 0xC 1-2 DHR12L%s DHR12L%s channel%s 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACCDHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 0 4095 2 0xC 1-2 DHR8R%s DHR8R%s channel%s 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACCDHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 0 255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit right-aligned data 0 12 0 4095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 2 0x10 1-2 DACC%sDHR DAC channel%s 12-bit left-aligned data 4 12 0 4095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 2 0x8 1-2 DACC%sDHR DAC channel%s 8-bit right-aligned data 0 8 0 255 2 0x4 1-2 DOR%s DOR%s channel%s data output register 0x2C 0x20 read-only 0x00000000 DACCDOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 0 4095 SR SR DAC status register 0x34 0x20 0x00000000 2 0x10 1-2 DMAUDR%s DAC channel%s DMA underrun flag 13 1 read-write DMAUDR1 NoUnderrun No DMA underrun error condition occurred for DAC channel x 0 Underrun DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) 1 2 0x10 1-2 CAL_FLAG%s DAC channel%s calibration offset status 14 1 read-only CAL_FLAG1 Lower Calibration trimming value is lower than the offset correction value 0 Equal_Higher Calibration trimming value is equal or greater than the offset correction value 1 2 0x10 1-2 BWST%s DAC channel%s busy writing sample time flag 15 1 read-only BWST1 Idle There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 0 Busy There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written 1 CCR CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 2 0x10 1-2 OTRIM%s DAC channel%s offset trimming value 0 5 0 31 MCR MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 2 0x10 1-2 MODE%s DAC channel%s mode 0 3 MODE1 NormalPinBuffer Normal mode - DAC channelx is connected to external pin with Buffer enabled 0 NormalPinChipBuffer Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 1 NormalPinNoBuffer Normal mode - DAC channelx is connected to external pin with Buffer disabled 2 NormalChipNoBuffer Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled 3 SHPinBuffer S&H mode - DAC channelx is connected to external pin with Buffer enabled 4 SHPinChipBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled 5 SHPinNoBuffer S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled 6 SHChipNoBuffer S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled 7 2 0x4 1-2 SHSR%s SHSR%s DAC channel%s sample and hold sample time register 0x40 0x20 read-write 0x00000000 TSAMPLE DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 0 1023 SHHR SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 2 0x10 1-2 THOLD%s DAC channel%s hold time (only valid in Sample and hold mode) 0 10 0 1023 SHRR SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 2 0x10 1-2 TREFRESH%s DAC channel%s refresh time (only valid in Sample and hold mode) 0 8 0 255 BDMA BDMA BDMA 0x58025400 0x0 0x400 registers BDMA_CH0 BDMA channel 0 interrupt 129 BDMA_CH1 BDMA channel 1 interrupt 130 BDMA_CH2 BDMA channel 2 interrupt 131 BDMA_CH3 BDMA channel 3 interrupt 132 BDMA_CH4 BDMA channel 4 interrupt 133 BDMA_CH5 BDMA channel 5 interrupt 134 BDMA_CH6 BDMA channel 6 interrupt 135 BDMA_CH7 BDMA channel 7 interrupt 136 ISR ISR BDMA interrupt status register 0x0 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 GIF%s Channel %s Global interrupt flag 0 1 read-only GIF0 NoEvent No TE, HT or TC event on channel x 0 Event A TE, HT or TC event occurred on channel x 1 8 0x4 0-7 TCIF%s Channel %s Transfer Complete flag 1 1 read-only TCIF0 NotComplete No transfer complete event on channel x 0 Complete A transfer complete event occurred on channel x 1 8 0x4 0-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 read-only HTIF0 NotHalf No half transfer event on channel x 0 Half A half transfer event occurred on channel x 1 8 0x4 0-7 TEIF%s Channel %s Transfer Error flag 3 1 read-only TEIF0 NoError No transfer error on channel x 0 Error A transfer error occurred on channel x 1 IFCR IFCR BDMA interrupt flag clear register 0x4 0x20 0x00000000 0xFFFFFFFF 8 0x4 0-7 CGIF%s Channel %s Global interrupt clear 0 1 write-only CGIF0 Clear Clear the corresponding CGIFx flag 1 8 0x4 0-7 CTCIF%s Channel %s Transfer Complete clear 1 1 write-only CTCIF0 Clear Clear the corresponding TCIFx flag 1 8 0x4 0-7 CHTIF%s Channel %s Half Transfer clear 2 1 write-only CHTIF0 Clear Clear the corresponding HTIFx flag 1 8 0x4 0-7 CTEIF%s Channel %s Transfer Error clear 3 1 write-only CTEIF0 Clear Clear the corresponding TEIFx flag 1 8 0x14 0-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR? registers 0x8 CR CCR0 BDMA channel 0 configuration register 0x0 0x20 0x00000000 0xFFFFFFFF EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the BDMA_ISR register is cleared (by setting the CTEIFx bit of the BDMA_IFCR register). Note: this bit is set and cleared by software. 0 1 read-write EN Disabled Channel disabled 0 Enabled Channel enabled 1 TCIE transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 1 1 read-write TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 HTIE half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 2 1 read-write HTIE Disabled HT interrupt disabled 0 Enabled HT interrupt enabled 1 TEIE transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 3 1 read-write TEIE Disabled TE interrupt disabled 0 Enabled TE interrupt enabled 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the BDMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the BDMA_CM0/1ARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the BDMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the BDMA_CM0/1ARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 4 1 read-write DIR PeripheralToMemory Peripheral-to-memory 0 MemoryToPeripheral Memory-to-peripheral 1 CIRC circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 5 1 read-write CIRC Disabled Circular mode disabled 0 Enabled Circular mode enabled 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 6 1 read-write PINC Fixed Address pointer is fixed 0 Incremented Address pointer is incremented after each data transfer 1 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 7 1 read-write PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 8 2 read-write PSIZE Bits8 Byte (8-bit) 0 Bits16 Half-word (16-bit) 1 Bits32 Word (32-bit) 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 10 2 read-write PL priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 12 2 read-write PL Low Low 0 Medium Medium 1 High High 2 VeryHigh Very high 3 MEM2MEM memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 14 1 read-write MEM2MEM Disabled Memory-to-memory mode disabled 0 Enabled Memory-to-memory mode enabled 1 DBM double-buffer mode This bit must be set only in memory-to-peripheral and peripheral-to-memory transfers (MEM2MEM=0). The CIRC bit must also be set in double buffer mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 15 1 read-write DBM Disabled No buffer switching at the end of transfer 0 Enabled Memory target switched at the end of the DMA transfer 1 CT current target memory of DMA transfer in double-buffer mode This bit is toggled by hardware at the end of each channel transfer in double-buffer mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 16 1 read-write CT Memory0 The current target memory is Memory 0 0 Memory1 The current target memory is Memory 1 1 NDTR CNDTR0 0x4 0x20 0x00000000 0xFFFFFFFF NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single BDMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 16 read-write 0 65535 PAR CPAR0 0x8 0x20 0x00000000 0xFFFFFFFF PA peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 32 read-write M0AR CM0AR0 0xC 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 32 read-write M1AR CM1AR0 0x10 0x20 0x00000000 0xFFFFFFFF MA peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 32 read-write DMA2D DMA2D DMA2D 0x52001000 0x0 0x400 registers DMA2D DMA2D global interrupt 90 CR CR DMA2D control register 0x0 0x20 read-write 0x00000000 START Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers 0 1 START Start Launch the DMA2D 1 SUSP Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. 1 1 SUSP NotSuspended Transfer not suspended 0 Suspended Transfer suspended 1 ABORT Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. 2 1 ABORT AbortRequest Transfer abort requested 1 TEIE Transfer error interrupt enable This bit is set and cleared by software. 8 1 TEIE Disabled TE interrupt disabled 0 Enabled TE interrupt enabled 1 TCIE Transfer complete interrupt enable This bit is set and cleared by software. 9 1 TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 TWIE Transfer watermark interrupt enable This bit is set and cleared by software. 10 1 TWIE Disabled TW interrupt disabled 0 Enabled TW interrupt enabled 1 CAEIE CLUT access error interrupt enable This bit is set and cleared by software. 11 1 CAEIE Disabled CAE interrupt disabled 0 Enabled CAE interrupt enabled 1 CTCIE CLUT transfer complete interrupt enable This bit is set and cleared by software. 12 1 CTCIE Disabled CTC interrupt disabled 0 Enabled CTC interrupt enabled 1 CEIE Configuration Error Interrupt Enable This bit is set and cleared by software. 13 1 CEIE Disabled CE interrupt disabled 0 Enabled CE interrupt enabled 1 MODE DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. 16 2 MODE MemoryToMemory Memory-to-memory (FG fetch only) 0 MemoryToMemoryPFC Memory-to-memory with PFC (FG fetch only with FG PFC active) 1 MemoryToMemoryPFCBlending Memory-to-memory with blending (FG and BG fetch with PFC and blending) 2 RegisterToMemory Register-to-memory 3 ISR ISR DMA2D Interrupt Status Register 0x4 0x20 read-only 0x00000000 TEIF Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). 0 1 TCIF Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). 1 1 TWIF Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. 2 1 CAEIF CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. 3 1 CTCIF CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. 4 1 CEIF Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed. 5 1 IFCR IFCR DMA2D interrupt flag clear register 0x8 0x20 read-write 0x00000000 CTEIF Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register 0 1 CTEIF Clear Clear the TEIF flag in the ISR register 1 CTCIF Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register 1 1 CTCIF Clear Clear the TCIF flag in the ISR register 1 CTWIF Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register 2 1 CTWIF Clear Clear the TWIF flag in the ISR register 1 CAECIF Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register 3 1 CAECIF Clear Clear the CAEIF flag in the ISR register 1 CCTCIF Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register 4 1 CCTCIF Clear Clear the CTCIF flag in the ISR register 1 CCEIF Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register 5 1 CCEIF Clear Clear the CEIF flag in the ISR register 1 FGMAR FGMAR DMA2D foreground memory address register 0xC 0x20 read-write 0x00000000 MA Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. 0 32 FGOR FGOR DMA2D foreground offset register 0x10 0x20 read-write 0x00000000 LO Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. 0 16 0 65535 BGMAR BGMAR DMA2D background memory address register 0x14 0x20 read-write 0x00000000 MA Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. 0 32 BGOR BGOR DMA2D background offset register 0x18 0x20 read-write 0x00000000 LO Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. 0 16 0 65535 FGPFCCR FGPFCCR DMA2D foreground PFC control register 0x1C 0x20 read-write 0x00000000 CM Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless 0 4 CM ARGB8888 Color mode ARGB8888 0 RGB888 Color mode RGB888 1 RGB565 Color mode RGB565 2 ARGB1555 Color mode ARGB1555 3 ARGB4444 Color mode ARGB4444 4 L8 Color mode L8 5 AL44 Color mode AL44 6 AL88 Color mode AL88 7 L4 Color mode L4 8 A8 Color mode A8 9 A4 Color mode A4 10 YCbCr Color mode YCbCr 11 CCM CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. 4 1 CCM ARGB8888 CLUT color format ARGB8888 0 RGB888 CLUT color format RGB888 1 START Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer). 5 1 START Start Start the automatic loading of the CLUT 1 CS CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. 8 8 0 255 AM Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless 16 2 AM NoModify No modification of alpha channel 0 Replace Replace with value in ALPHA[7:0] 1 Multiply Multiply with value in ALPHA[7:0] 2 CSS Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless 18 2 AI Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. 20 1 AI RegularAlpha Regular alpha 0 InvertedAlpha Inverted alpha 1 RBS Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 21 1 RBS Regular No Red Blue Swap (RGB or ARGB) 0 Swap Red Blue Swap (BGR or ABGR) 1 ALPHA Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only. 24 8 0 255 FGCOLR FGCOLR DMA2D foreground color register 0x20 0x20 read-write 0x00000000 BLUE Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. 0 8 0 255 GREEN Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. 8 8 0 255 RED Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 16 8 0 255 BGPFCCR BGPFCCR DMA2D background PFC control register 0x24 0x20 read-write 0x00000000 CM Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless 0 4 CM ARGB8888 Color mode ARGB8888 0 RGB888 Color mode RGB888 1 RGB565 Color mode RGB565 2 ARGB1555 Color mode ARGB1555 3 ARGB4444 Color mode ARGB4444 4 L8 Color mode L8 5 AL44 Color mode AL44 6 AL88 Color mode AL88 7 L4 Color mode L4 8 A8 Color mode A8 9 A4 Color mode A4 10 CCM CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. 4 1 CCM ARGB8888 CLUT color format ARGB8888 0 RGB888 CLUT color format RGB888 1 START Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer). 5 1 START Start Start the automatic loading of the CLUT 1 CS CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. 8 8 0 255 AM Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless 16 2 AM NoModify No modification of alpha channel 0 Replace Replace with value in ALPHA[7:0] 1 Multiply Multiply with value in ALPHA[7:0] 2 AI Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. 20 1 AI RegularAlpha Regular alpha 0 InvertedAlpha Inverted alpha 1 RBS Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 21 1 RBS Regular No Red Blue Swap (RGB or ARGB) 0 Swap Red Blue Swap (BGR or ABGR) 1 ALPHA Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 24 8 0 255 BGCOLR BGCOLR DMA2D background color register 0x28 0x20 read-write 0x00000000 BLUE Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 0 8 0 255 GREEN Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 8 8 0 255 RED Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 16 8 0 255 FGCMAR FGCMAR DMA2D foreground CLUT memory address register 0x2C 0x20 read-write 0x00000000 MA Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. 0 32 BGCMAR BGCMAR DMA2D background CLUT memory address register 0x30 0x20 read-write 0x00000000 MA Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned. 0 32 OPFCCR OPFCCR DMA2D output PFC control register 0x34 0x20 read-write 0x00000000 CM Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless 0 3 CM ARGB8888 ARGB8888 0 RGB888 RGB888 1 RGB565 RGB565 2 ARGB1555 ARGB1555 3 ARGB4444 ARGB4444 4 AI Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. 20 1 AI RegularAlpha Regular alpha 0 InvertedAlpha Inverted alpha 1 RBS Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 21 1 RBS Regular No Red Blue Swap (RGB or ARGB) 0 Swap Red Blue Swap (BGR or ABGR) 1 SB Swap Bytes 8 1 SB Regular Regular byte order 0 SwapBytes Bytes are swapped two by two 1 OCOLR OCOLR DMA2D output color register 0x38 0x20 read-write 0x00000000 BLUE Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 0 8 GREEN Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 8 8 RED Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 16 8 ALPHA Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 24 8 OMAR OMAR DMA2D output memory address register 0x3C 0x20 read-write 0x00000000 MA Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned. 0 32 OOR OOR DMA2D output offset register 0x40 0x20 read-write 0x00000000 LO Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 0 16 0 65535 NLR NLR DMA2D number of line register 0x44 0x20 read-write 0x00000000 NL Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 0 16 0 65535 PL Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even. 16 14 0 16383 LWR LWR DMA2D line watermark register 0x48 0x20 read-write 0x00000000 LW Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 0 16 AMTCR AMTCR DMA2D AXI master timer configuration register 0x4C 0x20 read-write 0x00000000 EN Enable Enables the dead time functionality. 0 1 EN Disabled Disabled AHB/AXI dead-time functionality 0 Enabled Enabled AHB/AXI dead-time functionality 1 DT Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. 8 8 0 255 DMAMUX1 DMAMUX DMAMUX 0x40020800 0x0 0x400 registers DMAMUX1_OV DMAMUX1 overrun interrupt 102 16 0x4 0-15 C%sCR C%sCR 0x0 0x20 0x00000000 0xFFFFFFFF DMAREQ_ID DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 0 7 read-write DMAREQ_ID none No signal selected as request input 0 dmamux1_req_gen0 Signal `dmamux1_req_gen0` selected as request input 1 dmamux1_req_gen1 Signal `dmamux1_req_gen1` selected as request input 2 dmamux1_req_gen2 Signal `dmamux1_req_gen2` selected as request input 3 dmamux1_req_gen3 Signal `dmamux1_req_gen3` selected as request input 4 dmamux1_req_gen4 Signal `dmamux1_req_gen4` selected as request input 5 dmamux1_req_gen5 Signal `dmamux1_req_gen5` selected as request input 6 dmamux1_req_gen6 Signal `dmamux1_req_gen6` selected as request input 7 dmamux1_req_gen7 Signal `dmamux1_req_gen7` selected as request input 8 adc1_dma Signal `adc1_dma` selected as request input 9 adc2_dma Signal `adc2_dma` selected as request input 10 tim1_ch1 Signal `tim1_ch1` selected as request input 11 tim1_ch2 Signal `tim1_ch2` selected as request input 12 tim1_ch3 Signal `tim1_ch3` selected as request input 13 tim1_ch4 Signal `tim1_ch4` selected as request input 14 tim1_up Signal `tim1_up` selected as request input 15 tim1_trig Signal `tim1_trig` selected as request input 16 tim1_com Signal `tim1_com` selected as request input 17 tim2_ch1 Signal `tim2_ch1` selected as request input 18 tim2_ch2 Signal `tim2_ch2` selected as request input 19 tim2_ch3 Signal `tim2_ch3` selected as request input 20 tim2_ch4 Signal `tim2_ch4` selected as request input 21 tim2_up Signal `tim2_up` selected as request input 22 tim3_ch1 Signal `tim3_ch1` selected as request input 23 tim3_ch2 Signal `tim3_ch2` selected as request input 24 tim3_ch3 Signal `tim3_ch3` selected as request input 25 tim3_ch4 Signal `tim3_ch4` selected as request input 26 tim3_up Signal `tim3_up` selected as request input 27 tim3_trig Signal `tim3_trig` selected as request input 28 tim4_ch1 Signal `tim4_ch1` selected as request input 29 tim4_ch2 Signal `tim4_ch2` selected as request input 30 tim4_ch3 Signal `tim4_ch3` selected as request input 31 tim4_up Signal `tim4_up` selected as request input 32 i2c1_rx_dma Signal `i2c1_rx_dma` selected as request input 33 i2c1_tx_dma Signal `i2c1_tx_dma` selected as request input 34 i2c2_rx_dma Signal `i2c2_rx_dma` selected as request input 35 i2c2_tx_dma Signal `i2c2_tx_dma` selected as request input 36 spi1_rx_dma Signal `spi1_rx_dma` selected as request input 37 spi1_tx_dma Signal `spi1_tx_dma` selected as request input 38 spi2_rx_dma Signal `spi2_rx_dma` selected as request input 39 spi2_tx_dma Signal `spi2_tx_dma` selected as request input 40 usart1_rx_dma Signal `usart1_rx_dma` selected as request input 41 usart1_tx_dma Signal `usart1_tx_dma` selected as request input 42 usart2_rx_dma Signal `usart2_rx_dma` selected as request input 43 usart2_tx_dma Signal `usart2_tx_dma` selected as request input 44 usart3_rx_dma Signal `usart3_rx_dma` selected as request input 45 usart3_tx_dma Signal `usart3_tx_dma` selected as request input 46 tim8_ch1 Signal `tim8_ch1` selected as request input 47 tim8_ch2 Signal `tim8_ch2` selected as request input 48 tim8_ch3 Signal `tim8_ch3` selected as request input 49 tim8_ch4 Signal `tim8_ch4` selected as request input 50 tim8_up Signal `tim8_up` selected as request input 51 tim8_trig Signal `tim8_trig` selected as request input 52 tim8_com Signal `tim8_com` selected as request input 53 tim5_ch1 Signal `tim5_ch1` selected as request input 55 tim5_ch2 Signal `tim5_ch2` selected as request input 56 tim5_ch3 Signal `tim5_ch3` selected as request input 57 tim5_ch4 Signal `tim5_ch4` selected as request input 58 tim5_up Signal `tim5_up` selected as request input 59 tim5_trig Signal `tim5_trig` selected as request input 60 spi3_rx_dma Signal `spi3_rx_dma` selected as request input 61 spi3_tx_dma Signal `spi3_tx_dma` selected as request input 62 uart4_rx_dma Signal `uart4_rx_dma` selected as request input 63 uart4_tx_dma Signal `uart4_tx_dma` selected as request input 64 uart5_rx_dma Signal `uart5_rx_dma` selected as request input 65 uart5_tx_dma Signal `uart5_tx_dma` selected as request input 66 dac_ch1_dma Signal `dac_ch1_dma` selected as request input 67 dac_ch2_dma Signal `dac_ch2_dma` selected as request input 68 tim6_up Signal `tim6_up` selected as request input 69 tim7_up Signal `tim7_up` selected as request input 70 usart6_rx_dma Signal `usart6_rx_dma` selected as request input 71 usart6_tx_dma Signal `usart6_tx_dma` selected as request input 72 i2c3_rx_dma Signal `i2c3_rx_dma` selected as request input 73 i2c3_tx_dma Signal `i2c3_tx_dma` selected as request input 74 dcmi_dma Signal `dcmi_dma` selected as request input 75 cryp_in_dma Signal `cryp_in_dma` selected as request input 76 cryp_out_dma Signal `cryp_out_dma` selected as request input 77 hash_in_dma Signal `hash_in_dma` selected as request input 78 uart7_rx_dma Signal `uart7_rx_dma` selected as request input 79 uart7_tx_dma Signal `uart7_tx_dma` selected as request input 80 uart8_rx_dma Signal `uart8_rx_dma` selected as request input 81 uart8_tx_dma Signal `uart8_tx_dma` selected as request input 82 spi4_rx_dma Signal `spi4_rx_dma` selected as request input 83 spi4_tx_dma Signal `spi4_tx_dma` selected as request input 84 spi5_rx_dma Signal `spi5_rx_dma` selected as request input 85 spi5_tx_dma Signal `spi5_tx_dma` selected as request input 86 sai1a_dma Signal `sai1a_dma` selected as request input 87 sai1b_dma Signal `sai1b_dma` selected as request input 88 sai2a_dma Signal `sai2a_dma` selected as request input 89 sai2b_dma Signal `sai2b_dma` selected as request input 90 swpmi_rx_dma Signal `swpmi_rx_dma` selected as request input 91 swpmi_tx_dma Signal `swpmi_tx_dma` selected as request input 92 spdifrx_dat_dma Signal `spdifrx_dat_dma` selected as request input 93 spdifrx_ctrl_dma Signal `spdifrx_ctrl_dma` selected as request input 94 hr_req1 Signal `hr_req(1)` selected as request input 95 hr_req2 Signal `hr_req(2)` selected as request input 96 hr_req3 Signal `hr_req(3)` selected as request input 97 hr_req4 Signal `hr_req(4)` selected as request input 98 hr_req5 Signal `hr_req(5)` selected as request input 99 hr_req6 Signal `hr_req(6)` selected as request input 100 dfsdm1_dma0 Signal `dfsdm1_dma0` selected as request input 101 dfsdm1_dma1 Signal `dfsdm1_dma1` selected as request input 102 dfsdm1_dma2 Signal `dfsdm1_dma2` selected as request input 103 dfsdm1_dma3 Signal `dfsdm1_dma3` selected as request input 104 tim15_ch1 Signal `tim15_ch1` selected as request input 105 tim15_up Signal `tim15_up` selected as request input 106 tim15_trig Signal `tim15_trig` selected as request input 107 tim15_com Signal `tim15_com` selected as request input 108 tim16_ch1 Signal `tim16_ch1` selected as request input 109 tim16_up Signal `tim16_up` selected as request input 110 tim17_ch1 Signal `tim17_ch1` selected as request input 111 tim17_up Signal `tim17_up` selected as request input 112 sai3_a_dma Signal `sai3_a_dma` selected as request input 113 sai3_b_dma Signal `sai3_b_dma` selected as request input 114 adc3_dma Signal `adc3_dma` selected as request input 115 SOIE Synchronization overrun interrupt enable 8 1 read-write SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 EGE Event generation enable 9 1 read-write EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SE Synchronization enable 16 1 read-write SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 SPOL Synchronization polarity Defines the edge polarity of the selected synchronization input: 17 2 read-write SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 NBREQ Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. 19 5 read-write 0 31 SYNC_ID Synchronization identification Selects the synchronization input (see inputs to resources). 24 3 read-write SYNC_ID dmamux1_evt0 Signal `dmamux1_evt0` selected as synchronization input 0 dmamux1_evt1 Signal `dmamux1_evt1` selected as synchronization input 1 dmamux1_evt2 Signal `dmamux1_evt2` selected as synchronization input 2 lptim1_out Signal `lptim1_out` selected as synchronization input 3 lptim2_out Signal `lptim2_out` selected as synchronization input 4 lptim3_out Signal `lptim3_out` selected as synchronization input 5 extit0 Signal `extit0` selected as synchronization input 6 tim12_trgo Signal `tim12_trgo` selected as synchronization input 7 CSR CSR 0x80 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 SOF%s Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. For DMAMUX2 bits 15:8 are reserved, keep them at reset value. 0 1 read-only SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CFR CFR 0x84 0x20 0x00000000 0xFFFFFFFF 16 0x1 0-15 CSOF%s Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 0 1 write-only oneToClear CSOF0W Clear Clear synchronization flag 1 8 0x4 0-7 RG%sCR RG%sCR 0x100 0x20 0x00000000 0xFFFFFFFF SIG_ID Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 0 3 read-write SIG_ID dmamux1_evt0 Signal `dmamux1_evt0` selected as trigger input 0 dmamux1_evt1 Signal `dmamux1_evt1` selected as trigger input 1 dmamux1_evt2 Signal `dmamux1_evt2` selected as trigger input 2 lptim1_out Signal `lptim1_out` selected as trigger input 3 lptim2_out Signal `lptim2_out` selected as trigger input 4 lptim3_out Signal `lptim3_out` selected as trigger input 5 extit0 Signal `extit0` selected as trigger input 6 tim12_trgo Signal `tim12_trgo` selected as trigger input 7 OIE Trigger overrun interrupt enable 8 1 read-write OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 GE DMA request generator channel x enable 16 1 read-write GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 GPOL DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 17 2 read-write GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GNBREQ Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled. 19 5 read-write 0 31 RGSR RGSR 0x140 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 OF%s [:0]: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. 0 1 read-only OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR 0x144 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 COF%s Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. 0 1 write-only oneToClear COF0W Clear Clear overrun flag 1 DMAMUX2 DMAMUX DMAMUX 0x58025800 0x0 0x400 registers DMAMUX2_OVR DMAMUX2 overrun interrupt 128 8 0x4 0-7 C%sCR C%sCR DMAMux - DMA request line multiplexer channel x control register 0x0 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 5 DMAREQ_ID none No signal selected as request input 0 dmamux2_req_gen0 Signal `dmamux2_req_gen0` selected as request input 1 dmamux2_req_gen1 Signal `dmamux2_req_gen1` selected as request input 2 dmamux2_req_gen2 Signal `dmamux2_req_gen2` selected as request input 3 dmamux2_req_gen3 Signal `dmamux2_req_gen3` selected as request input 4 dmamux2_req_gen4 Signal `dmamux2_req_gen4` selected as request input 5 dmamux2_req_gen5 Signal `dmamux2_req_gen5` selected as request input 6 dmamux2_req_gen6 Signal `dmamux2_req_gen6` selected as request input 7 dmamux2_req_gen7 Signal `dmamux2_req_gen7` selected as request input 8 lpuart1_rx_dma Signal `lpuart1_rx_dma` selected as request input 9 lpuart1_tx_dma Signal `lpuart1_tx_dma` selected as request input 10 spi6_rx_dma Signal `spi6_rx_dma` selected as request input 11 spi6_tx_dma Signal `spi6_tx_dma` selected as request input 12 i2c4_rx_dma Signal `i2c4_rx_dma` selected as request input 13 i2c4_tx_dma Signal `i2c4_tx_dma` selected as request input 14 sai4_a_dma Signal `sai4_a_dma` selected as request input 15 sai4_b_dma Signal `sai4_b_dma` selected as request input 16 adc3_dma Signal `adc3_dma` selected as request input 17 SOIE Interrupt enable at synchronization event overrun 8 1 SOIE Disabled Synchronization overrun interrupt disabled 0 Enabled Synchronization overrun interrupt enabled 1 EGE Event generation enable/disable 9 1 EGE Disabled Event generation disabled 0 Enabled Event generation enabled 1 SE Synchronous operating mode enable/disable 16 1 SE Disabled Synchronization disabled 0 Enabled Synchronization enabled 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SPOL NoEdge No event, i.e. no synchronization nor detection 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 0 31 SYNC_ID Synchronization input selected 24 5 SYNC_ID dmamux2_evt0 Signal `dmamux2_evt0` selected as synchronization input 0 dmamux2_evt1 Signal `dmamux2_evt1` selected as synchronization input 1 dmamux2_evt2 Signal `dmamux2_evt2` selected as synchronization input 2 dmamux2_evt3 Signal `dmamux2_evt3` selected as synchronization input 3 dmamux2_evt4 Signal `dmamux2_evt4` selected as synchronization input 4 dmamux2_evt5 Signal `dmamux2_evt5` selected as synchronization input 5 lpuart1_rx_wkup Signal `lpuart1_rx_wkup` selected as synchronization input 6 lpuart1_tx_wkup Signal `lpuart1_tx_wkup` selected as synchronization input 7 lptim2_out Signal `lptim2_out` selected as synchronization input 8 lptim3_out Signal `lptim3_out` selected as synchronization input 9 i2c4_wkup Signal `i2c4_wkup` selected as synchronization input 10 spi6_wkup Signal `spi6_wkup` selected as synchronization input 11 comp1_out Signal `comp1_out` selected as synchronization input 12 rtc_wkup Signal `rtc_wkup` selected as synchronization input 13 syscfg_exti0_mux Signal `syscfg_exti0_mux` selected as synchronization input 14 syscfg_exti2_mux Signal `syscfg_exti2_mux` selected as synchronization input 15 8 0x4 0-7 RG%sCR RG%sCR DMAMux - DMA request generator channel x control register 0x100 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 SIG_ID dmamux2_evt0 Signal `dmamux2_evt0` selected as trigger input 0 dmamux2_evt1 Signal `dmamux2_evt1` selected as trigger input 1 dmamux2_evt2 Signal `dmamux2_evt2` selected as trigger input 2 dmamux2_evt3 Signal `dmamux2_evt3` selected as trigger input 3 dmamux2_evt4 Signal `dmamux2_evt4` selected as trigger input 4 dmamux2_evt5 Signal `dmamux2_evt5` selected as trigger input 5 dmamux2_evt6 Signal `dmamux2_evt6` selected as trigger input 6 lpuart_rx_wkup Signal `lpuart_rx_wkup` selected as trigger input 7 lpuart_tx_wkup Signal `lpuart_tx_wkup` selected as trigger input 8 lptim2_wkup Signal `lptim2_wkup` selected as trigger input 9 lptim2_out Signal `lptim2_out` selected as trigger input 10 lptim3_wkup Signal `lptim3_wkup` selected as trigger input 11 lptim3_out Signal `lptim3_out` selected as trigger input 12 lptim4_ait Signal `lptim4_ait` selected as trigger input 13 lptim5_ait Signal `lptim5_ait` selected as trigger input 14 i2c4_wkup Signal `i2c4_wkup` selected as trigger input 15 spi6_wkup Signal `spi6_wkup` selected as trigger input 16 comp1_out Signal `comp1_out` selected as trigger input 17 comp2_out Signal `comp2_out` selected as trigger input 18 rtc_wkup Signal `rtc_wkup` selected as trigger input 19 syscfg_exti0_mux Signal `syscfg_exti0_mux` selected as trigger input 20 syscfg_exti2_mux Signal `syscfg_exti2_mux` selected as trigger input 21 i2c4_event_it Signal `i2c4_event_it` selected as trigger input 22 spi6_it Signal `spi6_it` selected as trigger input 23 lpuart1_it_t Signal `lpuart1_it_t` selected as trigger input 24 lpuart1_it_r Signal `lpuart1_it_r` selected as trigger input 25 adc3_it Signal `adc3_it` selected as trigger input 26 adc3_awd1 Signal `adc3_awd1` selected as trigger input 27 bdma_ch0_it Signal `bdma_ch0_it` selected as trigger input 28 bdma_ch1_it Signal `bdma_ch1_it` selected as trigger input 29 OIE Interrupt enable at trigger event overrun 8 1 OIE Disabled Trigger overrun interrupt disabled 0 Enabled Trigger overrun interrupt enabled 1 GE DMA request generator channel enable/disable 16 1 GE Disabled DMA request generation disabled 0 Enabled DMA request enabled 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GPOL NoEdge No event, i.e. no detection nor generation 0 RisingEdge Rising edge 1 FallingEdge Falling edge 2 BothEdges Rising and falling edges 3 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 0 31 RGSR RGSR 0x140 0x20 read-only 0x00000000 0xFFFFFFFF 8 0x1 0-7 OF%s Trigger overrun event flag 0 1 read-only OF0 NoTrigger No new trigger event occured on DMA request generator channel x, before the request counter underrun 0 Trigger New trigger event occured on DMA request generator channel x, before the request counter underrun 1 RGCFR RGCFR 0x144 0x20 write-only 0x00000000 0xFFFFFFFF 8 0x1 0-7 COF%s Clear trigger overrun event flag 0 1 oneToClear COF0W Clear Clear overrun flag 1 CSR CSR 0x80 0x20 read-only 0x00000000 0xFFFFFFFF 8 0x1 0-7 SOF%s Synchronization overrun event flag 0 1 read-only SOF0 NoSyncEvent No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 0 SyncEvent Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ 1 CFR CFR 0x84 0x20 0x00000000 0xFFFFFFFF 8 0x1 0-7 CSOF%s Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 0 1 write-only oneToClear CSOF0W Clear Clear synchronization flag 1 FMC FMC FMC 0x52004000 0x0 0x400 registers FMC FMC global interrupt 48 BCR1 BCR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 0x0 0x20 read-write 0x000030DB MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MUXEN Disabled Address/Data non-multiplexed 0 Enabled Address/Data multiplexed on databus 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MTYP SRAM SRAM memory type 0 PSRAM PSRAM (CRAM) memory type 1 Flash NOR Flash/OneNAND Flash 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 FACCEN Disabled Corresponding NOR Flash memory access is disabled 0 Enabled Corresponding NOR Flash memory access is enabled 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 BURSTEN Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITPOL ActiveLow NWAIT active low 0 ActiveHigh NWAIT active high 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WAITCFG BeforeWaitState NWAIT signal is active one data cycle before wait state 0 DuringWaitState NWAIT signal is active during wait state 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WREN Disabled Write operations disabled for the bank by the FMC 0 Enabled Write operations enabled for the bank by the FMC 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 WAITEN Disabled Values inside the FMC_BWTR are taken into account 0 Enabled NWAIT signal enabled 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 EXTMOD Disabled Values inside the FMC_BWTR are not taken into account 0 Enabled Values inside the FMC_BWTR are taken into account 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 ASYNCWAIT Disabled Wait signal not used in asynchronous mode 0 Enabled Wait signal used even in asynchronous mode 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CPSIZE NoBurstSplit No burst split when crossing page boundary 0 Bytes128 128 bytes CRAM page size 1 Bytes256 256 bytes CRAM page size 2 Bytes512 512 bytes CRAM page size 3 Bytes1024 1024 bytes CRAM page size 4 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CBURSTRW Disabled Write operations are always performed in asynchronous mode 0 Enabled Write operations are performed in synchronous mode 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 CCLKEN Disabled The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set 0 Enabled The FMC_CLK is only generated during the synchronous memory access (read/write transaction) 1 WFDIS Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 21 1 WFDIS Enabled Write FIFO enabled 0 Disabled Write FIFO disabled 1 BMAP FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register. 24 2 BMAP Default Default mapping 0 Swapped NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped 1 Remapped SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping 2 FMCEN FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 31 1 FMCEN Disabled Disable the FMC controller 0 Enabled Enable the FMC controller 1 4 0x8 1-4 BTR%s BTR%s This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x4 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 0 15 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 1 15 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 1 255 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 0 15 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 1 15 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 0 15 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 3 0x8 2-4 BCR%s BCR%s This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 0x8 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 PCR PCR NAND Flash control registers 0x80 0x20 read-write 0x00000018 PWAITEN Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank: 1 1 PWAITEN Disabled Wait feature disabled 0 Enabled Wait feature enabled 1 PBKEN NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 2 1 PBKEN Disabled Corresponding memory bank is disabled 0 Enabled Corresponding memory bank is enabled 1 PWID Data bus width. These bits define the external memory device width. 4 2 PWID Bits8 External memory device width 8 bits 0 Bits16 External memory device width 16 bits 1 ECCEN ECC computation logic enable bit 6 1 ECCEN Disabled ECC logic is disabled and reset 0 Enabled ECC logic is enabled 1 TCLR CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 9 4 0 15 TAR ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 13 4 0 15 ECCPS ECC page size. These bits define the page size for the extended ECC: 17 3 ECCPS Bytes256 ECC page size 256 bytes 0 Bytes512 ECC page size 512 bytes 1 Bytes1024 ECC page size 1024 bytes 2 Bytes2048 ECC page size 2048 bytes 3 Bytes4096 ECC page size 4096 bytes 4 Bytes8192 ECC page size 8192 bytes 5 SR SR This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty. 0x84 0x20 0x00000040 IRS Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 0 1 read-write IRS DidNotOccur Interrupt rising edge did not occur 0 Occurred Interrupt rising edge occurred 1 ILS Interrupt high-level status The flag is set by hardware and reset by software. 1 1 read-write ILS DidNotOccur Interrupt high-level did not occur 0 Occurred Interrupt high-level occurred 1 IFS Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 2 1 read-write IFS DidNotOccur Interrupt falling edge did not occur 0 Occurred Interrupt falling edge occurred 1 IREN Interrupt rising edge detection enable bit 3 1 read-write IREN Disabled Interrupt rising edge detection request disabled 0 Enabled Interrupt rising edge detection request enabled 1 ILEN Interrupt high-level detection enable bit 4 1 read-write ILEN Disabled Interrupt high-level detection request disabled 0 Enabled Interrupt high-level detection request enabled 1 IFEN Interrupt falling edge detection enable bit 5 1 read-write IFEN Disabled Interrupt falling edge detection request disabled 0 Enabled Interrupt falling edge detection request enabled 1 FEMPT FIFO empty. Read-only bit that provides the status of the FIFO 6 1 read-only FEMPT NotEmpty FIFO not empty 0 Empty FIFO empty 1 PMEM PMEM The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access. 0x88 0x20 read-write 0xFCFCFCFC MEMSET Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0 8 0 254 MEMWAIT Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 1 254 MEMHOLD Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 16 8 1 254 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 24 8 0 254 PATT PATT The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature). 0x8C 0x20 read-write 0xFCFCFCFC ATTSET Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0 8 0 254 ATTWAIT Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 1 254 ATTHOLD Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 16 8 1 254 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 0 254 ECCR ECCR This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 0x20 read-only 0x00000000 ECC ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. 0 32 0 4294967295 4 0x8 1-4 BWTR%s BWTR%s This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x104 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 0 15 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 1 15 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 1 255 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 0 15 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ACCMOD A Access mode A 0 B Access mode B 1 C Access mode C 2 D Access mode D 3 SDCR1 SDCR1 This register contains the control parameters for each SDRAM memory bank 0x140 0x20 read-write 0x000002D0 NC Number of column address bits These bits define the number of bits of a column address. 0 2 NC Bits8 8 bits 0 Bits9 9 bits 1 Bits10 10 bits 2 Bits11 11 bits 3 NR Number of row address bits These bits define the number of bits of a row address. 2 2 NR Bits11 11 bits 0 Bits12 12 bits 1 Bits13 13 bits 2 MWID Memory data bus width. These bits define the memory device width. 4 2 MWID Bits8 Memory data bus width 8 bits 0 Bits16 Memory data bus width 16 bits 1 Bits32 Memory data bus width 32 bits 2 NB Number of internal banks This bit sets the number of internal banks. 6 1 NB NB2 Two internal Banks 0 NB4 Four internal Banks 1 CAS CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles 7 2 CAS Clocks1 1 cycle 1 Clocks2 2 cycles 2 Clocks3 3 cycles 3 WP Write protection This bit enables write mode access to the SDRAM bank. 9 1 WP Disabled Write accesses allowed 0 Enabled Write accesses ignored 1 SDCLK SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only. 10 2 SDCLK Disabled SDCLK clock disabled 0 Div2 SDCLK period = 2 x HCLK period 2 Div3 SDCLK period = 3 x HCLK period 3 RBURST Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only. 12 1 RBURST Disabled Single read requests are not managed as bursts 0 Enabled Single read requests are always managed as bursts 1 RPIPE Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. 13 2 RPIPE NoDelay No clock cycle delay 0 Clocks1 One clock cycle delay 1 Clocks2 Two clock cycles delay 2 SDCR2 SDCR2 This register contains the control parameters for each SDRAM memory bank 0x144 0x20 read-write 0x000002D0 NC Number of column address bits These bits define the number of bits of a column address. 0 2 NR Number of row address bits These bits define the number of bits of a row address. 2 2 MWID Memory data bus width. These bits define the memory device width. 4 2 NB Number of internal banks This bit sets the number of internal banks. 6 1 CAS CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles 7 2 WP Write protection This bit enables write mode access to the SDRAM bank. 9 1 SDCLK SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only. 10 2 RBURST Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only. 12 1 RBURST Disabled Single read requests are not managed as bursts 0 Enabled Single read requests are always managed as bursts 1 RPIPE Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. 13 2 RPIPE NoDelay No clock cycle delay 0 Clocks1 One clock cycle delay 1 Clocks2 Two clock cycles delay 2 2 0x4 1-2 SDTR%s SDTR%s This register contains the timing parameters of each SDRAM bank 0x148 0x20 read-write 0x0FFFFFFF TMRD Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .... 0 4 0 15 TXSR Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device. 4 4 0 15 TRAS Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .... 8 4 0 15 TRC Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care. 12 4 0 15 TWR Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR &#8805; TRAS - TRCD and TWR &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. 16 4 0 15 TRP Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care. 20 4 0 15 TRCD Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .... 24 4 0 15 SDCMR SDCMR This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks. 0x150 0x20 read-write 0x00000000 MODE Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0. 0 3 MODE Normal Normal Mode 0 ClockConfigurationEnable Clock Configuration Enable 1 PALL PALL (All Bank Precharge) command 2 AutoRefreshCommand Auto-refresh command 3 LoadModeRegister Load Mode Resgier 4 SelfRefreshCommand Self-refresh command 5 PowerDownCommand Power-down command 6 CTB2 Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. 3 1 CTB2 NotIssued Command not issued to SDRAM Bank 1 0 Issued Command issued to SDRAM Bank 1 1 CTB1 Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. 4 1 NRFS Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. .... 5 4 0 15 MRD Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM. 9 14 0 8191 SDRTR SDRTR This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2. 0x154 0x20 0x00000000 CRE Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. 0 1 write-only CRE Clear Refresh Error Flag is cleared 1 COUNT Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 1 13 read-write 0 8191 REIE RES Interrupt Enable 14 1 read-write REIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated if RE = 1 1 SDSR SDSR SDRAM Status register 0x158 0x20 read-only 0x00000000 RE Refresh error flag An interrupt is generated if REIE = 1 and RE = 1 0 1 RE NoError No refresh error has been detected 0 Error A refresh error has been detected 1 MODES1 Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1. 1 2 MODES1 Normal Normal Mode 0 SelfRefresh Self-refresh mode 1 PowerDown Power-down mode 2 MODES2 Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2. 3 2 CEC CEC CEC 0x40006C00 0x0 0x400 registers CEC HDMI-CEC global interrupt 94 CR CR CEC control register 0x0 0x20 read-write 0x00000000 CECEN CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. 0 1 TXSOM Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception 1 1 TXEOM Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message) 2 1 CFGR CFGR This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. 0x4 0x20 read-write 0x00000000 SFT Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods 0 3 0 7 RXTOL Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall 3 1 BRESTP Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software. 4 1 BREGEN Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0 5 1 LBPEGEN Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0 6 1 BRDNOGEN Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software. 7 1 SFTOPT SFT Option Bit The SFTOPT bit is set and cleared by software. 8 1 OAR Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. 16 15 0 32767 LSTN Listen mode LSTN bit is set and cleared by software. 31 1 TXDR TXDR CEC Tx data register 0x8 0x20 write-only 0x00000000 TXD Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1 0 8 0 255 RXDR RXDR CEC Rx Data Register 0xC 0x20 read-only 0x00000000 RXD Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line. 0 8 ISR ISR CEC Interrupt and Status Register 0x10 0x20 read-write 0x00000000 RXBR Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. 0 1 RXEND End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. 1 1 RXOVR Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. 2 1 BRE Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1. 3 1 SBPE Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1. 4 1 LBPE Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1. 5 1 RXACKE Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. 6 1 ARBLST Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. 7 1 TXBR Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. 8 1 TXEND End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. 9 1 TXUDR Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1 10 1 TXERR Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. 11 1 TXACKE Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. 12 1 IER IER CEC interrupt enable register 0x14 0x20 read-write 0x00000000 RXBRIE Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software. 0 1 RXENDIE End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software. 1 1 RXOVRIE Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software. 2 1 BREIE Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software. 3 1 SBPEIE Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software. 4 1 LBPEIE Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software. 5 1 RXACKIE Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software. 6 1 ARBLSTIE Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software. 7 1 TXBRIE Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. 8 1 TXENDIE Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. 9 1 TXUDRIE Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software. 10 1 TXERRIE Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software. 11 1 TXACKIE Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software. 12 1 HSEM HSEM HSEM 0x58026400 0x0 0x400 registers HSEM0 HSEM global interrupt 1 125 32 0x4 0-31 R%s R%s HSEM register HSEM_R%s 0x0 0x20 read-write 0x00000000 PROCID Semaphore ProcessID 0 8 0 255 MASTERID Semaphore MasterID 8 8 0 15 LOCK Lock indication 31 1 LOCKR read Free Semaphore is free 0 Locked Semaphore is locked 1 LOCKW write Free Free semaphore 0 TryLock Try to lock semaphore 1 32 0x4 0-31 RLR%s RLR%s Semaphore %s read lock register 0x80 0x20 read-only 0x00000000 PROCID Semaphore ProcessID 0 8 0 255 MASTERID Semaphore MasterID 8 8 0 15 LOCK Lock indication 31 1 LOCKR Free Semaphore is free 0 Locked Semaphore is locked 1 IER IER HSEM Interrupt enable register 0x100 0x20 read-write 0x00000000 32 0x1 0-31 ISE%s Interrupt semaphore %s enable bit 0 1 ISE0 Disabled Interrupt generation disabled 0 Enabled Interrupt generation enabled 1 ICR ICR HSEM Interrupt clear register 0x104 0x20 read-write 0x00000000 32 0x1 0-31 ISC%s Interrupt semaphore %s clear bit 0 1 ISC0R read NoEffect Always reads 0 0 ISC0W write NoEffect Interrupt semaphore x status ISFx and masked status MISFx not affected 0 Clear Interrupt semaphore x status ISFx and masked status MISFx cleared 1 ISR ISR HSEM Interrupt status register 0x108 0x20 read-only 0x00000000 32 0x1 0-31 ISF%s Interrupt semaphore %s status bit before enable (mask) 0 1 ISF0 NotPending No interrupt pending 0 Pending Interrupt pending 1 MISR MISR HSEM Masked interrupt status register 0x10C 0x20 read-only 0x00000000 32 0x1 0-31 MISF%s Masked interrupt semaphore %s status bit after enable (mask) 0 1 MISF0 NotPending No interrupt pending after masking 0 Pending Interrupt pending after masking 1 CR CR HSEM Clear register 0x140 0x20 read-write 0x00000000 MASTERID MasterID of semaphores to be cleared 8 4 0 15 KEY Semaphore clear Key 16 16 0 65535 KEYR KEYR HSEM Interrupt clear register 0x144 0x20 read-write 0x00000000 KEY Semaphore Clear Key 16 16 0 65535 I2C1 I2C I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK. 0x0 0x20 read-write 0x00000000 PE Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match Interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received Interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR) 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0). 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control This bit is used to enable hardware byte control in slave mode. 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK. 0x4 0x20 read-write 0x00000000 SADD Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed. 0 10 0 1023 RD_WRN Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 ADD10 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 HEAD10R 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 START Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set. 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 STOP Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect. 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 NACK NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 NBYTES Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. 16 8 0 255 RELOAD NBYTES reload mode This bit is set and cleared by software. 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 AUTOEND Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 PECBYTE Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 OAR1 OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK. 0x8 0x20 read-write 0x00000000 OA1 Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0. 0 10 0 1023 OA1MODE Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0. 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK. 0xC 0x20 read-write 0x00000000 OA2 Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0. 1 7 0 127 OA2MSK Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Access: No wait states 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings. 0 8 0 255 SCLH SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing. 8 8 0 255 SDADEL Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing. 16 4 0 15 SCLDEL Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing. 20 4 0 15 PRESC Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK 28 4 0 15 TIMEOUTR TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK. 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0. 0 12 0 4095 TIDLE Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0. 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0. 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Access: No wait states 0x18 0x20 0x00000001 TXE Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0. 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 TXIS Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0. 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 RXNE Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0. 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 ADDR Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0. 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 NACKF Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0. 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 STOPF Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0. 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 TC Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0. 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TCR Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set. 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 BERR Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0. 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 ARLO Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0. 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 OVR Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0. 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 PECERR PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 TIMEOUT Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 ALERT SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 BUSY Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 DIR Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1). 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 ADDCODE Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. 17 7 read-only 0 127 ICR ICR Access: No wait states 0x1C 0x20 write-only 0x00000000 ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register. 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 STOPCF Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 BERRCF Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 ARLOCF Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 OVRCF Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 PECCF PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 TIMOUTCF Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 ALERTCF Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 PECR PECR Access: No wait states 0x20 0x20 read-only 0x00000000 PEC Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0. 0 8 0 255 RXDR RXDR Access: No wait states 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data Data byte received from the I2C bus. 0 8 0 255 TXDR TXDR Access: No wait states 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1. 0 8 0 255 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 I2C4 0x58001C00 I2C4_EV I2C4 event interrupt 95 I2C4_ER I2C4 error interrupt 96 GPIOA GPIO GPIO 0x58020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 Mode Input Input mode (reset state) 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 IDR%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 ODR%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODRx bit 1 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODRx bit 1 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 0x20 read-write 0x00000000 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset. 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 0-7 AFR%s [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AF8 AF8 8 AF9 AF9 9 AF10 AF10 10 AF11 AF11 11 AF12 AF12 12 AF13 AF13 13 AF14 AF14 14 AF15 AF15 15 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 8-15 AFR%s [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os 0 4 GPIOC GPIO GPIO 0x58020800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 GPIOD 0x58020C00 GPIOE 0x58021000 GPIOF 0x58021400 GPIOG 0x58021800 GPIOH 0x58021C00 GPIOI 0x58022000 GPIOJ 0x58022400 GPIOK 0x58022800 JPEG JPEG JPEG 0x52003000 0x0 0x400 registers JPEG JPEG global interrupt 121 CONFR0 CONFR0 JPEG codec control register 0x0 0x20 write-only 0x00000000 START Start This bit start or stop the encoding or decoding process. Read this register always return 0. 0 1 CONFR1 CONFR1 JPEG codec configuration register 1 0x4 0x20 read-write 0x00000000 NF Number of color components This field defines the number of color components minus 1. 0 2 DE Decoding Enable This bit selects the coding or decoding process 3 1 COLORSPACE Color Space This filed defines the number of quantization tables minus 1 to insert in the output stream. 4 2 NS Number of components for Scan This field defines the number of components minus 1 for scan header marker segment. 6 2 HDR Header Processing This bit enable the header processing (generation/parsing). 8 1 YSIZE Y Size This field defines the number of lines in source image. 16 16 CONFR2 CONFR2 JPEG codec configuration register 2 0x8 0x20 read-write 0x00000000 NMCU Number of MCU For encoding: this field defines the number of MCU units minus 1 to encode. For decoding: this field indicates the number of complete MCU units minus 1 to be decoded (this field is updated after the JPEG header parsing). If the decoded image size has not a X or Y size multiple of 8 or 16 (depending on the sub-sampling process), the resulting incomplete or empty MCU must be added to this value to get the total number of MCU generated. 0 26 CONFR3 CONFR3 JPEG codec configuration register 3 0xC 0x20 read-write 0x00000000 XSIZE X size This field defines the number of pixels per line. 16 16 CONFRN1 CONFRN1 JPEG codec configuration register 4-7 0x10 0x20 read-write 0x00000000 HD Huffman DC Selects the Huffman table for encoding the DC coefficients. 0 1 HA Huffman AC Selects the Huffman table for encoding the AC coefficients. 1 1 QT Quantization Table Selects quantization table associated with a color component. 2 2 NB Number of Block Number of data units minus 1 that belong to a particular color in the MCU. 4 4 VSF Vertical Sampling Factor Vertical sampling factor for component i. 8 4 HSF Horizontal Sampling Factor Horizontal sampling factor for component i. 12 4 CONFRN2 CONFRN2 JPEG codec configuration register 4-7 0x14 0x20 read-write 0x00000000 HD Huffman DC Selects the Huffman table for encoding the DC coefficients. 0 1 HA Huffman AC Selects the Huffman table for encoding the AC coefficients. 1 1 QT Quantization Table Selects quantization table associated with a color component. 2 2 NB Number of Block Number of data units minus 1 that belong to a particular color in the MCU. 4 4 VSF Vertical Sampling Factor Vertical sampling factor for component i. 8 4 HSF Horizontal Sampling Factor Horizontal sampling factor for component i. 12 4 CONFRN3 CONFRN3 JPEG codec configuration register 4-7 0x18 0x20 read-write 0x00000000 HD Huffman DC Selects the Huffman table for encoding the DC coefficients. 0 1 HA Huffman AC Selects the Huffman table for encoding the AC coefficients. 1 1 QT Quantization Table Selects quantization table associated with a color component. 2 2 NB Number of Block Number of data units minus 1 that belong to a particular color in the MCU. 4 4 VSF Vertical Sampling Factor Vertical sampling factor for component i. 8 4 HSF Horizontal Sampling Factor Horizontal sampling factor for component i. 12 4 CONFRN4 CONFRN4 JPEG codec configuration register 4-7 0x1C 0x20 read-write 0x00000000 HD Huffman DC Selects the Huffman table for encoding the DC coefficients. 0 1 HA Huffman AC Selects the Huffman table for encoding the AC coefficients. 1 1 QT Quantization Table Selects quantization table associated with a color component. 2 2 NB Number of Block Number of data units minus 1 that belong to a particular color in the MCU. 4 4 VSF Vertical Sampling Factor Vertical sampling factor for component i. 8 4 HSF Horizontal Sampling Factor Horizontal sampling factor for component i. 12 4 CR CR JPEG control register 0x30 0x20 read-write 0x00000000 JCEN JPEG Core Enable Enable the JPEG codec Core. 0 1 IFTIE Input FIFO Threshold Interrupt Enable This bit enables the interrupt generation when input FIFO reach the threshold. 1 1 IFNFIE Input FIFO Not Full Interrupt Enable This bit enables the interrupt generation when input FIFO is not empty. 2 1 OFTIE Output FIFO Threshold Interrupt Enable This bit enables the interrupt generation when output FIFO reach the threshold. 3 1 OFNEIE Output FIFO Not Empty Interrupt Enable This bit enables the interrupt generation when output FIFO is not empty. 4 1 EOCIE End of Conversion Interrupt Enable This bit enables the interrupt generation on the end of conversion. 5 1 HPDIE Header Parsing Done Interrupt Enable This bit enables the interrupt generation on the Header Parsing Operation. 6 1 IDMAEN Input DMA Enable Enable the DMA request generation for the input FIFO. 11 1 ODMAEN Output DMA Enable Enable the DMA request generation for the output FIFO. 12 1 IFF Input FIFO Flush This bit flush the input FIFO. This bit is always read as 0. 13 1 OFF Output FIFO Flush This bit flush the output FIFO. This bit is always read as 0. 14 1 SR SR JPEG status register 0x34 0x20 read-only 0x00000006 IFTF Input FIFO Threshold Flag This bit is set when the input FIFO is not full and is bellow its threshold. 1 1 IFNFF Input FIFO Not Full Flag This bit is set when the input FIFO is not full (a data can be written). 2 1 OFTF Output FIFO Threshold Flag This bit is set when the output FIFO is not empty and has reach its threshold. 3 1 OFNEF Output FIFO Not Empty Flag This bit is set when the output FIFO is not empty (a data is available). 4 1 EOCF End of Conversion Flag This bit is set when the JPEG codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO. 5 1 HPDF Header Parsing Done Flag This bit is set in decode mode when the JPEG codec has finished the parsing of the headers and the internal registers have been updated. 6 1 COF Codec Operation Flag This bit is set when when a JPEG codec operation is on going (encoding or decoding). 7 1 CFR CFR JPEG clear flag register 0x38 0x20 read-write 0x00000000 CEOCF Clear End of Conversion Flag Writing 1 clears the End of Conversion Flag of the JPEG Status Register. 5 1 CHPDF Clear Header Parsing Done Flag Writing 1 clears the Header Parsing Done Flag of the JPEG Status Register. 6 1 DIR DIR JPEG data input register 0x40 0x20 write-only 0x00000000 DATAIN Data Input FIFO Input FIFO data register. 0 32 DOR DOR JPEG data output register 0x44 0x20 read-only 0x00000000 DATAOUT Data Output FIFO Output FIFO data register. 0 32 MDMA MDMA MDMA 0x52000000 0x0 0x1000 registers MDMA MDMA 122 GISR0 GISR0 MDMA Global Interrupt/Status Register 0x0 0x20 read-only 0x00000000 16 0x1 0-15 GIF%s Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx) 0 1 16 0x40 0-15 CH%s Channel cluster: C?ISR, C?IFCR, C?ESR, C?CR, C?TCR, C?BNDTR, C?SAR, C?DAR, C?BRUR, C?LAR, C?TBR, C?MAR and C?MDR registers 0x40 ISR C0ISR MDMA channel x interrupt/status register 0x0 0x20 read-only 0x00000000 TEIF Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. 0 1 CTCIF Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0. 1 1 BRTIF Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. 2 1 BTIF Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. 3 1 TCIF channel x buffer transfer complete 4 1 CRQA channel x request active flag 16 1 IFCR C0IFCR MDMA channel x interrupt flag clear register 0x4 0x20 write-only 0x00000000 CTEIF Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register 0 1 CCTCIF Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register 1 1 CBRTIF Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register 2 1 CBTIF Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register 3 1 CLTCIF CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register 4 1 ESR C0ESR MDMA Channel x error status register 0x8 0x20 read-only 0x00000000 TEA Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error. 0 7 TED Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error. 7 1 TELD Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register. 8 1 TEMD Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register. 9 1 ASE Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register. 10 1 BSE Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register. 11 1 CR C0CR This register is used to control the concerned channel. 0xC 0x20 0x00000000 EN channel enable 0 1 read-write TEIE Transfer error interrupt enable This bit is set and cleared by software. 1 1 read-write CTCIE Channel Transfer Complete interrupt enable This bit is set and cleared by software. 2 1 read-write BRTIE Block Repeat transfer interrupt enable This bit is set and cleared by software. 3 1 read-write BTIE Block Transfer interrupt enable This bit is set and cleared by software. 4 1 read-write TCIE buffer Transfer Complete interrupt enable This bit is set and cleared by software. 5 1 read-write PL Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. 6 2 read-write BEX byte Endianness exchange 12 1 read-write HEX Half word Endianes exchange 13 1 read-write WEX Word Endianness exchange 14 1 read-write SWRQ SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access). 16 1 write-only TCR C0TCR This register is used to configure the concerned channel. 0x10 0x20 read-write 0x00000000 SINC Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0 2 DINC Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden. 2 2 SSIZE Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1). 4 2 DSIZE Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1). 6 2 SINCOS source increment offset size 8 2 DINCOS Destination increment offset 10 2 SBURST source burst transfer configuration 12 3 DBURST Destination burst transfer configuration 15 3 TLEN buffer transfer lengh 18 7 PKE PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0 25 1 PAM Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0 26 2 TRGM Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0. 28 2 SWRM SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0. 30 1 BWM Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable. 31 1 BNDTR C0BNDTR MDMA Channel x block number of data register 0x14 0x20 read-write 0x00000000 BNDT block number of data to transfer 0 17 BRSUM Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0. 18 1 BRDUM Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0. 19 1 BRC Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0. 20 12 SAR C0SAR MDMA channel x source address register 0x18 0x20 read-write 0x00000000 SAR source adr base 0 32 DAR C0DAR MDMA channel x destination address register 0x1C 0x20 read-write 0x00000000 DAR Destination adr base 0 32 BRUR C0BRUR MDMA channel x Block Repeat address Update register 0x20 0x20 read-write 0x00000000 SUV source adresse update value 0 16 DUV destination address update 16 16 LAR C0LAR MDMA channel x Link Address register 0x24 0x20 read-write 0x00000000 LAR Link address register 0 32 TBR C0TBR MDMA channel x Trigger and Bus selection Register 0x28 0x20 read-write 0x00000000 TSEL Trigger selection 0 6 SBUS Source BUS select This bit is protected and can be written only if EN is 0. 16 1 DBUS Destination BUS slect This bit is protected and can be written only if EN is 0. 17 1 MAR C0MAR MDMA channel x Mask address register 0x30 0x20 read-write 0x00000000 MAR Mask address 0 32 MDR C0MDR MDMA channel x Mask Data register 0x34 0x20 read-write 0x00000000 MDR Mask data 0 32 QUADSPI QUADSPI QUADSPI 0x52005000 0x0 0x400 registers QUADSPI QuadSPI global interrupt 92 CR CR QUADSPI control register 0x0 0x20 read-write 0x00000000 EN Enable Enable the QUADSPI. 0 1 EN Disabled QUADSPI is disabled 0 Enabled QUADSPI is enabled 1 ABORT Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit. 1 1 ABORT NoAbortRequested No abort requested 0 AbortRequested Abort requested 1 DMAEN DMA enable In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set. 2 1 DMAEN Disabled DMA is disabled for indirect mode 0 Enabled DMA is enabled for indirect mode 1 TCEN Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. This bit can be modified only when BUSY = 0. 3 1 TCEN Disabled Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode. 0 Enabled Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity. 1 SSHIFT Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0. 4 1 SSHIFT NoShift No shift 0 OneHalfCycleShift 1/2 cycle shift 1 DFM Dual-flash mode This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. This bit can be modified only when BUSY = 0. 6 1 DFM Disabled Dual-flash mode disabled 0 Enabled Dual-flash mode enabled 1 FSEL Flash memory selection This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1. 7 1 FSEL SelectFlash1 FLASH 1 selected 0 SelectFlash2 FLASH 2 selected 1 FTHRES FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): ... In indirect read mode (FMODE = 01): ... If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value. 8 5 TEIE Transfer error interrupt enable This bit enables the transfer error interrupt. 16 1 TEIE Disabled Interrupt disable 0 Enabled Interrupt enabled 1 TCIE Transfer complete interrupt enable This bit enables the transfer complete interrupt. 17 1 FTIE FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 18 1 SMIE Status match interrupt enable This bit enables the status match interrupt. 19 1 TOIE TimeOut interrupt enable This bit enables the TimeOut interrupt. 20 1 APMS Automatic poll mode stop This bit determines if automatic polling is stopped after a match. This bit can be modified only when BUSY = 0. 22 1 APMS NotStopOnMatch Automatic polling mode is stopped only by abort or by disabling the QUADSPI. 0 StopOnMatch Automatic polling mode stops as soon as there is a match. 1 PMM Polling match mode This bit indicates which method should be used for determining a match during automatic polling mode. This bit can be modified only when BUSY = 0. 23 1 PMM AndMatch AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register. 0 OrMatch OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register. 1 PRESCALER clock prescaler 24 8 0 255 DCR DCR QUADSPI device configuration register 0x4 0x20 read-write 0x00000000 CKMODE indicates the level that clk takes between command 0 1 CKMODE Mode0 CLK must stay low while nCS is high (chip select released). This is referred to as mode 0. 0 Mode3 CLK must stay high while nCS is high (chip select released). This is referred to as mode 3. 1 CSHT Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. ... This field can be modified only when BUSY = 0. 8 3 0 7 FSIZE Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. This field can be modified only when BUSY = 0. 16 5 0 31 SR SR QUADSPI status register 0x8 0x20 read-only 0x00000000 TEF Transfer error flag This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF. 0 1 TEF NoError 0 Error 1 TCF Transfer complete flag This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. 1 1 TCF NotComplete 0 Complete 1 FTF FIFO threshold flag In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true. In automatic polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read. 2 1 FTF NotReached 0 Reached 1 SMF Status match flag This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF. 3 1 SMF NotMatched 0 Matched 1 TOF Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. 4 1 TOF NotTimeout 0 Timeout 1 BUSY Busy This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty. 5 1 BUSY NotBusy 0 Busy 1 FLEVEL FIFO level This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 16 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero. 8 6 0 31 FCR FCR QUADSPI flag clear register 0xC 0x20 read-write 0x00000000 CTEF Clear transfer error flag Writing 1 clears the TEF flag in the QUADSPI_SR register 0 1 CTEF Clear clears the TEF flag in the QUADSPI_SR register 1 CTCF Clear transfer complete flag Writing 1 clears the TCF flag in the QUADSPI_SR register 1 1 CTCF Clear clears the TCF flag in the QUADSPI_SR register 1 CSMF Clear status match flag Writing 1 clears the SMF flag in the QUADSPI_SR register 3 1 CSMF Clear clears the SMF flag in the QUADSPI_SR register 1 CTOF Clear timeout flag Writing 1 clears the TOF flag in the QUADSPI_SR register 4 1 CTOF Clear clears the TOF flag in the QUADSPI_SR register 1 DLR DLR QUADSPI data length register 0x10 0x20 read-write 0x00000000 DL Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE. 0x0000_0000: 1 byte is to be transferred 0x0000_0001: 2 bytes are to be transferred 0x0000_0002: 3 bytes are to be transferred 0x0000_0003: 4 bytes are to be transferred ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred 0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F. DL[0] is stuck at 1 in dual-flash mode (DFM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in memory-mapped mode (FMODE = 10). This field can be written only when BUSY = 0. 0 32 0 4294967295 CCR CCR QUADSPI communication configuration register 0x14 0x20 read-write 0x00000000 INSTRUCTION Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0. 0 8 0 255 IMODE Instruction mode This field defines the instruction phase mode of operation: This field can be written only when BUSY = 0. 8 2 IMODE NoInstruction No instruction 0 SingleLine Instruction on a single line 1 TwoLines Instruction on two lines 2 FourLines Instruction on four lines 3 ADMODE Address mode This field defines the address phase mode of operation: This field can be written only when BUSY = 0. 10 2 ADMODE NoAddress No address 0 SingleLine Address on a single line 1 TwoLines Address on two lines 2 FourLines Address on four lines 3 ADSIZE Address size This bit defines address size: This field can be written only when BUSY = 0. 12 2 ADSIZE Bit8 8-bit address 0 Bit16 16-bit address 1 Bit24 24-bit address 2 Bit32 32-bit address 3 ABMODE Alternate bytes mode This field defines the alternate-bytes phase mode of operation: This field can be written only when BUSY = 0. 14 2 ABMODE NoAlternateBytes No alternate bytes 0 SingleLine Alternate bytes on a single line 1 TwoLines Alternate bytes on two lines 2 FourLines Alternate bytes on four lines 3 ABSIZE Alternate bytes size This bit defines alternate bytes size: This field can be written only when BUSY = 0. 16 2 ABSIZE Bit8 8-bit alternate byte 0 Bit16 16-bit alternate bytes 1 Bit24 24-bit alternate bytes 2 Bit32 32-bit alternate bytes 3 DCYC Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0. 18 5 0 31 DMODE Data mode This field defines the data phases mode of operation: This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0. 24 2 DMODE NoData No data 0 SingleLine Data on a single line 1 TwoLines Data on two lines 2 FourLines Data on four lines 3 FMODE Functional mode This field defines the QUADSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0. 26 2 FMODE IndirectWrite Indirect write mode 0 IndirectRead Indirect read mode 1 AutomaticPolling Automatic polling mode 2 MemoryMapped Memory-mapped mode 3 SIOO Send instruction only once mode See Section15.3.11: Sending the instruction only once on page13. This bit has no effect when IMODE = 00. This field can be written only when BUSY = 0. 28 1 SIOO SendEveryTransaction Send instruction on every transaction 0 SendFirstCommand Send instruction only for the first command 1 DHHC DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: This feature is only active in DDR mode. This field can be written only when BUSY = 0. 30 1 DHHC NoDelay Delay the data output using analog delay 0 Delayed Delay the data output by 1/4 of a QUADSPI output clock cycle. 1 DDRM Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: This field can be written only when BUSY = 0. 31 1 DDRM Disabled DDR Mode disabled 0 Enabled DDR Mode enabled 1 AR AR QUADSPI address register 0x18 0x20 read-write 0x00000000 ADDRESS [31 0]: Address Address to be send to the external Flash memory Writes to this field are ignored when BUSY = 0 or when FMODE = 11 (memory-mapped mode). In dual flash mode, ADDRESS[0] is automatically stuck to 0 as the address should always be even 0 32 0 4294967295 ABR ABR QUADSPI alternate bytes registers 0x1C 0x20 read-write 0x00000000 ALTERNATE Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 0 32 0 4294967295 DR DR Data register: full word (32 bit) access 0x20 0x20 read-write 0x00000000 DATA Data Data to be sent/received to/from the external SPI device. In indirect write mode, data written to this register is stored on the FIFO before it is sent to the Flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In indirect read mode, reading this register gives (via the FIFO) the data which was received from the Flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In automatic polling mode, this register contains the last data read from the Flash memory (without masking). Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0]. 0 32 0 4294967295 DR16 Data register: half word (16 bit) access DR 0x20 0x10 DATA Data 0 16 0 65535 DR8 Data register: one byte (8 bit) access DR 0x20 0x8 DATA Data 0 8 0 255 PSMKR PSMKR QUADSPI polling status mask register 0x24 0x20 read-write 0x00000000 MASK Status mask Mask to be applied to the status bytes received in polling mode. For bit n: This field can be written only when BUSY = 0. 0 32 0 4294967295 PSMAR PSMAR QUADSPI polling status match register 0x28 0x20 read-write 0x00000000 MATCH Status match Value to be compared with the masked status register to get a match. This field can be written only when BUSY = 0. 0 32 0 4294967295 PIR PIR QUADSPI polling interval register 0x2C 0x20 read-write 0x00000000 INTERVAL Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0. 0 16 0 65535 LPTR LPTR QUADSPI low-power timeout register 0x30 0x20 read-write 0x00000000 TIMEOUT Timeout period After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state. This field can be written only when BUSY = 0. 0 16 0 65535 RNG RNG RNG 0x48021800 0x0 0x400 registers CR CR RNG control register 0x0 0x20 read-write 0x00000000 RNGEN Random number generator enable 2 1 RNGEN Disabled Random number generator is disabled 0 Enabled Random number generator is enabled 1 IE Interrupt enable 3 1 IE Disabled RNG interrupt is disabled 0 Enabled RNG interrupt is enabled 1 CED Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled. 5 1 CED Enabled Clock error detection is enabled 0 Disabled Clock error detection is disabled 1 SR SR RNG status register 0x4 0x20 0x00000000 DRDY Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated. 0 1 read-only DRDY Invalid The RNG_DR register is not yet valid, no random data is available 0 Valid The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated. 1 CECS Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1. 1 1 read-only CECS Correct The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 0 Slow The RNG clock is too slow 1 SECS Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) 2 1 read-only SECS NoFault No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 0 Fault At least one faulty sequence has been detected - see ref manual for details 1 CEIS Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1. 5 1 read-write zeroToClear CEISW write Clear Clear flag 0 CEISR read Correct The RNG clock is correct 0 Slow The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register 1 SEIS Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register. 6 1 read-write zeroToClear write SEISR read NoFault No faulty sequence detected 0 Fault At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register. 1 DR DR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0. 0x8 0x20 read-only 0x00000000 RNDATA Random data 32-bit random data which are valid when DRDY=1. 0 32 0 4294967295 RTC RTC RTC 0x58004000 0x0 0x400 registers RTC_TAMP_STAMP_CSS_LSE RTC tamper, timestamp 2 RTC_WKUP RTC Wakeup interrupt 3 RTC_ALARM RTC alarms (A and B) 41 TR TR The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9. 0x0 0x20 read-write 0x00000000 SU Second units in BCD format 0 4 0 15 ST Second tens in BCD format 4 3 0 7 MNU Minute units in BCD format 8 4 0 15 MNT Minute tens in BCD format 12 3 0 7 HU Hour units in BCD format 16 4 0 15 HT Hour tens in BCD format 20 2 0 3 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 DR DR The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9. 0x4 0x20 read-write 0x00002101 DU Date units in BCD format 0 4 0 15 DT Date tens in BCD format 4 2 0 3 MU Month units in BCD format 8 4 0 15 MT Month tens in BCD format 12 1 MT Zero Month tens is 0 0 One Month tens is 1 1 WDU Week day units 13 3 1 7 YU Year units in BCD format 16 4 0 15 YT Year tens in BCD format 20 4 0 15 CR CR RTC control register 0x8 0x20 0x00000000 WUCKSEL Wakeup clock selection 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 TSEDGE Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF. 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 BYPSHAD Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 FMT Hour format 6 1 read-write FMT Twenty_Four_Hour 24 hour/day format 0 AM_PM AM/PM hour format 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 WUTE Wakeup timer enable 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 TSIE Time-stamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 ADD1H Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 SUB1H Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 BKP Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. 18 1 read-write BKP DST_Not_Changed Daylight Saving Time change has not been performed 0 DST_Changed Daylight Saving Time change has been performed 1 COSEL Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 POL Output polarity This bit is used to configure the polarity of RTC_ALARM output 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 OSEL Output selection These bits are used to select the flag to be routed to RTC_ALARM output 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 COE Calibration output enable This bit enables the RTC_CALIB output 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 ITSE timestamp on internal event enable 24 1 read-write ITSE Disabled Internal event timestamp is disabled 0 Enabled Internal event timestamp is enabled 1 ISR ISR This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9. 0xC 0x20 0x00000007 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only ALRAWFR UpdateNotAllowed Alarm update not allowed 0 UpdateAllowed Alarm update allowed 1 WUTWF Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set. 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 SHPF Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 INITS Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITF Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 2 0x1 A,B ALR%sF Alarm %s flag 8 1 read-write zeroToClear ALRAFR read Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 ALRAFW write Clear This flag is cleared by software by writing 0 0 WUTF Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. 10 1 read-write zeroToClear WUTFR read Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 WUTFW write Clear This flag is cleared by software by writing 0 0 TSF Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0. 11 1 read-write zeroToClear TSFR read TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSFW write Clear This flag is cleared by software by writing 0 0 TSOVF Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared. 12 1 read-write zeroToClear TSOVFR read Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSOVFW write Clear This flag is cleared by software by writing 0 0 TAMP1F RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0 13 1 read-write zeroToClear TAMP1FR read Tampered This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input 1 TAMP1FW write Clear Flag cleared by software writing 0 0 TAMP2F RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0 14 1 read-write zeroToClear read write TAMP3F RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0 15 1 read-write zeroToClear read write RECALPF Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. 16 1 read-only RECALPFR Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 ITSF Internal tTime-stamp flag 17 1 read-write zeroToClear ITSFR read Match This flag is set by hardware when a time-stamp on the internal event occurs 1 ITSFW write Clear This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits 0 PRER PRER This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9. 0x10 0x20 read-write 0x007F00FF PREDIV_S Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 0 15 0 32767 PREDIV_A Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) 16 7 0 127 WUTR WUTR This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9. 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. 0 16 0 65535 2 0x4 A,B ALRM%sR ALRM%sR Alarm %s register 0x1C 0x20 read-write 0x00000000 SU Second units in BCD format 0 4 0 15 ST Second tens in BCD format 4 3 0 7 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MNU Minute units in BCD format 8 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MSK2 Alarm minutes mask 15 1 HU Hour units in BCD format 16 4 0 15 HT Hour tens in BCD format 20 2 0 3 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 MSK3 Alarm hours mask 23 1 DU Date units or day in BCD format 24 4 0 15 DT Date tens in BCD format 28 2 0 3 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 MSK4 Alarm date mask 31 1 WPR WPR RTC write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 0 8 0 255 SSR SSR RTC sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. 0 16 0 65535 SHIFTR SHIFTR This register is write protected. The write access procedure is described in RTC register write protection on page9. 0x2C 0x20 write-only 0x00000000 SUBFS Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time. 0 15 0 32767 ADD1S Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 TSTR TSTR The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. 0x30 TSDR TSDR The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. 0x34 TSSSR TSSSR The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. 0x38 CALR CALR This register is write protected. The write access procedure is described in RTC register write protection on page9. 0x3C 0x20 read-write 0x00000000 CALM Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13. 0 9 0 511 CALW16 Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration. 13 1 CALW16 Sixteen_Second When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALW8 Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration. 14 1 CALW8 Eight_Second When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALP Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration. 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 TAMPCR TAMPCR RTC tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 TAMP1E RTC_TAMP1 input detection enable 0 1 TAMP1TRG Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00: 1 1 TAMPIE Tamper interrupt enable 2 1 TAMP2E RTC_TAMP2 input detection enable 3 1 TAMP2TRG Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00: 4 1 TAMP3E RTC_TAMP3 detection enable 5 1 TAMP3TRG Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00: 6 1 TAMPTS Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register. 7 1 TAMPFREQ Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled. 8 3 TAMPFLT RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs. 11 2 TAMPPRCH RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 13 2 TAMPPUDIS RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample. 15 1 TAMP1IE Tamper 1 interrupt enable 16 1 TAMP1NOERASE Tamper 1 no erase 17 1 TAMP1MF Tamper 1 mask flag 18 1 TAMP2IE Tamper 2 interrupt enable 19 1 TAMP2NOERASE Tamper 2 no erase 20 1 TAMP2MF Tamper 2 mask flag 21 1 TAMP3IE Tamper 3 interrupt enable 22 1 TAMP3NOERASE Tamper 3 no erase 23 1 TAMP3MF Tamper 3 mask flag 24 1 2 0x4 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 SS Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 0 15 0 32767 MASKSS Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. 24 4 0 15 32 0x4 0-31 BKP%sR BKP%sR RTC backup registers 0x50 0x20 read-write 0x00000000 BKP The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled. 0 32 0 4294967295 OR OR RTC option register 0x4C 0x20 read-write 0x00000000 RTC_ALARM_TYPE RTC_ALARM output type on PC13 0 1 RTC_OUT_RMP RTC_OUT remap 1 1 SAI4 SAI SAI 0x58005400 0x0 0x400 registers SAI4 SAI4 global interrupt 146 GCR GCR Global configuration register 0x0 0x20 read-write 0x00000000 SYNCOUT Synchronization outputs These bits are set and cleared by software. 4 2 SYNCIN Synchronization inputs 0 2 2 0x20 A,B CH%s Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR 0x4 CR1 ACR1 Configuration register 1 0x0 0x20 read-write 0x00000040 MODE SAIx audio block mode immediately 0 2 MODE MasterTx Master transmitter 0 MasterRx Master receiver 1 SlaveTx Slave transmitter 2 SlaveRx Slave receiver 3 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 PRTCFG Free Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol 0 Spdif SPDIF protocol 1 Ac97 AC’97 protocol 2 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 DS Bit8 8 bits 2 Bit10 10 bits 3 Bit16 16 bits 4 Bit20 20 bits 5 Bit24 24 bits 6 Bit32 32 bits 7 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 LSBFIRST MsbFirst Data are transferred with MSB first 0 LsbFirst Data are transferred with LSB first 1 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 CKSTR FallingEdge Data strobing edge is falling edge of SCK 0 RisingEdge Data strobing edge is rising edge of SCK 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SYNCEN Asynchronous audio sub-block in asynchronous mode 0 Internal audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 1 External audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 MONO Stereo Stereo mode 0 Mono Mono mode 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 OUTDRIV OnStart Audio block output driven when SAIEN is set 0 Immediately Audio block output driven immediately after the setting of this bit 1 SAIEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SAIEN Disabled SAI audio block disabled 0 Enabled SAI audio block enabled 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 OSR Oversampling ratio for master clock 26 1 NODIV No fixed divider between MCLK and FS 19 1 NODIV MasterClock MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value 0 NoDiv MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. 1 CR2 ACR2 Configuration register 2 0x4 0x20 0x00000000 FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write FTH Empty FIFO empty 0 Quarter1 1⁄4 FIFO 1 Quarter2 1⁄2 FIFO 2 Quarter3 3⁄4 FIFO 3 Full FIFO full 4 FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FFLUSH NoFlush No FIFO flush 0 Flush FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared 1 TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTE Disabled No mute mode 0 Enabled Mute mode enabled 1 MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write MUTEVAL SendZero Bit value 0 is sent during the mute mode 0 SendLast Last values are sent during the mute mode 1 MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write CPL OnesComplement 1’s complement representation 0 TwosComplement 2’s complement representation 1 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write COMP NoCompanding No companding algorithm 0 MuLaw μ-Law algorithm 2 ALaw A-Law algorithm 3 FRCR AFRCR This register has no meaning in AC97 and SPDIF audio protocol 0x8 0x20 0x00000007 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write FSPOL FallingEdge FS is active low (falling edge) 0 RisingEdge FS is active high (rising edge) 1 FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSOFF OnFirst FS is asserted on the first bit of the slot 0 0 BeforeFirst FS is asserted one bit before the first bit of the slot 0 1 SLOTR ASLOTR This register has no meaning in AC97 and SPDIF audio protocol 0xC 0x20 read-write 0x00000000 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SLOTSZ DataSize The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) 0 Bit16 16-bit 1 Bit32 32-bit 2 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTEN Inactive Inactive slot 0 Active Active slot 1 IM AIM Interrupt mask register 2 0x10 0x20 read-write 0x00000000 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 OVRUDRIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 MUTEDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 WCKCFGIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 FREQIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 CNRDYIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 AFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 LFSDETIE Disabled Interrupt is disabled 0 Enabled Interrupt is enabled 1 SR ASR Status register 0x14 0x20 read-only 0x00000008 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 OVRUDRR NoError No overrun/underrun error 0 Overrun Overrun/underrun error detection 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 MUTEDETR NoMute No MUTE detection on the SD input line 0 Mute MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 WCKCFGR Correct Clock configuration is correct 0 Wrong Clock configuration does not respect the rule concerning the frame length specification 1 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 FREQR NoRequest No FIFO request 0 Request FIFO request to read or to write the SAI_xDR 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 CNRDYR Ready External AC’97 Codec is ready 0 NotReady External AC’97 Codec is not ready 1 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 AFSDETR NoError No error 0 EarlySync Frame synchronization signal is detected earlier than expected 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 LFSDETR NoError No error 0 NoSync Frame synchronization signal is not present at the right time 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FLVLR Empty FIFO empty 0 Quarter1 FIFO <= 1⁄4 but not empty 1 Quarter2 1⁄4 < FIFO <= 1⁄2 2 Quarter3 1⁄2 < FIFO <= 3⁄4 3 Quarter4 3⁄4 < FIFO but not full 4 Full FIFO full 5 CLRFR ACLRFR Clear flag register 0x18 0x20 write-only 0x00000000 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 COVRUDRW Clear Clears the OVRUDR flag 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 CMUTEDETW Clear Clears the MUTEDET flag 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 CWCKCFGW Clear Clears the WCKCFG flag 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CCNRDYW Clear Clears the CNRDY flag 1 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CAFSDETW Clear Clears the AFSDET flag 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CLFSDETW Clear Clears the LFSDET flag 1 DR ADR Data register 0x1C 0x20 read-write 0x00000000 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDM enable 0 1 MICNBR Number of microphones 4 2 4 0x1 1-4 CKEN%s Clock enable of bitstream clock number %s 8 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 4 0x8 1-4 DLYM%sL Delay line adjust for first microphone of pair %s 0 3 4 0x8 1-4 DLYM%sR Delay line adjust for second microphone of pair %s 4 3 SAI1 0x40015800 SAI1 SAI1 global interrupt 87 SAI2 0x40015C00 SAI2 SAI2 global interrupt 91 SAI3 0x40016000 SAI3 SAI3 global interrupt 114 SDMMC1 SDMMC1 SDMMC 0x52007000 0x0 0x3FD registers SDMMC1 SDMMC global interrupt 49 SDMMC SDMMC global interrupt 124 POWER POWER SDMMC power control register 0x0 0x20 read-write 0x00000000 PWRCTRL SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. 0 2 VSWITCH Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 2 1 VSWITCHEN Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 DIRPOL Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 CLKCR CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. 0x4 0x20 read-write 0x00000000 CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. 0 10 PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 NEGEDGE SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. 16 1 HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. 17 1 DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0) 18 1 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 SELCLKRX Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 ARGR ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 0x20 read-write 0x00000000 CMDARG Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 CMDR CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 0x20 read-write 0x00000000 CMDINDEX Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. 7 1 WAITRESP Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 WAITINT CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. 10 1 WAITPEND CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 CPSMEN Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. 12 1 DTHOLD Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 BOOTMODE Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 BOOTEN Enable boot mode procedure. 15 1 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 4 0x4 1-4 RESP%sR RESP%sR SDMMC response %s register 0x14 0x20 read-only 0x00000000 CARDSTATUS Status of a card, which is part of the received response 0 32 DTIMER DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 0x20 read-write 0x00000000 DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 DLENR DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. 0 25 DCTRL DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 0x20 read-write 0x00000000 DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0 1 DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 DTMODE Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) 4 4 RWSTART Read wait start. If this bit is set, read wait operation starts. 8 1 RWSTOP Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 9 1 RWMOD Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 BOOTACKEN Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 FIFORST FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 13 1 DCNTR DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 STAR STAR The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 0x20 read-only 0x00000000 CCRCFAIL Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 DCRCFAIL Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 CTIMEOUT Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 DTIMEOUT Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 TXUNDERR Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 RXOVERR Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 CMDREND Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 CMDSENT Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 DATAEND Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 DHOLD Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 DBCKEND Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 DABORT Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 DPSMACT Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 12 1 CPSMACT Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 13 1 TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 SDIOIT SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 ACKTIMEOUT Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 VSWEND Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 IDMATE IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 IDMABTC IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 ICR ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 0x20 read-write 0x00000000 CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 MASKR MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 0x20 read-write 0x00000000 CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 ACKTIMER ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 0x20 read-write 0x00000000 ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 IDMACTRLR IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 0x20 read-write 0x00000000 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMABACT Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 2 1 IDMABSIZER IDMABSIZER The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 0x54 0x20 read-write 0x00000000 IDMABNDT Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 8 IDMABASE0R IDMABASE0R The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. 0x58 0x20 read-write 0x00000000 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). 0 32 IDMABASE1R IDMABASE1R The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 0x5C 0x20 read-write 0x00000000 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). 0 32 FIFOR FIFOR The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. 0 32 RESPCMDR RESPCMDR SDMMC command response register 0x10 0x20 read-only 0xA3C5DD01 RESPCMD Response command index 0 6 SDMMC2 0x48022400 VREFBUF VREFBUF VREFBUF 0x58003C00 0x0 0x400 registers CSR CSR VREFBUF control and status register 0x0 0x20 0x00000002 ENVR Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. 0 1 read-write HIZ High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved 4 3 read-write CCR CCR VREFBUF calibration control register 0x4 0x20 read-write 0x00000000 TRIM Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. 0 6 IWDG IWDG IWDG 0x58004800 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section23.3.6: Register access protection) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider These bits are write access protected see Section23.3.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value These bits are write access protected see Section23.3.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 PVU Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. 0 1 RVU Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. 1 1 WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic window = 1 2 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value These bits are write access protected see Section23.3.6. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset. 0 12 0 4095 WWDG WWDG WWDG 0x50003000 0x0 0x400 registers WWDG1 Window Watchdog interrupt 0 WWDG1_RST Window Watchdog interrupt 143 CR CR Control register 0x0 0x10 read-write 0x0000007F T 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 0 7 0 127 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset. 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F W 7-bit window value These bits contain the window value to be compared to the downcounter. 0 7 0 127 WDGTB Timer base The time base of the prescaler can be modified as follows: 11 3 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 Div16 Counter clock (PCLK1 div 4096) div 16 4 Div32 Counter clock (PCLK1 div 4096) div 32 5 Div64 Counter clock (PCLK1 div 4096) div 64 6 Div128 Counter clock (PCLK1 div 4096) div 128 7 EWI Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled. 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 PWR PWR PWR 0x58024800 0x0 0x400 registers CR1 CR1 PWR control register 1 0x0 0x20 read-write 0xF000C000 LPDS Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) 0 1 PVDE Programmable voltage detector enable 4 1 PLS Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. 5 3 DBP Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. 8 1 FLPS Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. 9 1 SVOS System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. 14 2 AVDEN Peripheral voltage monitor on VDDA enable 16 1 ALS Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. 17 2 CSR1 CSR1 PWR control status register 1 0x4 0x20 read-only 0x00004000 PVDO Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. 4 1 ACTVOSRDY Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). 13 1 ACTVOS VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. 14 2 AVDO Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. 16 1 CR2 CR2 This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. 0x8 0x20 0x00000000 BREN Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. 0 1 read-write MONEN VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. 4 1 read-write BRRDY Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. 16 1 read-only VBATL VBAT level monitoring versus low threshold 20 1 read-only VBATH VBAT level monitoring versus high threshold 21 1 read-only TEMPL Temperature level monitoring versus low threshold 22 1 read-only TEMPH Temperature level monitoring versus high threshold 23 1 read-only CR3 CR3 Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. 0xC 0x20 0x00000006 BYPASS Power management unit bypass 0 1 read-write LDOEN Low drop-out regulator enable 1 1 read-write SDEN SD converter Enable 2 1 read-write VBE VBAT charging enable 8 1 read-write VBRS VBAT charging resistor selection 9 1 read-write USB33DEN VDD33USB voltage level detector enable. 24 1 write-only USBREGEN USB regulator enable. 25 1 read-write USB33RDY USB supply ready. 26 1 read-only CPUCR CPUCR This register allows controlling CPU1 power. 0x10 0x20 0x00000000 PDDS_D1 D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. 0 1 read-write PDDS_D2 D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. 1 1 read-write PDDS_D3 System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. 2 1 read-write STOPF STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. 5 1 read-only SBF System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit 6 1 read-only SBF_D1 D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. 7 1 read-only SBF_D2 D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. 8 1 read-only CSSF Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. 9 1 read-write RUN_D3 Keep system D3 domain in Run mode regardless of the CPU sub-systems modes 11 1 read-write D3CR D3CR This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software 0x18 0x20 0x00004000 VOSRDY VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). 13 1 read-only VOS Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. 14 2 read-write WKUPCR WKUPCR reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). 0x20 0x20 read-write 0x00000000 WKUPC Clear Wakeup pin flag for WKUP. These bits are always read as 0. 0 6 WKUPFR WKUPFR reset only by system reset, not reset by wakeup from Standby mode 0x24 0x20 read-write 0x00000000 WKUPF1 Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 0 1 WKUPF2 Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 1 1 WKUPF3 Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 2 1 WKUPF4 Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 3 1 WKUPF5 Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 4 1 WKUPF6 Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 5 1 WKUPEPR WKUPEPR Reset only by system reset, not reset by wakeup from Standby mode 0x28 0x20 read-write 0x00000000 WKUPEN1 Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. 0 1 WKUPEN2 Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. 1 1 WKUPEN3 Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. 2 1 WKUPEN4 Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. 3 1 WKUPEN5 Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. 4 1 WKUPEN6 Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. 5 1 WKUPP1 Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 8 1 WKUPP2 Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 9 1 WKUPP3 Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 10 1 WKUPP4 Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 11 1 WKUPP5 Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 12 1 WKUPP6 Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 13 1 WKUPPUPD1 Wakeup pin pull configuration 16 2 WKUPPUPD2 Wakeup pin pull configuration 18 2 WKUPPUPD3 Wakeup pin pull configuration 20 2 WKUPPUPD4 Wakeup pin pull configuration 22 2 WKUPPUPD5 Wakeup pin pull configuration 24 2 WKUPPUPD6 Wakeup pin pull configuration for WKUP(truncate(n/2)-7) These bits define the I/O pad pull configuration used when WKUPEN(truncate(n/2)-7) = 1. The associated GPIO port pull configuration shall be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode. 26 2 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x20 0x00000000 IOLOCK Locking the AF configuration of associated IOs 16 1 read-only IOLOCK Unlocked IO configuration unlocked 0 Locked IO configuration locked 1 TCRCINI CRC calculation initialization pattern control for transmitter 15 1 read-write TCRCINI AllZeros All zeros TX CRC initialization pattern 0 AllOnes All ones TX CRC initialization pattern 1 RCRCINI CRC calculation initialization pattern control for receiver 14 1 read-write RCRCINI AllZeros All zeros RX CRC initialization pattern 0 AllOnes All ones RX CRC initialization pattern 1 CRC33_17 32-bit CRC polynomial configuration 13 1 read-write CRC33_17 Disabled Full size (33/17 bit) CRC polynomial is not used 0 Enabled Full size (33/17 bit) CRC polynomial is used 1 SSI Internal SS signal input level 12 1 read-write SSI SlaveSelected 0 is forced onto the SS signal and the I/O value of the SS pin is ignored 0 SlaveNotSelected 1 is forced onto the SS signal and the I/O value of the SS pin is ignored 1 HDDIR Rx/Tx direction at Half-duplex mode 11 1 read-write HDDIR Receiver Receiver in half duplex mode 0 Transmitter Transmitter in half duplex mode 1 CSUSP Master SUSPend request 10 1 write-only CSUSPW NotRequested Do not request master suspend 0 Requested Request master suspend 1 CSTART Master transfer start 9 1 read-write CSTART NotStarted Do not start master transfer 0 Started Start master transfer 1 MASRX Master automatic SUSP in Receive mode 8 1 read-write MASRX Disabled Automatic suspend in master receive-only mode disabled 0 Enabled Automatic suspend in master receive-only mode enabled 1 SPE Serial Peripheral Enable 0 1 read-write SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 CR2 CR2 control register 2 0x4 0x20 0x00000000 TSER Number of data transfer extension to be reload into TSIZE just when a previous 16 16 read-only 0 65535 TSIZE Number of data at current transfer 0 16 read-write 0 65535 CFG1 CFG1 configuration register 1 0x8 0x20 read-write 0x00070007 MBR Master baud rate 28 3 MBR Div2 f_spi_ker_ck / 2 0 Div4 f_spi_ker_ck / 4 1 Div8 f_spi_ker_ck / 8 2 Div16 f_spi_ker_ck / 16 3 Div32 f_spi_ker_ck / 32 4 Div64 f_spi_ker_ck / 64 5 Div128 f_spi_ker_ck / 128 6 Div256 f_spi_ker_ck / 256 7 CRCEN Hardware CRC computation enable 22 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCSIZE Length of CRC frame to be transacted and compared 16 5 0 31 TXDMAEN Tx DMA stream enable 15 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 RXDMAEN Rx DMA stream enable 14 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 UDRDET Detection of underrun condition at slave transmitter 11 2 UDRDET StartOfFrame Underrun is detected at begin of data frame 0 EndOfFrame Underrun is detected at end of last data frame 1 StartOfSlaveSelect Underrun is detected at begin of active SS signal 2 UDRCFG Behavior of slave transmitter at underrun condition 9 2 UDRCFG Constant Slave sends a constant underrun pattern 0 RepeatReceived Slave repeats last received data frame from master 1 RepeatTransmitted Slave repeats last transmitted data frame 2 FTHLV threshold level 5 4 FTHLV OneFrame 1 frame 0 TwoFrames 2 frames 1 ThreeFrames 3 frames 2 FourFrames 4 frames 3 FiveFrames 5 frames 4 SixFrames 6 frames 5 SevenFrames 7 frames 6 EightFrames 8 frames 7 NineFrames 9 frames 8 TenFrames 10 frames 9 ElevenFrames 11 frames 10 TwelveFrames 12 frames 11 ThirteenFrames 13 frames 12 FourteenFrames 14 frames 13 FifteenFrames 15 frames 14 SixteenFrames 16 frames 15 DSIZE Number of bits in at single SPI data frame 0 5 0 31 CFG2 CFG2 configuration register 2 0xC 0x20 read-write 0x00000000 AFCNTR Alternate function GPIOs control 31 1 AFCNTR NotControlled Peripheral takes no control of GPIOs while disabled 0 Controlled Peripheral controls GPIOs while disabled 1 SSOM SS output management in master mode 30 1 SSOM Asserted SS is asserted until data transfer complete 0 NotAsserted Data frames interleaved with SS not asserted during MIDI 1 SSOE SS output enable 29 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 SSIOP SS input/output polarity 28 1 SSIOP ActiveLow Low level is active for SS signal 0 ActiveHigh High level is active for SS signal 1 SSM Software management of SS signal input 26 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 CPOL Clock polarity 25 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 24 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 LSBFRST Data frame format 23 1 LSBFRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 MASTER SPI Master 22 1 MASTER Slave Slave configuration 0 Master Master configuration 1 SP Serial Protocol 19 3 SP Motorola Motorola SPI protocol 0 TI TI SPI protocol 1 COMM SPI Communication Mode 17 2 COMM FullDuplex Full duplex 0 Transmitter Simplex transmitter only 1 Receiver Simplex receiver only 2 HalfDuplex Half duplex 3 IOSWP Swap functionality of MISO and MOSI pins 15 1 IOSWP Disabled MISO and MOSI not swapped 0 Enabled MISO and MOSI swapped 1 MIDI Master Inter-Data Idleness 4 4 0 15 MSSI Master SS Idleness 0 4 0 15 IER IER Interrupt Enable Register 0x10 0x20 0x00000000 RXPIE RXP Interrupt Enable 0 1 read-write RXPIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 TSERFIE Additional number of transactions reload interrupt enable 10 1 read-write MODFIE Mode Fault interrupt enable 9 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write CRCEIE CRC Interrupt enable 7 1 read-write OVRIE OVR interrupt enable 6 1 read-write UDRIE UDR interrupt enable 5 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write DXPIE DXP interrupt enabled 2 1 read-write TXPIE TXP interrupt enable 1 1 read-write SR SR Status Register 0x14 0x20 read-only 0x00001002 CTSIZE Number of data frames remaining in current TSIZE session 16 16 0 65535 RXWNE RxFIFO Word Not Empty 15 1 RXWNE LessThan32 Less than 32-bit data frame received 0 AtLeast32 At least 32-bit data frame received 1 RXPLVL RxFIFO Packing LeVeL 13 2 RXPLVL ZeroFrames Zero frames beyond packing ratio available 0 OneFrame One frame beyond packing ratio available 1 TwoFrames Two frame beyond packing ratio available 2 ThreeFrames Three frame beyond packing ratio available 3 TXC TxFIFO transmission complete 12 1 TXC Ongoing Transmission ongoing 0 Completed Transmission completed 1 SUSP SUSPend 11 1 SUSP NotSuspended Master not suspended 0 Suspended Master suspended 1 TSERF Additional number of SPI data to be transacted was reload 10 1 TSERF NotLoaded Additional number of SPI data to be transacted not yet loaded 0 Loaded Additional number of SPI data to be transacted was reloaded 1 MODF Mode Fault 9 1 MODF NoFault No mode fault detected 0 Fault Mode fault detected 1 TIFRE TI frame format error 8 1 TIFRE NoError TI frame format error detected 0 Error TI frame format error detected 1 CRCE CRC Error 7 1 CRCE NoError No CRC error detected 0 Error CRC error detected 1 OVR Overrun 6 1 OVR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 UDR Underrun at slave transmission mode 5 1 UDR NoUnderrun No underrun occurred 0 Underrun Underrun occurred 1 TXTF Transmission Transfer Filled 4 1 TXTF NotCompleted Transmission buffer incomplete 0 Completed Transmission buffer filled with at least one transfer 1 EOT End Of Transfer 3 1 EOT NotCompleted Transfer ongoing or not started 0 Completed Transfer complete 1 DXP Duplex Packet 2 1 DXP Unavailable Duplex packet unavailable: no space for transmission and/or no data received 0 Available Duplex packet available: space for transmission and data received 1 TXP Tx-Packet space available 1 1 TXP Full Tx buffer full 0 NotFull Tx buffer not full 1 RXP Rx-Packet available 0 1 RXP Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 IFCR IFCR Interrupt/Status Flags Clear Register 0x18 0x20 write-only 0x00000000 EOTC End Of Transfer flag clear 3 1 oneToClear EOTCW Clear Clear interrupt flag 1 SUSPC SUSPend flag clear 11 1 oneToClear TSERFC TSERFC flag clear 10 1 oneToClear MODFC Mode Fault flag clear 9 1 oneToClear TIFREC TI frame format error flag clear 8 1 oneToClear CRCEC CRC Error flag clear 7 1 oneToClear OVRC Overrun flag clear 6 1 oneToClear UDRC Underrun flag clear 5 1 oneToClear TXTFC Transmission Transfer Filled flag clear 4 1 oneToClear TXDR TXDR Transmit Data Register 0x20 0x20 write-only 0x00000000 TXDR Transmit data register 0 32 0 4294967295 TXDR16 Direct 16-bit access to transmit data register TXDR 0x20 0x10 write-only TXDR Transmit data register 0 16 0 65535 TXDR8 Direct 8-bit access to transmit data register TXDR 0x20 0x8 write-only TXDR Transmit data register 0 8 0 255 RXDR RXDR Receive Data Register 0x30 0x20 read-only 0x00000000 RXDR Receive data register 0 32 RXDR16 Direct 16-bit access to receive data register RXDR 0x30 0x10 read-only RXDR Receive data register 0 16 RXDR8 Direct 8-bit access to receive data register RXDR 0x30 0x8 read-only RXDR Receive data register 0 8 CRCPOLY CRCPOLY Polynomial Register 0x40 0x20 read-write 0x00000107 CRCPOLY CRC polynomial register 0 32 0 4294967295 TXCRC TXCRC Transmitter CRC Register 0x44 0x20 read-only 0x00000000 TXCRC CRC register for transmitter 0 32 0 4294967295 RXCRC RXCRC Receiver CRC Register 0x48 0x20 read-only 0x00000000 RXCRC CRC register for receiver 0 32 0 4294967295 UDRDR UDRDR Underrun Data Register 0x4C 0x20 read-write 0x00000000 UDRDR Data at slave underrun condition 0 32 0 4294967295 I2SCFGR CGFR configuration register 0x50 0x20 read-write 0x00000000 MCKOE Master clock output enable 25 1 MCKOE Disabled Master clock output disabled 0 Enabled Master clock output enabled 1 ODD Odd factor for the prescaler 24 1 ODD Even Real divider value is I2SDIV*2 0 Odd Real divider value is I2SDIV*2 + 1 1 I2SDIV I2S linear prescaler 16 8 DATFMT Data format 14 1 DATFMT RightAligned The data inside RXDR and TXDR are right aligned 0 LeftAligned The data inside RXDR and TXDR are left aligned 1 WSINV Fixed channel length in SLAVE 13 1 WSINV Disabled Word select inversion disabled 0 Enabled Word select inversion enabled 1 FIXCH Word select inversion 12 1 FIXCH NotFixed The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) 0 Fixed The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) 1 CKPOL Serial audio clock polarity 11 1 CKPOL SampleOnRising Signals are sampled on rising and changed on falling clock edges 0 SampleOnFalling Signals are sampled on falling and changed on rising clock edges 1 CHLEN Channel length (number of bits per audio channel) 10 1 CHLEN Bits16 16 bit per channel 0 Bits32 32 bit per channel 1 DATLEN Data length to be transferred 8 2 DATLEN Bits16 16 bit data length 0 Bits24 24 bit data length 1 Bits32 32 bit data length 2 PCMSYNC PCM frame synchronization 7 1 PCMSYNC Short Short PCM frame synchronization 0 Long Long PCM frame synchronization 1 I2SSTD I2S standard selection 4 2 I2SSTD Philips I2S Philips standard 0 LeftAligned MSB/left justified standard 1 RightAligned LSB/right justified standard 2 PCM PCM standard 3 I2SCFG I2S configuration mode 1 3 I2SCFG SlaveTransmit Slave, transmit 0 SlaveReceive Slave, recteive 1 MasterTransmit Master, transmit 2 MasterReceive Master, receive 3 SlaveFullDuplex Slave, full duplex 4 MasterFullDuplex Master, full duplex 5 I2SMOD I2S mode selection 0 1 I2SMOD SPI SPI mode selected 0 I2S I2S/PCM mode selected 1 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SPI3 0x40003C00 SPI3 SPI3 global interrupt 51 SPI4 0x40013400 SPI4 SPI4 global interrupt 84 SPI5 0x40015000 SPI5 SPI5 global interrupt 85 SPI6 0x58001400 SPI6 SPI6 global interrupt 86 LTDC LCD-TFT Controller LTDC 0x50001000 0x0 0x1000 registers LTDC LCD-TFT global interrupt 88 LTDC_ER LCD-TFT error interrupt 89 SSCR SSCR Synchronization Size Configuration Register 0x8 0x20 read-write 0x00000000 HSW Horizontal Synchronization Width (in units of pixel clock period) 16 12 0 4095 VSH Vertical Synchronization Height (in units of horizontal scan line) 0 11 0 2047 BPCR BPCR Back Porch Configuration Register 0xC 0x20 read-write 0x00000000 AHBP Accumulated Horizontal back porch (in units of pixel clock period) 16 12 0 4095 AVBP Accumulated Vertical back porch (in units of horizontal scan line) 0 11 0 2047 AWCR AWCR Active Width Configuration Register 0x10 0x20 read-write 0x00000000 AAW Accumulated Active Width (in units of pixel clock period) 16 12 0 4095 AAH Accumulated Active Height (in units of horizontal scan line) 0 11 0 2047 TWCR TWCR Total Width Configuration Register 0x14 0x20 read-write 0x00000000 TOTALW Total Width (in units of pixel clock period) 16 12 0 4095 TOTALH Total Height (in units of horizontal scan line) 0 11 0 2047 GCR GCR Global Control Register 0x18 0x20 0x00002220 HSPOL Horizontal Synchronization Polarity 31 1 read-write HSPOL ActiveLow Horizontal synchronization polarity is active low 0 ActiveHigh Horizontal synchronization polarity is active high 1 VSPOL Vertical Synchronization Polarity 30 1 read-write VSPOL ActiveLow Vertical synchronization polarity is active low 0 ActiveHigh Vertical synchronization polarity is active high 1 DEPOL Data Enable Polarity 29 1 read-write DEPOL ActiveLow Data enable polarity is active low 0 ActiveHigh Data enable polarity is active high 1 PCPOL Pixel Clock Polarity 28 1 read-write PCPOL RisingEdge Pixel clock on rising edge 0 FallingEdge Pixel clock on falling edge 1 DEN Dither Enable 16 1 read-write DEN Disabled Dither disabled 0 Enabled Dither enabled 1 DRW Dither Red Width 12 3 read-only DGW Dither Green Width 8 3 read-only DBW Dither Blue Width 4 3 read-only LTDCEN LCD-TFT controller enable bit 0 1 read-write LTDCEN Disabled LCD-TFT controller disabled 0 Enabled LCD-TFT controller enabled 1 SRCR SRCR Shadow Reload Configuration Register 0x24 0x20 read-write 0x00000000 VBR Vertical Blanking Reload 1 1 VBR NoEffect This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) 0 Reload The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). 1 IMR Immediate Reload 0 1 IMR NoEffect This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) 0 Reload The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload 1 BCCR BCCR Background Color Configuration Register 0x2C 0x20 read-write 0x00000000 BCBLUE Background Color Blue value 0 8 0 255 BCGREEN Background Color Green value 8 8 0 255 BCRED Background Color Red value 16 8 0 255 IER IER Interrupt Enable Register 0x34 0x20 read-write 0x00000000 RRIE Register Reload interrupt enable 3 1 RRIE Disabled Register reload interrupt disabled 0 Enabled Register reload interrupt enabled 1 TERRIE Transfer Error Interrupt Enable 2 1 TERRIE Disabled Transfer error interrupt disabled 0 Enabled Transfer error interrupt enabled 1 FUIE FIFO Underrun Interrupt Enable 1 1 FUIE Disabled FIFO underrun interrupt disabled 0 Enabled FIFO underrun interrupt enabled 1 LIE Line Interrupt Enable 0 1 LIE Disabled Line interrupt disabled 0 Enabled Line interrupt enabled 1 ISR ISR Interrupt Status Register 0x38 0x20 read-only 0x00000000 RRIF Register Reload Interrupt Flag 3 1 RRIF NoReload No register reload 0 Reload Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) 1 TERRIF Transfer Error interrupt flag 2 1 TERRIF NoError No transfer error 0 Error Transfer error interrupt generated when a bus error occurs 1 FUIF FIFO Underrun Interrupt flag 1 1 FUIF NoUnderrun No FIFO underrun 0 Underrun FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO 1 LIF Line Interrupt flag 0 1 LIF NotReached Programmed line not reached 0 Reached Line interrupt generated when a programmed line is reached 1 ICR ICR Interrupt Clear Register 0x3C 0x20 write-only 0x00000000 CRRIF Clears Register Reload Interrupt Flag 3 1 oneToClear CRRIFW Clear Clears the RRIF flag in the ISR register 1 CTERRIF Clears the Transfer Error Interrupt Flag 2 1 oneToClear CTERRIFW Clear Clears the TERRIF flag in the ISR register 1 CFUIF Clears the FIFO Underrun Interrupt flag 1 1 oneToClear CFUIFW Clear Clears the FUIF flag in the ISR register 1 CLIF Clears the Line Interrupt Flag 0 1 oneToClear CLIFW Clear Clears the LIF flag in the ISR register 1 LIPCR LIPCR Line Interrupt Position Configuration Register 0x40 0x20 read-write 0x00000000 LIPOS Line Interrupt Position 0 11 0 2047 CPSR CPSR Current Position Status Register 0x44 0x20 read-only 0x00000000 CXPOS Current X Position 16 16 CYPOS Current Y Position 0 16 CDSR CDSR Current Display Status Register 0x48 0x20 read-only 0x0000000F HSYNCS Horizontal Synchronization display Status 3 1 HSYNCS NotActive Currently not in HSYNC phase 0 Active Currently in HSYNC phase 1 VSYNCS Vertical Synchronization display Status 2 1 VSYNCS NotActive Currently not in VSYNC phase 0 Active Currently in VSYNC phase 1 HDES Horizontal Data Enable display Status 1 1 HDES NotActive Currently not in horizontal Data Enable phase 0 Active Currently in horizontal Data Enable phase 1 VDES Vertical Data Enable display Status 0 1 VDES NotActive Currently not in vertical Data Enable phase 0 Active Currently in vertical Data Enable phase 1 2 0x80 1-2 LAYER%s Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR 0x84 CR L1CR Layerx Control Register 0x0 0x20 read-write 0x00000000 CLUTEN Color Look-Up Table Enable 4 1 CLUTEN Disabled Color look-up table disabled 0 Enabled Color look-up table enabled 1 COLKEN Color Keying Enable 1 1 COLKEN Disabled Color keying disabled 0 Enabled Color keying enabled 1 LEN Layer Enable 0 1 LEN Disabled Layer disabled 0 Enabled Layer enabled 1 WHPCR L1WHPCR Layerx Window Horizontal Position Configuration Register 0x4 0x20 read-write 0x00000000 WHSPPOS Window Horizontal Stop Position 16 12 0 4095 WHSTPOS Window Horizontal Start Position 0 12 0 4095 WVPCR L1WVPCR Layerx Window Vertical Position Configuration Register 0x8 0x20 read-write 0x00000000 WVSPPOS Window Vertical Stop Position 16 11 0 2047 WVSTPOS Window Vertical Start Position 0 11 0 2047 CKCR L1CKCR Layerx Color Keying Configuration Register 0xC 0x20 read-write 0x00000000 CKRED Color Key Red value 16 8 0 255 CKGREEN Color Key Green value 8 8 0 255 CKBLUE Color Key Blue value 0 8 0 255 PFCR L1PFCR Layerx Pixel Format Configuration Register 0x10 0x20 read-write 0x00000000 PF Pixel Format 0 3 PF ARGB8888 ARGB8888 0 RGB888 RGB888 1 RGB565 RGB565 2 ARGB1555 ARGB1555 3 ARGB4444 ARGB4444 4 L8 L8 (8-bit luminance) 5 AL44 AL44 (4-bit alpha, 4-bit luminance) 6 AL88 AL88 (8-bit alpha, 8-bit luminance) 7 CACR L1CACR Layerx Constant Alpha Configuration Register 0x14 0x20 read-write 0x00000000 CONSTA Constant Alpha 0 8 0 255 DCCR L1DCCR Layerx Default Color Configuration Register 0x18 0x20 read-write 0x00000000 DCALPHA Default Color Alpha 24 8 0 255 DCRED Default Color Red 16 8 0 255 DCGREEN Default Color Green 8 8 0 255 DCBLUE Default Color Blue 0 8 0 255 BFCR L1BFCR Layerx Blending Factors Configuration Register 0x1C 0x20 read-write 0x00000607 BF1 Blending Factor 1 8 3 BF1 Constant BF1 = constant alpha 4 Pixel BF1 = pixel alpha * constant alpha 6 BF2 Blending Factor 2 0 3 BF2 Constant BF2 = 1 - constant alpha 5 Pixel BF2 = 1 - pixel alpha * constant alpha 7 CFBAR L1CFBAR Layerx Color Frame Buffer Address Register 0x28 0x20 read-write 0x00000000 CFBADD Color Frame Buffer Start Address 0 32 0 4294967295 CFBLR L1CFBLR Layerx Color Frame Buffer Length Register 0x2C 0x20 read-write 0x00000000 CFBP Color Frame Buffer Pitch in bytes 16 13 0 8191 CFBLL Color Frame Buffer Line Length 0 13 0 8191 CFBLNR L1CFBLNR Layerx ColorFrame Buffer Line Number Register 0x30 0x20 read-write 0x00000000 CFBLNBR Frame Buffer Line Number 0 11 0 2047 CLUTWR L1CLUTWR Layerx CLUT Write Register 0x40 0x20 write-only 0x00000000 CLUTADD CLUT Address 24 8 0 255 RED Red value 16 8 0 255 GREEN Green value 8 8 0 255 BLUE Blue value 0 8 0 255 SPDIFRX Receiver Interface SPDIFRX 0x40004000 0x0 0x400 registers SPDIF SPDIFRX global interrupt 97 CR CR Control register 0x0 0x20 read-write 0x00000000 SPDIFRXEN Peripheral Block Enable 0 2 RXDMAEN Receiver DMA ENable for data flow 2 1 RXSTEO STerEO Mode 3 1 DRFMT RX Data format 4 2 PMSK Mask Parity error bit 6 1 VMSK Mask of Validity bit 7 1 CUMSK Mask of channel status and user bits 8 1 PTMSK Mask of Preamble Type bits 9 1 CBDMAEN Control Buffer DMA ENable for control flow 10 1 CHSEL Channel Selection 11 1 NBTR Maximum allowed re-tries during synchronization phase 12 2 WFA Wait For Activity 14 1 INSEL input selection 16 3 CKSEN Symbol Clock Enable 20 1 CKSBKPEN Backup Symbol Clock Enable 21 1 IMR IMR Interrupt mask register 0x4 0x20 read-write 0x00000000 RXNEIE RXNE interrupt enable 0 1 CSRNEIE Control Buffer Ready Interrupt Enable 1 1 PERRIE Parity error interrupt enable 2 1 OVRIE Overrun error Interrupt Enable 3 1 SBLKIE Synchronization Block Detected Interrupt Enable 4 1 SYNCDIE Synchronization Done 5 1 IFEIE Serial Interface Error Interrupt Enable 6 1 SR SR Status register 0x8 0x20 read-only 0x00000000 RXNE Read data register not empty 0 1 CSRNE Control Buffer register is not empty 1 1 PERR Parity error 2 1 OVR Overrun error 3 1 SBD Synchronization Block Detected 4 1 SYNCD Synchronization Done 5 1 FERR Framing error 6 1 SERR Synchronization error 7 1 TERR Time-out error 8 1 WIDTH5 Duration of 5 symbols counted with SPDIF_CLK 16 15 IFCR IFCR Interrupt Flag Clear register 0xC 0x20 write-only 0x00000000 PERRCF Clears the Parity error flag 2 1 OVRCF Clears the Overrun error flag 3 1 SBDCF Clears the Synchronization Block Detected flag 4 1 SYNCDCF Clears the Synchronization Done flag 5 1 DR_00 DR_00 Data input register 0x10 0x20 read-only 0x00000000 DR Parity Error bit 0 24 PE Parity Error bit 24 1 V Validity bit 25 1 U User bit 26 1 C Channel Status bit 27 1 PT Preamble Type 28 2 CSR CSR Channel Status register 0x14 0x20 read-only 0x00000000 USR User data information 0 16 CS Channel A status information 16 8 SOB Start Of Block 24 1 DIR DIR Debug Information register 0x18 0x20 read-only 0x00000000 THI Threshold HIGH 0 13 TLO Threshold LOW 16 13 VERR VERR SPDIFRX version register 0x3F4 0x20 read-only 0x00000012 MINREV Minor revision 0 4 MAJREV Major revision 4 4 IDR IDR SPDIFRX identification register 0x3F8 0x20 read-only 0x00130041 ID SPDIFRX identifier 0 32 SIDR SIDR SPDIFRX size identification register 0x3FC 0x20 read-only 0xA3C5DD01 SID Size identification 0 32 DR_01 DR_01 Data input register DR_00 0x10 0x20 read-only 0x00000000 PE Parity Error bit 0 1 V Validity bit 1 1 U User bit 2 1 C Channel Status bit 3 1 PT Preamble Type 4 2 DR Data value 8 24 DR_10 DR_10 Data input register 0x10 0x20 read-only 0x00000000 DRNL1 Data value 0 16 DRNL2 Data value 16 16 RAMECC1 ECC controller is associated to each RAM area RAMECC 0x52009000 0x0 0x400 registers IER IER RAMECC interrupt enable register 0x0 0x20 read-write 0x00000000 GIE Global interrupt enable 0 1 GECCSEIE Global ECC single error interrupt enable 1 1 GECCDEIE Global ECC double error interrupt enable 2 1 GECCDEBWIE Global ECC double error on byte write (BW) interrupt enable 3 1 5 0x20 1-5 M%s Cluster M%s, containing M?CR, M?SR, M?FAR, M?FDRL, M?FDRH, M?FECR 0x20 CR M1CR RAMECC monitor x configuration register 0x0 0x20 read-write 0x00000000 ECCSEIE ECC single error interrupt enable 2 1 ECCDEIE ECC double error interrupt enable 3 1 ECCDEBWIE ECC double error on byte write (BW) interrupt enable 4 1 ECCELEN ECC error latching enable 5 1 SR M1SR RAMECC monitor x status register 0x4 0x20 read-write 0x00000000 SEDCF ECC single error detected and corrected flag 0 1 DEDF ECC double error detected flag 1 1 DEBWDF ECC double error on byte write (BW) detected flag 2 1 FAR M1FAR RAMECC monitor x failing address register 0x8 0x20 read-only 0x00000000 FADD ECC error failing address 0 32 FDRL M1FDRL RAMECC monitor x failing data low register 0xC 0x20 read-only 0x00000000 FDATAL Failing data low 0 32 FDRH M1FDRH RAMECC monitor x failing data high register 0x10 0x20 read-only 0x00000000 FDATAH Failing data high (64-bit memory) 0 32 FECR M1FECR RAMECC monitor x failing ECC error code register 0x14 0x20 read-only 0x00000000 FEC Failing error code 0 32 RAMECC2 ECC controller is associated to each RAM area RAMECC 0x48023000 RAMECC3 ECC controller is associated to each RAM area RAMECC 0x58027000 0x0 0x400 registers IER IER RAMECC interrupt enable register 0x0 2 0x20 1-2 M%s Cluster M%s, containing M?CR, M?SR, M?FAR, M?FDRL, M?FDRH, M?FECR 0x20 ADC3 Analog to Digital Converter ADC 0x58026000 0x0 0xD1 registers ADC3 ADC3 global interrupt 127 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF ADC group injected contexts queue overflow flag 10 1 oneToClear JQOVFR read NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 JQOVFW write Clear Clear injected context queue overflow flag 1 3 0x1 1-3 AWD%s Analog watchdog %s flag 7 1 oneToClear AWD1R read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD1W write Clear Clear analog watchdog event occurred flag 1 JEOS ADC group injected end of sequence conversions flag 6 1 oneToClear JEOSR read NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 JEOSW write Clear Clear Injected sequence complete flag 1 JEOC ADC group injected end of unitary conversion flag 5 1 oneToClear JEOCR read NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOCW write Clear Clear injected conversion complete flag 1 OVR ADC group regular overrun flag 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear overrun occurred flag 1 EOS ADC group regular end of sequence conversions flag 3 1 oneToClear EOSR read NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 EOSW write Clear Clear regular sequence complete flag 1 EOC ADC group regular end of unitary conversion flag 2 1 oneToClear EOCR read NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOCW write Clear Clear regular conversion complete flag 1 EOSMP ADC group regular end of sampling flag 1 1 oneToClear EOSMPR read NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOSMPW write Clear Clear end of sampling phase reached flag 1 ADRDY ADC ready flag 0 1 oneToClear ADRDYR read NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 ADRDYW write Clear Clear ADC is ready to start conversion flag 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE ADC group injected contexts queue overflow interrupt 10 1 JQOVFIE Disabled Injected context queue overflow interrupt disabled 0 Enabled Injected context queue overflow interrupt enabled 1 3 0x1 1-3 AWD%sIE Analog watchdog %s interrupt enable 7 1 AWD1IE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 JEOSIE ADC group injected end of sequence conversions interrupt 6 1 JEOSIE Disabled End of injected sequence interrupt disabled 0 Enabled End of injected sequence interrupt enabled 1 JEOCIE ADC group injected end of unitary conversion interrupt 5 1 JEOCIE Disabled End of injected conversion interrupt disabled 0 Enabled End of injected conversion interrupt enabled 1 OVRIE ADC group regular overrun interrupt 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled 1 EOSIE ADC group regular end of sequence conversions interrupt 3 1 EOSIE Disabled End of regular sequence interrupt disabled 0 Enabled End of regular sequence interrupt enabled 1 EOCIE ADC group regular end of unitary conversion interrupt 2 1 EOCIE Disabled End of regular conversion interrupt disabled 0 Enabled End of regular conversion interrupt enabled 1 EOSMPIE ADC group regular end of sampling interrupt 1 1 EOSMPIE Disabled End of regular conversion sampling phase interrupt disabled 0 Enabled End of regular conversion sampling phase interrupt enabled 1 ADRDYIE ADC ready interrupt 0 1 ADRDYIE Disabled ADC ready interrupt disabled 0 Enabled ADC ready interrupt enabled 1 CR CR ADC control register 0x8 0x20 read-write 0x00000000 ADCAL ADC calibration 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 ADCALDIF ADC differential mode for calibration 30 1 ADCALDIF SingleEnded Calibration for single-ended mode 0 Differential Calibration for differential mode 1 DEEPPWD ADC deep power down enable 29 1 DEEPPWD PowerUp ADC not in deep power down 0 PowerDown ADC in deep power down 1 ADVREGEN ADC voltage regulator enable 28 1 ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 6 0x1 1-6 LINCALRDYW%s Linearity calibration ready Word %s 22 1 LINCALRDYW1 Reset LINCALFACT Word Read 0 Set LINCALFACT Word Write 1 ADCALLIN Linearity calibration 16 1 ADCALLIN NoLinearity ADC calibration without linearaity calibration 0 Linearity ADC calibration with linearaity calibration 1 BOOST Boost mode control 8 1 ADSTP ADC group regular conversion stop 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 JADSTP ADC group injected conversion stop 5 1 oneToSet read write ADSTART ADC group regular conversion start 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 JADSTART ADC group injected conversion start 3 1 oneToSet read write ADDIS ADC disable 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADEN ADC enable 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 CFGR CFGR ADC configuration register 1 0xC 0x20 read-write 0x00000000 JQDIS ADC group injected contexts queue disable 31 1 JQDIS Enabled Injected Queue enabled 0 Disabled Injected Queue disabled 1 AWD1CH ADC analog watchdog 1 monitored channel selection 26 5 0 19 JAUTO ADC group injected automatic trigger mode 25 1 JAUTO Disabled Automatic injected group conversion disabled 0 Enabled Automatic injected group conversion enabled 1 JAWD1EN ADC analog watchdog 1 enable on scope ADC group injected 24 1 JAWD1EN Disabled Analog watchdog 1 disabled on injected channels 0 Enabled Analog watchdog 1 enabled on injected channels 1 AWD1EN ADC analog watchdog 1 enable on scope ADC group regular 23 1 AWD1EN Disabled Analog watchdog 1 disabled on regular channels 0 Enabled Analog watchdog 1 enabled on regular channels 1 AWD1SGL ADC analog watchdog 1 monitoring a single channel or all channels 22 1 AWD1SGL All Analog watchdog 1 enabled on all channels 0 Single Analog watchdog 1 enabled on single channel selected in AWD1CH 1 JQM ADC group injected contexts queue mode 21 1 JQM Mode0 JSQR Mode 0: Queue maintains the last written configuration into JSQR 0 Mode1 JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence 1 JDISCEN ADC group injected sequencer discontinuous mode 20 1 JDISCEN Disabled Discontinuous mode on injected channels disabled 0 Enabled Discontinuous mode on injected channels enabled 1 DISCNUM ADC group regular sequencer discontinuous number of ranks 17 3 0 7 DISCEN ADC group regular sequencer discontinuous mode 16 1 DISCEN Disabled Discontinuous mode on regular channels disabled 0 Enabled Discontinuous mode on regular channels enabled 1 AUTDLY ADC low power auto wait 14 1 AUTDLY Off Auto delayed conversion mode off 0 On Auto delayed conversion mode on 1 CONT ADC group regular continuous conversion mode 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD ADC group regular overrun configuration 12 1 OVRMOD Preserve Preserve DR register when an overrun is detected 0 Overwrite Overwrite DR register when an overrun is detected 1 EXTEN ADC group regular external trigger polarity 10 2 EXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 EXTSEL ADC group regular external trigger source 5 5 EXTSEL TIM1_CC1 Timer 1 CC1 event 0 TIM1_CC2 Timer 1 CC2 event 1 TIM1_CC3 Timer 1 CC3 event 2 TIM2_CC2 Timer 2 CC2 event 3 TIM3_TRGO Timer 3 TRGO event 4 TIM4_CC4 Timer 4 CC4 event 5 EXTI11 EXTI line 11 6 TIM8_TRGO Timer 8 TRGO event 7 TIM8_TRGO2 Timer 8 TRGO2 event 8 TIM1_TRGO Timer 1 TRGO event 9 TIM1_TRGO2 Timer 1 TRGO2 event 10 TIM2_TRGO Timer 2 TRGO event 11 TIM4_TRGO Timer 4 TRGO event 12 TIM6_TRGO Timer 6 TRGO event 13 TIM15_TRGO Timer 15 TRGO event 14 TIM3_CC4 Timer 3 CC4 event 15 HRTIM1_ADCTRG1 HRTIM1_ADCTRG1 event 16 HRTIM1_ADCTRG3 HRTIM1_ADCTRG3 event 17 LPTIM1_OUT LPTIM1_OUT event 18 LPTIM2_OUT LPTIM2_OUT event 19 LPTIM3_OUT LPTIM3_OUT event 20 RES ADC data resolution 2 2 DMNGT ADC DMA transfer enable 0 2 DMNGT DR Store output data in DR only 0 DMA_OneShot DMA One Shot Mode selected 1 DFSDM DFSDM mode selected 2 DMA_Circular DMA Circular Mode selected 3 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 ROVSE ADC oversampler enable on scope ADC group regular 0 1 ROVSE Disabled Regular oversampling disabled 0 Enabled Regular oversampling enabled 1 JOVSE ADC oversampler enable on scope ADC group injected 1 1 JOVSE Disabled Injected oversampling disabled 0 Enabled Injected oversampling enabled 1 OVSS ADC oversampling shift 5 4 0 11 TROVS ADC oversampling discontinuous mode (triggered mode) for ADC group regular 9 1 TROVS Automatic All oversampled conversions for a channel are run following a trigger 0 Triggered Each oversampled conversion for a channel needs a new trigger 1 ROVSM Regular Oversampling mode 10 1 ROVSM Continued Oversampling is temporary stopped and continued after injection sequence 0 Resumed Oversampling is aborted and resumed from start after injection sequence 1 4 0x1 1-4 RSHIFT%s Right-shift data after Offset %s correction 11 1 RSHIFT1 Disabled Right-shifting disabled 0 Enabled Data is right-shifted 1-bit 1 OSVR Oversampling ratio 16 10 0 1023 LSHIFT Left shift factor 28 4 0 15 SMPR1 SMPR1 ADC sampling time register 1 0x14 0x20 read-write 0x00000000 10 0x3 0-9 SMP%s Channel %s sample time selection 0 3 read-write SMP0 Cycles1_5 1.5 ADC clock cycles 0 Cycles2_5 2.5 ADC clock cycles 1 Cycles8_5 8.5 ADC clock cycles 2 Cycles16_5 16.5 ADC clock cycles 3 Cycles32_5 32.5 ADC clock cycles 4 Cycles64_5 64.5 ADC clock cycles 5 Cycles387_5 387.5 ADC clock cycles 6 Cycles810_5 810.5 ADC clock cycles 7 SMPR2 SMPR2 ADC sampling time register 2 0x18 0x20 read-write 0x00000000 10 0x3 10-19 SMP%s Channel %s sample time selection 0 3 LTR1 LTR1 ADC analog watchdog 1 threshold register 0x20 0x20 read-write 0x0FFF0000 LTR1 ADC analog watchdog 1 threshold low 0 26 0 67108863 HTR1 LHTR1 ADC analog watchdog 2 threshold register 0x24 0x20 read-write 0x0FFF0000 HTR1 ADC analog watchdog 2 threshold low 0 26 0 67108863 SQR1 SQR1 ADC group regular sequencer ranks register 1 0x30 0x20 read-write 0x00000000 4 0x6 1-4 SQ%s %s conversion in regular sequence 6 5 0 19 L L3 0 4 0 15 SQR2 SQR2 ADC group regular sequencer ranks register 2 0x34 0x20 read-write 0x00000000 5 0x6 5-9 SQ%s %s conversion in regular sequence 0 5 SQR3 SQR3 ADC group regular sequencer ranks register 3 0x38 0x20 read-write 0x00000000 5 0x6 10-14 SQ%s %s conversion in regular sequence 0 5 SQR4 SQR4 ADC group regular sequencer ranks register 4 0x3C 0x20 read-write 0x00000000 2 0x6 15-16 SQ%s %s conversion in regular sequence 0 5 DR DR ADC group regular conversion data register 0x40 0x20 read-only 0x00000000 RDATA ADC group regular conversion data 0 16 JSQR JSQR ADC group injected sequencer register 0x4C 0x20 read-write 0x00000000 4 0x6 1-4 JSQ%s %s conversion in injected sequence 9 5 0 19 JEXTEN ADC group injected external trigger polarity 7 2 JEXTEN Disabled Trigger detection disabled 0 RisingEdge Trigger detection on the rising edge 1 FallingEdge Trigger detection on the falling edge 2 BothEdges Trigger detection on both the rising and falling edges 3 JEXTSEL ADC group injected external trigger source 2 5 JEXTSEL TIM1_TRGO Timer 1 TRGO event 0 TIM1_CC4 Timer 1 CC4 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CC1 Timer 2 CC1 event 3 TIM3_CC4 Timer 3 CC4 event 4 TIM4_TRGO Timer 4 TRGO event 5 EXTI15 EXTI line 15 6 TIM8_CC4 Timer 8 CC4 event 7 TIM1_TRGO2 Timer 1 TRGO2 event 8 TIM8_TRGO Timer 8 TRGO event 9 TIM8_TRGO2 Timer 8 TRGO2 event 10 TIM3_CC3 Timer 3 CC3 event 11 TIM3_TRGO Timer 3 TRGO event 12 TIM3_CC1 Timer 3 CC1 event 13 TIM6_TRGO Timer 6 TRGO event 14 TIM15_TRGO Timer 15 TRGO event 15 HRTIM1_ADCTRG2 HRTIM1_ADCTRG2 event 16 HRTIM1_ADCTRG4 HRTIM1_ADCTRG4 event 17 LPTIM1_OUT LPTIM1_OUT event 18 LPTIM2_OUT LPTIM2_OUT event 19 LPTIM3_OUT LPTIM3_OUT event 20 JL ADC group injected sequencer scan length 0 2 0 3 4 0x4 1-4 OFR%s OFR%s ADC offset number %s register 0x60 0x20 read-write 0x00000000 SSATE Signed saturation enable 31 1 SSATE Disabled Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format) 0 Enabled Offset is subtracted and result is saturated to maintain result size 1 OFFSET_CH Channel selection for the data offset X 26 5 0 31 OFFSET Data offset X for the channel programmed into bits OFFSET_CH 0 26 0 67108863 4 0x4 1-4 JDR%s JDR%s ADC group injected sequencer rank %s register 0x80 0x20 read-only 0x00000000 JDATA Injected data 0 32 AWD2CR AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 read-write 0x00000000 20 0x1 0-19 AWD2CH%s ADC analog watchdog 2 monitored channel selection 0 1 AWD2CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 AWD3CR AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 read-write 0x00000000 20 0x1 0-19 AWD3CH%s ADC analog watchdog 3 monitored channel selection 1 1 AWD3CH0 NotMonitored Input channel not monitored by AWDx 0 Monitored Input channel monitored by AWDx 1 DIFSEL DIFSEL ADC channel differential or single-ended mode selection register 0xC0 0x20 read-write 0x00000000 20 0x1 0-19 DIFSEL%s Differential mode for channel %s 0 1 DIFSEL0 SingleEnded Input channel is configured in single-ended mode 0 Differential Input channel is configured in differential mode 1 CALFACT CALFACT ADC calibration factors register 0xC4 0x20 read-write 0x00000000 CALFACT_D ADC calibration factor in differential mode 16 11 0 2047 CALFACT_S ADC calibration factor in single-ended mode 0 11 0 2047 CCR CCR ADC common control register CR 0x8 0x20 read-write 0x00000000 CKMODE ADC clock mode 16 2 PRESC ADC prescaler 18 4 VREFEN VREFINT enable 22 1 VSENSEEN Temperature sensor enable 23 1 VBATEN VBAT enable 24 1 PCSEL PCSEL ADC pre channel selection register 0x1C 0x20 read-write 0x00000000 PCSEL Channel x (VINP[i]) pre selection 0 20 PCSEL NotPreselected Input channel x is not pre-selected 0 Preselected Pre-select input channel x 1 LTR2 LTR2 ADC watchdog lower threshold register 2 0xB0 0x20 read-write 0x00000000 LTR2 Analog watchdog 2 lower threshold 0 26 0 67108863 HTR2 HTR2 ADC watchdog higher threshold register 2 0xB4 0x20 read-write 0x00000000 HTR2 Analog watchdog 2 higher threshold 0 26 0 67108863 LTR3 LTR3 ADC watchdog lower threshold register 3 0xB8 0x20 read-write 0x00000000 LTR3 Analog watchdog 3 lower threshold 0 26 0 67108863 HTR3 HTR3 ADC watchdog higher threshold register 3 0xBC 0x20 read-write 0x00000000 HTR3 Analog watchdog 3 higher threshold 0 26 0 67108863 CALFACT2 CALFACT2 ADC Calibration Factor register 2 0xC8 0x20 read-write 0x00000000 LINCALFACT Linearity Calibration Factor 0 30 0 1073741823 ADC1 0x40022000 ADC1_2 ADC1 and ADC2 18 ADC2 0x40022100 ADC3_Common Analog-to-Digital Converter ADC 0x58026300 0x0 0x11 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADRDY_MST Master ADC ready 0 1 ADRDY_MST NotReady ADC is not ready to start conversion 0 Ready ADC is ready to start conversion 1 EOSMP_MST End of Sampling phase flag of the master ADC 1 1 EOSMP_MST NotEnded End of sampling phase no yet reached 0 Ended End of sampling phase reached 1 EOC_MST End of regular conversion of the master ADC 2 1 EOC_MST NotComplete Regular conversion is not complete 0 Complete Regular conversion complete 1 EOS_MST End of regular sequence flag of the master ADC 3 1 EOS_MST NotComplete Regular sequence is not complete 0 Complete Regular sequence complete 1 OVR_MST Overrun flag of the master ADC 4 1 OVR_MST NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 JEOC_MST End of injected conversion flag of the master ADC 5 1 JEOC_MST NotComplete Injected conversion is not complete 0 Complete Injected conversion complete 1 JEOS_MST End of injected sequence flag of the master ADC 6 1 JEOS_MST NotComplete Injected sequence is not complete 0 Complete Injected sequence complete 1 AWD1_MST Analog watchdog 1 flag of the master ADC 7 1 AWD1_MST NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWD2_MST Analog watchdog 2 flag of the master ADC 8 1 AWD3_MST Analog watchdog 3 flag of the master ADC 9 1 JQOVF_MST Injected Context Queue Overflow flag of the master ADC 10 1 JQOVF_MST NoOverflow No injected context queue overflow has occurred 0 Overflow Injected context queue overflow has occurred 1 ADRDY_SLV Slave ADC ready 16 1 EOSMP_SLV End of Sampling phase flag of the slave ADC 17 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 OVR_SLV Overrun flag of the slave ADC 20 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 DUAL Dual ADC mode selection 0 5 DUAL Independent Independent mode 0 DualRJ Dual, combined regular simultaneous + injected simultaneous mode 1 DualRA Dual, combined regular simultaneous + alternate trigger mode 2 DualIJ Dual, combined interleaved mode + injected simultaneous mode 3 DualJ Dual, injected simultaneous mode only 5 DualR Dual, regular simultaneous mode only 6 DualI Dual, interleaved mode only 7 DualA Dual, alternate trigger mode only 9 DELAY Delay between 2 sampling phases 8 4 0 15 DAMDF Dual ADC Mode Data Format 14 2 DAMDF NoPack Without data packing, CDR/CDR2 not used 0 Format32to10 CDR formatted for 32-bit down to 10-bit resolution 2 Format8 CDR formatted for 8-bit resolution 3 CKMODE ADC clock mode 16 2 CKMODE Asynchronous Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock 0 SyncDiv1 Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck 1 SyncDiv2 Use AHB clock rcc_hclk3 divided by 2 2 SyncDiv4 Use AHB clock rcc_hclk3 divided by 4 3 PRESC ADC prescaler 18 4 PRESC Div1 adc_ker_ck_input not divided 0 Div2 adc_ker_ck_input divided by 2 1 Div4 adc_ker_ck_input divided by 4 2 Div6 adc_ker_ck_input divided by 6 3 Div8 adc_ker_ck_input divided by 8 4 Div10 adc_ker_ck_input divided by 10 5 Div12 adc_ker_ck_input divided by 12 6 Div16 adc_ker_ck_input divided by 16 7 Div32 adc_ker_ck_input divided by 32 8 Div64 adc_ker_ck_input divided by 64 9 Div128 adc_ker_ck_input divided by 128 10 Div256 adc_ker_ck_input divided by 256 11 VREFEN VREFINT enable 22 1 VREFEN Disabled V_REFINT channel disabled 0 Enabled V_REFINT channel enabled 1 VSENSEEN Temperature sensor enable 23 1 VSENSEEN Disabled The selected ADC channel disabled 0 Enabled The selected ADC channel enabled 1 VBATEN VBAT enable 24 1 CDR CDR ADC common regular data register for dual and triple modes 0xC 0x20 read-only 0x00000000 RDATA_SLV Regular data of the slave ADC 16 16 RDATA_MST Regular data of the master ADC 0 16 ADC12_Common 0x40022300 CRC Cryptographic processor CRC 0x58024C00 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent Data register 0x4 0x20 read-write 0x00000000 IDR Independent Data register 0 32 0 4294967295 CR CR Control register 0x8 0x20 0x00000000 RESET RESET bit 0 1 write-only RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL CRC polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 RCC Reset and clock control RCC 0x58024400 0x0 0x400 registers RCC RCC global interrupt 5 CR CR clock control register 0x0 0x20 read-write 0x00000083 HSION Internal high-speed clock enable 0 1 HSION Off Clock Off 0 On Clock On 1 HSIKERON High Speed Internal clock enable in Stop mode 1 1 HSIRDY HSI clock ready flag 2 1 HSIRDYR read NotReady Clock not ready 0 Ready Clock ready 1 HSIDIV HSI clock divider 3 2 HSIDIV Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 HSIDIVF HSI divider flag 5 1 HSIDIVFR read NotPropagated New HSIDIV ratio has not yet propagated to hsi_ck 0 Propagated HSIDIV ratio has propagated to hsi_ck 1 CSION CSI clock enable 7 1 CSIRDY CSI clock ready flag 8 1 CSIKERON CSI clock enable in Stop mode 9 1 HSI48ON RC48 clock enable 12 1 HSI48RDY RC48 clock ready flag 13 1 D1CKRDY D1 domain clocks ready flag 14 1 D2CKRDY D2 domain clocks ready flag 15 1 HSEON HSE clock enable 16 1 HSERDY HSE clock ready flag 17 1 HSEBYP HSE clock bypass 18 1 HSEBYP NotBypassed HSE crystal oscillator not bypassed 0 Bypassed HSE crystal oscillator bypassed with external clock 1 HSECSSON HSE Clock Security System enable 19 1 PLL1ON PLL1 enable 24 1 PLL1RDY PLL1 clock ready flag 25 1 PLL2ON PLL2 enable 26 1 PLL2RDY PLL2 clock ready flag 27 1 PLL3ON PLL3 enable 28 1 PLL3RDY PLL3 clock ready flag 29 1 ICSCR ICSCR RCC Internal Clock Source Calibration Register 0x4 0x20 0x40000000 HSICAL HSI clock calibration 0 12 read-only HSITRIM HSI clock trimming 12 6 read-write 0 63 CSICAL CSI clock calibration 18 8 read-only CSITRIM CSI clock trimming 26 5 read-write 0 31 HSICFGR HSICFGR RCC HSI configuration register ICSCR 0x4 0x20 0x40000000 HSICAL HSI clock calibration 0 12 read-only HSITRIM HSI clock trimming 24 7 read-write CRRCR CRRCR RCC Clock Recovery RC Register 0x8 0x20 read-only 0x00000000 HSI48CAL Internal RC 48 MHz clock calibration 0 10 CFGR CFGR RCC Clock Configuration Register 0x10 0x20 read-write 0x00000000 SW System clock switch 0 3 SW HSI HSI selected as system clock 0 CSI CSI selected as system clock 1 HSE HSE selected as system clock 2 PLL1 PLL1 selected as system clock 3 SWS System clock switch status 3 3 SWSR read HSI HSI oscillator used as system clock 0 CSI CSI oscillator used as system clock 1 HSE HSE oscillator used as system clock 2 PLL1 PLL1 used as system clock 3 STOPWUCK System clock selection after a wake up from system Stop 6 1 STOPWUCK HSI HSI selected as wake up clock from system Stop 0 CSI CSI selected as wake up clock from system Stop 1 STOPKERWUCK Kernel clock selection after a wake up from system Stop 7 1 RTCPRE HSE division factor for RTC clock 8 6 0 63 HRTIMSEL High Resolution Timer clock prescaler selection 14 1 HRTIMSEL TIMY_KER The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) 0 C_CK The HRTIM prescaler clock source is the CPU clock (c_ck) 1 TIMPRE Timers clocks prescaler selection 15 1 TIMPRE DefaultX2 Timer kernel clock equal to 2x pclk by default 0 DefaultX4 Timer kernel clock equal to 4x pclk by default 1 MCO1PRE MCO1 prescaler 18 4 0 15 MCO1 Micro-controller clock output 1 22 3 MCO1 HSI HSI selected for micro-controller clock output 0 LSE LSE selected for micro-controller clock output 1 HSE HSE selected for micro-controller clock output 2 PLL1_Q pll1_q selected for micro-controller clock output 3 HSI48 HSI48 selected for micro-controller clock output 4 MCO2PRE MCO2 prescaler 25 4 0 15 MCO2 Micro-controller clock output 2 29 3 MCO2 SYSCLK System clock selected for micro-controller clock output 0 PLL2_P pll2_p selected for micro-controller clock output 1 HSE HSE selected for micro-controller clock output 2 PLL1_P pll1_p selected for micro-controller clock output 3 CSI CSI selected for micro-controller clock output 4 LSI LSI selected for micro-controller clock output 5 D1CFGR D1CFGR RCC Domain 1 Clock Configuration Register 0x18 0x20 read-write 0x00000000 HPRE D1 domain AHB prescaler 0 4 HPRE Div2 sys_ck divided by 2 8 Div4 sys_ck divided by 4 9 Div8 sys_ck divided by 8 10 Div16 sys_ck divided by 16 11 Div64 sys_ck divided by 64 12 Div128 sys_ck divided by 128 13 Div256 sys_ck divided by 256 14 Div512 sys_ck divided by 512 15 Div1 sys_ck not divided true D1PPRE D1 domain APB3 prescaler 4 3 D1PPRE Div2 rcc_hclk divided by 2 4 Div4 rcc_hclk divided by 4 5 Div8 rcc_hclk divided by 8 6 Div16 rcc_hclk divided by 16 7 Div1 rcc_hclk not divided true D1CPRE D1 domain Core prescaler 8 4 D2CFGR D2CFGR RCC Domain 2 Clock Configuration Register 0x1C 0x20 read-write 0x00000000 D2PPRE1 D2 domain APB1 prescaler 4 3 D2PPRE1 Div2 rcc_hclk divided by 2 4 Div4 rcc_hclk divided by 4 5 Div8 rcc_hclk divided by 8 6 Div16 rcc_hclk divided by 16 7 Div1 rcc_hclk not divided true D2PPRE2 D2 domain APB2 prescaler 8 3 D3CFGR D3CFGR RCC Domain 3 Clock Configuration Register 0x20 0x20 read-write 0x00000000 D3PPRE D3 domain APB4 prescaler 4 3 D3PPRE Div2 rcc_hclk divided by 2 4 Div4 rcc_hclk divided by 4 5 Div8 rcc_hclk divided by 8 6 Div16 rcc_hclk divided by 16 7 Div1 rcc_hclk not divided true PLLCKSELR PLLCKSELR RCC PLLs Clock Source Selection Register 0x28 0x20 read-write 0x02020200 PLLSRC DIVMx and PLLs clock source selection 0 2 PLLSRC HSI HSI selected as PLL clock 0 CSI CSI selected as PLL clock 1 HSE HSE selected as PLL clock 2 None No clock sent to DIVMx dividers and PLLs 3 DIVM1 Prescaler for PLL1 4 6 0 63 DIVM2 Prescaler for PLL2 12 6 0 63 DIVM3 Prescaler for PLL3 20 6 0 63 PLLCFGR PLLCFGR RCC PLLs Configuration Register 0x2C 0x20 read-write 0x01FF0000 PLL1FRACEN PLL1 fractional latch enable 0 1 PLL1FRACEN Reset Reset latch to tranfer FRACN to the Sigma-Delta modulator 0 Set Set latch to tranfer FRACN to the Sigma-Delta modulator 1 PLL1VCOSEL PLL1 VCO selection 1 1 PLL1VCOSEL WideVCO VCO frequency range 192 to 836 MHz 0 MediumVCO VCO frequency range 150 to 420 MHz 1 PLL1RGE PLL1 input frequency range 2 2 PLL1RGE Range1 Frequency is between 1 and 2 MHz 0 Range2 Frequency is between 2 and 4 MHz 1 Range4 Frequency is between 4 and 8 MHz 2 Range8 Frequency is between 8 and 16 MHz 3 PLL2FRACEN PLL2 fractional latch enable 4 1 PLL2VCOSEL PLL2 VCO selection 5 1 PLL2RGE PLL2 input frequency range 6 2 PLL3FRACEN PLL3 fractional latch enable 8 1 PLL3VCOSEL PLL3 VCO selection 9 1 PLL3RGE PLL3 input frequency range 10 2 DIVP1EN PLL1 DIVP divider output enable 16 1 DIVP1EN Disabled Clock ouput is disabled 0 Enabled Clock output is enabled 1 DIVQ1EN PLL1 DIVQ divider output enable 17 1 DIVR1EN PLL1 DIVR divider output enable 18 1 DIVP2EN PLL2 DIVP divider output enable 19 1 DIVQ2EN PLL2 DIVQ divider output enable 20 1 DIVR2EN PLL2 DIVR divider output enable 21 1 DIVP3EN PLL3 DIVP divider output enable 22 1 DIVQ3EN PLL3 DIVQ divider output enable 23 1 DIVR3EN PLL3 DIVR divider output enable 24 1 PLL1DIVR PLL1DIVR RCC PLL1 Dividers Configuration Register 0x30 0x20 read-write 0x01010280 DIVN1 Multiplication factor for PLL1 VCO 0 9 3 511 DIVP1 PLL1 DIVP division factor 9 7 DIVP1 Div1 pll_p_ck = vco_ck 0 Div2 pll_p_ck = vco_ck / 2 1 Div4 pll_p_ck = vco_ck / 4 3 Div6 pll_p_ck = vco_ck / 6 5 Div8 pll_p_ck = vco_ck / 8 7 Div10 pll_p_ck = vco_ck / 10 9 Div12 pll_p_ck = vco_ck / 12 11 Div14 pll_p_ck = vco_ck / 14 13 Div16 pll_p_ck = vco_ck / 16 15 Div18 pll_p_ck = vco_ck / 18 17 Div20 pll_p_ck = vco_ck / 20 19 Div22 pll_p_ck = vco_ck / 22 21 Div24 pll_p_ck = vco_ck / 24 23 Div26 pll_p_ck = vco_ck / 26 25 Div28 pll_p_ck = vco_ck / 28 27 Div30 pll_p_ck = vco_ck / 30 29 Div32 pll_p_ck = vco_ck / 32 31 Div34 pll_p_ck = vco_ck / 34 33 Div36 pll_p_ck = vco_ck / 36 35 Div38 pll_p_ck = vco_ck / 38 37 Div40 pll_p_ck = vco_ck / 40 39 Div42 pll_p_ck = vco_ck / 42 41 Div44 pll_p_ck = vco_ck / 44 43 Div46 pll_p_ck = vco_ck / 46 45 Div48 pll_p_ck = vco_ck / 48 47 Div50 pll_p_ck = vco_ck / 50 49 Div52 pll_p_ck = vco_ck / 52 51 Div54 pll_p_ck = vco_ck / 54 53 Div56 pll_p_ck = vco_ck / 56 55 Div58 pll_p_ck = vco_ck / 58 57 Div60 pll_p_ck = vco_ck / 60 59 Div62 pll_p_ck = vco_ck / 62 61 Div64 pll_p_ck = vco_ck / 64 63 Div66 pll_p_ck = vco_ck / 66 65 Div68 pll_p_ck = vco_ck / 68 67 Div70 pll_p_ck = vco_ck / 70 69 Div72 pll_p_ck = vco_ck / 72 71 Div74 pll_p_ck = vco_ck / 74 73 Div76 pll_p_ck = vco_ck / 76 75 Div78 pll_p_ck = vco_ck / 78 77 Div80 pll_p_ck = vco_ck / 80 79 Div82 pll_p_ck = vco_ck / 82 81 Div84 pll_p_ck = vco_ck / 84 83 Div86 pll_p_ck = vco_ck / 86 85 Div88 pll_p_ck = vco_ck / 88 87 Div90 pll_p_ck = vco_ck / 90 89 Div92 pll_p_ck = vco_ck / 92 91 Div94 pll_p_ck = vco_ck / 94 93 Div96 pll_p_ck = vco_ck / 96 95 Div98 pll_p_ck = vco_ck / 98 97 Div100 pll_p_ck = vco_ck / 100 99 Div102 pll_p_ck = vco_ck / 102 101 Div104 pll_p_ck = vco_ck / 104 103 Div106 pll_p_ck = vco_ck / 106 105 Div108 pll_p_ck = vco_ck / 108 107 Div110 pll_p_ck = vco_ck / 110 109 Div112 pll_p_ck = vco_ck / 112 111 Div114 pll_p_ck = vco_ck / 114 113 Div116 pll_p_ck = vco_ck / 116 115 Div118 pll_p_ck = vco_ck / 118 117 Div120 pll_p_ck = vco_ck / 120 119 Div122 pll_p_ck = vco_ck / 122 121 Div124 pll_p_ck = vco_ck / 124 123 Div126 pll_p_ck = vco_ck / 126 125 Div128 pll_p_ck = vco_ck / 128 127 DIVQ1 PLL1 DIVQ division factor 16 7 0 127 DIVR1 PLL1 DIVR division factor 24 7 0 127 PLL1FRACR PLL1FRACR RCC PLL1 Fractional Divider Register 0x34 0x20 read-write 0x00000000 FRACN1 Fractional part of the multiplication factor for PLL1 VCO 3 13 0 8191 PLL2DIVR PLL2DIVR RCC PLL2 Dividers Configuration Register 0x38 0x20 read-write 0x01010280 DIVN2 Multiplication factor for PLL1 VCO 0 9 3 511 DIVP2 PLL1 DIVP division factor 9 7 DIVQ2 PLL1 DIVQ division factor 16 7 0 127 DIVR2 PLL1 DIVR division factor 24 7 0 127 PLL2FRACR PLL2FRACR RCC PLL2 Fractional Divider Register 0x3C 0x20 read-write 0x00000000 FRACN2 Fractional part of the multiplication factor for PLL VCO 3 13 0 8191 PLL3DIVR PLL3DIVR RCC PLL3 Dividers Configuration Register 0x40 0x20 read-write 0x01010280 DIVN3 Multiplication factor for PLL1 VCO 0 9 3 511 DIVP3 PLL DIVP division factor 9 7 DIVQ3 PLL DIVQ division factor 16 7 0 127 DIVR3 PLL DIVR division factor 24 7 0 127 PLL3FRACR PLL3FRACR RCC PLL3 Fractional Divider Register 0x44 0x20 read-write 0x00000000 FRACN3 Fractional part of the multiplication factor for PLL3 VCO 3 13 0 8191 D1CCIPR D1CCIPR RCC Domain 1 Kernel Clock Configuration Register 0x4C 0x20 read-write 0x00000000 FMCSEL FMC kernel clock source selection 0 2 FMCSEL RCC_HCLK3 rcc_hclk3 selected as peripheral clock 0 PLL1_Q pll1_q selected as peripheral clock 1 PLL2_R pll2_r selected as peripheral clock 2 PER PER selected as peripheral clock 3 QSPISEL QUADSPI kernel clock source selection 4 2 SDMMCSEL SDMMC kernel clock source selection 16 1 SDMMCSEL PLL1_Q pll1_q selected as peripheral clock 0 PLL2_R pll2_r selected as peripheral clock 1 CKPERSEL per_ck clock source selection 28 2 CKPERSEL HSI HSI selected as peripheral clock 0 CSI CSI selected as peripheral clock 1 HSE HSE selected as peripheral clock 2 D2CCIP1R D2CCIP1R RCC Domain 2 Kernel Clock Configuration Register 0x50 0x20 read-write 0x00000000 SAI1SEL SAI1 and DFSDM1 kernel Aclk clock source selection 0 3 SAI1SEL PLL1_Q pll1_q selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_P pll3_p selected as peripheral clock 2 I2S_CKIN I2S_CKIN selected as peripheral clock 3 PER PER selected as peripheral clock 4 SAI23SEL SAI2 and SAI3 kernel clock source selection 6 3 SPI123SEL SPI/I2S1,2 and 3 kernel clock source selection 12 3 SPI45SEL SPI4 and 5 kernel clock source selection 16 3 SPI45SEL APB APB clock selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 HSE HSE selected as peripheral clock 5 SPDIFSEL SPDIFRX kernel clock source selection 20 2 SPDIFSEL PLL1_Q pll1_q selected as peripheral clock 0 PLL2_R pll2_r selected as peripheral clock 1 PLL3_R pll3_r selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 DFSDM1SEL DFSDM1 kernel Clk clock source selection 24 1 DFSDM1SEL RCC_PCLK2 rcc_pclk2 selected as peripheral clock 0 SYS System clock selected as peripheral clock 1 FDCANSEL FDCAN kernel clock source selection 28 2 FDCANSEL HSE HSE selected as peripheral clock 0 PLL1_Q pll1_q selected as peripheral clock 1 PLL2_Q pll2_q selected as peripheral clock 2 SWPSEL SWPMI kernel clock source selection 31 1 SWPSEL PCLK pclk selected as peripheral clock 0 HSI_KER hsi_ker selected as peripheral clock 1 D2CCIP2R D2CCIP2R RCC Domain 2 Kernel Clock Configuration Register 0x54 0x20 read-write 0x00000000 USART234578SEL USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection 0 3 USART234578SEL RCC_PCLK1 rcc_pclk1 selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 LSE LSE selected as peripheral clock 5 USART16SEL USART1 and 6 kernel clock source selection 3 3 USART16SEL RCC_PCLK2 rcc_pclk2 selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 LSE LSE selected as peripheral clock 5 RNGSEL RNG kernel clock source selection 8 2 RNGSEL HSI48 HSI48 selected as peripheral clock 0 PLL1_Q pll1_q selected as peripheral clock 1 LSE LSE selected as peripheral clock 2 LSI LSI selected as peripheral clock 3 I2C123SEL I2C1,2,3 kernel clock source selection 12 2 I2C123SEL RCC_PCLK1 rcc_pclk1 selected as peripheral clock 0 PLL3_R pll3_r selected as peripheral clock 1 HSI_KER hsi_ker selected as peripheral clock 2 CSI_KER csi_ker selected as peripheral clock 3 USBSEL USBOTG 1 and 2 kernel clock source selection 20 2 USBSEL DISABLE Disable the kernel clock 0 PLL1_Q pll1_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI48 HSI48 selected as peripheral clock 3 CECSEL HDMI-CEC kernel clock source selection 22 2 CECSEL LSE LSE selected as peripheral clock 0 LSI LSI selected as peripheral clock 1 CSI_KER csi_ker selected as peripheral clock 2 LPTIM1SEL LPTIM1 kernel clock source selection 28 3 LPTIM1SEL RCC_PCLK1 rcc_pclk1 selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_R pll3_r selected as peripheral clock 2 LSE LSE selected as peripheral clock 3 LSI LSI selected as peripheral clock 4 PER PER selected as peripheral clock 5 D3CCIPR D3CCIPR RCC Domain 3 Kernel Clock Configuration Register 0x58 0x20 read-write 0x00000000 LPUART1SEL LPUART1 kernel clock source selection 0 3 LPUART1SEL RCC_PCLK_D3 rcc_pclk_d3 selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 LSE LSE selected as peripheral clock 5 I2C4SEL I2C4 kernel clock source selection 8 2 I2C4SEL RCC_PCLK4 rcc_pclk4 selected as peripheral clock 0 PLL3_R pll3_r selected as peripheral clock 1 HSI_KER hsi_ker selected as peripheral clock 2 CSI_KER csi_ker selected as peripheral clock 3 LPTIM2SEL LPTIM2 kernel clock source selection 10 3 LPTIM2SEL RCC_PCLK4 rcc_pclk4 selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_R pll3_r selected as peripheral clock 2 LSE LSE selected as peripheral clock 3 LSI LSI selected as peripheral clock 4 PER PER selected as peripheral clock 5 LPTIM345SEL LPTIM3,4,5 kernel clock source selection 13 3 ADCSEL SAR ADC kernel clock source selection 16 2 ADCSEL PLL2_P pll2_p selected as peripheral clock 0 PLL3_R pll3_r selected as peripheral clock 1 PER PER selected as peripheral clock 2 SAI4ASEL Sub-Block A of SAI4 kernel clock source selection 21 3 SAI4ASEL PLL1_Q pll1_q selected as peripheral clock 0 PLL2_P pll2_p selected as peripheral clock 1 PLL3_P pll3_p selected as peripheral clock 2 I2S_CKIN i2s_ckin selected as peripheral clock 3 PER PER selected as peripheral clock 4 SAI4BSEL Sub-Block B of SAI4 kernel clock source selection 24 3 SPI6SEL SPI6 kernel clock source selection 28 3 SPI6SEL RCC_PCLK4 rcc_pclk4 selected as peripheral clock 0 PLL2_Q pll2_q selected as peripheral clock 1 PLL3_Q pll3_q selected as peripheral clock 2 HSI_KER hsi_ker selected as peripheral clock 3 CSI_KER csi_ker selected as peripheral clock 4 HSE HSE selected as peripheral clock 5 CIER CIER RCC Clock Source Interrupt Enable Register 0x60 0x20 read-write 0x00000000 LSIRDYIE LSI ready Interrupt Enable 0 1 LSIRDYIE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 LSERDYIE LSE ready Interrupt Enable 1 1 HSIRDYIE HSI ready Interrupt Enable 2 1 HSERDYIE HSE ready Interrupt Enable 3 1 CSIRDYIE CSI ready Interrupt Enable 4 1 HSI48RDYIE RC48 ready Interrupt Enable 5 1 PLL1RDYIE PLL1 ready Interrupt Enable 6 1 PLL2RDYIE PLL2 ready Interrupt Enable 7 1 PLL3RDYIE PLL3 ready Interrupt Enable 8 1 LSECSSIE LSE clock security system Interrupt Enable 9 1 CIFR CIFR RCC Clock Source Interrupt Flag Register 0x64 0x20 read-only 0x00000000 LSIRDYF LSI ready Interrupt Flag 0 1 LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 LSERDYF LSE ready Interrupt Flag 1 1 HSIRDYF HSI ready Interrupt Flag 2 1 HSERDYF HSE ready Interrupt Flag 3 1 CSIRDY CSI ready Interrupt Flag 4 1 HSI48RDYF RC48 ready Interrupt Flag 5 1 PLL1RDYF PLL1 ready Interrupt Flag 6 1 PLL2RDYF PLL2 ready Interrupt Flag 7 1 PLL3RDYF PLL3 ready Interrupt Flag 8 1 LSECSSF LSE clock security system Interrupt Flag 9 1 HSECSSF HSE clock security system Interrupt Flag 10 1 CICR CICR RCC Clock Source Interrupt Clear Register 0x68 0x20 read-write 0x00000000 LSIRDYC LSI ready Interrupt Clear 0 1 LSIRDYC Clear Clear interrupt flag 1 LSERDYC LSE ready Interrupt Clear 1 1 HSIRDYC HSI ready Interrupt Clear 2 1 HSERDYC HSE ready Interrupt Clear 3 1 HSE_ready_Interrupt_Clear CSI ready Interrupt Clear 4 1 HSI48RDYC RC48 ready Interrupt Clear 5 1 PLL1RDYC PLL1 ready Interrupt Clear 6 1 PLL2RDYC PLL2 ready Interrupt Clear 7 1 PLL3RDYC PLL3 ready Interrupt Clear 8 1 LSECSSC LSE clock security system Interrupt Clear 9 1 HSECSSC HSE clock security system Interrupt Clear 10 1 BDCR BDCR RCC Backup Domain Control Register 0x70 0x20 read-write 0x00000000 LSEON LSE oscillator enabled 0 1 LSEON Off LSE oscillator Off 0 On LSE oscillator On 1 LSERDY LSE oscillator ready 1 1 LSERDYR read NotReady LSE oscillator not ready 0 Ready LSE oscillator ready 1 LSEBYP LSE oscillator bypass 2 1 LSEBYP NotBypassed LSE crystal oscillator not bypassed 0 Bypassed LSE crystal oscillator bypassed with external clock 1 LSEDRV LSE oscillator driving capability 3 2 LSEDRV Lowest Lowest LSE oscillator driving capability 0 MediumLow Medium low LSE oscillator driving capability 1 MediumHigh Medium high LSE oscillator driving capability 2 Highest Highest LSE oscillator driving capability 3 LSECSSON LSE clock security system enable 5 1 LSECSSON SecurityOff Clock security system on 32 kHz oscillator off 0 SecurityOn Clock security system on 32 kHz oscillator on 1 LSECSSD LSE clock security system failure detection 6 1 LSECSSDR read NoFailure No failure detected on 32 kHz oscillator 0 Failure Failure detected on 32 kHz oscillator 1 RTCSEL RTC clock source selection 8 2 RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a prescaler used as RTC clock 3 RTCEN RTC clock enable 15 1 RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 BDRST VSwitch domain software reset 16 1 BDRST NotActivated Reset not activated 0 Reset Resets the entire VSW domain 1 CSR CSR RCC Clock Control and Status Register 0x74 0x20 read-write 0x00000000 LSION LSI oscillator enable 0 1 LSION Off LSI oscillator Off 0 On LSI oscillator On 1 LSIRDY LSI oscillator ready 1 1 LSIRDYR read NotReady LSI oscillator not ready 0 Ready LSI oscillator ready 1 AHB3RSTR AHB3RSTR RCC AHB3 Reset Register 0x7C 0x20 read-write 0x00000000 MDMARST MDMA block reset 0 1 MDMARST Reset Reset the selected module 1 DMA2DRST DMA2D block reset 4 1 JPGDECRST JPGDEC block reset 5 1 FMCRST FMC block reset 12 1 QSPIRST QUADSPI and QUADSPI delay block reset 14 1 SDMMC1RST SDMMC1 and SDMMC1 delay block reset 16 1 CPURST CPU reset 31 1 AHB1RSTR AHB1RSTR RCC AHB1 Peripheral Reset Register 0x80 0x20 read-write 0x00000000 DMA1RST DMA1 block reset 0 1 DMA1RST Reset Reset the selected module 1 DMA2RST DMA2 block reset 1 1 ADC12RST ADC1&2 block reset 5 1 ETH1MACRST ETH1MAC block reset 15 1 USB1OTGRST USB1OTG block reset 25 1 USB2OTGRST USB2OTG block reset 27 1 AHB2RSTR AHB2RSTR RCC AHB2 Peripheral Reset Register 0x84 0x20 read-write 0x00000000 CAMITFRST CAMITF block reset 0 1 CAMITFRST Reset Reset the selected module 1 CRYPTRST Cryptography block reset 4 1 HASHRST Hash block reset 5 1 RNGRST Random Number Generator block reset 6 1 SDMMC2RST SDMMC2 and SDMMC2 Delay block reset 9 1 AHB4RSTR AHB4RSTR RCC AHB4 Peripheral Reset Register 0x88 0x20 read-write 0x00000000 GPIOARST GPIO block reset 0 1 GPIOARST Reset Reset the selected module 1 GPIOBRST GPIO block reset 1 1 GPIOCRST GPIO block reset 2 1 GPIODRST GPIO block reset 3 1 GPIOERST GPIO block reset 4 1 GPIOFRST GPIO block reset 5 1 GPIOGRST GPIO block reset 6 1 GPIOHRST GPIO block reset 7 1 GPIOIRST GPIO block reset 8 1 GPIOJRST GPIO block reset 9 1 GPIOKRST GPIO block reset 10 1 CRCRST CRC block reset 19 1 BDMARST BDMA block reset 21 1 ADC3RST ADC3 block reset 24 1 HSEMRST HSEM block reset 25 1 APB3RSTR APB3RSTR RCC APB3 Peripheral Reset Register 0x8C 0x20 read-write 0x00000000 LTDCRST LTDC block reset 3 1 LTDCRST Reset Reset the selected module 1 APB1LRSTR APB1LRSTR RCC APB1 Peripheral Reset Register 0x90 0x20 read-write 0x00000000 TIM2RST TIM block reset 0 1 TIM2RST Reset Reset the selected module 1 TIM3RST TIM block reset 1 1 TIM4RST TIM block reset 2 1 TIM5RST TIM block reset 3 1 TIM6RST TIM block reset 4 1 TIM7RST TIM block reset 5 1 TIM12RST TIM block reset 6 1 TIM13RST TIM block reset 7 1 TIM14RST TIM block reset 8 1 LPTIM1RST TIM block reset 9 1 SPI2RST SPI2 block reset 14 1 SPI3RST SPI3 block reset 15 1 SPDIFRXRST SPDIFRX block reset 16 1 USART2RST USART2 block reset 17 1 USART3RST USART3 block reset 18 1 UART4RST UART4 block reset 19 1 UART5RST UART5 block reset 20 1 I2C1RST I2C1 block reset 21 1 I2C2RST I2C2 block reset 22 1 I2C3RST I2C3 block reset 23 1 CECRST HDMI-CEC block reset 27 1 DAC12RST DAC1 and 2 Blocks Reset 29 1 UART7RST UART7 block reset 30 1 UART8RST UART8 block reset 31 1 APB1HRSTR APB1HRSTR RCC APB1 Peripheral Reset Register 0x94 0x20 read-write 0x00000000 CRSRST Clock Recovery System reset 1 1 CRSRST Reset Reset the selected module 1 SWPRST SWPMI block reset 2 1 OPAMPRST OPAMP block reset 4 1 MDIOSRST MDIOS block reset 5 1 FDCANRST FDCAN block reset 8 1 APB2RSTR APB2RSTR RCC APB2 Peripheral Reset Register 0x98 0x20 read-write 0x00000000 TIM1RST TIM1 block reset 0 1 TIM1RST Reset Reset the selected module 1 TIM8RST TIM8 block reset 1 1 USART1RST USART1 block reset 4 1 USART6RST USART6 block reset 5 1 SPI1RST SPI1 block reset 12 1 SPI4RST SPI4 block reset 13 1 TIM15RST TIM15 block reset 16 1 TIM16RST TIM16 block reset 17 1 TIM17RST TIM17 block reset 18 1 SPI5RST SPI5 block reset 20 1 SAI1RST SAI1 block reset 22 1 SAI2RST SAI2 block reset 23 1 SAI3RST SAI3 block reset 24 1 DFSDM1RST DFSDM1 block reset 28 1 HRTIMRST HRTIM block reset 29 1 APB4RSTR APB4RSTR RCC APB4 Peripheral Reset Register 0x9C 0x20 read-write 0x00000000 SYSCFGRST SYSCFG block reset 1 1 SYSCFGRST Reset Reset the selected module 1 LPUART1RST LPUART1 block reset 3 1 SPI6RST SPI6 block reset 5 1 I2C4RST I2C4 block reset 7 1 LPTIM2RST LPTIM2 block reset 9 1 LPTIM3RST LPTIM3 block reset 10 1 LPTIM4RST LPTIM4 block reset 11 1 LPTIM5RST LPTIM5 block reset 12 1 COMP12RST COMP12 Blocks Reset 14 1 VREFRST VREF block reset 15 1 SAI4RST SAI4 block reset 21 1 GCR GCR RCC Global Control Register 0xA0 0x20 read-write 0x00000000 WW1RSC WWDG1 reset scope control 0 1 WW1RSC Clear Clear WWDG1 scope control 0 Set Set WWDG1 scope control 1 D3AMR D3AMR RCC D3 Autonomous mode Register 0xA8 0x20 read-write 0x00000000 BDMAAMEN BDMA and DMAMUX Autonomous mode enable 0 1 BDMAAMEN Disabled Clock disabled in autonomous mode 0 Enabled Clock enabled in autonomous mode 1 LPUART1AMEN LPUART1 Autonomous mode enable 3 1 SPI6AMEN SPI6 Autonomous mode enable 5 1 I2C4AMEN I2C4 Autonomous mode enable 7 1 LPTIM2AMEN LPTIM2 Autonomous mode enable 9 1 LPTIM3AMEN LPTIM3 Autonomous mode enable 10 1 LPTIM4AMEN LPTIM4 Autonomous mode enable 11 1 LPTIM5AMEN LPTIM5 Autonomous mode enable 12 1 COMP12AMEN COMP12 Autonomous mode enable 14 1 VREFAMEN VREF Autonomous mode enable 15 1 RTCAMEN RTC Autonomous mode enable 16 1 CRCAMEN CRC Autonomous mode enable 19 1 SAI4AMEN SAI4 Autonomous mode enable 21 1 ADC3AMEN ADC3 Autonomous mode enable 24 1 BKPRAMAMEN Backup RAM Autonomous mode enable 28 1 SRAM4AMEN SRAM4 Autonomous mode enable 29 1 RSR RSR RCC Reset Status Register 0xD0 0x20 read-write 0x00000000 RMVF Remove reset flag 16 1 RMVF NotActivated Reset not activated 0 Reset Reset the reset status flags 1 CPURSTF CPU reset flag 17 1 CPURSTFR read NoResetOccurred No reset occurred for block 0 ResetOccurred Reset occurred for block 1 D1RSTF D1 domain power switch reset flag 19 1 D2RSTF D2 domain power switch reset flag 20 1 BORRSTF BOR reset flag 21 1 PINRSTF Pin reset flag (NRST) 22 1 PORRSTF POR/PDR reset flag 23 1 SFTRSTF System reset from CPU reset flag 24 1 IWDG1RSTF Independent Watchdog reset flag 26 1 WWDG1RSTF Window Watchdog reset flag 28 1 LPWRRSTF Reset due to illegal D1 DStandby or CPU CStop flag 30 1 C1_RSR C1_RSR RCC Reset Status Register 0x130 0x20 read-write 0x00000000 RMVF Remove reset flag 16 1 RMVF NotActivated Reset not activated 0 Reset Reset the reset status flags 1 CPURSTF CPU reset flag 17 1 CPURSTFR read NoResetOccurred No reset occurred for block 0 ResetOccurred Reset occurred for block 1 D1RSTF D1 domain power switch reset flag 19 1 D2RSTF D2 domain power switch reset flag 20 1 BORRSTF BOR reset flag 21 1 PINRSTF Pin reset flag (NRST) 22 1 PORRSTF POR/PDR reset flag 23 1 SFTRSTF System reset from CPU reset flag 24 1 IWDG1RSTF Independent Watchdog reset flag 26 1 WWDG1RSTF Window Watchdog reset flag 28 1 LPWRRSTF Reset due to illegal D1 DStandby or CPU CStop flag 30 1 C1_AHB3ENR C1_AHB3ENR RCC AHB3 Clock Register 0x134 0x20 read-write 0x00000000 MDMAEN MDMA Peripheral Clock Enable 0 1 MDMAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2DEN DMA2D Peripheral Clock Enable 4 1 JPGDECEN JPGDEC Peripheral Clock Enable 5 1 FMCEN FMC Peripheral Clocks Enable 12 1 QSPIEN QUADSPI and QUADSPI Delay Clock Enable 14 1 SDMMC1EN SDMMC1 and SDMMC1 Delay Clock Enable 16 1 AHB3ENR AHB3ENR RCC AHB3 Clock Register 0xD4 0x20 read-write 0x00000000 MDMAEN MDMA Peripheral Clock Enable 0 1 MDMAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2DEN DMA2D Peripheral Clock Enable 4 1 JPGDECEN JPGDEC Peripheral Clock Enable 5 1 FMCEN FMC Peripheral Clocks Enable 12 1 QSPIEN QUADSPI and QUADSPI Delay Clock Enable 14 1 SDMMC1EN SDMMC1 and SDMMC1 Delay Clock Enable 16 1 AHB1ENR AHB1ENR RCC AHB1 Clock Register 0xD8 0x20 read-write 0x00000000 DMA1EN DMA1 Clock Enable 0 1 DMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2EN DMA2 Clock Enable 1 1 ADC12EN ADC1/2 Peripheral Clocks Enable 5 1 ETH1MACEN Ethernet MAC bus interface Clock Enable 15 1 ETH1TXEN Ethernet Transmission Clock Enable 16 1 ETH1RXEN Ethernet Reception Clock Enable 17 1 USB1OTGHSEN USB1OTG (OTG_HS1) Peripheral Clocks Enable 25 1 USB1OTGULPIEN USB_PHY1 Clocks Enable 26 1 USB2OTGHSEN USB2OTG Peripheral Clocks Enable 27 1 USB2OTGHSULPIEN USB_PHY2 Clocks Enable 28 1 C1_AHB1ENR C1_AHB1ENR RCC AHB1 Clock Register 0x138 0x20 read-write 0x00000000 DMA1EN DMA1 Clock Enable 0 1 DMA1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 DMA2EN DMA2 Clock Enable 1 1 ADC12EN ADC1/2 Peripheral Clocks Enable 5 1 ETH1MACEN Ethernet MAC bus interface Clock Enable 15 1 ETH1TXEN Ethernet Transmission Clock Enable 16 1 ETH1RXEN Ethernet Reception Clock Enable 17 1 USB1OTGHSEN USB1OTG (OTG_HS1) Peripheral Clocks Enable 25 1 USB1OTGULPIEN USB_PHY1 Clocks Enable 26 1 USB2OTGHSEN USB2OTG Peripheral Clocks Enable 27 1 USB2OTGHSULPIEN USB_PHY2 Clocks Enable 28 1 C1_AHB2ENR C1_AHB2ENR RCC AHB2 Clock Register 0x13C 0x20 read-write 0x00000000 DCMIEN DCMI peripheral clock enable 0 1 DCMIEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 CRYPTEN CRYPT peripheral clock enable 4 1 HASHEN HASH peripheral clock enable 5 1 RNGEN RNG peripheral clocks enable 6 1 SDMMC2EN SDMMC2 and SDMMC2 delay clock enable 9 1 SRAM1EN SRAM1 block enable 29 1 SRAM2EN SRAM2 block enable 30 1 SRAM3EN SRAM3 block enable 31 1 AHB2ENR AHB2ENR RCC AHB2 Clock Register 0xDC 0x20 read-write 0x00000000 DCMIEN DCMI peripheral clock enable 0 1 DCMIEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 CRYPTEN CRYPT peripheral clock enable 4 1 HASHEN HASH peripheral clock enable 5 1 RNGEN RNG peripheral clocks enable 6 1 SDMMC2EN SDMMC2 and SDMMC2 delay clock enable 9 1 SRAM1EN SRAM1 block enable 29 1 SRAM2EN SRAM2 block enable 30 1 SRAM3EN SRAM3 block enable 31 1 AHB4ENR AHB4ENR RCC AHB4 Clock Register 0xE0 0x20 read-write 0x00000000 GPIOAEN 0GPIO peripheral clock enable 0 1 GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN 0GPIO peripheral clock enable 1 1 GPIOCEN 0GPIO peripheral clock enable 2 1 GPIODEN 0GPIO peripheral clock enable 3 1 GPIOEEN 0GPIO peripheral clock enable 4 1 GPIOFEN 0GPIO peripheral clock enable 5 1 GPIOGEN 0GPIO peripheral clock enable 6 1 GPIOHEN 0GPIO peripheral clock enable 7 1 GPIOIEN 0GPIO peripheral clock enable 8 1 GPIOJEN 0GPIO peripheral clock enable 9 1 GPIOKEN 0GPIO peripheral clock enable 10 1 CRCEN CRC peripheral clock enable 19 1 BDMAEN BDMA and DMAMUX2 Clock Enable 21 1 ADC3EN ADC3 Peripheral Clocks Enable 24 1 HSEMEN HSEM peripheral clock enable 25 1 BKPRAMEN Backup RAM Clock Enable 28 1 C1_AHB4ENR C1_AHB4ENR RCC AHB4 Clock Register 0x140 0x20 read-write 0x00000000 GPIOAEN 0GPIO peripheral clock enable 0 1 GPIOAEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 GPIOBEN 0GPIO peripheral clock enable 1 1 GPIOCEN 0GPIO peripheral clock enable 2 1 GPIODEN 0GPIO peripheral clock enable 3 1 GPIOEEN 0GPIO peripheral clock enable 4 1 GPIOFEN 0GPIO peripheral clock enable 5 1 GPIOGEN 0GPIO peripheral clock enable 6 1 GPIOHEN 0GPIO peripheral clock enable 7 1 GPIOIEN 0GPIO peripheral clock enable 8 1 GPIOJEN 0GPIO peripheral clock enable 9 1 GPIOKEN 0GPIO peripheral clock enable 10 1 CRCEN CRC peripheral clock enable 19 1 BDMAEN BDMA and DMAMUX2 Clock Enable 21 1 ADC3EN ADC3 Peripheral Clocks Enable 24 1 HSEMEN HSEM peripheral clock enable 25 1 BKPRAMEN Backup RAM Clock Enable 28 1 C1_APB3ENR C1_APB3ENR RCC APB3 Clock Register 0x144 0x20 read-write 0x00000000 LTDCEN LTDC peripheral clock enable 3 1 LTDCEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 WWDG1EN WWDG1 Clock Enable 6 1 APB3ENR APB3ENR RCC APB3 Clock Register 0xE4 0x20 read-write 0x00000000 LTDCEN LTDC peripheral clock enable 3 1 LTDCEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 WWDG1EN WWDG1 Clock Enable 6 1 APB1LENR APB1LENR RCC APB1 Clock Register 0xE8 0x20 read-write 0x00000000 TIM2EN TIM peripheral clock enable 0 1 TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM peripheral clock enable 1 1 TIM4EN TIM peripheral clock enable 2 1 TIM5EN TIM peripheral clock enable 3 1 TIM6EN TIM peripheral clock enable 4 1 TIM7EN TIM peripheral clock enable 5 1 TIM12EN TIM peripheral clock enable 6 1 TIM13EN TIM peripheral clock enable 7 1 TIM14EN TIM peripheral clock enable 8 1 LPTIM1EN LPTIM1 Peripheral Clocks Enable 9 1 SPI2EN SPI2 Peripheral Clocks Enable 14 1 SPI3EN SPI3 Peripheral Clocks Enable 15 1 SPDIFRXEN SPDIFRX Peripheral Clocks Enable 16 1 USART2EN USART2 Peripheral Clocks Enable 17 1 USART3EN USART3 Peripheral Clocks Enable 18 1 UART4EN UART4 Peripheral Clocks Enable 19 1 UART5EN UART5 Peripheral Clocks Enable 20 1 I2C1EN I2C1 Peripheral Clocks Enable 21 1 I2C2EN I2C2 Peripheral Clocks Enable 22 1 I2C3EN I2C3 Peripheral Clocks Enable 23 1 CECEN HDMI-CEC peripheral clock enable 27 1 DAC12EN DAC1&2 peripheral clock enable 29 1 UART7EN UART7 Peripheral Clocks Enable 30 1 UART8EN UART8 Peripheral Clocks Enable 31 1 C1_APB1LENR C1_APB1LENR RCC APB1 Clock Register 0x148 0x20 read-write 0x00000000 TIM2EN TIM peripheral clock enable 0 1 TIM2EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM3EN TIM peripheral clock enable 1 1 TIM4EN TIM peripheral clock enable 2 1 TIM5EN TIM peripheral clock enable 3 1 TIM6EN TIM peripheral clock enable 4 1 TIM7EN TIM peripheral clock enable 5 1 TIM12EN TIM peripheral clock enable 6 1 TIM13EN TIM peripheral clock enable 7 1 TIM14EN TIM peripheral clock enable 8 1 LPTIM1EN LPTIM1 Peripheral Clocks Enable 9 1 SPI2EN SPI2 Peripheral Clocks Enable 14 1 SPI3EN SPI3 Peripheral Clocks Enable 15 1 SPDIFRXEN SPDIFRX Peripheral Clocks Enable 16 1 USART2EN USART2 Peripheral Clocks Enable 17 1 USART3EN USART3 Peripheral Clocks Enable 18 1 UART4EN UART4 Peripheral Clocks Enable 19 1 UART5EN UART5 Peripheral Clocks Enable 20 1 I2C1EN I2C1 Peripheral Clocks Enable 21 1 I2C2EN I2C2 Peripheral Clocks Enable 22 1 I2C3EN I2C3 Peripheral Clocks Enable 23 1 CECEN HDMI-CEC peripheral clock enable 27 1 DAC12EN DAC1&2 peripheral clock enable 29 1 UART7EN UART7 Peripheral Clocks Enable 30 1 UART8EN UART8 Peripheral Clocks Enable 31 1 APB1HENR APB1HENR RCC APB1 Clock Register 0xEC 0x20 read-write 0x00000000 CRSEN Clock Recovery System peripheral clock enable 1 1 CRSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SWPEN SWPMI Peripheral Clocks Enable 2 1 OPAMPEN OPAMP peripheral clock enable 4 1 MDIOSEN MDIOS peripheral clock enable 5 1 FDCANEN FDCAN Peripheral Clocks Enable 8 1 C1_APB1HENR C1_APB1HENR RCC APB1 Clock Register 0x14C 0x20 read-write 0x00000000 CRSEN Clock Recovery System peripheral clock enable 1 1 CRSEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 SWPEN SWPMI Peripheral Clocks Enable 2 1 OPAMPEN OPAMP peripheral clock enable 4 1 MDIOSEN MDIOS peripheral clock enable 5 1 FDCANEN FDCAN Peripheral Clocks Enable 8 1 C1_APB2ENR C1_APB2ENR RCC APB2 Clock Register 0x150 0x20 read-write 0x00000000 TIM1EN TIM1 peripheral clock enable 0 1 TIM1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM8EN TIM8 peripheral clock enable 1 1 USART1EN USART1 Peripheral Clocks Enable 4 1 USART6EN USART6 Peripheral Clocks Enable 5 1 SPI1EN SPI1 Peripheral Clocks Enable 12 1 SPI4EN SPI4 Peripheral Clocks Enable 13 1 TIM16EN TIM16 peripheral clock enable 17 1 TIM15EN TIM15 peripheral clock enable 16 1 TIM17EN TIM17 peripheral clock enable 18 1 SPI5EN SPI5 Peripheral Clocks Enable 20 1 SAI1EN SAI1 Peripheral Clocks Enable 22 1 SAI2EN SAI2 Peripheral Clocks Enable 23 1 SAI3EN SAI3 Peripheral Clocks Enable 24 1 DFSDM1EN DFSDM1 Peripheral Clocks Enable 28 1 HRTIMEN HRTIM peripheral clock enable 29 1 APB2ENR APB2ENR RCC APB2 Clock Register 0xF0 0x20 read-write 0x00000000 TIM1EN TIM1 peripheral clock enable 0 1 TIM1EN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 TIM8EN TIM8 peripheral clock enable 1 1 USART1EN USART1 Peripheral Clocks Enable 4 1 USART6EN USART6 Peripheral Clocks Enable 5 1 SPI1EN SPI1 Peripheral Clocks Enable 12 1 SPI4EN SPI4 Peripheral Clocks Enable 13 1 TIM16EN TIM16 peripheral clock enable 17 1 TIM15EN TIM15 peripheral clock enable 16 1 TIM17EN TIM17 peripheral clock enable 18 1 SPI5EN SPI5 Peripheral Clocks Enable 20 1 SAI1EN SAI1 Peripheral Clocks Enable 22 1 SAI2EN SAI2 Peripheral Clocks Enable 23 1 SAI3EN SAI3 Peripheral Clocks Enable 24 1 DFSDM1EN DFSDM1 Peripheral Clocks Enable 28 1 HRTIMEN HRTIM peripheral clock enable 29 1 APB4ENR APB4ENR RCC APB4 Clock Register 0xF4 0x20 read-write 0x00000000 SYSCFGEN SYSCFG peripheral clock enable 1 1 SYSCFGEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 LPUART1EN LPUART1 Peripheral Clocks Enable 3 1 SPI6EN SPI6 Peripheral Clocks Enable 5 1 I2C4EN I2C4 Peripheral Clocks Enable 7 1 LPTIM2EN LPTIM2 Peripheral Clocks Enable 9 1 LPTIM3EN LPTIM3 Peripheral Clocks Enable 10 1 LPTIM4EN LPTIM4 Peripheral Clocks Enable 11 1 LPTIM5EN LPTIM5 Peripheral Clocks Enable 12 1 COMP12EN COMP1/2 peripheral clock enable 14 1 VREFEN VREF peripheral clock enable 15 1 RTCAPBEN RTC APB Clock Enable 16 1 SAI4EN SAI4 Peripheral Clocks Enable 21 1 C1_APB4ENR C1_APB4ENR RCC APB4 Clock Register 0x154 0x20 read-write 0x00000000 SYSCFGEN SYSCFG peripheral clock enable 1 1 SYSCFGEN Disabled The selected clock is disabled 0 Enabled The selected clock is enabled 1 LPUART1EN LPUART1 Peripheral Clocks Enable 3 1 SPI6EN SPI6 Peripheral Clocks Enable 5 1 I2C4EN I2C4 Peripheral Clocks Enable 7 1 LPTIM2EN LPTIM2 Peripheral Clocks Enable 9 1 LPTIM3EN LPTIM3 Peripheral Clocks Enable 10 1 LPTIM4EN LPTIM4 Peripheral Clocks Enable 11 1 LPTIM5EN LPTIM5 Peripheral Clocks Enable 12 1 COMP12EN COMP1/2 peripheral clock enable 14 1 VREFEN VREF peripheral clock enable 15 1 RTCAPBEN RTC APB Clock Enable 16 1 SAI4EN SAI4 Peripheral Clocks Enable 21 1 C1_AHB3LPENR C1_AHB3LPENR RCC AHB3 Sleep Clock Register 0x15C 0x20 read-write 0x00000000 MDMALPEN MDMA Clock Enable During CSleep Mode 0 1 MDMALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 DMA2DLPEN DMA2D Clock Enable During CSleep Mode 4 1 JPGDECLPEN JPGDEC Clock Enable During CSleep Mode 5 1 FLASHPREN Flash interface clock enable during csleep mode 8 1 FMCLPEN FMC Peripheral Clocks Enable During CSleep Mode 12 1 QSPILPEN QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode 14 1 SDMMC1LPEN SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode 16 1 D1DTCM1LPEN D1DTCM1 Block Clock Enable During CSleep mode 28 1 DTCM2LPEN D1 DTCM2 Block Clock Enable During CSleep mode 29 1 ITCMLPEN D1ITCM Block Clock Enable During CSleep mode 30 1 AXISRAMLPEN AXISRAM Block Clock Enable During CSleep mode 31 1 AHB3LPENR AHB3LPENR RCC AHB3 Sleep Clock Register 0xFC 0x20 read-write 0x00000000 MDMALPEN MDMA Clock Enable During CSleep Mode 0 1 MDMALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 DMA2DLPEN DMA2D Clock Enable During CSleep Mode 4 1 JPGDECLPEN JPGDEC Clock Enable During CSleep Mode 5 1 FLASHLPEN FLITF Clock Enable During CSleep Mode 8 1 FMCLPEN FMC Peripheral Clocks Enable During CSleep Mode 12 1 QSPILPEN QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode 14 1 SDMMC1LPEN SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode 16 1 D1DTCM1LPEN D1DTCM1 Block Clock Enable During CSleep mode 28 1 DTCM2LPEN D1 DTCM2 Block Clock Enable During CSleep mode 29 1 ITCMLPEN D1ITCM Block Clock Enable During CSleep mode 30 1 AXISRAMLPEN AXISRAM Block Clock Enable During CSleep mode 31 1 AHB1LPENR AHB1LPENR RCC AHB1 Sleep Clock Register 0x100 0x20 read-write 0x00000000 DMA1LPEN DMA1 Clock Enable During CSleep Mode 0 1 DMA1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 DMA2LPEN DMA2 Clock Enable During CSleep Mode 1 1 ADC12LPEN ADC1/2 Peripheral Clocks Enable During CSleep Mode 5 1 ETH1MACLPEN Ethernet MAC bus interface Clock Enable During CSleep Mode 15 1 ETH1TXLPEN Ethernet Transmission Clock Enable During CSleep Mode 16 1 ETH1RXLPEN Ethernet Reception Clock Enable During CSleep Mode 17 1 USB1OTGLPEN USB1OTG peripheral clock enable during CSleep mode 25 1 USB1OTGULPILPEN USB_PHY1 clock enable during CSleep mode 26 1 USB2OTGHSLPEN USB2OTG peripheral clock enable during CSleep mode 27 1 USB2OTGHSULPILPEN USB_PHY2 clocks enable during CSleep mode 28 1 C1_AHB1LPENR C1_AHB1LPENR RCC AHB1 Sleep Clock Register 0x160 0x20 read-write 0x00000000 DMA1LPEN DMA1 Clock Enable During CSleep Mode 0 1 DMA1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 DMA2LPEN DMA2 Clock Enable During CSleep Mode 1 1 ADC12LPEN ADC1/2 Peripheral Clocks Enable During CSleep Mode 5 1 ETH1MACLPEN Ethernet MAC bus interface Clock Enable During CSleep Mode 15 1 ETH1TXLPEN Ethernet Transmission Clock Enable During CSleep Mode 16 1 ETH1RXLPEN Ethernet Reception Clock Enable During CSleep Mode 17 1 USB1OTGLPEN USB1OTG peripheral clock enable during CSleep mode 25 1 USB1OTGULPILPEN USB_PHY1 clock enable during CSleep mode 26 1 USB2OTGLPEN USB2OTG peripheral clock enable during CSleep mode 27 1 USB2ULPILPEN USB_PHY2 clocks enable during CSleep mode 28 1 C1_AHB2LPENR C1_AHB2LPENR RCC AHB2 Sleep Clock Register 0x164 0x20 read-write 0x00000000 DCMILPEN DCMI peripheral clock enable during csleep mode 0 1 DCMILPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 CRYPTLPEN CRYPT peripheral clock enable during CSleep mode 4 1 HASHLPEN HASH peripheral clock enable during CSleep mode 5 1 SDMMC2LPEN SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode 9 1 RNGLPEN RNG peripheral clock enable during CSleep mode 6 1 SRAM1LPEN SRAM1 Clock Enable During CSleep Mode 29 1 SRAM2LPEN SRAM2 Clock Enable During CSleep Mode 30 1 SRAM3LPEN SRAM3 Clock Enable During CSleep Mode 31 1 AHB2LPENR AHB2LPENR RCC AHB2 Sleep Clock Register 0x104 0x20 read-write 0x00000000 DCMILPEN DCMI peripheral clock enable during csleep mode 0 1 DCMILPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 CRYPTLPEN CRYPT peripheral clock enable during CSleep mode 4 1 HASHLPEN HASH peripheral clock enable during CSleep mode 5 1 SDMMC2LPEN SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode 9 1 RNGLPEN RNG peripheral clock enable during CSleep mode 6 1 SRAM1LPEN SRAM1 Clock Enable During CSleep Mode 29 1 SRAM2LPEN SRAM2 Clock Enable During CSleep Mode 30 1 SRAM3LPEN SRAM3 Clock Enable During CSleep Mode 31 1 AHB4LPENR AHB4LPENR RCC AHB4 Sleep Clock Register 0x108 0x20 read-write 0x00000000 GPIOALPEN GPIO peripheral clock enable during CSleep mode 0 1 GPIOALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPIOBLPEN GPIO peripheral clock enable during CSleep mode 1 1 GPIOCLPEN GPIO peripheral clock enable during CSleep mode 2 1 GPIODLPEN GPIO peripheral clock enable during CSleep mode 3 1 GPIOELPEN GPIO peripheral clock enable during CSleep mode 4 1 GPIOFLPEN GPIO peripheral clock enable during CSleep mode 5 1 GPIOGLPEN GPIO peripheral clock enable during CSleep mode 6 1 GPIOHLPEN GPIO peripheral clock enable during CSleep mode 7 1 GPIOILPEN GPIO peripheral clock enable during CSleep mode 8 1 GPIOJLPEN GPIO peripheral clock enable during CSleep mode 9 1 GPIOKLPEN GPIO peripheral clock enable during CSleep mode 10 1 CRCLPEN CRC peripheral clock enable during CSleep mode 19 1 BDMALPEN BDMA Clock Enable During CSleep Mode 21 1 ADC3LPEN ADC3 Peripheral Clocks Enable During CSleep Mode 24 1 BKPRAMLPEN Backup RAM Clock Enable During CSleep Mode 28 1 SRAM4LPEN SRAM4 Clock Enable During CSleep Mode 29 1 C1_AHB4LPENR C1_AHB4LPENR RCC AHB4 Sleep Clock Register 0x168 0x20 read-write 0x00000000 GPIOALPEN GPIO peripheral clock enable during CSleep mode 0 1 GPIOALPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 GPIOBLPEN GPIO peripheral clock enable during CSleep mode 1 1 GPIOCLPEN GPIO peripheral clock enable during CSleep mode 2 1 GPIODLPEN GPIO peripheral clock enable during CSleep mode 3 1 GPIOELPEN GPIO peripheral clock enable during CSleep mode 4 1 GPIOFLPEN GPIO peripheral clock enable during CSleep mode 5 1 GPIOGLPEN GPIO peripheral clock enable during CSleep mode 6 1 GPIOHLPEN GPIO peripheral clock enable during CSleep mode 7 1 GPIOILPEN GPIO peripheral clock enable during CSleep mode 8 1 GPIOJLPEN GPIO peripheral clock enable during CSleep mode 9 1 GPIOKLPEN GPIO peripheral clock enable during CSleep mode 10 1 CRCLPEN CRC peripheral clock enable during CSleep mode 19 1 BDMALPEN BDMA Clock Enable During CSleep Mode 21 1 ADC3LPEN ADC3 Peripheral Clocks Enable During CSleep Mode 24 1 BKPRAMLPEN Backup RAM Clock Enable During CSleep Mode 28 1 SRAM4LPEN SRAM4 Clock Enable During CSleep Mode 29 1 C1_APB3LPENR C1_APB3LPENR RCC APB3 Sleep Clock Register 0x16C 0x20 read-write 0x00000000 LTDCLPEN LTDC peripheral clock enable during CSleep mode 3 1 LTDCLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 WWDG1LPEN WWDG1 Clock Enable During CSleep Mode 6 1 APB3LPENR APB3LPENR RCC APB3 Sleep Clock Register 0x10C 0x20 read-write 0x00000000 LTDCLPEN LTDC peripheral clock enable during CSleep mode 3 1 LTDCLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 WWDG1LPEN WWDG1 Clock Enable During CSleep Mode 6 1 APB1LLPENR APB1LLPENR RCC APB1 Low Sleep Clock Register 0x110 0x20 read-write 0x00000000 TIM2LPEN TIM2 peripheral clock enable during CSleep mode 0 1 TIM2LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM3LPEN TIM3 peripheral clock enable during CSleep mode 1 1 TIM4LPEN TIM4 peripheral clock enable during CSleep mode 2 1 TIM5LPEN TIM5 peripheral clock enable during CSleep mode 3 1 TIM6LPEN TIM6 peripheral clock enable during CSleep mode 4 1 TIM7LPEN TIM7 peripheral clock enable during CSleep mode 5 1 TIM12LPEN TIM12 peripheral clock enable during CSleep mode 6 1 TIM13LPEN TIM13 peripheral clock enable during CSleep mode 7 1 TIM14LPEN TIM14 peripheral clock enable during CSleep mode 8 1 LPTIM1LPEN LPTIM1 Peripheral Clocks Enable During CSleep Mode 9 1 SPI2LPEN SPI2 Peripheral Clocks Enable During CSleep Mode 14 1 SPI3LPEN SPI3 Peripheral Clocks Enable During CSleep Mode 15 1 SPDIFRXLPEN SPDIFRX Peripheral Clocks Enable During CSleep Mode 16 1 USART2LPEN USART2 Peripheral Clocks Enable During CSleep Mode 17 1 USART3LPEN USART3 Peripheral Clocks Enable During CSleep Mode 18 1 UART4LPEN UART4 Peripheral Clocks Enable During CSleep Mode 19 1 UART5LPEN UART5 Peripheral Clocks Enable During CSleep Mode 20 1 I2C1LPEN I2C1 Peripheral Clocks Enable During CSleep Mode 21 1 I2C2LPEN I2C2 Peripheral Clocks Enable During CSleep Mode 22 1 I2C3LPEN I2C3 Peripheral Clocks Enable During CSleep Mode 23 1 CECLPEN HDMI-CEC Peripheral Clocks Enable During CSleep Mode 27 1 DAC12LPEN DAC1/2 peripheral clock enable during CSleep mode 29 1 UART7LPEN UART7 Peripheral Clocks Enable During CSleep Mode 30 1 UART8LPEN UART8 Peripheral Clocks Enable During CSleep Mode 31 1 C1_APB1LLPENR C1_APB1LLPENR RCC APB1 Low Sleep Clock Register 0x170 0x20 read-write 0x00000000 TIM2LPEN TIM2 peripheral clock enable during CSleep mode 0 1 TIM2LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM3LPEN TIM3 peripheral clock enable during CSleep mode 1 1 TIM4LPEN TIM4 peripheral clock enable during CSleep mode 2 1 TIM5LPEN TIM5 peripheral clock enable during CSleep mode 3 1 TIM6LPEN TIM6 peripheral clock enable during CSleep mode 4 1 TIM7LPEN TIM7 peripheral clock enable during CSleep mode 5 1 TIM12LPEN TIM12 peripheral clock enable during CSleep mode 6 1 TIM13LPEN TIM13 peripheral clock enable during CSleep mode 7 1 TIM14LPEN TIM14 peripheral clock enable during CSleep mode 8 1 LPTIM1LPEN LPTIM1 Peripheral Clocks Enable During CSleep Mode 9 1 SPI2LPEN SPI2 Peripheral Clocks Enable During CSleep Mode 14 1 SPI3LPEN SPI3 Peripheral Clocks Enable During CSleep Mode 15 1 SPDIFRXLPEN SPDIFRX Peripheral Clocks Enable During CSleep Mode 16 1 USART2LPEN USART2 Peripheral Clocks Enable During CSleep Mode 17 1 USART3LPEN USART3 Peripheral Clocks Enable During CSleep Mode 18 1 UART4LPEN UART4 Peripheral Clocks Enable During CSleep Mode 19 1 UART5LPEN UART5 Peripheral Clocks Enable During CSleep Mode 20 1 I2C1LPEN I2C1 Peripheral Clocks Enable During CSleep Mode 21 1 I2C2LPEN I2C2 Peripheral Clocks Enable During CSleep Mode 22 1 I2C3LPEN I2C3 Peripheral Clocks Enable During CSleep Mode 23 1 CECLPEN HDMI-CEC Peripheral Clocks Enable During CSleep Mode 27 1 DAC12LPEN DAC1/2 peripheral clock enable during CSleep mode 29 1 UART7LPEN UART7 Peripheral Clocks Enable During CSleep Mode 30 1 UART8LPEN UART8 Peripheral Clocks Enable During CSleep Mode 31 1 C1_APB1HLPENR C1_APB1HLPENR RCC APB1 High Sleep Clock Register 0x174 0x20 read-write 0x00000000 CRSLPEN Clock Recovery System peripheral clock enable during CSleep mode 1 1 CRSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 SWPLPEN SWPMI Peripheral Clocks Enable During CSleep Mode 2 1 OPAMPLPEN OPAMP peripheral clock enable during CSleep mode 4 1 MDIOSLPEN MDIOS peripheral clock enable during CSleep mode 5 1 FDCANLPEN FDCAN Peripheral Clocks Enable During CSleep Mode 8 1 APB1HLPENR APB1HLPENR RCC APB1 High Sleep Clock Register 0x114 0x20 read-write 0x00000000 CRSLPEN Clock Recovery System peripheral clock enable during CSleep mode 1 1 CRSLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 SWPLPEN SWPMI Peripheral Clocks Enable During CSleep Mode 2 1 OPAMPLPEN OPAMP peripheral clock enable during CSleep mode 4 1 MDIOSLPEN MDIOS peripheral clock enable during CSleep mode 5 1 FDCANLPEN FDCAN Peripheral Clocks Enable During CSleep Mode 8 1 APB2LPENR APB2LPENR RCC APB2 Sleep Clock Register 0x118 0x20 read-write 0x00000000 TIM1LPEN TIM1 peripheral clock enable during CSleep mode 0 1 TIM1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM8LPEN TIM8 peripheral clock enable during CSleep mode 1 1 USART1LPEN USART1 Peripheral Clocks Enable During CSleep Mode 4 1 USART6LPEN USART6 Peripheral Clocks Enable During CSleep Mode 5 1 SPI1LPEN SPI1 Peripheral Clocks Enable During CSleep Mode 12 1 SPI4LPEN SPI4 Peripheral Clocks Enable During CSleep Mode 13 1 TIM15LPEN TIM15 peripheral clock enable during CSleep mode 16 1 TIM16LPEN TIM16 peripheral clock enable during CSleep mode 17 1 TIM17LPEN TIM17 peripheral clock enable during CSleep mode 18 1 SPI5LPEN SPI5 Peripheral Clocks Enable During CSleep Mode 20 1 SAI1LPEN SAI1 Peripheral Clocks Enable During CSleep Mode 22 1 SAI2LPEN SAI2 Peripheral Clocks Enable During CSleep Mode 23 1 SAI3LPEN SAI3 Peripheral Clocks Enable During CSleep Mode 24 1 DFSDM1LPEN DFSDM1 Peripheral Clocks Enable During CSleep Mode 28 1 HRTIMLPEN HRTIM peripheral clock enable during CSleep mode 29 1 C1_APB2LPENR C1_APB2LPENR RCC APB2 Sleep Clock Register 0x178 0x20 read-write 0x00000000 TIM1LPEN TIM1 peripheral clock enable during CSleep mode 0 1 TIM1LPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 TIM8LPEN TIM8 peripheral clock enable during CSleep mode 1 1 USART1LPEN USART1 Peripheral Clocks Enable During CSleep Mode 4 1 USART6LPEN USART6 Peripheral Clocks Enable During CSleep Mode 5 1 SPI1LPEN SPI1 Peripheral Clocks Enable During CSleep Mode 12 1 SPI4LPEN SPI4 Peripheral Clocks Enable During CSleep Mode 13 1 TIM15LPEN TIM15 peripheral clock enable during CSleep mode 16 1 TIM16LPEN TIM16 peripheral clock enable during CSleep mode 17 1 TIM17LPEN TIM17 peripheral clock enable during CSleep mode 18 1 SPI5LPEN SPI5 Peripheral Clocks Enable During CSleep Mode 20 1 SAI1LPEN SAI1 Peripheral Clocks Enable During CSleep Mode 22 1 SAI2LPEN SAI2 Peripheral Clocks Enable During CSleep Mode 23 1 SAI3LPEN SAI3 Peripheral Clocks Enable During CSleep Mode 24 1 DFSDM1LPEN DFSDM1 Peripheral Clocks Enable During CSleep Mode 28 1 HRTIMLPEN HRTIM peripheral clock enable during CSleep mode 29 1 C1_APB4LPENR C1_APB4LPENR RCC APB4 Sleep Clock Register 0x17C 0x20 read-write 0x00000000 SYSCFGLPEN SYSCFG peripheral clock enable during CSleep mode 1 1 SYSCFGLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 LPUART1LPEN LPUART1 Peripheral Clocks Enable During CSleep Mode 3 1 SPI6LPEN SPI6 Peripheral Clocks Enable During CSleep Mode 5 1 I2C4LPEN I2C4 Peripheral Clocks Enable During CSleep Mode 7 1 LPTIM2LPEN LPTIM2 Peripheral Clocks Enable During CSleep Mode 9 1 LPTIM3LPEN LPTIM3 Peripheral Clocks Enable During CSleep Mode 10 1 LPTIM4LPEN LPTIM4 Peripheral Clocks Enable During CSleep Mode 11 1 LPTIM5LPEN LPTIM5 Peripheral Clocks Enable During CSleep Mode 12 1 COMP12LPEN COMP1/2 peripheral clock enable during CSleep mode 14 1 VREFLPEN VREF peripheral clock enable during CSleep mode 15 1 RTCAPBLPEN RTC APB Clock Enable During CSleep Mode 16 1 SAI4LPEN SAI4 Peripheral Clocks Enable During CSleep Mode 21 1 APB4LPENR APB4LPENR RCC APB4 Sleep Clock Register 0x11C 0x20 read-write 0x00000000 SYSCFGLPEN SYSCFG peripheral clock enable during CSleep mode 1 1 SYSCFGLPEN Disabled The selected clock is disabled during csleep mode 0 Enabled The selected clock is enabled during csleep mode 1 LPUART1LPEN LPUART1 Peripheral Clocks Enable During CSleep Mode 3 1 SPI6LPEN SPI6 Peripheral Clocks Enable During CSleep Mode 5 1 I2C4LPEN I2C4 Peripheral Clocks Enable During CSleep Mode 7 1 LPTIM2LPEN LPTIM2 Peripheral Clocks Enable During CSleep Mode 9 1 LPTIM3LPEN LPTIM3 Peripheral Clocks Enable During CSleep Mode 10 1 LPTIM4LPEN LPTIM4 Peripheral Clocks Enable During CSleep Mode 11 1 LPTIM5LPEN LPTIM5 Peripheral Clocks Enable During CSleep Mode 12 1 COMP12LPEN COMP1/2 peripheral clock enable during CSleep mode 14 1 VREFLPEN VREF peripheral clock enable during CSleep mode 15 1 RTCAPBLPEN RTC APB Clock Enable During CSleep Mode 16 1 SAI4LPEN SAI4 Peripheral Clocks Enable During CSleep Mode 21 1 LPTIM1 Low power timer LPTIM 0x40002400 0x0 0x400 registers LPTIM1 LPTIM1 global interrupt 93 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE counter mode enabled 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD Registers update mode 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL Waveform shape polarity 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE Waveform shape 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT Timeout enable 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN Trigger enable and polarity 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL Trigger selector 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC Clock prescaler 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT Configurable digital filter for trigger 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT Configurable digital filter for external clock 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL Clock Polarity 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL Clock selector 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 ENABLE LPTIM Enable 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 SNGSTRT LPTIM start in single mode 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 CNTSTRT Timer start in continuous mode 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 COUNTRST Counter reset 3 1 COUNTRSTR read Idle Triggering of reset is possible 0 Busy Reset in progress, do not write 1 to this field 1 COUNTRSTW write Reset Trigger synchronous reset of CNT (3 LPTimer core clock cycles) 1 RSTARE Reset after read enable 4 1 RSTARE Disabled CNT Register reads do not trigger reset 0 Enabled CNT Register reads trigger reset of LPTIM 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 0 65535 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 0 65535 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 0 65535 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IN1SEL LPTIM Input 1 selection 0 2 IN2SEL LPTIM Input 2 selection 4 2 LPTIM2 0x58002400 LPTIM2 LPTIM2 timer interrupt 138 LPTIM3 Low power timer LPTIM 0x58002800 LPTIM3 LPTIM2 timer interrupt 139 LPTIM4 0x58002C00 LPTIM4 LPTIM2 timer interrupt 140 LPTIM5 0x58003000 LPTIM5 LPTIM2 timer interrupt 141 LPUART1 LPUART1 LPUART 0x58000C00 0x0 0x400 registers LPUART LPUART global interrupt 142 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFIFO Full interrupt enable 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 TXFEIE TXFIFO empty interrupt enable 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 FIFOEN FIFO mode enable 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable deassertion time 16 5 0 31 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop2 2 stop bit 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFIFO threshold configuration 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 TXFTIE TXFIFO threshold interrupt enable 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 20 0 1048575 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFIFO threshold flag 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 RXFT RXFIFO threshold flag 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 RXFF RXFIFO Full 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TXFE TXFIFO Empty 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NE NE 2 1 NE NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 4 PRESCALER Div1 /1 0 Div2 /2 1 Div4 /4 2 Div6 /6 3 Div8 /8 4 Div10 /10 5 Div12 /12 6 Div16 /16 7 Div32 /32 8 Div64 /64 9 Div128 /128 10 Div256 /256 11 SYSCFG System configuration controller SYSCFG 0x58000400 0x0 0x400 registers PMCR PMCR peripheral mode configuration register 0x4 0x20 read-write 0x00000000 I2C1FMP I2C1 Fm+ 0 1 I2C2FMP I2C2 Fm+ 1 1 I2C3FMP I2C3 Fm+ 2 1 I2C4FMP I2C4 Fm+ 3 1 PB6FMP PB(6) Fm+ 4 1 PB7FMP PB(7) Fast Mode Plus 5 1 PB8FMP PB(8) Fast Mode Plus 6 1 PB9FMP PB(9) Fm+ 7 1 BOOSTE Booster Enable 8 1 EPIS Ethernet PHY Interface Selection 21 3 PA0SO PA0 Switch Open 24 1 PA1SO PA1 Switch Open 25 1 PC2SO PC2 Switch Open 26 1 PC3SO PC3 Switch Open 27 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI x configuration (x = 12 to 15) 8 4 EXTI13 EXTI x configuration (x = 12 to 15) 4 4 EXTI12 EXTI x configuration (x = 12 to 15) 0 4 CCCSR CCCSR compensation cell control/status register 0x20 0x20 read-write 0x00000000 EN enable 0 1 CS Code selection 1 1 READY Compensation cell ready flag 8 1 HSLV High-speed at low-voltage 16 1 CCVR CCVR SYSCFG compensation cell value register 0x24 0x20 read-only 0x00000000 NCV NMOS compensation value 0 4 PCV PMOS compensation value 4 4 CCCR CCCR SYSCFG compensation cell code register 0x28 0x20 read-write 0x00000000 NCC NMOS compensation code 0 4 PCC PMOS compensation code 4 4 PKGR PKGR SYSCFG package register 0x124 0x20 read-only 0x00000000 PKG Package 0 4 UR0 UR0 SYSCFG user register 0 0x300 0x20 read-only 0x00000000 BKS Bank Swap 0 1 RDP Readout protection 16 8 UR2 UR2 SYSCFG user register 2 0x308 0x20 read-write 0x00000000 BORH BOR_LVL Brownout Reset Threshold Level 0 2 BOOT_ADD0 Boot Address 0 16 16 UR3 UR3 SYSCFG user register 3 0x30C 0x20 read-write 0x00000000 BOOT_ADD1 Boot Address 1 16 16 UR4 UR4 SYSCFG user register 4 0x310 0x20 read-only 0x00000000 MEPAD_1 Mass Erase Protected Area Disabled for bank 1 16 1 UR5 UR5 SYSCFG user register 5 0x314 0x20 read-only 0x00000000 MESAD_1 Mass erase secured area disabled for bank 1 0 1 WRPN_1 Write protection for flash bank 1 16 8 UR6 UR6 SYSCFG user register 6 0x318 0x20 read-only 0x00000000 PA_BEG_1 Protected area start address for bank 1 0 12 PA_END_1 Protected area end address for bank 1 16 12 UR7 UR7 SYSCFG user register 7 0x31C 0x20 read-only 0x00000000 SA_BEG_1 Secured area start address for bank 1 0 12 SA_END_1 Secured area end address for bank 1 16 12 UR8 UR8 SYSCFG user register 8 0x320 0x20 read-only 0x00000000 MEPAD_2 Mass erase protected area disabled for bank 2 0 1 MESAD_2 Mass erase secured area disabled for bank 2 16 1 UR9 UR9 SYSCFG user register 9 0x324 0x20 read-only 0x00000000 WRPN_2 Write protection for flash bank 2 0 8 PA_BEG_2 Protected area start address for bank 2 16 12 UR10 UR10 SYSCFG user register 10 0x328 0x20 read-only 0x00000000 PA_END_2 Protected area end address for bank 2 0 12 SA_BEG_2 Secured area start address for bank 2 16 12 UR11 UR11 SYSCFG user register 11 0x32C 0x20 read-only 0x00000000 SA_END_2 Secured area end address for bank 2 0 12 IWDG1M Independent Watchdog 1 mode 16 1 UR12 UR12 SYSCFG user register 12 0x330 0x20 read-only 0x00000000 SECURE Secure mode 16 1 UR13 UR13 SYSCFG user register 13 0x334 0x20 read-only 0x00000000 SDRS Secured DTCM RAM Size 0 2 D1SBRST D1 Standby reset 16 1 UR14 UR14 SYSCFG user register 14 0x338 0x20 read-write 0x00000000 D1STPRST D1 Stop Reset 0 1 UR15 UR15 SYSCFG user register 15 0x33C 0x20 read-only 0x00000000 FZIWDGSTB Freeze independent watchdog in Standby mode 16 1 UR16 UR16 SYSCFG user register 16 0x340 0x20 read-only 0x00000000 FZIWDGSTP Freeze independent watchdog in Stop mode 0 1 PKP Private key programmed 16 1 UR17 UR17 SYSCFG user register 17 0x344 0x20 read-only 0x00000000 IO_HSLV I/O high speed / low voltage 0 1 EXTI External interrupt/event controller EXTI 0x58000000 0x0 0x400 registers PVD_PVM PVD through EXTI line 1 EXTI0 EXTI Line 0 interrupt 6 EXTI1 EXTI Line 1 interrupt 7 EXTI2 EXTI Line 2 interrupt 8 EXTI3 EXTI Line 3interrupt 9 EXTI4 EXTI Line 4interrupt 10 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI15_10 EXTI Line[15:10] interrupts 40 FPU CPU FPU interrupt 81 WKUP WKUP1 to WKUP6 pins 149 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 TR0 Rising trigger event configuration bit of Configurable Event input 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 TR1 Rising trigger event configuration bit of Configurable Event input 1 1 TR2 Rising trigger event configuration bit of Configurable Event input 2 1 TR3 Rising trigger event configuration bit of Configurable Event input 3 1 TR4 Rising trigger event configuration bit of Configurable Event input 4 1 TR5 Rising trigger event configuration bit of Configurable Event input 5 1 TR6 Rising trigger event configuration bit of Configurable Event input 6 1 TR7 Rising trigger event configuration bit of Configurable Event input 7 1 TR8 Rising trigger event configuration bit of Configurable Event input 8 1 TR9 Rising trigger event configuration bit of Configurable Event input 9 1 TR10 Rising trigger event configuration bit of Configurable Event input 10 1 TR11 Rising trigger event configuration bit of Configurable Event input 11 1 TR12 Rising trigger event configuration bit of Configurable Event input 12 1 TR13 Rising trigger event configuration bit of Configurable Event input 13 1 TR14 Rising trigger event configuration bit of Configurable Event input 14 1 TR15 Rising trigger event configuration bit of Configurable Event input 15 1 TR16 Rising trigger event configuration bit of Configurable Event input 16 1 TR17 Rising trigger event configuration bit of Configurable Event input 17 1 TR18 Rising trigger event configuration bit of Configurable Event input 18 1 TR19 Rising trigger event configuration bit of Configurable Event input 19 1 TR20 Rising trigger event configuration bit of Configurable Event input 20 1 TR21 Rising trigger event configuration bit of Configurable Event input 21 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 TR0 Rising trigger event configuration bit of Configurable Event input 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 TR1 Rising trigger event configuration bit of Configurable Event input 1 1 TR2 Rising trigger event configuration bit of Configurable Event input 2 1 TR3 Rising trigger event configuration bit of Configurable Event input 3 1 TR4 Rising trigger event configuration bit of Configurable Event input 4 1 TR5 Rising trigger event configuration bit of Configurable Event input 5 1 TR6 Rising trigger event configuration bit of Configurable Event input 6 1 TR7 Rising trigger event configuration bit of Configurable Event input 7 1 TR8 Rising trigger event configuration bit of Configurable Event input 8 1 TR9 Rising trigger event configuration bit of Configurable Event input 9 1 TR10 Rising trigger event configuration bit of Configurable Event input 10 1 TR11 Rising trigger event configuration bit of Configurable Event input 11 1 TR12 Rising trigger event configuration bit of Configurable Event input 12 1 TR13 Rising trigger event configuration bit of Configurable Event input 13 1 TR14 Rising trigger event configuration bit of Configurable Event input 14 1 TR15 Rising trigger event configuration bit of Configurable Event input 15 1 TR16 Rising trigger event configuration bit of Configurable Event input 16 1 TR17 Rising trigger event configuration bit of Configurable Event input 17 1 TR18 Rising trigger event configuration bit of Configurable Event input 18 1 TR19 Rising trigger event configuration bit of Configurable Event input 19 1 TR20 Rising trigger event configuration bit of Configurable Event input 20 1 TR21 Rising trigger event configuration bit of Configurable Event input 21 1 SWIER1 SWIER1 EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWIER0 Rising trigger event configuration bit of Configurable Event input 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWIER1 Rising trigger event configuration bit of Configurable Event input 1 1 SWIER2 Rising trigger event configuration bit of Configurable Event input 2 1 SWIER3 Rising trigger event configuration bit of Configurable Event input 3 1 SWIER4 Rising trigger event configuration bit of Configurable Event input 4 1 SWIER5 Rising trigger event configuration bit of Configurable Event input 5 1 SWIER6 Rising trigger event configuration bit of Configurable Event input 6 1 SWIER7 Rising trigger event configuration bit of Configurable Event input 7 1 SWIER8 Rising trigger event configuration bit of Configurable Event input 8 1 SWIER9 Rising trigger event configuration bit of Configurable Event input 9 1 SWIER10 Rising trigger event configuration bit of Configurable Event input 10 1 SWIER11 Rising trigger event configuration bit of Configurable Event input 11 1 SWIER12 Rising trigger event configuration bit of Configurable Event input 12 1 SWIER13 Rising trigger event configuration bit of Configurable Event input 13 1 SWIER14 Rising trigger event configuration bit of Configurable Event input 14 1 SWIER15 Rising trigger event configuration bit of Configurable Event input 15 1 SWIER16 Rising trigger event configuration bit of Configurable Event input 16 1 SWIER17 Rising trigger event configuration bit of Configurable Event input 17 1 SWIER18 Rising trigger event configuration bit of Configurable Event input 18 1 SWIER19 Rising trigger event configuration bit of Configurable Event input 19 1 SWIER20 Rising trigger event configuration bit of Configurable Event input 20 1 SWIER21 Rising trigger event configuration bit of Configurable Event input 21 1 D3PMR1 D3PMR1 EXTI D3 pending mask register 0xC 0x20 read-write 0x00000000 MR0 Rising trigger event configuration bit of Configurable Event input 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR1 Rising trigger event configuration bit of Configurable Event input 1 1 MR2 Rising trigger event configuration bit of Configurable Event input 2 1 MR3 Rising trigger event configuration bit of Configurable Event input 3 1 MR4 Rising trigger event configuration bit of Configurable Event input 4 1 MR5 Rising trigger event configuration bit of Configurable Event input 5 1 MR6 Rising trigger event configuration bit of Configurable Event input 6 1 MR7 Rising trigger event configuration bit of Configurable Event input 7 1 MR8 Rising trigger event configuration bit of Configurable Event input 8 1 MR9 Rising trigger event configuration bit of Configurable Event input 9 1 MR10 Rising trigger event configuration bit of Configurable Event input 10 1 MR11 Rising trigger event configuration bit of Configurable Event input 11 1 MR12 Rising trigger event configuration bit of Configurable Event input 12 1 MR13 Rising trigger event configuration bit of Configurable Event input 13 1 MR14 Rising trigger event configuration bit of Configurable Event input 14 1 MR15 Rising trigger event configuration bit of Configurable Event input 15 1 MR19 Rising trigger event configuration bit of Configurable Event input 19 1 MR20 Rising trigger event configuration bit of Configurable Event input 20 1 MR21 Rising trigger event configuration bit of Configurable Event input 21 1 MR25 Rising trigger event configuration bit of Configurable Event input 25 1 D3PCR1L D3PCR1L EXTI D3 pending clear selection register low 0x10 0x20 read-write 0x00000000 PCS0 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 0 2 PCS0 DMA_CH6 DMA ch6 event selected as D3 domain pendclear source 0 DMA_CH7 DMA ch7 event selected as D3 domain pendclear source 1 LPTIM4 LPTIM4 out selected as D3 domain pendclear source 2 LPTIM5 LPTIM5 out selected as D3 domain pendclear source 3 PCS1 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 2 2 PCS2 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 4 2 PCS3 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 6 2 PCS4 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 8 2 PCS5 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 10 2 PCS6 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 12 2 PCS7 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 14 2 PCS8 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 16 2 PCS9 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 18 2 PCS10 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 20 2 PCS11 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 22 2 PCS12 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 24 2 PCS13 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 26 2 PCS14 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 28 2 PCS15 D3 Pending request clear input signal selection on Event input x = truncate (n/2) 30 2 D3PCR1H D3PCR1H EXTI D3 pending clear selection register high 0x14 0x20 read-write 0x00000000 PCS19 D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2) 6 2 PCS19 DMA_CH6 DMA ch6 event selected as D3 domain pendclear source 0 DMA_CH7 DMA ch7 event selected as D3 domain pendclear source 1 LPTIM4 LPTIM4 out selected as D3 domain pendclear source 2 LPTIM5 LPTIM5 out selected as D3 domain pendclear source 3 PCS20 D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2) 8 2 PCS21 D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2) 10 2 PCS25 D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2) 18 2 RTSR2 RTSR2 EXTI rising trigger selection register 0x20 0x20 read-write 0x00000000 TR49 Rising trigger event configuration bit of Configurable Event input x+32 17 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 TR51 Rising trigger event configuration bit of Configurable Event input x+32 19 1 FTSR2 FTSR2 EXTI falling trigger selection register 0x24 0x20 read-write 0x00000000 TR49 Falling trigger event configuration bit of Configurable Event input x+32 17 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 TR51 Falling trigger event configuration bit of Configurable Event input x+32 19 1 SWIER2 SWIER2 EXTI software interrupt event register 0x28 0x20 read-write 0x00000000 SWIER49 Software interrupt on line x+32 17 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWIER51 Software interrupt on line x+32 19 1 D3PMR2 D3PMR2 EXTI D3 pending mask register 0x2C 0x20 read-write 0x00000000 MR34 D3 Pending Mask on Event input x+32 2 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR35 D3 Pending Mask on Event input x+32 3 1 MR41 D3 Pending Mask on Event input x+32 9 1 MR48 D3 Pending Mask on Event input x+32 16 1 MR49 D3 Pending Mask on Event input x+32 17 1 MR50 D3 Pending Mask on Event input x+32 18 1 MR51 D3 Pending Mask on Event input x+32 19 1 MR52 D3 Pending Mask on Event input x+32 20 1 MR53 D3 Pending Mask on Event input x+32 21 1 D3PCR2L D3PCR2L EXTI D3 pending clear selection register low 0x30 0x20 read-write 0x00000000 PCS34 D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2) 4 2 PCS34 DMA_CH6 DMA ch6 event selected as D3 domain pendclear source 0 DMA_CH7 DMA ch7 event selected as D3 domain pendclear source 1 LPTIM4 LPTIM4 out selected as D3 domain pendclear source 2 LPTIM5 LPTIM5 out selected as D3 domain pendclear source 3 PCS35 D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2) 6 2 PCS41 D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2) 18 2 D3PCR2H D3PCR2H EXTI D3 pending clear selection register high 0x34 0x20 read-write 0x00000000 PCS48 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 0 2 PCS48 DMA_CH6 DMA ch6 event selected as D3 domain pendclear source 0 DMA_CH7 DMA ch7 event selected as D3 domain pendclear source 1 LPTIM4 LPTIM4 out selected as D3 domain pendclear source 2 LPTIM5 LPTIM5 out selected as D3 domain pendclear source 3 PCS49 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 2 2 PCS50 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 4 2 PCS51 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 6 2 PCS52 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 8 2 PCS53 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 10 2 RTSR3 RTSR3 EXTI rising trigger selection register 0x40 0x20 read-write 0x00000000 TR82 Rising trigger event configuration bit of Configurable Event input x+64 18 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 TR84 Rising trigger event configuration bit of Configurable Event input x+64 20 1 TR85 Rising trigger event configuration bit of Configurable Event input x+64 21 1 TR86 Rising trigger event configuration bit of Configurable Event input x+64 22 1 FTSR3 FTSR3 EXTI falling trigger selection register 0x44 0x20 read-write 0x00000000 TR82 Falling trigger event configuration bit of Configurable Event input x+64 18 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 TR84 Falling trigger event configuration bit of Configurable Event input x+64 20 1 TR85 Falling trigger event configuration bit of Configurable Event input x+64 21 1 TR86 Falling trigger event configuration bit of Configurable Event input x+64 22 1 SWIER3 SWIER3 EXTI software interrupt event register 0x48 0x20 read-write 0x00000000 SWIER82 Software interrupt on line x+64 18 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWIER84 Software interrupt on line x+64 20 1 SWIER85 Software interrupt on line x+64 21 1 SWIER86 Software interrupt on line x+64 22 1 D3PMR3 D3PMR3 EXTI D3 pending mask register 0x4C 0x20 read-write 0x00000000 MR88 D3 Pending Mask on Event input x+64 24 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 D3PCR3H D3PCR3H EXTI D3 pending clear selection register high 0x54 0x20 read-write 0x00000000 PCS88 D3 Pending request clear input signal selection on Event input x= truncate N+160/2 18 2 PCS88 DMA_CH6 DMA ch6 event selected as D3 domain pendclear source 0 DMA_CH7 DMA ch7 event selected as D3 domain pendclear source 1 LPTIM4 LPTIM4 out selected as D3 domain pendclear source 2 LPTIM5 LPTIM5 out selected as D3 domain pendclear source 3 CPUIMR1 CPUIMR1 EXTI interrupt mask register 0x80 0x20 read-write 0xFFC00000 MR0 Rising trigger event configuration bit of Configurable Event input 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR1 Rising trigger event configuration bit of Configurable Event input 1 1 MR2 Rising trigger event configuration bit of Configurable Event input 2 1 MR3 Rising trigger event configuration bit of Configurable Event input 3 1 MR4 Rising trigger event configuration bit of Configurable Event input 4 1 MR5 Rising trigger event configuration bit of Configurable Event input 5 1 MR6 Rising trigger event configuration bit of Configurable Event input 6 1 MR7 Rising trigger event configuration bit of Configurable Event input 7 1 MR8 Rising trigger event configuration bit of Configurable Event input 8 1 MR9 Rising trigger event configuration bit of Configurable Event input 9 1 MR10 Rising trigger event configuration bit of Configurable Event input 10 1 MR11 Rising trigger event configuration bit of Configurable Event input 11 1 MR12 Rising trigger event configuration bit of Configurable Event input 12 1 MR13 Rising trigger event configuration bit of Configurable Event input 13 1 MR14 Rising trigger event configuration bit of Configurable Event input 14 1 MR15 Rising trigger event configuration bit of Configurable Event input 15 1 MR16 Rising trigger event configuration bit of Configurable Event input 16 1 MR17 Rising trigger event configuration bit of Configurable Event input 17 1 MR18 Rising trigger event configuration bit of Configurable Event input 18 1 MR19 Rising trigger event configuration bit of Configurable Event input 19 1 MR20 Rising trigger event configuration bit of Configurable Event input 20 1 MR21 Rising trigger event configuration bit of Configurable Event input 21 1 MR22 Rising trigger event configuration bit of Configurable Event input 22 1 MR23 Rising trigger event configuration bit of Configurable Event input 23 1 MR24 Rising trigger event configuration bit of Configurable Event input 24 1 MR25 Rising trigger event configuration bit of Configurable Event input 25 1 MR26 Rising trigger event configuration bit of Configurable Event input 26 1 MR27 Rising trigger event configuration bit of Configurable Event input 27 1 MR28 Rising trigger event configuration bit of Configurable Event input 28 1 MR29 Rising trigger event configuration bit of Configurable Event input 29 1 MR30 Rising trigger event configuration bit of Configurable Event input 30 1 MR31 Rising trigger event configuration bit of Configurable Event input 31 1 CPUEMR1 CPUEMR1 EXTI event mask register 0x84 0x20 read-write 0x00000000 MR0 CPU Event mask on Event input x 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR1 CPU Event mask on Event input x 1 1 MR2 CPU Event mask on Event input x 2 1 MR3 CPU Event mask on Event input x 3 1 MR4 CPU Event mask on Event input x 4 1 MR5 CPU Event mask on Event input x 5 1 MR6 CPU Event mask on Event input x 6 1 MR7 CPU Event mask on Event input x 7 1 MR8 CPU Event mask on Event input x 8 1 MR9 CPU Event mask on Event input x 9 1 MR10 CPU Event mask on Event input x 10 1 MR11 CPU Event mask on Event input x 11 1 MR12 CPU Event mask on Event input x 12 1 MR13 CPU Event mask on Event input x 13 1 MR14 CPU Event mask on Event input x 14 1 MR15 CPU Event mask on Event input x 15 1 MR16 CPU Event mask on Event input x 16 1 MR17 CPU Event mask on Event input x 17 1 MR18 CPU Event mask on Event input x 18 1 MR19 CPU Event mask on Event input x 19 1 MR20 CPU Event mask on Event input x 20 1 MR21 CPU Event mask on Event input x 21 1 MR22 CPU Event mask on Event input x 22 1 MR23 CPU Event mask on Event input x 23 1 MR24 CPU Event mask on Event input x 24 1 MR25 CPU Event mask on Event input x 25 1 MR26 CPU Event mask on Event input x 26 1 MR27 CPU Event mask on Event input x 27 1 MR28 CPU Event mask on Event input x 28 1 MR29 CPU Event mask on Event input x 29 1 MR30 CPU Event mask on Event input x 30 1 MR31 CPU Event mask on Event input x 31 1 CPUPR1 CPUPR1 EXTI pending register 0x88 0x20 read-write 0x00000000 PR0 CPU Event mask on Event input x 0 1 oneToClear PR0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR0W write Clear Clears pending bit 1 PR1 CPU Event mask on Event input x 1 1 oneToClear read write PR2 CPU Event mask on Event input x 2 1 oneToClear read write PR3 CPU Event mask on Event input x 3 1 oneToClear read write PR4 CPU Event mask on Event input x 4 1 oneToClear read write PR5 CPU Event mask on Event input x 5 1 oneToClear read write PR6 CPU Event mask on Event input x 6 1 oneToClear read write PR7 CPU Event mask on Event input x 7 1 oneToClear read write PR8 CPU Event mask on Event input x 8 1 oneToClear read write PR9 CPU Event mask on Event input x 9 1 oneToClear read write PR10 CPU Event mask on Event input x 10 1 oneToClear read write PR11 CPU Event mask on Event input x 11 1 oneToClear read write PR12 CPU Event mask on Event input x 12 1 oneToClear read write PR13 CPU Event mask on Event input x 13 1 oneToClear read write PR14 CPU Event mask on Event input x 14 1 oneToClear read write PR15 CPU Event mask on Event input x 15 1 oneToClear read write PR16 CPU Event mask on Event input x 16 1 oneToClear read write PR17 CPU Event mask on Event input x 17 1 oneToClear read write PR18 CPU Event mask on Event input x 18 1 oneToClear read write PR19 CPU Event mask on Event input x 19 1 oneToClear read write PR20 CPU Event mask on Event input x 20 1 oneToClear read write PR21 CPU Event mask on Event input x 21 1 oneToClear read write CPUIMR2 CPUIMR2 EXTI interrupt mask register 0x90 0x20 read-write 0x00000000 MR0 CPU Interrupt Mask on Direct Event input x+32 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR1 CPU Interrupt Mask on Direct Event input x+32 1 1 MR2 CPU Interrupt Mask on Direct Event input x+32 2 1 MR3 CPU Interrupt Mask on Direct Event input x+32 3 1 MR4 CPU Interrupt Mask on Direct Event input x+32 4 1 MR5 CPU Interrupt Mask on Direct Event input x+32 5 1 MR6 CPU Interrupt Mask on Direct Event input x+32 6 1 MR7 CPU Interrupt Mask on Direct Event input x+32 7 1 MR8 CPU Interrupt Mask on Direct Event input x+32 8 1 MR9 CPU Interrupt Mask on Direct Event input x+32 9 1 MR10 CPU Interrupt Mask on Direct Event input x+32 10 1 MR11 CPU Interrupt Mask on Direct Event input x+32 11 1 MR12 CPU Interrupt Mask on Direct Event input x+32 12 1 MR14 CPU Interrupt Mask on Direct Event input x+32 14 1 MR15 CPU Interrupt Mask on Direct Event input x+32 15 1 MR16 CPU Interrupt Mask on Direct Event input x+32 16 1 MR17 CPU Interrupt Mask on Direct Event input x+32 17 1 MR18 CPU Interrupt Mask on Direct Event input x+32 18 1 MR19 CPU Interrupt Mask on Direct Event input x+32 19 1 MR20 CPU Interrupt Mask on Direct Event input x+32 20 1 MR21 CPU Interrupt Mask on Direct Event input x+32 21 1 MR22 CPU Interrupt Mask on Direct Event input x+32 22 1 MR23 CPU Interrupt Mask on Direct Event input x+32 23 1 MR24 CPU Interrupt Mask on Direct Event input x+32 24 1 MR25 CPU Interrupt Mask on Direct Event input x+32 25 1 MR26 CPU Interrupt Mask on Direct Event input x+32 26 1 MR27 CPU Interrupt Mask on Direct Event input x+32 27 1 MR28 CPU Interrupt Mask on Direct Event input x+32 28 1 MR29 CPU Interrupt Mask on Direct Event input x+32 29 1 MR30 CPU Interrupt Mask on Direct Event input x+32 30 1 MR31 CPU Interrupt Mask on Direct Event input x+32 31 1 CPUEMR2 CPUEMR2 EXTI event mask register 0x94 0x20 read-write 0x00000000 MR32 CPU Interrupt Mask on Direct Event input x+32 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR33 CPU Interrupt Mask on Direct Event input x+32 1 1 MR34 CPU Interrupt Mask on Direct Event input x+32 2 1 MR35 CPU Interrupt Mask on Direct Event input x+32 3 1 MR36 CPU Interrupt Mask on Direct Event input x+32 4 1 MR37 CPU Interrupt Mask on Direct Event input x+32 5 1 MR38 CPU Interrupt Mask on Direct Event input x+32 6 1 MR39 CPU Interrupt Mask on Direct Event input x+32 7 1 MR40 CPU Interrupt Mask on Direct Event input x+32 8 1 MR41 CPU Interrupt Mask on Direct Event input x+32 9 1 MR42 CPU Interrupt Mask on Direct Event input x+32 10 1 MR43 CPU Interrupt Mask on Direct Event input x+32 11 1 MR44 CPU Interrupt Mask on Direct Event input x+32 12 1 MR46 CPU Interrupt Mask on Direct Event input x+32 14 1 MR47 CPU Interrupt Mask on Direct Event input x+32 15 1 MR48 CPU Interrupt Mask on Direct Event input x+32 16 1 MR49 CPU Interrupt Mask on Direct Event input x+32 17 1 MR50 CPU Interrupt Mask on Direct Event input x+32 18 1 MR51 CPU Interrupt Mask on Direct Event input x+32 19 1 MR52 CPU Interrupt Mask on Direct Event input x+32 20 1 MR53 CPU Interrupt Mask on Direct Event input x+32 21 1 MR54 CPU Interrupt Mask on Direct Event input x+32 22 1 MR55 CPU Interrupt Mask on Direct Event input x+32 23 1 MR56 CPU Interrupt Mask on Direct Event input x+32 24 1 MR57 CPU Interrupt Mask on Direct Event input x+32 25 1 MR58 CPU Interrupt Mask on Direct Event input x+32 26 1 MR59 CPU Interrupt Mask on Direct Event input x+32 27 1 MR60 CPU Interrupt Mask on Direct Event input x+32 28 1 MR61 CPU Interrupt Mask on Direct Event input x+32 29 1 MR62 CPU Interrupt Mask on Direct Event input x+32 30 1 MR63 CPU Interrupt Mask on Direct Event input x+32 31 1 CPUPR2 CPUPR2 EXTI pending register 0x98 0x20 read-write 0x00000000 PR49 Configurable event inputs x+32 Pending bit 17 1 oneToClear PR49R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR49W write Clear Clears pending bit 1 PR51 Configurable event inputs x+32 Pending bit 19 1 oneToClear read write CPUIMR3 CPUIMR3 EXTI interrupt mask register 0xA0 0x20 read-write 0x00000000 MR64 CPU Interrupt Mask on Direct Event input x+64 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 MR65 CPU Interrupt Mask on Direct Event input x+64 1 1 MR66 CPU Interrupt Mask on Direct Event input x+64 2 1 MR67 CPU Interrupt Mask on Direct Event input x+64 3 1 MR68 CPU Interrupt Mask on Direct Event input x+64 4 1 MR69 CPU Interrupt Mask on Direct Event input x+64 5 1 MR70 CPU Interrupt Mask on Direct Event input x+64 6 1 MR71 CPU Interrupt Mask on Direct Event input x+64 7 1 MR72 CPU Interrupt Mask on Direct Event input x+64 8 1 MR73 CPU Interrupt Mask on Direct Event input x+64 9 1 MR74 CPU Interrupt Mask on Direct Event input x+64 10 1 MR75 CPU Interrupt Mask on Direct Event input x+64 11 1 MR76 CPU Interrupt Mask on Direct Event input x+64 12 1 MR77 CPU Interrupt Mask on Direct Event input x+64 13 1 MR78 CPU Interrupt Mask on Direct Event input x+64 14 1 MR79 CPU Interrupt Mask on Direct Event input x+64 15 1 MR80 CPU Interrupt Mask on Direct Event input x+64 16 1 MR82 CPU Interrupt Mask on Direct Event input x+64 18 1 MR84 CPU Interrupt Mask on Direct Event input x+64 20 1 MR85 CPU Interrupt Mask on Direct Event input x+64 21 1 MR86 CPU Interrupt Mask on Direct Event input x+64 22 1 MR87 CPU Interrupt Mask on Direct Event input x+64 23 1 MR88 CPU Interrupt Mask on Direct Event input x+64 24 1 CPUEMR3 CPUEMR3 EXTI event mask register 0xA4 0x20 read-write 0x00000000 MR64 CPU Event mask on Event input x+64 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 MR65 CPU Event mask on Event input x+64 1 1 MR66 CPU Event mask on Event input x+64 2 1 MR67 CPU Event mask on Event input x+64 3 1 MR68 CPU Event mask on Event input x+64 4 1 MR69 CPU Event mask on Event input x+64 5 1 MR70 CPU Event mask on Event input x+64 6 1 MR71 CPU Event mask on Event input x+64 7 1 MR72 CPU Event mask on Event input x+64 8 1 MR73 CPU Event mask on Event input x+64 9 1 MR74 CPU Event mask on Event input x+64 10 1 MR75 CPU Event mask on Event input x+64 11 1 MR76 CPU Event mask on Event input x+64 12 1 MR77 CPU Event mask on Event input x+64 13 1 MR78 CPU Event mask on Event input x+64 14 1 MR79 CPU Event mask on Event input x+64 15 1 MR80 CPU Event mask on Event input x+64 16 1 MR82 CPU Event mask on Event input x+64 18 1 MR84 CPU Event mask on Event input x+64 20 1 MR85 CPU Event mask on Event input x+64 21 1 MR86 CPU Event mask on Event input x+64 22 1 MR87 CPU Event mask on Event input x+64 23 1 MR88 CPU Event mask on Event input x+64 24 1 CPUPR3 CPUPR3 EXTI pending register 0xA8 0x20 read-write 0x00000000 PR82 Configurable event inputs x+64 Pending bit 18 1 oneToClear PR82R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PR82W write Clear Clears pending bit 1 PR84 Configurable event inputs x+64 Pending bit 20 1 oneToClear read write PR85 Configurable event inputs x+64 Pending bit 21 1 oneToClear read write PR86 Configurable event inputs x+64 Pending bit 22 1 oneToClear read write DELAY_Block_SDMMC1 DELAY_Block_SDMMC1 DLYB 0x52008000 0x0 0x8 registers CR CR DLYB control register 0x0 0x20 read-write 0x00000000 DEN Delay block enable bit 0 1 SEN Sampler length enable bit 1 1 CFGR CFGR DLYB configuration register 0x4 0x20 read-write 0x00000000 SEL Select the phase for the Output clock 0 4 UNIT Delay Defines the delay of a Unit delay cell 8 7 LNG Delay line length value 16 12 LNGF Length valid flag 31 1 DELAY_Block_QUADSPI 0x52006000 DELAY_Block_SDMMC2 0x48022800 FLASH Flash FLASH 0x52002000 0x0 0x1000 registers FLASH Flash memory 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000037 LATENCY Read latency 0 4 WRHIGHFREQ Flash signal delay 4 2 2 0x100 1-2 BANK%s Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R 0x4 KEYR KEYR1 FLASH key register for bank 1 0x0 0x20 write-only 0x00000000 KEY1R Bank 1 access configuration unlock key 0 32 CR CR1 FLASH control register for bank 1 0x8 0x20 read-write 0x00000000 LOCK Bank 1 configuration lock bit 0 1 PG Bank 1 program enable bit 1 1 SER Bank 1 sector erase request 2 1 BER Bank 1 erase request 3 1 PSIZE Bank 1 program size 4 2 FW Bank 1 write forcing control bit 6 1 START Bank 1 bank or sector erase start control bit 7 1 SNB Bank 1 sector erase selection number 8 3 CRC_EN Bank 1 CRC control bit 15 1 EOPIE Bank 1 end-of-program interrupt control bit 16 1 WRPERRIE Bank 1 write protection error interrupt enable bit 17 1 PGSERRIE Bank 1 programming sequence error interrupt enable bit 18 1 STRBERRIE Bank 1 strobe error interrupt enable bit 19 1 INCERRIE Bank 1 inconsistency error interrupt enable bit 21 1 OPERRIE Bank 1 write/erase error interrupt enable bit 22 1 RDPERRIE Bank 1 read protection error interrupt enable bit 23 1 RDSERRIE Bank 1 secure error interrupt enable bit 24 1 SNECCERR Bank 1 ECC single correction error interrupt enable bit 25 1 DBECCERRIE Bank 1 ECC double detection error interrupt enable bit 26 1 CRCENDIE Bank 1 end of CRC calculation interrupt enable bit 27 1 CRCRDERRIE Bank 1 CRC read error interrupt enable bit When CRCRDERRIE1 bit is set to 1, an interrupt is generated when a protected area (PCROP or secure-only) has been detected during the last CRC computation on bank 1. CRCRDERRIE1 can be programmed only when LOCK1 is cleared to 0. 28 1 read-write SPSS Bank 2 special sector selection bit 14 1 SR SR1 FLASH status register for bank 1 0xC 0x20 read-write 0x00000000 BSY Bank 1 ongoing program flag 0 1 WBNE Bank 1 write buffer not empty flag 1 1 QW Bank 1 wait queue flag 2 1 CRC_BUSY Bank 1 CRC busy flag 3 1 EOP Bank 1 end-of-program flag 16 1 WRPERR Bank 1 write protection error flag 17 1 PGSERR Bank 1 programming sequence error flag 18 1 STRBERR Bank 1 strobe error flag 19 1 INCERR Bank 1 inconsistency error flag 21 1 OPERR Bank 1 write/erase error flag 22 1 RDPERR Bank 1 read protection error flag 23 1 RDSERR Bank 1 secure error flag 24 1 SNECCERR Bank 1 single correction error flag 25 1 DBECCERR Bank 1 ECC double detection error flag 26 1 CRCEND Bank 1 CRC-complete flag 27 1 CCR CCR1 FLASH clear control register for bank 1 0x10 0x20 read-write 0x00000000 CLR_EOP Bank 1 EOP1 flag clear bit 16 1 CLR_WRPERR Bank 1 WRPERR1 flag clear bit 17 1 CLR_PGSERR Bank 1 PGSERR1 flag clear bi 18 1 CLR_STRBERR Bank 1 STRBERR1 flag clear bit 19 1 CLR_INCERR Bank 1 INCERR1 flag clear bit 21 1 CLR_OPERR Bank 1 OPERR1 flag clear bit 22 1 CLR_RDPERR Bank 1 RDPERR1 flag clear bit 23 1 CLR_RDSERR Bank 1 RDSERR1 flag clear bit 24 1 CLR_SNECCERR Bank 1 SNECCERR1 flag clear bit 25 1 CLR_DBECCERR Bank 1 DBECCERR1 flag clear bit 26 1 CLR_CRCEND Bank 1 CRCEND1 flag clear bit 27 1 PRAR_CUR PRAR_CUR1 FLASH protection address for bank 1 0x24 0x20 read-only 0x00000000 PROT_AREA_START Bank 1 lowest PCROP protected address 0 12 PROT_AREA_END Bank 1 highest PCROP protected address 16 12 DMEP Bank 1 PCROP protected erase enable option status bit 31 1 PRAR_PRG PRAR_PRG1 FLASH protection address for bank 1 0x28 0x20 read-write 0x00000000 PROT_AREA_START Bank 1 lowest PCROP protected address configuration 0 12 PROT_AREA_END Bank 1 highest PCROP protected address configuration 16 12 DMEP Bank 1 PCROP protected erase enable option configuration bit 31 1 SCAR_CUR SCAR_CUR1 FLASH secure address for bank 1 0x2C 0x20 read-write 0x00000000 SEC_AREA_START Bank 1 lowest secure protected address 0 12 SEC_AREA_END Bank 1 highest secure protected address 16 12 DMES Bank 1 secure protected erase enable option status bit 31 1 SCAR_PRG SCAR_PRG1 FLASH secure address for bank 1 0x30 0x20 read-write 0x00000000 SEC_AREA_START Bank 1 lowest secure protected address configuration 0 12 SEC_AREA_END Bank 1 highest secure protected address configuration 16 12 DMES Bank 1 secure protected erase enable option configuration bit 31 1 WPSN_CURR WPSN_CUR1R FLASH write sector protection for bank 1 0x34 0x20 read-only 0x00000000 WRPSn Bank 1 sector write protection option status byte 0 8 WPSN_PRGR WPSN_PRG1R FLASH write sector protection for bank 1 0x38 0x20 read-write 0x00000000 WRPSn Bank 1 sector write protection configuration byte 0 8 CRCCR CRCCR1 FLASH CRC control register for bank 1 0x4C 0x20 read-write 0x00000000 CRC_SECT Bank 1 CRC sector number 0 3 ALL_BANK Bank 1 CRC select bit 7 1 CRC_BY_SECT Bank 1 CRC sector mode select bit 8 1 ADD_SECT Bank 1 CRC sector select bit 9 1 CLEAN_SECT Bank 1 CRC sector list clear bit 10 1 START_CRC Bank 1 CRC start bit 16 1 CLEAN_CRC Bank 1 CRC clear bit 17 1 CRC_BURST Bank 1 CRC burst size 20 2 CRCSADDR CRCSADD1R FLASH CRC start address register for bank 1 0x50 0x20 read-write 0x00000000 CRC_START_ADDR CRC start address on bank 1 2 18 read-write CRCEADDR CRCEADD1R FLASH CRC end address register for bank 1 0x54 0x20 read-write 0x00000000 CRC_END_ADDR CRC end address on bank 1 2 18 read-write FAR ECC_FA1R FLASH ECC fail address for bank 1 0x5C 0x20 read-only 0x00000000 FAIL_ECC_ADDR Bank 1 ECC error address 0 15 OPTKEYR OPTKEYR FLASH option key register 0x8 0x20 write-only 0x00000000 OPTKEYR Unlock key option bytes 0 32 OPTCR OPTCR FLASH option control register 0x18 0x20 read-write 0x00000000 OPTLOCK FLASH_OPTCR lock option configuration bit 0 1 OPTSTART Option byte start change option configuration bit 1 1 MER Flash mass erase enable bit 4 1 OPTCHANGEERRIE Option byte change error interrupt enable bit 30 1 SWAP_BANK Bank swapping configuration bit 31 1 OPTSR_CUR OPTSR_CUR FLASH option status register 0x1C 0x20 read-write 0x00000000 OPT_BUSY Option byte change ongoing flag 0 1 BOR_LEV Brownout level option status bit 2 2 IWDG1_SW IWDG1 control option status bit 4 1 NRST_STOP_D1 D1 DStop entry reset option status bit 6 1 NRST_STBY_D1 D1 DStandby entry reset option status bit 7 1 RDP Readout protection level option status byte 8 8 IWDG_FZ_STOP IWDG Stop mode freeze option status bit 17 1 IWDG_FZ_SDBY IWDG Standby mode freeze option status bit 18 1 ST_RAM_SIZE DTCM RAM size option status 19 2 SECURITY Security enable option status bit 21 1 IO_HSLV I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) 29 1 OPTCHANGEERR Option byte change error flag 30 1 SWAP_BANK_OPT Bank swapping option status bit 31 1 OPTSR_PRG OPTSR_PRG FLASH option status register 0x20 0x20 read-write 0x00000000 BOR_LEV BOR reset level option configuration bits 2 2 IWDG1_SW IWDG1 option configuration bit 4 1 NRST_STOP_D1 Option byte erase after D1 DStop option configuration bit 6 1 NRST_STBY_D1 Option byte erase after D1 DStandby option configuration bit 7 1 RDP Readout protection level option configuration byte 8 8 IWDG_FZ_STOP IWDG Stop mode freeze option configuration bit 17 1 IWDG_FZ_SDBY IWDG Standby mode freeze option configuration bit 18 1 ST_RAM_SIZE DTCM size select option configuration bits 19 2 SECURITY Security option configuration bit 21 1 IO_HSLV I/O high-speed at low-voltage (PRODUCT_BELOW_25V) 29 1 SWAP_BANK_OPT Bank swapping option configuration bit 31 1 OPTCCR OPTCCR FLASH option clear control register 0x24 0x20 write-only 0x00000000 CLR_OPTCHANGEERR OPTCHANGEERR reset bit 30 1 BOOT_CURR BOOT_CURR FLASH register with boot address 0x40 0x20 read-only 0x00000000 BOOT_ADD0 Boot address 0 0 16 BOOT_ADD1 Boot address 1 16 16 BOOT_PRGR BOOT_PRGR FLASH register with boot address 0x44 0x20 read-write 0x00000000 BOOT_ADD0 Boot address 0 0 16 BOOT_ADD1 Boot address 1 16 16 CRCDATAR CRCDATAR FLASH CRC data register 0x5C 0x20 read-write 0x00000000 CRC_DATA CRC result 0 32 ACR_ ACR_ Access control register 0x100 0x20 read-write 0x00000037 LATENCY Read latency 0 4 WRHIGHFREQ Flash signal delay 4 2 OPTKEYR_ OPTKEYR_ FLASH option key register 0x108 0x20 read-write 0x00000000 OPTKEYR Unlock key option bytes 0 32 OPTCR_ OPTCR_ FLASH option control register 0x118 0x20 read-write 0x00000000 OPTLOCK FLASH_OPTCR lock option configuration bit 0 1 OPTSTART Option byte start change option configuration bit 1 1 MER Flash mass erase enable bit 4 1 OPTCHANGEERRIE Option byte change error interrupt enable bit 30 1 SWAP_BANK Bank swapping configuration bit 31 1 OPTSR_CUR_ OPTSR_CUR_ FLASH option status register 0x11C 0x20 read-write 0x00000000 OPT_BUSY Option byte change ongoing flag 0 1 BOR_LEV Brownout level option status bit 2 2 IWDG1_SW IWDG1 control option status bit 4 1 NRST_STOP_D1 D1 DStop entry reset option status bit 6 1 NRST_STBY_D1 D1 DStandby entry reset option status bit 7 1 RDP Readout protection level option status byte 8 8 IWDG_FZ_STOP IWDG Stop mode freeze option status bit 17 1 IWDG_FZ_SDBY IWDG Standby mode freeze option status bit 18 1 ST_RAM_SIZE DTCM RAM size option status 19 2 SECURITY Security enable option status bit 21 1 IO_HSLV I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) 29 1 OPTCHANGEERR Option byte change error flag 30 1 SWAP_BANK_OPT Bank swapping option status bit 31 1 OPTSR_PRG_ OPTSR_PRG_ FLASH option status register 0x120 0x20 read-write 0x00000000 BOR_LEV BOR reset level option configuration bits 2 2 IWDG1_SW IWDG1 option configuration bit 4 1 nRST_STOP Option byte erase after D1 DStop option configuration bit 6 1 nRST_STDY Option byte erase after D1 DStandby option configuration bit 7 1 RDP Readout protection level option configuration byte 8 8 FZ_IWDG_STOP IWDG Stop mode freeze option configuration bit 17 1 FZ_IWDG_SDBY IWDG Standby mode freeze option configuration bit 18 1 ST_RAM_SIZE DTCM size select option configuration bits 19 2 SECURITY Security option configuration bit 21 1 IO_HSLV I/O high-speed at low-voltage (PRODUCT_BELOW_25V) 29 1 SWAP_BANK_OPT Bank swapping option configuration bit 31 1 OPTCCR_ OPTCCR_ FLASH option clear control register 0x124 0x20 write-only 0x00000000 CLR_OPTCHANGEERR OPTCHANGEERR reset bit 30 1 BOOT_CURR_ BOOT_CURR_ FLASH register with boot address 0x140 0x20 read-only 0x00000000 BOOT_ADD0 Boot address 0 0 16 BOOT_ADD1 Boot address 1 16 16 BOOT_PRGR_ BOOT_PRGR_ FLASH register with boot address 0x144 0x20 read-only 0x00000000 BOOT_ADD0 Boot address 0 0 16 BOOT_ADD1 Boot address 1 16 16 CRCDATAR_ CRCDATAR_ FLASH CRC data register 0x15C 0x20 read-write 0x00000000 CRC_DATA CRC result 0 32 AXI AXI interconnect registers AXI 0x51000000 0x0 0x100000 registers PERIPH_ID_4 PERIPH_ID_4 AXI interconnect - peripheral ID4 register 0x1FD0 0x20 read-only 0x00000004 JEP106CON JEP106 continuation code 0 4 KCOUNT4 Register file size 4 4 PERIPH_ID_0 PERIPH_ID_0 AXI interconnect - peripheral ID0 register 0x1FE0 0x20 read-only 0x00000004 PARTNUM Peripheral part number bits 0 to 7 0 8 PERIPH_ID_1 PERIPH_ID_1 AXI interconnect - peripheral ID1 register 0x1FE4 0x20 read-only 0x00000004 PARTNUM Peripheral part number bits 8 to 11 0 4 JEP106I JEP106 identity bits 0 to 3 4 4 PERIPH_ID_2 PERIPH_ID_2 AXI interconnect - peripheral ID2 register 0x1FE8 0x20 read-only 0x00000004 JEP106ID JEP106 Identity bits 4 to 6 0 3 JEDEC JEP106 code flag 3 1 REVISION Peripheral revision number 4 4 PERIPH_ID_3 PERIPH_ID_3 AXI interconnect - peripheral ID3 register 0x1FEC 0x20 read-only 0x00000004 CUST_MOD_NUM Customer modification 0 4 REV_AND Customer version 4 4 COMP_ID_0 COMP_ID_0 AXI interconnect - component ID0 register 0x1FF0 0x20 read-only 0x00000004 PREAMBLE Preamble bits 0 to 7 0 8 COMP_ID_1 COMP_ID_1 AXI interconnect - component ID1 register 0x1FF4 0x20 read-only 0x00000004 PREAMBLE Preamble bits 8 to 11 0 4 CLASS Component class 4 4 COMP_ID_2 COMP_ID_2 AXI interconnect - component ID2 register 0x1FF8 0x20 read-only 0x00000004 PREAMBLE Preamble bits 12 to 19 0 8 COMP_ID_3 COMP_ID_3 AXI interconnect - component ID3 register 0x1FFC 0x20 read-only 0x00000004 PREAMBLE Preamble bits 20 to 27 0 8 TARG1_FN_MOD_ISS_BM TARG1_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x2008 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG2_FN_MOD_ISS_BM TARG2_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x3008 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG3_FN_MOD_ISS_BM TARG3_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x4008 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG4_FN_MOD_ISS_BM TARG4_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x5008 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG5_FN_MOD_ISS_BM TARG5_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x6008 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG6_FN_MOD_ISS_BM TARG6_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x7008 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG7_FN_MOD_ISS_BM TARG7_FN_MOD_ISS_BM AXI interconnect - TARG x bus matrix issuing functionality register 0x800C 0x20 read-write 0x00000004 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 WRITE_ISS_OVERRIDE Switch matrix write issuing override for target 1 1 TARG1_FN_MOD2 TARG1_FN_MOD2 AXI interconnect - TARG x bus matrix functionality 2 register 0x2024 0x20 read-write 0x00000004 BYPASS_MERGE Disable packing of beats to match the output data width 0 1 TARG2_FN_MOD2 TARG2_FN_MOD2 AXI interconnect - TARG x bus matrix functionality 2 register 0x3024 0x20 read-write 0x00000004 BYPASS_MERGE Disable packing of beats to match the output data width 0 1 TARG7_FN_MOD2 TARG7_FN_MOD2 AXI interconnect - TARG x bus matrix functionality 2 register 0x8024 0x20 read-write 0x00000004 BYPASS_MERGE Disable packing of beats to match the output data width 0 1 TARG1_FN_MOD_LB TARG1_FN_MOD_LB AXI interconnect - TARG x long burst functionality modification 0x202C 0x20 read-write 0x00000004 FN_MOD_LB Controls burst breaking of long bursts 0 1 TARG2_FN_MOD_LB TARG2_FN_MOD_LB AXI interconnect - TARG x long burst functionality modification 0x302C 0x20 read-write 0x00000004 FN_MOD_LB Controls burst breaking of long bursts 0 1 TARG1_FN_MOD TARG1_FN_MOD AXI interconnect - TARG x long burst functionality modification 0x2108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE Override AMIB write issuing capability 1 1 TARG2_FN_MOD TARG2_FN_MOD AXI interconnect - TARG x long burst functionality modification 0x3108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE Override AMIB write issuing capability 1 1 TARG7_FN_MOD TARG7_FN_MOD AXI interconnect - TARG x long burst functionality modification 0x8108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE Override AMIB write issuing capability 1 1 INI1_FN_MOD2 INI1_FN_MOD2 AXI interconnect - INI x functionality modification 2 register 0x42024 0x20 read-write 0x00000004 BYPASS_MERGE Disables alteration of transactions by the up-sizer unless required by the protocol 0 1 INI3_FN_MOD2 INI3_FN_MOD2 AXI interconnect - INI x functionality modification 2 register 0x44024 0x20 read-write 0x00000004 BYPASS_MERGE Disables alteration of transactions by the up-sizer unless required by the protocol 0 1 INI1_FN_MOD_AHB INI1_FN_MOD_AHB AXI interconnect - INI x AHB functionality modification register 0x42028 0x20 read-write 0x00000004 RD_INC_OVERRIDE Converts all AHB-Lite write transactions to a series of single beat AXI 0 1 WR_INC_OVERRIDE Converts all AHB-Lite read transactions to a series of single beat AXI 1 1 INI3_FN_MOD_AHB INI3_FN_MOD_AHB AXI interconnect - INI x AHB functionality modification register 0x44028 0x20 read-write 0x00000004 RD_INC_OVERRIDE Converts all AHB-Lite write transactions to a series of single beat AXI 0 1 WR_INC_OVERRIDE Converts all AHB-Lite read transactions to a series of single beat AXI 1 1 INI1_READ_QOS INI1_READ_QOS AXI interconnect - INI x read QoS register 0x42100 0x20 read-write 0x00000004 AR_QOS Read channel QoS setting 0 4 0 15 INI2_READ_QOS INI2_READ_QOS AXI interconnect - INI x read QoS register 0x43100 0x20 read-write 0x00000004 AR_QOS Read channel QoS setting 0 4 0 15 INI3_READ_QOS INI3_READ_QOS AXI interconnect - INI x read QoS register 0x44100 0x20 read-write 0x00000004 AR_QOS Read channel QoS setting 0 4 0 15 INI4_READ_QOS INI4_READ_QOS AXI interconnect - INI x read QoS register 0x45100 0x20 read-write 0x00000004 AR_QOS Read channel QoS setting 0 4 0 15 INI5_READ_QOS INI5_READ_QOS AXI interconnect - INI x read QoS register 0x46100 0x20 read-write 0x00000004 AR_QOS Read channel QoS setting 0 4 0 15 INI6_READ_QOS INI6_READ_QOS AXI interconnect - INI x read QoS register 0x47100 0x20 read-write 0x00000004 AR_QOS Read channel QoS setting 0 4 0 15 INI1_WRITE_QOS INI1_WRITE_QOS AXI interconnect - INI x write QoS register 0x42104 0x20 read-write 0x00000004 AW_QOS Write channel QoS setting 0 4 0 15 INI2_WRITE_QOS INI2_WRITE_QOS AXI interconnect - INI x write QoS register 0x43104 0x20 read-write 0x00000004 AW_QOS Write channel QoS setting 0 4 0 15 INI3_WRITE_QOS INI3_WRITE_QOS AXI interconnect - INI x write QoS register 0x44104 0x20 read-write 0x00000004 AW_QOS Write channel QoS setting 0 4 0 15 INI4_WRITE_QOS INI4_WRITE_QOS AXI interconnect - INI x write QoS register 0x45104 0x20 read-write 0x00000004 AW_QOS Write channel QoS setting 0 4 0 15 INI5_WRITE_QOS INI5_WRITE_QOS AXI interconnect - INI x write QoS register 0x46104 0x20 read-write 0x00000004 AW_QOS Write channel QoS setting 0 4 0 15 INI6_WRITE_QOS INI6_WRITE_QOS AXI interconnect - INI x write QoS register 0x47104 0x20 read-write 0x00000004 AW_QOS Write channel QoS setting 0 4 0 15 INI1_FN_MOD INI1_FN_MOD AXI interconnect - INI x issuing functionality modification register 0x42108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override ASIB read issuing capability 0 1 READ_ISS_OVERRIDE Normal Normal ASIB read issuing capability 0 Force1 Force ASIB read issuing capability to 1 1 WRITE_ISS_OVERRIDE Override ASIB write issuing capability 1 1 WRITE_ISS_OVERRIDE Normal Normal ASIB write issuing capability 0 Force1 Force ASIB write issuing capability to 1 1 INI2_FN_MOD INI2_FN_MOD AXI interconnect - INI x issuing functionality modification register 0x43108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override ASIB read issuing capability 0 1 READ_ISS_OVERRIDE Normal Normal ASIB read issuing capability 0 Force1 Force ASIB read issuing capability to 1 1 WRITE_ISS_OVERRIDE Override ASIB write issuing capability 1 1 WRITE_ISS_OVERRIDE Normal Normal ASIB write issuing capability 0 Force1 Force ASIB write issuing capability to 1 1 INI3_FN_MOD INI3_FN_MOD AXI interconnect - INI x issuing functionality modification register 0x44108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override ASIB read issuing capability 0 1 READ_ISS_OVERRIDE Normal Normal ASIB read issuing capability 0 Force1 Force ASIB read issuing capability to 1 1 WRITE_ISS_OVERRIDE Override ASIB write issuing capability 1 1 WRITE_ISS_OVERRIDE Normal Normal ASIB write issuing capability 0 Force1 Force ASIB write issuing capability to 1 1 INI4_FN_MOD INI4_FN_MOD AXI interconnect - INI x issuing functionality modification register 0x45108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override ASIB read issuing capability 0 1 READ_ISS_OVERRIDE Normal Normal ASIB read issuing capability 0 Force1 Force ASIB read issuing capability to 1 1 WRITE_ISS_OVERRIDE Override ASIB write issuing capability 1 1 WRITE_ISS_OVERRIDE Normal Normal ASIB write issuing capability 0 Force1 Force ASIB write issuing capability to 1 1 INI5_FN_MOD INI5_FN_MOD AXI interconnect - INI x issuing functionality modification register 0x46108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override ASIB read issuing capability 0 1 READ_ISS_OVERRIDE Normal Normal ASIB read issuing capability 0 Force1 Force ASIB read issuing capability to 1 1 WRITE_ISS_OVERRIDE Override ASIB write issuing capability 1 1 WRITE_ISS_OVERRIDE Normal Normal ASIB write issuing capability 0 Force1 Force ASIB write issuing capability to 1 1 INI6_FN_MOD INI6_FN_MOD AXI interconnect - INI x issuing functionality modification register 0x47108 0x20 read-write 0x00000004 READ_ISS_OVERRIDE Override ASIB read issuing capability 0 1 READ_ISS_OVERRIDE Normal Normal ASIB read issuing capability 0 Force1 Force ASIB read issuing capability to 1 1 WRITE_ISS_OVERRIDE Override ASIB write issuing capability 1 1 WRITE_ISS_OVERRIDE Normal Normal ASIB write issuing capability 0 Force1 Force ASIB write issuing capability to 1 1 HASH Hash processor HASH 0x48021400 0x0 0x400 registers HASH_RNG HASH and RNG 80 CR CR control register 0x0 0x20 0x00000000 INIT Initialize message digest calculation 2 1 write-only DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write ALGO0 Algorithm selection 7 1 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA Transfers 13 1 read-write LKEY Long key selection 16 1 read-write ALGO1 ALGO 18 1 read-write DIN DIN data input register 0x4 0x20 read-write 0x00000000 DATAIN Data input 0 32 STR STR start register 0x8 0x20 0x00000000 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write 5 0x4 0-4 HR%s HR%s digest registers 0xC 0x20 read-only 0x00000000 H H0 0 32 IMR IMR interrupt enable register 0x20 0x20 read-write 0x00000000 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 0x20 0x00000001 BUSY Busy bit 3 1 read-only DMAS DMA Status 2 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write 54 0x4 0-53 CSR%s CSR%s context swap registers 0xF8 0x20 read-write 0x00000000 CSR CSR0 0 32 8 0x4 0-7 HASH_HR%s HASH_HR%s HASH digest register %s 0x310 0x20 read-only 0x00000000 H H0 0 32 CRYP Cryptographic processor CRYP 0x48021000 0x0 0x400 registers CRYP CRYP global interrupt 79 CR CR control register 0x0 0x20 0x00000000 ALGODIR Algorithm direction 2 1 read-write ALGOMODE0 Algorithm mode 3 3 read-write DATATYPE Data type selection 6 2 read-write KEYSIZE Key size selection (AES mode only) 8 2 read-write FFLUSH FIFO flush 14 1 write-only CRYPEN Cryptographic processor enable 15 1 read-write GCM_CCMPH GCM_CCMPH 16 2 read-write ALGOMODE3 ALGOMODE 19 1 read-write SR SR status register 0x4 0x20 read-only 0x00000003 BUSY Busy bit 4 1 OFFU Output FIFO full 3 1 OFNE Output FIFO not empty 2 1 IFNF Input FIFO not full 1 1 IFEM Input FIFO empty 0 1 DIN DIN data input register 0x8 0x20 read-write 0x00000000 DATAIN Data input 0 32 DOUT DOUT data output register 0xC 0x20 read-only 0x00000000 DATAOUT Data output 0 32 DMACR DMACR DMA control register 0x10 0x20 read-write 0x00000000 DOEN DMA output enable 1 1 DIEN DMA input enable 0 1 IMSCR IMSCR interrupt mask set/clear register 0x14 0x20 read-write 0x00000000 OUTIM Output FIFO service interrupt mask 1 1 INIM Input FIFO service interrupt mask 0 1 RISR RISR raw interrupt status register 0x18 0x20 read-only 0x00000001 OUTRIS Output FIFO service raw interrupt status 1 1 INRIS Input FIFO service raw interrupt status 0 1 MISR MISR masked interrupt status register 0x1C 0x20 read-only 0x00000000 OUTMIS Output FIFO service masked interrupt status 1 1 INMIS Input FIFO service masked interrupt status 0 1 K0LR K0LR key registers 0x20 0x20 write-only 0x00000000 b224 b224 0 1 b225 b225 1 1 b226 b226 2 1 b227 b227 3 1 b228 b228 4 1 b229 b229 5 1 b230 b230 6 1 b231 b231 7 1 b232 b232 8 1 b233 b233 9 1 b234 b234 10 1 b235 b235 11 1 b236 b236 12 1 b237 b237 13 1 b238 b238 14 1 b239 b239 15 1 b240 b240 16 1 b241 b241 17 1 b242 b242 18 1 b243 b243 19 1 b244 b244 20 1 b245 b245 21 1 b246 b246 22 1 b247 b247 23 1 b248 b248 24 1 b249 b249 25 1 b250 b250 26 1 b251 b251 27 1 b252 b252 28 1 b253 b253 29 1 b254 b254 30 1 b255 b255 31 1 K0RR K0RR key registers 0x24 0x20 write-only 0x00000000 b192 b192 0 1 b193 b193 1 1 b194 b194 2 1 b195 b195 3 1 b196 b196 4 1 b197 b197 5 1 b198 b198 6 1 b199 b199 7 1 b200 b200 8 1 b201 b201 9 1 b202 b202 10 1 b203 b203 11 1 b204 b204 12 1 b205 b205 13 1 b206 b206 14 1 b207 b207 15 1 b208 b208 16 1 b209 b209 17 1 b210 b210 18 1 b211 b211 19 1 b212 b212 20 1 b213 b213 21 1 b214 b214 22 1 b215 b215 23 1 b216 b216 24 1 b217 b217 25 1 b218 b218 26 1 b219 b219 27 1 b220 b220 28 1 b221 b221 29 1 b222 b222 30 1 b223 b223 31 1 K1LR K1LR key registers 0x28 0x20 write-only 0x00000000 b160 b160 0 1 b161 b161 1 1 b162 b162 2 1 b163 b163 3 1 b164 b164 4 1 b165 b165 5 1 b166 b166 6 1 b167 b167 7 1 b168 b168 8 1 b169 b169 9 1 b170 b170 10 1 b171 b171 11 1 b172 b172 12 1 b173 b173 13 1 b174 b174 14 1 b175 b175 15 1 b176 b176 16 1 b177 b177 17 1 b178 b178 18 1 b179 b179 19 1 b180 b180 20 1 b181 b181 21 1 b182 b182 22 1 b183 b183 23 1 b184 b184 24 1 b185 b185 25 1 b186 b186 26 1 b187 b187 27 1 b188 b188 28 1 b189 b189 29 1 b190 b190 30 1 b191 b191 31 1 K1RR K1RR key registers 0x2C 0x20 write-only 0x00000000 b128 b128 0 1 b129 b129 1 1 b130 b130 2 1 b131 b131 3 1 b132 b132 4 1 b133 b133 5 1 b134 b134 6 1 b135 b135 7 1 b136 b136 8 1 b137 b137 9 1 b138 b138 10 1 b139 b139 11 1 b140 b140 12 1 b141 b141 13 1 b142 b142 14 1 b143 b143 15 1 b144 b144 16 1 b145 b145 17 1 b146 b146 18 1 b147 b147 19 1 b148 b148 20 1 b149 b149 21 1 b150 b150 22 1 b151 b151 23 1 b152 b152 24 1 b153 b153 25 1 b154 b154 26 1 b155 b155 27 1 b156 b156 28 1 b157 b157 29 1 b158 b158 30 1 b159 b159 31 1 K2LR K2LR key registers 0x30 0x20 write-only 0x00000000 b96 b96 0 1 b97 b97 1 1 b98 b98 2 1 b99 b99 3 1 b100 b100 4 1 b101 b101 5 1 b102 b102 6 1 b103 b103 7 1 b104 b104 8 1 b105 b105 9 1 b106 b106 10 1 b107 b107 11 1 b108 b108 12 1 b109 b109 13 1 b110 b110 14 1 b111 b111 15 1 b112 b112 16 1 b113 b113 17 1 b114 b114 18 1 b115 b115 19 1 b116 b116 20 1 b117 b117 21 1 b118 b118 22 1 b119 b119 23 1 b120 b120 24 1 b121 b121 25 1 b122 b122 26 1 b123 b123 27 1 b124 b124 28 1 b125 b125 29 1 b126 b126 30 1 b127 b127 31 1 K2RR K2RR key registers 0x34 0x20 write-only 0x00000000 b64 b64 0 1 b65 b65 1 1 b66 b66 2 1 b67 b67 3 1 b68 b68 4 1 b69 b69 5 1 b70 b70 6 1 b71 b71 7 1 b72 b72 8 1 b73 b73 9 1 b74 b74 10 1 b75 b75 11 1 b76 b76 12 1 b77 b77 13 1 b78 b78 14 1 b79 b79 15 1 b80 b80 16 1 b81 b81 17 1 b82 b82 18 1 b83 b83 19 1 b84 b84 20 1 b85 b85 21 1 b86 b86 22 1 b87 b87 23 1 b88 b88 24 1 b89 b89 25 1 b90 b90 26 1 b91 b91 27 1 b92 b92 28 1 b93 b93 29 1 b94 b94 30 1 b95 b95 31 1 K3LR K3LR key registers 0x38 0x20 write-only 0x00000000 b32 b32 0 1 b33 b33 1 1 b34 b34 2 1 b35 b35 3 1 b36 b36 4 1 b37 b37 5 1 b38 b38 6 1 b39 b39 7 1 b40 b40 8 1 b41 b41 9 1 b42 b42 10 1 b43 b43 11 1 b44 b44 12 1 b45 b45 13 1 b46 b46 14 1 b47 b47 15 1 b48 b48 16 1 b49 b49 17 1 b50 b50 18 1 b51 b51 19 1 b52 b52 20 1 b53 b53 21 1 b54 b54 22 1 b55 b55 23 1 b56 b56 24 1 b57 b57 25 1 b58 b58 26 1 b59 b59 27 1 b60 b60 28 1 b61 b61 29 1 b62 b62 30 1 b63 b63 31 1 K3RR K3RR key registers 0x3C 0x20 write-only 0x00000000 b0 b0 0 1 b1 b1 1 1 b2 b2 2 1 b3 b3 3 1 b4 b4 4 1 b5 b5 5 1 b6 b6 6 1 b7 b7 7 1 b8 b8 8 1 b9 b9 9 1 b10 b10 10 1 b11 b11 11 1 b12 b12 12 1 b13 b13 13 1 b14 b14 14 1 b15 b15 15 1 b16 b16 16 1 b17 b17 17 1 b18 b18 18 1 b19 b19 19 1 b20 b20 20 1 b21 b21 21 1 b22 b22 22 1 b23 b23 23 1 b24 b24 24 1 b25 b25 25 1 b26 b26 26 1 b27 b27 27 1 b28 b28 28 1 b29 b29 29 1 b30 b30 30 1 b31 b31 31 1 IV0LR IV0LR initialization vector registers 0x40 0x20 read-write 0x00000000 IV31 IV31 0 1 IV30 IV30 1 1 IV29 IV29 2 1 IV28 IV28 3 1 IV27 IV27 4 1 IV26 IV26 5 1 IV25 IV25 6 1 IV24 IV24 7 1 IV23 IV23 8 1 IV22 IV22 9 1 IV21 IV21 10 1 IV20 IV20 11 1 IV19 IV19 12 1 IV18 IV18 13 1 IV17 IV17 14 1 IV16 IV16 15 1 IV15 IV15 16 1 IV14 IV14 17 1 IV13 IV13 18 1 IV12 IV12 19 1 IV11 IV11 20 1 IV10 IV10 21 1 IV9 IV9 22 1 IV8 IV8 23 1 IV7 IV7 24 1 IV6 IV6 25 1 IV5 IV5 26 1 IV4 IV4 27 1 IV3 IV3 28 1 IV2 IV2 29 1 IV1 IV1 30 1 IV0 IV0 31 1 IV0RR IV0RR initialization vector registers 0x44 0x20 read-write 0x00000000 IV63 IV63 0 1 IV62 IV62 1 1 IV61 IV61 2 1 IV60 IV60 3 1 IV59 IV59 4 1 IV58 IV58 5 1 IV57 IV57 6 1 IV56 IV56 7 1 IV55 IV55 8 1 IV54 IV54 9 1 IV53 IV53 10 1 IV52 IV52 11 1 IV51 IV51 12 1 IV50 IV50 13 1 IV49 IV49 14 1 IV48 IV48 15 1 IV47 IV47 16 1 IV46 IV46 17 1 IV45 IV45 18 1 IV44 IV44 19 1 IV43 IV43 20 1 IV42 IV42 21 1 IV41 IV41 22 1 IV40 IV40 23 1 IV39 IV39 24 1 IV38 IV38 25 1 IV37 IV37 26 1 IV36 IV36 27 1 IV35 IV35 28 1 IV34 IV34 29 1 IV33 IV33 30 1 IV32 IV32 31 1 IV1LR IV1LR initialization vector registers 0x48 0x20 read-write 0x00000000 IV95 IV95 0 1 IV94 IV94 1 1 IV93 IV93 2 1 IV92 IV92 3 1 IV91 IV91 4 1 IV90 IV90 5 1 IV89 IV89 6 1 IV88 IV88 7 1 IV87 IV87 8 1 IV86 IV86 9 1 IV85 IV85 10 1 IV84 IV84 11 1 IV83 IV83 12 1 IV82 IV82 13 1 IV81 IV81 14 1 IV80 IV80 15 1 IV79 IV79 16 1 IV78 IV78 17 1 IV77 IV77 18 1 IV76 IV76 19 1 IV75 IV75 20 1 IV74 IV74 21 1 IV73 IV73 22 1 IV72 IV72 23 1 IV71 IV71 24 1 IV70 IV70 25 1 IV69 IV69 26 1 IV68 IV68 27 1 IV67 IV67 28 1 IV66 IV66 29 1 IV65 IV65 30 1 IV64 IV64 31 1 IV1RR IV1RR initialization vector registers 0x4C 0x20 read-write 0x00000000 IV127 IV127 0 1 IV126 IV126 1 1 IV125 IV125 2 1 IV124 IV124 3 1 IV123 IV123 4 1 IV122 IV122 5 1 IV121 IV121 6 1 IV120 IV120 7 1 IV119 IV119 8 1 IV118 IV118 9 1 IV117 IV117 10 1 IV116 IV116 11 1 IV115 IV115 12 1 IV114 IV114 13 1 IV113 IV113 14 1 IV112 IV112 15 1 IV111 IV111 16 1 IV110 IV110 17 1 IV109 IV109 18 1 IV108 IV108 19 1 IV107 IV107 20 1 IV106 IV106 21 1 IV105 IV105 22 1 IV104 IV104 23 1 IV103 IV103 24 1 IV102 IV102 25 1 IV101 IV101 26 1 IV100 IV100 27 1 IV99 IV99 28 1 IV98 IV98 29 1 IV97 IV97 30 1 IV96 IV96 31 1 CSGCMCCM0R CSGCMCCM0R context swap register 0x50 0x20 read-write 0x00000000 CSGCMCCM0R CSGCMCCM0R 0 32 CSGCMCCM1R CSGCMCCM1R context swap register 0x54 0x20 read-write 0x00000000 CSGCMCCM1R CSGCMCCM1R 0 32 CSGCMCCM2R CSGCMCCM2R context swap register 0x58 0x20 read-write 0x00000000 CSGCMCCM2R CSGCMCCM2R 0 32 CSGCMCCM3R CSGCMCCM3R context swap register 0x5C 0x20 read-write 0x00000000 CSGCMCCM3R CSGCMCCM3R 0 32 CSGCMCCM4R CSGCMCCM4R context swap register 0x60 0x20 read-write 0x00000000 CSGCMCCM4R CSGCMCCM4R 0 32 CSGCMCCM5R CSGCMCCM5R context swap register 0x64 0x20 read-write 0x00000000 CSGCMCCM5R CSGCMCCM5R 0 32 CSGCMCCM6R CSGCMCCM6R context swap register 0x68 0x20 read-write 0x00000000 CSGCMCCM6R CSGCMCCM6R 0 32 CSGCMCCM7R CSGCMCCM7R context swap register 0x6C 0x20 read-write 0x00000000 CSGCMCCM7R CSGCMCCM7R 0 32 CSGCM0R CSGCM0R context swap register 0x70 0x20 read-write 0x00000000 CSGCM0R CSGCM0R 0 32 CSGCM1R CSGCM1R context swap register 0x74 0x20 read-write 0x00000000 CSGCM1R CSGCM1R 0 32 CSGCM2R CSGCM2R context swap register 0x78 0x20 read-write 0x00000000 CSGCM2R CSGCM2R 0 32 CSGCM3R CSGCM3R context swap register 0x7C 0x20 read-write 0x00000000 CSGCM3R CSGCM3R 0 32 CSGCM4R CSGCM4R context swap register 0x80 0x20 read-write 0x00000000 CSGCM4R CSGCM4R 0 32 CSGCM5R CSGCM5R context swap register 0x84 0x20 read-write 0x00000000 CSGCM5R CSGCM5R 0 32 CSGCM6R CSGCM6R context swap register 0x88 0x20 read-write 0x00000000 CSGCM6R CSGCM6R 0 32 CSGCM7R CSGCM7R context swap register 0x8C 0x20 read-write 0x00000000 CSGCM7R CSGCM7R 0 32 DCMI Digital camera interface DCMI 0x48020000 0x0 0x400 registers DCMI DCMI global interrupt 78 CR CR control register 1 0x0 0x20 read-write 0x00000000 OELS Odd/Even Line Select (Line Select Start) 20 1 OELS Odd Interface captures first line after the frame start, second one being dropped 0 Even Interface captures second line from the frame start, first one being dropped 1 LSM Line Select mode 19 1 LSM All Interface captures all received lines 0 Half Interface captures one line out of two 1 OEBS Odd/Even Byte Select (Byte Select Start) 18 1 OEBS Odd Interface captures first data (byte or double byte) from the frame/line start, second one being dropped 0 Even Interface captures second data (byte or double byte) from the frame/line start, first one being dropped 1 BSM Byte Select mode 16 2 BSM All Interface captures all received data 0 EveryOther Interface captures every other byte from the received data 1 Fourth Interface captures one byte out of four 2 TwoOfFour Interface captures two bytes out of four 3 ENABLE DCMI enable 14 1 ENABLE Disabled DCMI disabled 0 Enabled DCMI enabled 1 EDM Extended data mode 10 2 EDM BitWidth8 Interface captures 8-bit data on every pixel clock 0 BitWidth10 Interface captures 10-bit data on every pixel clock 1 BitWidth12 Interface captures 12-bit data on every pixel clock 2 BitWidth14 Interface captures 14-bit data on every pixel clock 3 FCRC Frame capture rate control 8 2 FCRC All All frames are captured 0 Alternate Every alternate frame captured (50% bandwidth reduction) 1 OneOfFour One frame out of four captured (75% bandwidth reduction) 2 VSPOL Vertical synchronization polarity 7 1 VSPOL ActiveLow DCMI_VSYNC active low 0 ActiveHigh DCMI_VSYNC active high 1 HSPOL Horizontal synchronization polarity 6 1 HSPOL ActiveLow DCMI_HSYNC active low 0 ActiveHigh DCMI_HSYNC active high 1 PCKPOL Pixel clock polarity 5 1 PCKPOL FallingEdge Falling edge active 0 RisingEdge Rising edge active 1 ESS Embedded synchronization select 4 1 ESS Hardware Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals 0 Embedded Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow 1 JPEG JPEG format 3 1 JPEG Uncompressed Uncompressed video format 0 JPEG This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode 1 CROP Crop feature 2 1 CROP Full The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four 0 Cropped Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured 1 CM Capture mode 1 1 CM Continuous Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA 0 Snapshot Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset 1 CAPTURE Capture enable 0 1 CAPTURE Disabled Capture disabled 0 Enabled Capture enabled 1 SR SR status register 0x4 0x20 read-only 0x00000000 FNE FIFO not empty 2 1 FNE NotEmpty FIFO contains valid data 0 Empty FIFO empty 1 VSYNC VSYNC 1 1 VSYNC ActiveFrame Active frame 0 BetweenFrames Synchronization between frames 1 HSYNC HSYNC 0 1 HSYNC ActiveLine Active line 0 BetweenLines Synchronization between lines 1 RIS RIS raw interrupt status register 0x8 0x20 read-only 0x00000000 LINE_RIS Line raw interrupt status 4 1 LINE_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 VSYNC_RIS VSYNC raw interrupt status 3 1 VSYNC_RIS Cleared Interrupt cleared 0 Set Interrupt set 1 ERR_RIS Synchronization error raw interrupt status 2 1 ERR_RIS NoError No synchronization error detected 0 SynchronizationError Embedded synchronization characters are not received in the correct order 1 OVR_RIS Overrun raw interrupt status 1 1 OVR_RIS NoOverrun No data buffer overrun occurred 0 OverrunOccured A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register 1 FRAME_RIS Capture complete raw interrupt status 0 1 FRAME_RIS NoNewCapture No new capture 0 FrameCaptured A frame has been captured 1 IER IER interrupt enable register 0xC 0x20 read-write 0x00000000 LINE_IE Line interrupt enable 4 1 LINE_IE Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received 1 VSYNC_IE VSYNC interrupt enable 3 1 VSYNC_IE Disabled No interrupt generation 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state 1 ERR_IE Synchronization error interrupt enable 2 1 ERR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order 1 OVR_IE Overrun interrupt enable 1 1 OVR_IE Disabled No interrupt generation 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received 1 FRAME_IE Capture complete interrupt enable 0 1 FRAME_IE Disabled No interrupt generation 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) 1 MIS MIS masked interrupt status register 0x10 0x20 read-only 0x00000000 LINE_MIS Line masked interrupt status 4 1 LINE_MIS Disabled No interrupt generation when the line is received 0 Enabled An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER 1 VSYNC_MIS VSYNC masked interrupt status 3 1 VSYNC_MIS Disabled No interrupt is generated on DCMI_VSYNC transitions 0 Enabled An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER 1 ERR_MIS Synchronization error masked interrupt status 2 1 ERR_MIS Disabled No interrupt is generated on a synchronization error 0 Enabled An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set 1 OVR_MIS Overrun masked interrupt status 1 1 OVR_MIS Disabled No interrupt is generated on overrun 0 Enabled An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER 1 FRAME_MIS Capture complete masked interrupt status 0 1 FRAME_MIS Disabled No interrupt is generated after a complete capture 0 Enabled An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER 1 ICR ICR interrupt clear register 0x14 0x20 write-only 0x00000000 LINE_ISC line interrupt status clear 4 1 LINE_ISC Clear Setting this bit clears the LINE_RIS flag in the DCMI_RIS register 1 VSYNC_ISC Vertical synch interrupt status clear 3 1 VSYNC_ISC Clear Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register 1 ERR_ISC Synchronization error interrupt status clear 2 1 ERR_ISC Clear Setting this bit clears the ERR_RIS flag in the DCMI_RIS register 1 OVR_ISC Overrun interrupt status clear 1 1 OVR_ISC Clear Setting this bit clears the OVR_RIS flag in the DCMI_RIS register 1 FRAME_ISC Capture complete interrupt status clear 0 1 FRAME_ISC Clear Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register 1 ESCR ESCR embedded synchronization code register 0x18 0x20 read-write 0x00000000 FEC Frame end delimiter code 24 8 LEC Line end delimiter code 16 8 LSC Line start delimiter code 8 8 FSC Frame start delimiter code 0 8 ESUR ESUR embedded synchronization unmask register 0x1C 0x20 read-write 0x00000000 FEU Frame end delimiter unmask 24 8 LEU Line end delimiter unmask 16 8 LSU Line start delimiter unmask 8 8 FSU Frame start delimiter unmask 0 8 CWSTRT CWSTRT crop window start 0x20 0x20 read-write 0x00000000 VST Vertical start line count 16 13 0 8191 HOFFCNT Horizontal offset count 0 14 0 16383 CWSIZE CWSIZE crop window size 0x24 0x20 read-write 0x00000000 VLINE Vertical line count 16 14 0 16383 CAPCNT Capture count 0 14 0 16383 DR DR data register 0x28 0x20 read-only 0x00000000 4 0x8 0-3 BYTE%s Data byte %s 0 8 0 255 OTG1_HS_GLOBAL USB 1 on the go high speed USB_OTG_HS 0x40040000 0x0 0x400 registers OTG_HS_EP1_OUT OTG_HS out global interrupt 74 OTG_HS_EP1_IN OTG_HS in global interrupt 75 OTG_HS_WKUP OTG_HS wakeup interrupt 76 OTG_HS OTG_HS global interrupt 77 GOTGCTL GOTGCTL OTG_HS control and status register 0x0 0x20 0x00000800 SRQSCS Session request success 0 1 read-only SRQ Session request 1 1 read-write VBVALOEN VBUS valid override enable 2 1 read-write VBVALOVAL VBUS valid override value 3 1 read-write AVALOEN A-peripheral session valid override enable 4 1 read-write AVALOVAL A-peripheral session valid override value 5 1 read-write BVALOEN B-peripheral session valid override enable. 6 1 read-write BVALOVAL B-peripheral session valid override value 7 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write EHEN Embedded host enable 12 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only OTGVER OTG version 20 1 read-write CURMOD Current mode of operation 21 1 read-only GOTGINT GOTGINT OTG_HS interrupt register 0x4 0x20 read-write 0x00000000 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 HNSSCHG Host negotiation success status change 9 1 HNGDET Host negotiation detected 17 1 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 IDCHNG ID input pin changed 20 1 GAHBCFG GAHBCFG OTG_HS AHB configuration register 0x8 0x20 read-write 0x00000000 GINT Global interrupt mask 0 1 HBSTLEN Burst length/type 1 4 DMAEN DMA enable 5 1 TXFELVL TxFIFO empty level 7 1 PTXFELVL Periodic TxFIFO empty level 8 1 GUSBCFG GUSBCFG OTG_HS USB configuration register 0xC 0x20 0x00000A00 TOCAL FS timeout calibration 0 3 read-write PHYSEL USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write HNPCAP HNP-capable 9 1 read-write TRDT USB turnaround time 10 4 read-write PHYLPCS PHY Low-power clock select 15 1 read-write ULPIFSLS ULPI FS/LS select 17 1 read-write ULPIAR ULPI Auto-resume 18 1 read-write ULPICSM ULPI Clock SuspendM 19 1 read-write ULPIEVBUSD ULPI External VBUS Drive 20 1 read-write ULPIEVBUSI ULPI external VBUS indicator 21 1 read-write TSDPS TermSel DLine pulsing selection 22 1 read-write PCCI Indicator complement 23 1 read-write PTCI Indicator pass through 24 1 read-write ULPIIPD ULPI interface protect disable 25 1 read-write FHMOD Forced host mode 29 1 read-write FDMOD Forced peripheral mode 30 1 read-write GRSTCTL GRSTCTL OTG_HS reset register 0x10 0x20 0x20000000 CSRST Core soft reset 0 1 read-write HSRST HCLK soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write AHBIDL AHB master idle 31 1 read-only DMAREQ DMA request signal enabled for USB OTG HS 30 1 read-only GINTSTS GINTSTS OTG_HS core interrupt register 0x14 0x20 0x04000020 CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO nonempty 4 1 read-only NPTXFE Nonperiodic TxFIFO empty 5 1 read-only GINAKEFF Global IN nonperiodic NAK effective 6 1 read-only BOUTNAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write PXFR_INCOMPISOOUT Incomplete periodic transfer 21 1 read-write DATAFSUSP Data fetch suspended 22 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUINT Resume/remote wakeup detected interrupt 31 1 read-write GINTMSK GINTMSK OTG_HS interrupt mask register 0x18 0x20 0x00000000 MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO nonempty mask 4 1 read-write NPTXFEM Nonperiodic TxFIFO empty mask 5 1 read-write GINAKEFFM Global nonperiodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write PXFRM_IISOOXFRM Incomplete periodic transfer mask 21 1 read-write FSUSPM Data fetch suspended mask 22 1 read-write PRTIM Host port interrupt mask 24 1 read-only HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic TxFIFO empty mask 26 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write RSTDE Reset detected interrupt mask 23 1 read-write LPMINTM LPM interrupt mask 27 1 read-write GRXSTSR_Host GRXSTSR_Host OTG_HS Receive status debug read register (host mode) 0x1C 0x20 read-only 0x00000000 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXSTSP_Host GRXSTSP_Host OTG_HS status read and pop register (host mode) 0x20 0x20 read-only 0x00000000 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXFSIZ GRXFSIZ OTG_HS Receive FIFO size register 0x24 0x20 read-write 0x00000200 RXFD RxFIFO depth 0 16 HNPTXFSIZ HNPTXFSIZ_Host OTG_HS nonperiodic transmit FIFO size register (host mode) 0x28 0x20 read-write 0x00000200 NPTXFSA Nonperiodic transmit RAM start address 0 16 NPTXFD Nonperiodic TxFIFO depth 16 16 DIEPTXF0 DIEPTXF0_Device Endpoint 0 transmit FIFO size (peripheral mode) HNPTXFSIZ 0x28 0x20 read-write 0x00000200 TX0FSA Endpoint 0 transmit RAM start address 0 16 TX0FD Endpoint 0 TxFIFO depth 16 16 HNPTXSTS GNPTXSTS OTG_HS nonperiodic transmit FIFO/queue status register 0x2C 0x20 read-only 0x00080200 NPTXFSAV Nonperiodic TxFIFO space available 0 16 NPTQXSAV Nonperiodic transmit request queue space available 16 8 NPTXQTOP Top of the nonperiodic transmit request queue 24 7 GCCFG GCCFG OTG_HS general core configuration register 0x38 0x20 read-write 0x00000000 PWRDWN Power down 16 1 BCDEN Battery charging detector (BCD) enable 17 1 DCDEN Data contact detection (DCD) mode enable 18 1 PDEN Primary detection (PD) mode enable 19 1 SDEN Secondary detection (SD) mode enable 20 1 VBDEN USB VBUS detection enable 21 1 DCDET Data contact detection (DCD) status 0 1 PDET Primary detection (PD) status 1 1 SDET Secondary detection (SD) status 2 1 PS2DET DM pull-up detection status 3 1 CID CID OTG_HS core ID register 0x3C 0x20 read-write 0x00001200 PRODUCT_ID Product ID field 0 32 HPTXFSIZ HPTXFSIZ OTG_HS Host periodic transmit FIFO size register 0x100 0x20 read-write 0x02000600 PTXSA Host periodic TxFIFO start address 0 16 PTXFD Host periodic TxFIFO depth 16 16 8 0x4 1-8 DIEPTXF%s DIEPTXF%s OTG_HS device IN endpoint transmit FIFO size register 0x104 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 GRXSTSR_Device GRXSTSR_Device OTG_HS Receive status debug read register (peripheral mode mode) GRXSTSR_Host 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 GRXSTSP_Device GRXSTSP_Device OTG_HS status read and pop register (peripheral mode) GRXSTSP_Host 0x20 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 GLPMCFG GLPMCFG OTG core LPM configuration register 0x54 0x20 0x00000000 LPMEN LPM support enable 0 1 read-write LPMACK LPM token acknowledge enable 1 1 read-write BESL Best effort service latency 2 4 read-only REMWAKE bRemoteWake value 6 1 read-only L1SSEN L1 Shallow Sleep enable 7 1 read-write BESLTHRS BESL threshold 8 4 read-write L1DSEN L1 deep sleep enable 12 1 read-write LPMRST LPM response 13 2 read-only SLPSTS Port sleep status 15 1 read-only L1RSMOK Sleep State Resume OK 16 1 read-only LPMCHIDX LPM Channel Index 17 4 read-write LPMRCNT LPM retry count 21 3 read-write SNDLPM Send LPM transaction 24 1 read-write LPMRCNTSTS LPM retry count status 25 3 read-only ENBESL Enable best effort service latency 28 1 read-write OTG2_HS_GLOBAL 0x40080000 OTG_FS_EP1_OUT OTG_FS out global interrupt 98 OTG_FS_EP1_IN OTG_FS in global interrupt 99 OTG_FS_WKUP OTG_FS wakeup 100 OTG_FS OTG_FS global interrupt 101 OTG1_HS_HOST USB 1 on the go high speed USB_OTG_HS 0x40040400 0x0 0x400 registers HCFG HCFG OTG_HS host configuration register 0x0 0x20 0x00000000 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-only HFIR HFIR OTG_HS Host frame interval register 0x4 0x20 read-write 0x0000EA60 FRIVL Frame interval 0 16 HFNUM HFNUM OTG_HS host frame number/frame time remaining register 0x8 0x20 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 HPTXSTS HPTXSTS OTG_HS_Host periodic transmit FIFO/queue status register 0x10 0x20 0x00080100 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_HS Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_HS host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 HAINTM Channel interrupt mask 0 16 HPRT HPRT OTG_HS host port control and status register 0x40 0x20 0x00000000 PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only 16 0x20 0-15 HC%s Host channel 0x100 CHAR HCCHAR0 OTG_HS host channel-0 characteristics register 0x0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 SPLT HCSPLT0 OTG_HS host channel-0 split control register 0x4 0x20 read-write 0x00000000 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 INT HCINT0 OTG_HS host channel-11 interrupt register 0x8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 INTMSK HCINTMSK0 OTG_HS host channel-11 interrupt mask register 0xC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 TSIZ HCTSIZ0 OTG_HS host channel-11 transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 DMA HCDMA0 OTG_HS host channel-0 DMA address register 0x14 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 OTG2_HS_HOST 0x40080400 OTG1_HS_DEVICE USB 1 on the go high speed USB_OTG_HS 0x40040800 0x0 0x400 registers DCFG DCFG OTG_HS device configuration register 0x0 0x20 read-write 0x02200000 DSPD Device speed 0 2 NZLSOHSK Nonzero-length status OUT handshake 2 1 DAD Device address 4 7 PFIVL Periodic (micro)frame interval 11 2 PERSCHIVL Periodic scheduling interval 24 2 DCTL DCTL OTG_HS device control register 0x4 0x20 0x00000000 RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 write-only CGINAK Clear global IN NAK 8 1 write-only SGONAK Set global OUT NAK 9 1 write-only CGONAK Clear global OUT NAK 10 1 write-only POPRGDNE Power-on programming done 11 1 read-write DSTS DSTS OTG_HS device status register 0x8 0x20 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 EERR Erratic error 3 1 FNSOF Frame number of the received SOF 8 14 DIEPMSK DIEPMSK OTG_HS device IN endpoint common interrupt mask register 0x10 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (nonisochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 TXFURM FIFO underrun mask 8 1 BIM BNA interrupt mask 9 1 DOEPMSK DOEPMSK OTG_HS device OUT endpoint common interrupt mask register 0x14 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 B2BSTUP Back-to-back SETUP packets received mask 6 1 OPEM OUT packet error mask 8 1 BOIM BNA interrupt mask 9 1 DAINT DAINT OTG_HS device all endpoints interrupt register 0x18 0x20 read-only 0x00000000 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 DAINTMSK DAINTMSK OTG_HS all endpoints interrupt mask register 0x1C 0x20 read-write 0x00000000 IEPM IN EP interrupt mask bits 0 16 OEPM OUT EP interrupt mask bits 16 16 DVBUSDIS DVBUSDIS OTG_HS device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_HS device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSP Device VBUS pulsing time 0 12 DTHRCTL DTHRCTL OTG_HS Device threshold control register 0x30 0x20 read-write 0x00000000 NONISOTHREN Nonisochronous IN endpoints threshold enable 0 1 ISOTHREN ISO IN endpoint threshold enable 1 1 TXTHRLEN Transmit threshold length 2 9 RXTHREN Receive threshold enable 16 1 RXTHRLEN Receive threshold length 17 9 ARPEN Arbiter parking enable 27 1 DIEPEMPMSK DIEPEMPMSK OTG_HS device IN endpoint FIFO empty interrupt mask register 0x34 0x20 read-write 0x00000000 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 DEACHINT DEACHINT OTG_HS device each endpoint interrupt register 0x38 0x20 read-write 0x00000000 IEP1INT IN endpoint 1interrupt bit 1 1 OEP1INT OUT endpoint 1 interrupt bit 17 1 DEACHINTMSK DEACHINTMSK OTG_HS device each endpoint interrupt register mask 0x3C 0x20 read-write 0x00000000 IEP1INTM IN Endpoint 1 interrupt mask bit 1 1 OEP1INTM OUT Endpoint 1 interrupt mask bit 17 1 DIEPEACHMSK1 0x44 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 AHBERRM AHB error mask 2 1 TOM Timeout condition mask (Non-isochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNEM IN endpoint NAK effective mask 6 1 TXFURM FIFO underrun mask 8 1 BNAM BNA interrupt mask 9 1 NAKM NAK interrupt mask 13 1 DOEPEACHMSK1 0x84 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 AHBERRM AHB error mask 2 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 B2BSTUPM Back-to-back SETUP packets received mask 6 1 OUTPKTERRM Out packet error mask 8 1 BNAM BNA interrupt mask 9 1 BERRM Babble error interrupt mask 12 1 NAKMSK NAK interrupt mask 13 1 NYETMSK NYET interrupt mask 14 1 DIEP0 Device IN endpoint 0 0x100 CTL DIEPCTL0 OTG device endpoint-0 control register 0x0 0x20 0x00000000 MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM_DPID Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID_SEVNFRM Set DATA0 PID 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write INT DIEPINT0 OTG device endpoint-0 interrupt register 0x8 0x20 0x00000080 XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when TxFIFO is empty 4 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun 8 1 read-write BNA Buffer not available interrupt 9 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK interrupt 13 1 read-write TSIZ DIEPTSIZ0 OTG_HS device IN endpoint 0 transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 7 PKTCNT Packet count 19 2 DMA OTG_HS device endpoint-0 DMA address register 0x14 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 TXFSTS DTXFSTS0 OTG_HS device IN endpoint transmit FIFO status register 0x18 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space avail 0 16 8 0x20 1-8 DIEP%s Device IN endpoint X 0x120 CTL DIEPCTL1 OTG device endpoint-1 control register 0x0 0x20 0x00000000 MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM_DPID Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID_SEVNFRM Set DATA0 PID 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write INT DIEPINT1 OTG device endpoint-1 interrupt register 0x8 TSIZ DIEPTSIZ1 OTG_HS device endpoint transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 MCNT Multi count 29 2 DMA DIEPDMA1 OTG_HS device endpoint-1 DMA address register 0x14 TXFSTS DTXFSTS1 OTG_HS device IN endpoint transmit FIFO status register 0x18 DOEP0 Device OUT endpoint 0 0x300 CTL DOEPCTL0 OTG_HS device control OUT endpoint 0 control register 0x0 0x20 0x00008000 MPSIZ Maximum packet size 0 2 read-only USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 read-write INT DOEPINT0 OTG_HS device endpoint-0 interrupt register 0x8 0x20 read-write 0x00000080 XFRC Transfer completed interrupt 0 1 EPDISD Endpoint disabled interrupt 1 1 STUP SETUP phase done 3 1 OTEPDIS OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 NYET NYET interrupt 14 1 TSIZ DOEPTSIZ0 OTG_HS device endpoint-0 transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 7 PKTCNT Packet count 19 1 STUPCNT SETUP packet count 29 2 DMA OTG_HS device endpoint-0 DMA address register 0x14 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 8 0x20 1-8 DOEP%s Device IN endpoint X 0x320 CTL DOEPCTL1 OTG device endpoint-1 control register 0x0 0x20 0x00000000 MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM_DPID Even odd frame/Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID_SEVNFRM Set DATA0 PID/Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write INT DOEPINT1 OTG_HS device endpoint-1 interrupt register 0x8 DMA OTG_HS device endpoint-1 DMA address register 0x14 TSIZ DOEPTSIZ1 OTG_HS device endpoint-1 transfer size register 0x10 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 OTG2_HS_DEVICE 0x40080800 OTG1_HS_PWRCLK USB 1 on the go high speed USB_OTG_HS 0x40040E00 0x0 0x3F200 registers PCGCR PCGCR Power and clock gating control register 0x0 0x20 read-write 0x00000000 STPPCLK Stop PHY clock 0 1 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY suspended 4 1 OTG2_HS_PWRCLK 0x40080E00 ETH ETH register block Ethernet 0x40028000 0x0 0x11F0 registers ETH Ethernet global interrupt 61 ETH_WKUP Ethernet wakeup through EXTI 62 MACCR MACCR Operating mode configuration register 0x0 0x20 0x00000000 0xFFFFFFFF RE Receiver Enable When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the MII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the MII interface. 0 1 read-write TE Transmitter Enable When this bit is set, the Tx state machine of the MAC is enabled for transmission on the MII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets. 1 1 read-write PRELEN Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. 2 2 read-write DC Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288 bit times in 10 or 100 Mbps mode. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in the half-duplex mode. 4 1 read-write BL Back-Off Limit 5 2 read-write DR Disable Retry When this bit is set, the MAC attempts only one transmission. When a collision occurs on the MII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status. When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the half-duplex mode. 8 1 read-write DCRS Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission. When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission. 9 1 read-write DO Disable Receive Own When this bit is set, the MAC disables the reception of packets when the ETH_TX_EN is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets given by the PHY. This bit is not applicable in the full-duplex mode. This bit is reserved and read-only (RO) with default value in the full-duplex-only configurations. 10 1 read-write ECRSFD Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low. When this bit is reset, the MAC transmitter ignores the status of the CRS signal. 11 1 read-write LM Loopback Mode When this bit is set, the MAC operates in the loopback mode at MII. The MII Rx clock input (eth_mii_rx_clk) is required for the loopback to work properly. This is because the Tx clock is not internally looped back. 12 1 read-write DM Duplex Mode When this bit is set, the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. 13 1 read-write FES MAC Speed This bit selects the speed in the 10/100 Mbps mode: 14 1 read-write JE Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see . 16 1 read-write JD Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes. When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet. 17 1 read-write WD Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes. When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes. 19 1 read-write ACS Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. All received packets with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming packets to the application, without any modification. Note: For information about how the settings of CST bit and this bit impact the packet length, see . 20 1 read-write CST CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. Note: For information about how the settings of the ACS bit and this bit impact the packet length, see . 21 1 read-write S2KP IEEE 802.3as Support for 2K Packets When this bit is set, the MAC considers all packets with up to 2,000 bytes length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2K bytes as Giant packets. When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1,518 bytes (1,522 bytes for tagged) as giant packets. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see Packet Status based on S2KP and JE Bits. Note: When the JE bit is set, setting this bit has no effect on the giant packet status. 22 1 read-write GPSLCE Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the value in GPSL field in ETH_MACECR register to declare a received packet as Giant packet. This field must be programmed to more than 1,518 bytes. Otherwise, the MAC considers 1,518 bytes as giant packet limit. When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1,518 bytes (1522 bytes for tagged packet). The watchdog timeout limit, Jumbo Packet Enable and 2K Packet Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9,018 bytes (9,022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2,000 bytes with 2K Packet Enabled. The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status. 23 1 read-write IPG Inter-Packet Gap These bits control the minimum IPG between packets during transmission. ... This range of minimum IPG is valid in full-duplex mode. In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IPG. The above function (IPG less than 96 bit times) is valid only when EIPGEN bit in ETH_MACECR register is reset. When EIPGEN is set, then the minimum IPG (greater than 96 bit times) is controlled as per the description given in EIPG field in ETH_MACECR register. 24 3 read-write IPC Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled. The Layer 3 and Layer 4 Packet Filter feature automatically selects the IPC Full Checksum Offload Engine on the Receive side. When this feature is enabled, you must set the IPC bit. 27 1 read-write SARC Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[29:28]: Others: Reserved, must not be used. Note: Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. 28 3 read-write ARPEN ARP Offload Enable When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It will forward the ARP packet to the application and also indicate the events in the RxStatus. When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the RxStatus. 31 1 read-write MACECR MACECR Extended operating mode configuration register 0x4 0x20 0x00000000 0xFFFFFFFF GPSL Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1,518 bytes. Any other programmed value is considered as 1,518 bytes. For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. For double VLAN tagged packets, the MAC adds 8 bytes to the programmed value. The value in this field is applicable when the GPSLCE bit is set in ETH_MACCR register. 0 14 read-write DCRCC Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets. 16 1 read-write SPEN Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types. When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets. 17 1 read-write USP Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the and MAC Address 0 low register . The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-00-00-02). When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2008, Section 5. 18 1 read-write EIPGEN Extended Inter-Packet Gap Enable When this bit is set, the MAC interprets EIPG field and IPG field in configuration register (ETH_MACCR) together as minimum IPG greater than 96 bit times in steps of 8 bit times. When this bit is reset, the MAC ignores EIPG field and interprets IPG field in configuration register (ETH_MACCR) as minimum IPG less than or equal to 96 bit times in steps of 8 bit times. Note: The extended Inter-Packet Gap feature must be enabled when operating in Full-Duplex mode only. There may be undesirable effects on back-pressure function and frame transmission if it is enabled in Half-Duplex mode. 24 1 read-write EIPG Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits) along with IPG field in , gives the minimum IPG greater than 96 bit times in steps of 8 bit times. For example: EIPG = 0 and IPG = 0 give 104 bit times EIPG = 0 and IPG = 1 give 112 bit times EIPG = 0 and IPG = 2 give 120 bit times .. EIPG = 7 and IPG = 31 give 2144 bit times 25 5 read-write MACPFR MACPFR Packet filtering control register 0x8 0x20 0x00000000 0xFFFFFFFF PR Promiscuous Mode When this bit is set, the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set. 0 1 read-write HUC Hash Unicast When this bit is set, the MAC performs the destination address filtering of unicast packets according to the Hash table. When this bit is reset, the MAC performs a perfect destination address filtering for unicast packets, that is, it compares the DA field with the values programmed in DA registers. 1 1 read-write HMC Hash Multicast When this bit is set, the MAC performs the destination address filtering of received multicast packets according to the Hash table. When this bit is reset, the MAC performs the perfect destination address filtering for multicast packets, that is, it compares the DA field with the values programmed in DA registers. 2 1 read-write DAIF DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset, normal filtering of packets is performed. 3 1 read-write PM Pass All Multicast When this bit is set, it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset, filtering of multicast packet depends on HMC bit. 4 1 read-write DBF Disable Broadcast Packets When this bit is set, the AFM module blocks all incoming broadcast packets. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast packets. 5 1 read-write PCF Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets). 6 2 read-write SAIF SA Inverse Filtering When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers, it is marked as failing the SA Address filter. When this bit is reset, if the SA of a packet does not match the values programmed in the SA registers, it is marked as failing the SA Address filter. 8 1 read-write SAF Source Address Filter Enable When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the packet. When this bit is reset, the MAC forwards the received packet to the application with updated SAF bit of the Rx Status depending on the SA address comparison. Note: According to the IEEE specification, Bit 47 of the SA is reserved. However, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA. 9 1 read-write HPF Hash or Perfect Filter When this bit is set, the address filter passes a packet if it matches either the perfect filtering or Hash filtering as set by the HMC or HUC bit. When this bit is reset and the HUC or HMC bit is set, the packet is passed only if it matches the Hash filter. 10 1 read-write VTFE VLAN Tag Filter Enable When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset, the MAC forwards all packets irrespective of the match status of the VLAN Tag. 16 1 read-write IPFE Layer 3 and Layer 4 Filter Enable When this bit is set, the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When this bit is reset, the MAC forwards all packets irrespective of the match status of the Layer 3 and Layer 4 fields. 20 1 read-write DNTU Drop Non-TCP/UDP over IP Packets When this bit is set, the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset, the MAC forwards all non-TCP or UDP over IP packets. 21 1 read-write RA Receive All When this bit is set, the MAC Receiver module passes all received packets to the application, irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bit in the Rx Status Word. When this bit is reset, the Receiver module passes only those packets to the application that pass the SA or DA address filter. 31 1 read-write MACWTR MACWTR Watchdog timeout register 0xC 0x20 0x00000000 0xFFFFFFFF WTO Watchdog Timeout When the PWE bit is set and the WD bit of the (ETH_MACCR) register is reset, this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field, such packet is terminated and declared as an error packet. Encoding is as follows: .. Note: When the PWE bit is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE 802.3-specified valid tagged packets are declared as error packets and then dropped. 0 4 read-write PWE Programmable Watchdog Enable When this bit is set and the WD bit of the (ETH_MACCR) register is reset, the WTO field is used as watchdog timeout for a received packet. When this bit is cleared, the watchdog timeout for a received packet is controlled by setting of WD and JE bits in register. 8 1 read-write MACHT0R MACHT0R Hash Table 0 register 0x10 0x20 0x00000000 0xFFFFFFFF HT31T0 MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. 0 32 read-write MACHT1R MACHT1R Hash Table 1 register 0x14 0x20 0x00000000 0xFFFFFFFF HT63T32 MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. 0 32 read-write MACVTR MACVTR VLAN tag register 0x50 0x20 0x00000000 0xFFFFFFFF VL VLAN Tag Identifier for Receive Packets This field contains the 802.1Q VLAN tag to identify the VLAN packets. This VLAN tag identifier is compared to the 15th and 16th bytes of the packets being received for VLAN packets. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag When the ETV bit is set, only the VID is used for comparison. If this field ([11:0] if ETV is set) is all zeros, the MAC does not check the 15th and 16th bytes for VLAN tag comparison and declares all packets with Type field value of 0x8100 or 0x88a8 as VLAN packets. 0 16 read-write ETV Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits[11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet. Similarly, when enabled, only 12 bits of the VLAN tag in the received packet are used for Hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN packet are used for comparison and VLAN Hash filtering. 16 1 read-write VTIM VLAN Tag Inverse Match Enable When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched. 17 1 read-write ESVL Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. 18 1 read-write ERSVLM Enable Receive S-VLAN Match When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset, the MAC receiver enables filtering or matching for C-VLAN (Type = 0x8100) packets. The ERIVLT bit determines the VLAN tag position considered for filtering or matching. 19 1 read-write DOVLTC Disable VLAN Type Check When this bit is set, the MAC does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN. When this bit is reset, the MAC filters or matches the VLAN Tag specified by the ERIVLT bit only when VLAN Tag type is similar to the one specified by the ERSVLM bit. 20 1 read-write EVLS Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet: 21 2 read-write EVLRXS Enable VLAN Tag in Rx status When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status. 24 1 read-write VTHM VLAN Tag Hash Table Match Enable When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the ETH_MACVLANHTR register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN Hash table. When the ETV bit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison. When this bit is reset, the VLAN Hash Match operation is not performed. 25 1 read-write EDVLP Enable Double VLAN Processing When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present). 26 1 read-write ERIVLT Enable Inner VLAN Tag When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present). The ERSVLM bit determines which VLAN type is enabled for filtering or matching.The ERSVLM bit and DOVLTC bit determines which VLAN type is enabled for filtering. 27 1 read-write EIVLS Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet: 28 2 read-write EIVLRXS Enable Inner VLAN Tag in Rx Status When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status. 31 1 read-write MACVHTR MACVHTR VLAN Hash table register 0x58 0x20 0x00000000 0xFFFFFFFF VLHT VLAN Hash Table This field contains the 16-bit VLAN Hash Table. 0 16 read-write MACVIR MACVIR VLAN inclusion register 0x60 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag 0 16 read-write VLC VLAN Tag Control in Transmit Packets Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. 16 2 read-write VLP VLAN Priority Control When this bit is set, the control bits[17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, bits[17:16] are ignored. 18 1 read-write CSVL C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. 19 1 read-write VLTI VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor. 20 1 read-write CBTI Channel based tag insertion When this bit is set, outer VLAN tag is inserted for every packets transmitted by the MAC. The tag value is taken from the queue/channel specific VLAN tag register. This will override VLTI, VLP, VLC and VLT fields of this register When this bit is set, a write operation to byte 3 of this register initiates the read/write access to the indirect register. When reset outer VLAN operation is based on the setting of VLTI, VLP, VLC and VLT fields of this register 21 1 read-write ADDR Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access This does not have any effect when CBTI is reset 24 1 read-write RDWR Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register. When set indicates write operation and when reset indicates read operation This has no effect when CBTI is reset 30 1 read-write BUSY Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register. For write operation write to a register is complete when this bit is reset. For read operation the read data is valid when the bit is reset. No further writes are allowed to this register when this bit is set. This does not have any effect when CBTI is reset 31 1 read-only MACVIRALTERNATE MACVIRALTERNATE VLAN inclusion register MACVIR 0x60 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag 0 16 read-write CSVL C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. 19 1 read-write MACIVIR MACIVIR Inner VLAN inclusion register 0x64 0x20 0x00000000 0xFFFFFFFF VLT VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag 0 16 read-write VLC VLAN Tag Control in Transmit Packets The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags. The MAC inserts VLT in bytes 19 and 20 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 17 and 18. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag. The MAC replaces VLT in bytes 19 and 20 of all VLAN-type transmitted packets (Bytes 17 and 18 are 0x8100 or 0x88a8). Note: Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. 16 2 read-write VLP VLAN Priority Control When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. When this bit is reset, the VLC field is ignored. 18 1 read-write CSVL C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. 19 1 read-write VLTI VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor 20 1 read-write MACQTXFCR MACQTXFCR Tx Queue flow control register 0x70 0x20 0x00000000 0xFFFFFFFF FCB_BPA Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. Full-Duplex Mode: this bit should be read as 0 before writing to this register. To initiate a Pause packet, the application must set this bit to 1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 0. You should not write to this register until this bit is cleared. Half-Duplex Mode: When this bit is set (and TFE bit is set) in the half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. 0 1 read-write TFE Transmit Flow Control Enable Full-Duplex Mode: when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets. Half-Duplex Mode: when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. 1 1 read-write PLT Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow is checked for automatic retransmission of the Pause packet. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot times), and PLT = 001, a second Pause packet is automatically transmitted at 228 (256-28) slot times after the first Pause packet is transmitted. The following list provides the threshold values for different values: The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface. This (approximate) computation is based on the packet size (64, 1518, 2000, 9018, 16384, or 32768) + 2 Pause Packet Size + IPG in Slot Times. 4 3 read-write DZPQ Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of the zero-quanta Pause packets. When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled. 7 1 read-write PT Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. I 16 16 read-write MACRXFCR MACRXFCR Rx flow control register 0x90 0x20 0x00000000 0xFFFFFFFF RFE Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in half-duplex mode, the decode function of the Pause packet is disabled. When PFC is enabled, flow control is enabled for PFC packets. The MAC decodes the received PFC packet and disables the Transmit queue, with matching priorities, for a duration of received Pause time. 0 1 read-write UP Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set, the MAC can also detect Pause packets with unicast address of the station. This unicast address should be as specified in (ETH_MACA0HR) and MAC Address 0 low register (ETH_MACAxLR). When this bit is reset, the MAC only detects Pause packets with unique multicast address. Note: The MAC does not process a Pause packet if the multicast address is different from the unique multicast address. This is also applicable to the received PFC packet when the Priority Flow Control (PFC) is enabled. The unique multicast address (0x01_80_C2_00_00_01) is as specified in IEEE 802.1 Qbb-2011. 1 1 read-write MACISR MACISR Interrupt status register 0xB0 0x20 0x00000000 0xFFFFFFFF PHYIS PHY Interrupt This bit is set when rising edge is detected on the ETH_PHY_INTN input. This bit is cleared when this register is read. 3 1 read-only PMTIS PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in ETH_MACPCSR register). This bit is cleared when Bits[6:5] are cleared because of a Read operation to the (ETH_MACPCSR). 4 1 read-only LPIIS LPI Interrupt Status This bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the TLPIEN bit of is read. 5 1 read-only MMCIS MMC Interrupt Status This bit is set high when MMCTXIS or MMCRXIS is set high. This bit is cleared only when all these bits are low. 8 1 read-only MMCRXIS MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the (ETH_MMC_RX_INTERRUPT). This bit is cleared when all bits in this interrupt register are cleared. 9 1 read-only MMCTXIS MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the (ETH_MMC_TX_INTERRUPT). This bit is cleared when all bits in this interrupt register are cleared. 10 1 read-only TSIS Timestamp Interrupt Status If the Timestamp feature is enabled, this bit is set when any of the following conditions is true: The system time value is equal to or exceeds the value specified in the Target Time High and Low registers. There is an overflow in the Seconds register. The Target Time Error occurred, that is, programmed target time already elapsed. If the Auxiliary Snapshot feature is enabled, this bit is set when the auxiliary snapshot trigger is asserted. When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the (ETH_MACTXTSSNR) and registers. When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the and timestamp status seconds register (ETH_MACTXTSSSR) registers, for PTO generated Delay Request and Pdelay request packets. This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of (ETH_MACCSRSWCR) is set) in the . 12 1 read-write clear TXSTSIS Transmit Status Interrupt This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the : Excessive Collision (EXCOL) Late Collision (LCOL) Excessive Deferral (EXDEF) Loss of Carrier (LCARR) No Carrier (NCARR) Jabber Timeout (TJT) This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of (ETH_MACCSRSWCR) is set) in the ETH_MACISR register. 13 1 read-write clear RXSTSIS Receive Status Interrupt This bit indicates the status of received packets. This bit is set when the RWT bit is set in the . This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of is set) in the ETH_MACISR register. 14 1 read-write clear MACIER MACIER Interrupt enable register 0xB4 0x20 0x00000000 0xFFFFFFFF PHYIE PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in . 3 1 read-write PMTIE PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PMTIS bit in . 4 1 read-write LPIIE LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of LPIIS bit in . 5 1 read-write TSIE Timestamp Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of TSIS bit in . 12 1 read-write TXSTSIE Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the . 13 1 read-write RXSTSIE Receive Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the . 14 1 read-write MACRXTXSR MACRXTXSR Rx Tx status register 0xB8 0x20 0x00000000 0xFFFFFFFF TJT Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the . This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the register (ETH_MACCR). Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 0 1 read-write clear NCARR No Carrier When the DTXSTS bit is set in the , this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 1 1 read-write clear LCARR Loss of Carrier When the DTXSTS bit is set in the , this bit indicates that the loss of carrier occurred during packet transmission, that is, the ETH_CRS signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 2 1 read-write clear EXDEF Excessive Deferral When the DTXSTS bit is set in the and the DC bit is set in the , this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when Jumbo packet is enabled). Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 3 1 read-write clear LCOL Late Collision When the DTXSTS bit is set in the , this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode. This bit is not valid if the Underflow error occurs. Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 4 1 read-write clear EXCOL Excessive Collisions When the DTXSTS bit is set in the , this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the (ETH_MACCR), this bit is set after the first collision and the packet transmission is aborted. Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 5 1 read-write clear RWT Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the configuration register (ETH_MACCR). This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the (ETH_MACCR). Cleared on read (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 8 1 read-write clear MACPCSR MACPCSR 0xC0 0x20 0x00000000 0xFFFFFFFF PWRDWN Power Down When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wakeup packet. This bit is then self-cleared and the power-down mode is disabled. The software can clear this bit before the expected magic packet or remote wakeup packet is received. The packets received by the MAC after this bit is cleared are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote wakeup Packet Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. 0 1 read-write MGKPKTEN Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. 1 1 read-write RWKPKTEN Remote wakeup Packet Enable When this bit is set, a power management event is generated when the MAC receives a remote wakeup packet. 2 1 read-write MGKPRCVD Magic Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read (or write of 1 when RCWE bit in is set). 5 1 read-write clear RWKPRCVD Remote wakeup Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a remote wakeup packet. This bit is cleared when this register is read. 6 1 read-only GLBLUCAST Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wakeup packet. 9 1 read-write RWKPFE Remote wakeup Packet Forwarding Enable When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected wakeup frame. All frames after that event including the received wakeup frame are forwarded to application. This bit is then self-cleared on receiving the wakeup packet. The application can also clear this bit before the expected wakeup frame is received. In such cases, the MAC reverts to the default behavior where packets received are forwarded to the application. This bit must only be set when RWKPKTEN is set high and PWRDWN is set low. The setting of this bit has no effect when PWRDWN is set high. Note: If Magic Packet Enable and wakeup Frame Enable are both set along with setting of this bit and Magic Packet is received prior to wakeup frame, this bit is self-cleared on receiving Magic Packet, the received Magic packet is dropped, and all frames after received Magic Packet are forwarded to application. 10 1 read-write RWKPTR Remote wakeup FIFO Pointer This field gives the current value (0 to 7) of the Remote wakeup Packet Filter register pointer. When the value of this pointer is equal to 7, the contents of the Remote wakeup Packet Filter Register are transferred to the eth_mii_rx_clk domain when a Write occurs to that register. 24 5 read-only RWKFILTRST Remote wakeup Packet Filter Register Pointer Reset When this bit is set, the remote wakeup packet filter register pointer is reset to 0. It is automatically cleared after 1 clock cycle. 31 1 read-write MACRWKPFR MACRWKPFR 0xC4 0x20 0x00000000 0xFFFFFFFF MACRWKPFR Remote wakeup packet filter Refer to , and for details on register content and programming sequence. 0 32 read-write MACLCSR MACLCSR LPI control and status register 0xD0 0x20 0x00000000 0xFFFFFFFF TLPIEN Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register (or write of 1 when RCWE bit in is set). 0 1 read-only TLPIEX Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register (or write of 1 when RCWE bit in (ETH_MACCSRSWCR) is set). 1 1 read-only RLPIEN Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register (or write of 1 when RCWE bit in is set). Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. 2 1 read-only RLPIEX Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register (or write of 1 when RCWE bit in register (ETH_MACCSRSWCR) is set). Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. 3 1 read-only TLPIST Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface. 8 1 read-only RLPIST Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface. 9 1 read-only LPIEN LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. When this bit is reset, it instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. 16 1 read-write PLS PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. When this bit is set, the link is considered to be okay (UP) and when this bit is reset, the link is considered to be down. 17 1 read-write LPITXA LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding packets (in the core) and pending packets (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any packet for transmission or the application issues a Tx FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If Tx FIFO Flush is set in the FTQ bit of ETH_MTLTxQOMR, when the MAC is in the LPI mode, it exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. 19 1 read-write LPITE LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPITE, LPITXA and LPIEN bits are set, the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for a period indicated by the ETH_MACLETR register. After entering LPI state, if the data path becomes non-IDLE (due to a new packet being accepted for transmission), the Transmitter exits LPI state but does not clear LPIEN bit. This enables the re-entry into LPI state when it is IDLE again. When LPITE is 0, the LPI Auto timer is disabled and MAC Transmitter enters LPI state based on the settings of LPITXA and LPIEN bit descriptions. 20 1 read-write LPITCSE LPI Tx Clock Stop Enable When this bit is set, the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. When this bit is reset, the MAC does not assert sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode. If RGMII Interface is selected, the Tx clock is required for transmitting the LPI pattern. The Tx Clock cannot be gated and so the LPITCSE bit cannot be programmed. 21 1 read-write MACLTCR MACLTCR LPI timers control register 0xD4 0x20 0x03E80000 0xFFFFFFFF TWT LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. 0 16 read-write LST LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. 16 10 read-write MACLETR MACLETR LPI entry timer register 0xD8 0x20 0x00000000 0xFFFFFFFF LPIET LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter LPI mode, after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1. Bits [2:0] are read-only so that the granularity of this timer is in steps of 8 micro-seconds. 0 20 read-write MAC1USTCR MAC1USTCR One-microsecond-tick counter register 0xDC 0x20 0x00000000 0xFFFFFFFF TIC_1US_CNTR 1 s tick Counter The application must program this counter so that the number of clock cycles of CSR clock is 1 s (subtract 1 from the value before programming). For example if the CSR clock is 100 MHz then this field needs to be programmed to 100 - 1 = 99 (which is 0x63). This is required to generate the 1 s events that are used to update some of the EEE related counters. 0 12 read-write MACVR MACVR Version register 0x110 0x20 0x00003142 0xFFFFFFFF SNPSVER IP version 0 8 read-only USERVER ST-defined version 8 8 read-only MACDR MACDR Debug register 0x114 0x20 0x00000000 0xFFFFFFFF RPESTS MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC MII receive protocol engine is actively receiving data, and it is not in the Idle state. 0 1 read-only RFCFCSTS MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. 1 2 read-only TPESTS MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. 16 1 read-only TFCSTS MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module: Status of the previous packet IPG or backoff period to be over 17 2 read-only MACHWF0R MACHWF0R HW feature 0 register 0x11C 0x20 0x0A0D73F7 0xFFFFFFFF MIISEL 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as operating mode. 0 1 read-only GMIISEL 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as operating mode. 1 1 read-only HDSEL Half-duplex Support This bit is set to 1 when the half-duplex mode is selected 2 1 read-only PCSSEL PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, SGMII, or RTBI PHY interface option is selected 3 1 read-only VLHASH VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected 4 1 read-only SMASEL SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected 5 1 read-only RWKSEL PMT Remote Wakeup Packet Enable This bit is set to 1 when the Enable Remote wakeup Packet Detection option is selected 6 1 read-only MGKSEL PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected 7 1 read-only MMCSEL RMON Module Enable This bit is set to 1 when the Enable MAC management counters (MMC) option is selected 8 1 read-only ARPOFFSEL ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected 9 1 read-only TSSEL IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 12 1 read-only EEESEL Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected 13 1 read-only TXCOESEL Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected 14 1 read-only RXCOESEL Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected 16 1 read-only ADDMACADRSEL MAC Addresses 1-31 Selected This bit is set to 1 when the Enable Additional 1-31 MAC Address Registers option is selected 18 5 read-only MACADR32SEL MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected 23 1 read-only MACADR64SEL MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected 24 1 read-only TSSTSSEL Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 25 2 read-only SAVLANINS Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected 27 1 read-only ACTPHYSEL Active PHY Selected When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion: Others: Reserved, must not be used 28 3 read-only MACHWF1R MACHWF1R HW feature 1 register 0x120 0x20 0x11041904 0xFFFFFFFF RXFIFOSIZE MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: 0 5 read-only TXFIFOSIZE MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: 6 5 read-only OSTEN One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. 11 1 read-only PTOEN PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. 12 1 read-only ADVTHWORD IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected 13 1 read-only ADDR64 Address width This field indicates the configured address width. Others: Reserved, must not be used 14 2 read-only DCBEN DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected 16 1 read-only SPHEN Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected 17 1 read-only TSOEN TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected 18 1 read-only DBGMEMA DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected 19 1 read-only AVSEL AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. 20 1 read-only RAVSEL Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected. 21 1 read-only POUOST One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable one step timestamp for PTP over UDP/IP feature is selected. 23 1 read-only HASHTBLSZ Hash Table Size This field indicates the size of the Hash table: 24 2 read-only L3L4FNUM Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: .. 27 4 read-only MACHWF2R MACHWF2R HW feature 2 register 0x124 0x20 0x41000000 0xFFFFFFFF RXQCNT Number of MTL Receive Queues This field indicates the number of MTL Receive queues: .. 0 4 read-only TXQCNT Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: .. 6 4 read-only RXCHCNT Number of DMA Receive Channels This field indicates the number of DMA Receive channels: .. 12 4 read-only RDCSZ Rx DMA Descriptor Cache Size in terms of 16-byte descriptors 16 2 read-only TXCHCNT Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: .. 18 4 read-only TDCSZ Tx DMA Descriptor Cache Size in terms of 16-byte descriptors 22 2 read-only PPSOUTNUM Number of PPS Outputs This field indicates the number of PPS outputs: 24 3 read-only AUXSNAPNUM Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: 28 3 read-only MACHWF3R MACHWF3R HW feature 3 register 0x128 0x20 0x00000020 0xFFFFFFFF NRVF Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: 0 3 read-only CBTISEL Queue/Channel based VLAN tag insertion on Tx enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx feature is selected. 4 1 read-only DVLAN Double VLAN processing enable This bit is set to 1 when Double VLAN processing is enabled. 5 1 read-only MACMDIOAR MACMDIOAR MDIO address register 0x200 0x20 0x00000000 0xFFFFFFFF MB MII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIOS. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in and (ETH_MACMDIODR) as long as this bit is set. For write transfers, the application must first write 16-bit data in the MD field (and also RA field when C45E is set) in register before setting this bit. When C45E is set, it should also write into the RA field of (ETH_MACMDIODR) before initiating a read transfer. When a read transfer is completed (MII busy=0), the data read from the PHY register is valid in the MD field of the register (ETH_MACMDIODR). Note: Even if the addressed PHY is not present, there is no change in the functionality of this bit. 0 1 read-write C45E Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO. 1 1 read-write GOC MII Operation Command This bit indicates the operation command to the PHY. When Clause 22 PHY is enabled, only Write and Read commands are valid. 2 2 read-write SKAP Skip Address Packet When this bit is set, the SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set. 4 1 read-write CR CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits to 1010, the resultant MDC clock is of 12.5 MHz which is above the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks: 8 4 read-write NTC Number of Training Clocks This field controls the number of trailing clock cycles generated on ETH_MDC after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 011 indicates that there are additional three clock cycles on the MDC line after the end of MDIO frame transfer. 12 3 read-write RDA Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY. 16 5 read-write PA Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing. 21 5 read-write BTB Back to Back transactions When this bit is set and the NTC has value greater than 0, then the MAC will inform the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus initiate the next command which will be executed immediately irrespective of the number trailing clocks generated for the previous frame. When this bit is reset, then the read/write command completion (MII busy is cleared) only after the trailing clocks are generated. In this mode, it is ensured that the NTC is always generated after each frame. This bit must not be set when NTC=0. 26 1 read-write PSE Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit preamble and transmit MDIO frames with only 1 preamble bit. When this bit is 0, the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications. 27 1 read-write MACMDIODR MACMDIODR MDIO data register 0x204 0x20 0x00000000 0xFFFFFFFF MD MII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. 0 16 read-write RA Register Address This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for. 16 16 read-write MACARPAR MACARPAR ARP address register 0x210 0x20 0x00000000 0xFFFFFFFF ARPPA ARP Protocol Address This field contains the IPv4 Destination Address of the MAC. This address is used for perfect match with the Protocol Address of Target field in the received ARP packet. 0 32 read-write MACCSRSWCR MACCSRSWCR CSR software control register 0x230 0x20 0x00000000 0xFFFFFFFF RCWE Register Clear on Write 1 Enable When this bit is set, the access mode to some register fields changes to rc_w1 (clear on write) meaning that the application needs to set that respective bit to 1 to clear it. When this bit is reset, the access mode to these register fields remains rc_r (clear on read). 0 1 read-write SEEN Slave Error Response Enable When this bit is set, the MAC responds with a Slave Error for accesses to reserved registers in CSR space. When this bit is reset, the MAC responds with an Okay response to any register accessed from CSR space. 8 1 read-write MACA0HR MACA0HR MAC Address 0 high register 0x300 0x20 0x8000FFFF 0xFFFFFFFF ADDRHI MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 16 read-write AE Address Enable This bit is always set to 1. 31 1 read-only MACA0LR MACA0LR MAC Address 0 low register 0x304 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] (x = 0 to 3) This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MACA1HR MACA1HR MAC Address 1 high register 0x308 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: ETH_MACAxHR[15:8] Bit 28: ETH_MACAxHR[7:0] Bit 27: ETH_MACAxLR[31:24] Bit 26: ETH_MACAxLR[23:16] Bit 25: ETH_MACAxLR[15:8] Bit 24: ETH_MACAxLR[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write SA Source Address When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. 30 1 read-write AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write MACA1LR MACA1LR MAC Address 1 low register 0x30C 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] (x = 0 to 3) This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MACA2HR MACA2HR MAC Address 2 high register 0x310 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: ETH_MACAxHR[15:8] Bit 28: ETH_MACAxHR[7:0] Bit 27: ETH_MACAxLR[31:24] Bit 26: ETH_MACAxLR[23:16] Bit 25: ETH_MACAxLR[15:8] Bit 24: ETH_MACAxLR[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write SA Source Address When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. 30 1 read-write AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write MACA2LR MACA2LR MAC Address 2 low register 0x314 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] (x = 0 to 3) This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MACA3HR MACA3HR MAC Address 3 high register 0x318 0x20 0x0000FFFF 0xFFFFFFFF ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. 0 16 read-write MBC Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: ETH_MACAxHR[15:8] Bit 28: ETH_MACAxHR[7:0] Bit 27: ETH_MACAxLR[31:24] Bit 26: ETH_MACAxLR[23:16] Bit 25: ETH_MACAxLR[15:8] Bit 24: ETH_MACAxLR[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write SA Source Address When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. 30 1 read-write AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write MACA3LR MACA3LR MAC Address 3 low register 0x31C 0x20 0xFFFFFFFF 0xFFFFFFFF ADDRLO MAC Address x [31:0] (x = 0 to 3) This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. 0 32 read-write MMC_CONTROL MMC_CONTROL MMC control register 0x700 0x20 0x00000000 0xFFFFFFFF CNTRST Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. 0 1 read-write CNTSTOPRO Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. 1 1 read-write RSTONRD Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. 2 1 read-write CNTFREEZ MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. 3 1 read-write CNTPRST Counters Preset When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle. This bit, along with the CNTPRSTLVL bit, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. 4 1 read-write CNTPRSTLVL Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2Kbytes) and all packet-counters get preset to 0x7FFF_FFF0 (Half 16). When this bit is high and the CNTPRST bit is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (Full 2Kbytes) and all packet-counters get preset to 0xFFFF_FFF0 (Full 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and packet counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. 5 1 read-write UCDBC Update MMC Counters for Dropped Broadcast Packets The CNTRST bit has a higher priority than the CNTPRST bit. Therefore, when the software tries to set both bits in the same write cycle, all counters are cleared and the CNTPRST bit is not set. When set, the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of (ETH_MACPFR). When reset, the MMC Counters are not updated for dropped Broadcast packets. 8 1 read-write MMC_RX_INTERRUPT MMC_RX_INTERRUPT MMC Rx interrupt register 0x704 0x20 0x00000000 0xFFFFFFFF RXCRCERPIS MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the counter reaches half of the maximum value or the maximum value. 5 1 read-write clear RXALGNERPIS MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the (ETH_RX_ALIGNMENT_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 6 1 read-write clear RXUCGPIS MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the (ETH_RX_UNICAST_PACKETS_GOOD) counter reaches half of the maximum value or the maximum value. 17 1 read-write clear RXLPIUSCIS MMC Receive LPI microsecond counter interrupt status This bit is set when the counter reaches half of the maximum value or the maximum value. 26 1 read-write clear RXLPITRCIS MMC Receive LPI transition counter interrupt status This bit is set when the counter reaches half of the maximum value or the maximum value. 27 1 read-write clear MMC_TX_INTERRUPT MMC_TX_INTERRUPT MMC Tx interrupt register 0x708 0x20 0x00000000 0xFFFFFFFF TXSCOLGPIS MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the (ETH_TX_SINGLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 14 1 read-write clear TXMCOLGPIS MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the (ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 15 1 read-write clear TXGPKTIS MMC Transmit Good Packet Counter Interrupt Status This bit is set when the counter reaches half of the maximum value or the maximum value. 21 1 read-write clear TXLPIUSCIS MMC Transmit LPI microsecond counter interrupt status This bit is set when the counter reaches half of the maximum value or the maximum value. 26 1 read-write clear TXLPITRCIS MMC Transmit LPI transition counter interrupt status This bit is set when the counter reaches half of the maximum value or the maximum value. 27 1 read-write clear MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK MMC Rx interrupt mask register 0x70C 0x20 0x00000000 0xFFFFFFFF RXCRCERPIM MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the (ETH_RX_CRC_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 5 1 read-write RXALGNERPIM MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the (ETH_RX_ALIGNMENT_ERROR_PACKETS) counter reaches half of the maximum value or the maximum value. 6 1 read-write RXUCGPIM MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the (ETH_RX_UNICAST_PACKETS_GOOD) counter reaches half of the maximum value or the maximum value. 17 1 read-write RXLPIUSCIM MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the (ETH_RX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value. 26 1 read-write RXLPITRCIM MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the (ETH_RX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value. 27 1 read-write MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK MMC Tx interrupt mask register 0x710 0x20 0x00000000 0xFFFFFFFF TXSCOLGPIM MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the (ETH_TX_SINGLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 14 1 read-write TXMCOLGPIM MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the (ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value. 15 1 read-write TXGPKTIM MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the (ETH_TX_PACKET_COUNT_GOOD) counter reaches half of the maximum value or the maximum value. 21 1 read-write TXLPIUSCIM MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the (ETH_TX_LPI_USEC_CNTR) counter reaches half of the maximum value or the maximum value. 26 1 read-write TXLPITRCIM MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the (ETH_TX_LPI_TRAN_CNTR) counter reaches half of the maximum value or the maximum value. 27 1 read-write TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS Tx single collision good packets register 0x74C 0x20 0x00000000 0xFFFFFFFF TXSNGLCOLG Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode. 0 32 read-only TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS Tx multiple collision good packets register 0x750 0x20 0x00000000 0xFFFFFFFF TXMULTCOLG Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode. 0 32 read-only TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD Tx packet count good register 0x768 0x20 0x00000000 0xFFFFFFFF TXPKTG Tx Packet Count Good This field indicates the number of good packets transmitted. 0 32 read-only RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS Rx CRC error packets register 0x794 0x20 0x00000000 0xFFFFFFFF RXCRCERR Rx CRC Error Packets This field indicates the number of packets received with CRC error. 0 32 read-only RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS Rx alignment error packets register 0x798 0x20 0x00000000 0xFFFFFFFF RXALGNERR Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode. 0 32 read-only RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD Rx unicast packets good register 0x7C4 0x20 0x00000000 0xFFFFFFFF RXUCASTG Rx Unicast Packets Good This field indicates the number of good unicast packets received. 0 32 read-only TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR Tx LPI microsecond timer register 0x7EC 0x20 0x00000000 0xFFFFFFFF TXLPIUSC Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. 0 32 read-only TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR Tx LPI transition counter register 0x7F0 0x20 0x00000000 0xFFFFFFFF TXLPITRC Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate mode (because of LPITXA bit set in the (ETH_MACLCSR)), the counter will increment. 0 32 read-only RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR Rx LPI microsecond counter register 0x7F4 0x20 0x00000000 0xFFFFFFFF RXLPIUSC Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. 0 32 read-only RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR Rx LPI transition counter register 0x7F8 0x20 0x00000000 0xFFFFFFFF RXLPITRC Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. 0 32 read-only MACL3L4C0R MACL3L4C0R L3 and L4 control 0 register 0x900 0x20 0x00000000 0xFFFFFFFF L3PEN0 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set. 0 1 read-write L3SAM0 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering. 2 1 read-write L3SAIM0 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when the L3SAM0 bit is set. 3 1 read-write L3DAM0 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering. 4 1 read-write L3DAIM0 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when the L3DAM0 bit is set high. 5 1 read-write L3HSBM0 Layer 3 IP SA higher bits match This field contains the number of lower bits of IP source address that are masked for matching in the IPv4 packets. The following list describes the values of this field: 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. Condition: IPv6 packets: This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP source or destination address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high. 6 5 read-write L3HDBM0 Layer 3 IP DA higher bits match This field contains the number of higher bits of IP Destination Address that are masked in the IPv4 packets: 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. Number of bits masked is given by concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set. 11 5 read-write L4PEN0 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set. 16 1 read-write L4SPM0 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. 18 1 read-write L4SPIM0 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4SPM0 bit is set high. 19 1 read-write L4DPM0 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. 20 1 read-write L4DPIM0 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4DPM0 bit is set high. 21 1 read-write MACL4A0R MACL4A0R 0x904 0x20 0x00000000 0xFFFFFFFF L4SP0 Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the (ETH_MACL3L4C0R), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in (ETH_MACL3L4C0R), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP0 Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the (ETH_MACL3L4C0R), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in (ETH_MACL3L4C0R), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MACL3A00R MACL3A00R Layer3 Address 0 filter 0 register 0x910 0x20 0x00000000 0xFFFFFFFF L3A00 Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the (ETH_MACL3L4C0R), this field contains the value to be matched with the IP Source Address field in the IPv4 packets. 0 32 read-write MACL3A10R MACL3A10R Layer3 Address 1 filter 0 register 0x914 0x20 0x00000000 0xFFFFFFFF L3A10 Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the (ETH_MACL3L4C0R), this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. 0 32 read-write MACL3A20R MACL3A20R Layer3 Address 2 filter 0 register 0x918 0x20 0x00000000 0xFFFFFFFF L3A20 Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the , this field is not used. 0 32 read-write MACL3A30R MACL3A30R Layer3 Address 3 filter 0 register 0x91C 0x20 0x00000000 0xFFFFFFFF L3A30 Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the (ETH_MACL3L4C0R), this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the , this field is not used. 0 32 read-write MACL3L4C1R MACL3L4C1R L3 and L4 control 1 register 0x930 0x20 0x00000000 0xFFFFFFFF L3PEN1 Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3 matching is done only when the L3SAM1 or L3DAM1 bit is set. 0 1 read-write L3SAM1 Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN01 bit is set, you should set either this bit or the L3DAM1 bit because either IPv6 SA or DA can be checked for filtering. 2 1 read-write L3SAIM1 Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when the L3SAM1 bit is set. 3 1 read-write L3DAM1 Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN1 bit is set, you should set either this bit or the L3SAM1 bit because either IPv6 DA or SA can be checked for filtering. 4 1 read-write L3DAIM1 Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when the L3DAM1 bit is set high. 5 1 read-write L3HSBM1 Layer 3 IP SA Higher Bits Match This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. This field contains Bits[4:0] of L3HSBM1. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM1 or L3SAM1 bit is set high. 6 5 read-write L3HDBM1 Layer 3 IP DA higher bits match This field contains the number of lower bits of IP Destination Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM1, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM1[1:0] and L3HSBM1 bits: 2: Two LSbs [1:0] are masked .. 127: All bits except MSb are masked This field is valid and applicable only when the L3DAM1 or L3SAM1 bit is set. 11 5 read-write L4PEN1 Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. The Layer 4 matching is done only when the L4SPM1 or L4DPM1 bit is set. 16 1 read-write L4SPM1 Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. 18 1 read-write L4SPIM1 Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4SPM1 bit is set high. 19 1 read-write L4DPM1 Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. 20 1 read-write L4DPIM1 Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4DPM1 bit is set high. 21 1 read-write MACL4A1R MACL4A1R 0x934 0x20 0x00000000 0xFFFFFFFF L4SP1 Layer 4 Source Port Number Field When the L4PEN1 bit is reset and the L4DPM1 bit is set in the (ETH_MACL3L4C1R), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the L4PEN1 and L4DPM1 bits are set in (ETH_MACL3L4C1R), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. 0 16 read-write L4DP1 Layer 4 Destination Port Number Field When the L4PEN1 bit is reset and the L4DPM1 bit is set in the (ETH_MACL3L4C1R), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. When the L4PEN1 and L4DPM1 bits are set in (ETH_MACL3L4C1R), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. 16 16 read-write MACL3A01R MACL3A01R Layer3 address 0 filter 1 Register 0x940 0x20 0x00000000 0xFFFFFFFF L3A01 Layer 3 Address 0 Field When the L3PEN1 and L3SAM1bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset and the L3SAM1 bit is set in the (ETH_MACL3L4C1R), this field contains the value to be matched with the IP Source Address field in the IPv4 packets. 0 32 read-write MACL3A11R MACL3A11R Layer3 address 1 filter 1 register 0x944 0x20 0x00000000 0xFFFFFFFF L3A11 Layer 3 Address 1 Field When the L3PEN1 and L3SAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset and the L3SAM1 bit is set in the (ETH_MACL3L4C1R), this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. 0 32 read-write MACL3A21R MACL3A21R Layer3 address 2 filter 1 Register 0x948 0x20 0x00000000 0xFFFFFFFF L3A21 Layer 3 Address 2 Field When the L3PEN1 and L3SAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset in the , this field is not used. 0 32 read-write MACL3A31R MACL3A31R Layer3 address 3 filter 1 register 0x94C 0x20 0x00000000 0xFFFFFFFF L3A31 Layer 3 Address 3 Field When the L3PEN1 and L3SAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN1 and L3DAM1 bits are set in the (ETH_MACL3L4C1R), this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. When the L3PEN1 bit is reset in the , this field is not used. 0 32 read-write MACTSCR MACTSCR Timestamp control Register 0xB00 0x20 0x00002000 0xFFFFFFFF TSENA Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. When disabled, timestamp is not added for transmit and receive packets and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the Receive side, the MAC processes the 1588 packets only if this bit is set. 0 1 read-write TSCFUPDT Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. When this bit is reset, Coarse method is used to update the system timestamp. 1 1 read-write TSINIT Initialize Timestamp When this bit is set, the system time is initialized (overwritten) with the value specified in the and update register (ETH_MACSTNUR). This bit should be zero before it is updated. This bit is reset when the initialization is complete. 2 1 read-write TSUPDT Update Timestamp When this bit is set, the system time is updated (added or subtracted) with the value specified in and update register (ETH_MACSTNUR). This bit should be zero before updating it. This bit is reset when the update is complete in hardware. 3 1 read-write TSADDREG Update Addend Register When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set. 5 1 read-write TSENALL Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC. 8 1 read-write TSCTRLSSR Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment must be programmed correctly depending on the PTP reference clock frequency and the value of this bit. 9 1 read-write TSVER2ENA Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset, the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588 formats are described in 'PTP Processing and Control'. 10 1 read-write TSIPENA Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset, the MAC ignores the PTP over Ethernet packets. 11 1 read-write TSIPV6ENA Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear, the MAC ignores the PTP transported over IPv6-UDP packets. 12 1 read-write TSIPV4ENA Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset, the MAC ignores the PTP transported over IPv4-UDP packets. This bit is set by default. 13 1 read-write TSEVNTENA Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When this bit is reset, the snapshot is taken for all messages except Announce, Management, and Signaling. For more information about the timestamp snapshots, see . 14 1 read-write TSMSTRENA Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. 15 1 read-write SNAPTYPSEL Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, define the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Register Bits. 16 2 read-write TSENMACADDR Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. When this bit is set, received PTP packets with DA containing a special multicast or unicast address that matches the one programmed in MAC address registers are considered for processing as indicated below, when PTP is directly sent over Ethernet. For normal time stamping operation, MAC address registers 0 to 31 is considered for unicast destination address matching. For PTP offload, only MAC address register 0 is considered for unicast destination address matching. 18 1 read-write TXTSSTSM Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the timestamp status nanoseconds register (ETH_MACTXTSSNR) register. When this bit is reset, the MAC ignores the timestamp status of current packet if the timestamp status of previous packet is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the (ETH_MACTXTSSNR). 24 1 read-write AV8021ASMEN AV 802.1AS Mode Enable When this bit is set, the MAC processes only untagged PTP over Ethernet packets for providing PTP status and capturing timestamp snapshots, that is, IEEE 802.1AS operating mode. When PTP offload feature is enabled, for the purpose of PTP offload, the transport specific field in the PTP header is generated and checked based on the value of this bit. 28 1 read-write MACSSIR MACSSIR Sub-second increment register 0xB04 0x20 0x00000000 0xFFFFFFFF SSINC Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when the PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time Nanoseconds register has an accuracy of 1 ns [TSCTRLSSR bit is set in (ETH_MACTSCR)]. When TSCTRLSSR is cleared, the Nanoseconds register has a resolution of ~0.465 ns. In this case, you should program a value of 43 (0x2B) which is derived by 20 ns/0.465. 16 8 read-write MACSTSR MACSTSR System time seconds register 0xB08 0x20 0x00000000 0xFFFFFFFF TSS Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC. 0 32 read-only MACSTNR MACSTNR System time nanoseconds register 0xB0C 0x20 0x00000000 0xFFFFFFFF TSSS Timestamp Sub-seconds The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When TSCTRLSSR is set in , each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to zero. 0 31 read-only MACSTSUR MACSTSUR System time seconds update register 0xB10 0x20 0x00000000 0xFFFFFFFF TSS Timestamp Seconds The value in this field is the sub-second part of the update. When ADDSUB is reset, this field must be programmed with the sub-second part of the update value, with an accuracy based on the TSCTRLSSR bit of the . When ADDSUB is set, then this field must be programmed with the complement of the sub-second part of the update value as described below. When TSCTRLSSR is set, then the programmed value must be 10^9 - sub-second value>. When TSCTRLSSR is reset, then the programmed value must be 2^31 - sub-second_value> For example, when TSCTRLSSR bit is set and if 2.000000001 seconds need to be subtracted from the system time, then the TSS field in the register (ETH_MACSTSUR) must be 0xFFFF_FFFE (that is, 2^32 - 2), ADDSUB bit in this register should be set, and the TSSS field must be 0x3B9A_C9FF (that is, 10^9 - 1). 0 32 read-write MACSTNUR MACSTNUR 0xB14 0x20 0x00000000 0xFFFFFFFF TSSS Timestamp Sub-seconds The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When the TSCTRLSSR bit is set in the , each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. 0 31 read-write ADDSUB Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. 31 1 read-write MACTSAR MACTSAR Timestamp addend register 0xB18 0x20 0x00000000 0xFFFFFFFF TSAR Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. 0 32 read-write MACTSSR MACTSSR Timestamp status register 0xB20 0x20 0x00000000 0xFFFFFFFF TSSOVF Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in software control register (ETH_MACCSRSWCR) is set) 0 1 read-write clear TSTARGT0 Timestamp Target Time Reached When set, this bit indicates that the value of system time is greater than or equal to the value specified in the and nanoseconds register (ETH_MACPPSTTNR). This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in software control register (ETH_MACCSRSWCR) is set) 1 1 read-write clear AUXTSTRIG Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in software control register (ETH_MACCSRSWCR) is set). 2 1 read-write clear TSTRGTERR0 Timestamp Target Time Error This bit is set when the latest target time programmed in the register (ETH_MACPPSTTSR) and (ETH_MACPPSTTNR) elapses. This bit is cleared when the application reads this bit (or write of 1 when RCWE bit in is set). 3 1 read-write clear TXTSSIS Tx Timestamp Status Interrupt Status When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the (ETH_MACTXTSSNR) and . When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the and timestamp status seconds register (ETH_MACTXTSSSR), for PTO generated Delay Request and Pdelay request packets. This bit is cleared when the is read (or write of 1 when RCWE bit in is set). 15 1 read-write clear ATSSTN Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: Bit 16: Auxiliary trigger 0 Bit 17: Auxiliary trigger 1 Bit 18: Auxiliary trigger 2 Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. 16 4 read-write clear ATSSTM Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. 24 1 read-write clear ATSNS Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. A value equal to the depth of FIFO (4) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. 25 5 read-only MACTXTSSNR MACTXTSSNR Tx timestamp status nanoseconds register 0xB30 0x20 0x00000000 0xFFFFFFFF TXTSSLO Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp. 0 31 read-write clear TXTSSMIS Transmit Timestamp Status Missed When this bit is set, it indicates one of the following: The timestamp of the current packet is ignored if TXTSSTSM bit of the control Register (ETH_MACTSCR) is reset The timestamp of the previous packet is overwritten with timestamp of the current packet if TXTSSTSM bit of the is set. 31 1 read-only MACTXTSSSR MACTXTSSSR Tx timestamp status seconds register 0xB34 0x20 0x00000000 0xFFFFFFFF TXTSSHI Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp. 0 32 read-only MACACR MACACR Auxiliary control register 0xB40 0x20 0x00000000 0xFFFFFFFF ATSFC Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, the auxiliary snapshots are stored in the FIFO. 0 1 read-write ATSEN0 Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg0 input is enabled. When this bit is reset, the events on this input are ignored. 4 1 read-write ATSEN1 Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg1 input is enabled. When this bit is reset, the events on this input are ignored. 5 1 read-write ATSEN2 Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg2 input is enabled. When this bit is reset, the events on this input are ignored. 6 1 read-write ATSEN3 Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. When this bit is set, the auxiliary snapshot of the event on eth_ptp_trg3 input is enabled. When this bit is reset, the events on this input are ignored. 7 1 read-write MACATSNR MACATSNR Auxiliary timestamp nanoseconds register 0xB48 0x20 0x00000000 0xFFFFFFFF AUXTSLO Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. 0 31 read-only MACATSSR MACATSSR Auxiliary timestamp seconds register 0xB4C 0x20 0x00000000 0xFFFFFFFF AUXTSHI Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. 0 32 read-only MACTSIACR MACTSIACR Timestamp Ingress asymmetric correction register 0xB50 0x20 0x00000000 0xFFFFFFFF OSTIAC One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 2^16. For example, 2.5 ns is represented as 0x00028000. The value can also be negative, which is represented in 2's complement form with bit 31 representing the sign bit. 0 32 read-write MACTSEACR MACTSEACR Timestamp Egress asymmetric correction register 0xB54 0x20 0x00000000 0xFFFFFFFF OSTEAC One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied by 2^16. For example, if the required correction is +2.5 ns, the programmed value must be 0xFFFD_8000, which is the 2's complement of 0x0002_8000(2.5 * 2^16). Similarly, if the required correction is -3.3 ns, the programmed value is 0x0003_4CCC (3.3 *2^16). 0 32 read-write MACTSICNR MACTSICNR Timestamp Ingress correction nanosecond register 0xB58 0x20 0x00000000 0xFFFFFFFF TSIC Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression. 0 32 read-write MACTSECNR MACTSECNR Timestamp Egress correction nanosecond register 0xB5C 0x20 0x00000000 0xFFFFFFFF TSEC Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression. 0 32 read-write MACPPSCR MACPPSCR ETH_MACPPSCR 0xB70 0x20 0x00000000 0xFFFFFFFF PPSCTRL PPS Output Frequency Control This field controls the frequency of the PPS output (eth_ptp_pps_out) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: .. Note: In the binary rollover mode, the PPS output (eth_ptp_pps_out) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of One clock of 50 percent duty cycle and 537 ms period Second clock of 463 ms period (268 ms low and 195 ms high) When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of Three clocks of 50 percent duty cycle and 268 ms period Fourth clock of 195 ms period (134 ms low and 61 ms high) This behavior is because of the non-linear toggling of bits in the digital rollover mode in the ETH_MACSTNR register. 0 4 read-write PPSEN0 Flexible PPS Output Mode Enable When this bit is set, PPSCTRL[3:0] function as PPSCMD. When this bit is reset, PPSCTRL[3:0] function as PPSCTRL (Fixed PPS mode). 4 1 read-write TRGTMODSEL0 Target Time Register Mode for PPS Output This field indicates the Target Time registers ((ETH_MACPPSTTSR) and ) mode for PPS output signal: 5 2 read-write MACPPSCRALTERNATE MACPPSCRALTERNATE ETH_MACPPSCRALTERNATE MACPPSCR 0xB70 0x20 0x00000000 0xFFFFFFFF PPSCMD Flexible PPS Output (eth_ptp_pps_out) Control Programming these bits with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The software should ensure that these bits are programmed only when they are all zero. The following list describes the values of PPSCMD0: This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS Width Register. This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by the 'Stop Pulse train at time' or 'Stop Pulse Train immediately' commands. This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time. This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses. This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010). This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command. 0 4 read-write PPSEN0 Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode). 4 1 read-write TRGTMODSEL0 Target Time Register Mode for PPS Output This field indicates the Target Time registers (MAC registers 96 and 97) mode for PPS output signal: 5 2 read-write MACPPSTTSR MACPPSTTSR PPS target time seconds register 0xB80 0x20 0x00000000 0xFFFFFFFF TSTRH0 PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on Target Time mode selected for the corresponding PPS output in the . 0 32 read-write MACPPSTTNR MACPPSTTNR PPS target time nanoseconds register 0xB84 0x20 0x00000000 0xFFFFFFFF TTSL0 Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGTMODSEL0 field (Bits [6:5]) in . When the TSCTRLSSR bit is set in the , this value should not exceed 0x3B9A_C9FF. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. 0 31 read-write TRGTBUSY0 PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the (ETH_MACPPSCR) is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. 31 1 read-write MACPPSIR MACPPSIR PPS interval register 0xB88 0x20 0x00000000 0xFFFFFFFF PPSINT0 PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of sub-second increment value), you should program value 4 (5-1) in this register. 0 32 read-write MACPPSWR MACPPSWR PPS width register 0xB8C 0x20 0x00000000 0xFFFFFFFF PPSWIDTH0 PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20 ns), and width between the rising and corresponding falling edges of PPS signal output is 80 ns (that is, four units of sub-second increment value), you should program value 3 (4-1) in this register. Note: The value programmed in this register must be lesser than the value programmed in . 0 32 read-write MACPOCR MACPOCR PTP Offload control register 0xBC0 0x20 0x00000000 0xFFFFFFFF PTOEN PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. 0 1 read-write ASYNCEN Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Clock Master mode. 1 1 read-write APDREQEN Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Peer-to-Peer Transparent mode. 2 1 read-write ASYNCTRIG Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation. 4 1 read-write APDREQTRIG Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this operation. 5 1 read-write DRRDIS Disable PTO Delay Request/Response response generation When this bit is set, the Delay Request and Delay response will not be generated for received SYNC and Delay request packet respectively, as required by the programmed mode. 6 1 read-write DN Domain Number This field indicates the domain Number in which the PTP node is operating. 8 8 read-write MACSPI0R MACSPI0R PTP Source Port Identity 0 Register 0xBC4 0x20 0x00000000 0xFFFFFFFF SPI0 Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. 0 32 read-write MACSPI1R MACSPI1R PTP Source port identity 1 register 0xBC8 0x20 0x00000000 0xFFFFFFFF SPI1 Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. 0 32 read-write MACSPI2R MACSPI2R PTP Source port identity 2 register 0xBCC 0x20 0x00000000 0xFFFFFFFF SPI2 Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. 0 16 read-write MACLMIR MACLMIR Log message interval register 0xBD0 0x20 0x00000000 0xFFFFFFFF LSI Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. 0 8 read-write DRSYNCR Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. 2: for every 4 SYNC messages 3: for every 8 SYNC messages 4: for every 16 SYNC messages 5: for every 32 SYNC messages Others: Reserved, must not be used The master sends this information (logMinDelayReqInterval) in the DelayResp PTP messages to the slave. The reception processes this value from the received DelayResp messages and updates this field accordingly. In the Slave mode, the host must not write/update this register unless it has to override the received value. In Master mode, the sum of this field and logSyncInterval (LSI) field is provided in the logMinDelayReqInterval field of the generated multicast Delay_Resp PTP message. 8 3 read-write LMPDRI Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. 24 8 read-write MTLOMR MTLOMR Operating mode Register 0xC00 0x20 0x00000000 0xFFFFFFFF DTXSTS Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset, the Tx packet status received from the MAC is forwarded to the application. 1 1 read-write CNTPRST Counters Preset When this bit is set: is initialized/preset to 0x7F0. Missed Packet and Overflow Packet counters in overflow counter register (ETH_MTLRXQMPOCR) is initialized/preset to 0x7F0 This bit is cleared automatically. 8 1 read-write CNTCLR Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. If this bit is set along with CNTPRST bit, CNTPRST has precedence. 9 1 read-write MTLISR MTLISR Interrupt status Register 0xC20 0x20 0x00000000 0xFFFFFFFF Q0IS Queue interrupt status This bit indicates that an interrupt has been generated by Queue. To reset this bit, read ETH_MTLQICSR register to identify the interrupt cause and clear the source. 0 1 read-only MTLTXQOMR MTLTXQOMR Tx queue operating mode Register 0xD00 0x20 0x00070008 0xFFFFFFFF FTQ Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the ETH_MTLTXQOMR register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (eth_mii_tx_clk) should be active. 0 1 read-write TSF Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped. 1 1 read-write TXQEN Transmit Queue Enable This field is used to enable/disable the transmit queue . Others: Reserved, must not be used. Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field. 2 2 read-only TTC Transmit Threshold Control These bits control the threshold level of the MTL Tx queue. The transmission starts when the packet size within the MTL Tx queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. 4 3 read-write TQS Transmit queue size This field indicates the size of the allocated transmit queues in blocks of 256 bytes. Queue size range from 256 bytes (TQS=0b000) to 2048 bytes (TQS=0b111). 16 3 read-write MTLTXQUR MTLTXQUR Tx queue underflow register 0xD04 0x20 0x00000000 0xFFFFFFFF UFFRMCNT Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read. 0 11 read-write clear UFCNTOVF Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. 11 1 read-write clear MTLTXQDR MTLTXQDR Tx queue debug Register 0xD08 0x20 0x00000000 0xFFFFFFFF TXQPAUSED Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx queue is in the Pause condition (in the full-duplex only mode) because of the following: Reception of the PFC packet for the priorities assigned to the Tx queue when PFC is enabled Reception of 802.3x Pause packet when PFC is disabled 0 1 read-only TRCSTS MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 1 2 read-only TWCSTS MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx queue Write Controller is active, and it is transferring the data to the Tx queue. 3 1 read-only TXQSTS MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx queue is not empty and some data is left for transmission. 4 1 read-only TXSTSFSTS MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission. 5 1 read-only PTXQ Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx queue. When the DTXSTS bit of register is set to 1, this field does not reflect the number of packets in the Transmit queue. 16 3 read-only STXSTSF Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of status words in Tx Status FIFO. 20 3 read-only MTLQICSR MTLQICSR Queue interrupt control status Register 0xD2C 0x20 0x00000000 0xFFFFFFFF TXUNFIS Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit. 0 1 read-write TXUIE Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled. 8 1 read-write RXOVFIS Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit. 16 1 read-write RXOIE Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled. 24 1 read-write MTLRXQOMR MTLRXQOMR Rx queue operating mode register 0xD30 0x20 0x00700000 0xFFFFFFFF RTC Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred. This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1. 0 2 read-write FUP Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01. 3 1 read-write FEP Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, receive error, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped. When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA. 4 1 read-write RSF Receive Queue Store and Forward When this bit is set, the Ethernet peripheral reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register. 5 1 read-write DIS_TCP_EF Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC. When this bit is reset, all error packets are dropped if the FEP bit is reset. 6 1 read-write RQS Receive Queue Size This field is read-only and the configured Rx FIFO size in blocks of 256 bytes is reflected in the reset value. The size of the Queue is (RQS + 1) * 256 bytes. 20 3 read-only MTLRXQMPOCR MTLRXQMPOCR Rx queue missed packet and overflow counter register 0xD34 0x20 0x00000000 0xFFFFFFFF OVFPKTCNT Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet peripheral because of Receive queue overflow. This counter is incremented each time the Ethernet peripheral discards an incoming packet because of overflow. This counter is reset when this register is read. 0 11 read-write clear OVFCNTOVF Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. 11 1 read-write clear MISPKTCNT Missed Packet Counter This field indicates the number of packets missed by the Ethernet peripheral because the application requested to flush the packets for this queue. This counter is reset when this register is read. This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability. 16 11 read-write clear MISCNTOVF Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. 27 1 read-write clear MTLRXQDR MTLRXQDR Rx queue debug register 0xD38 0x20 0x00000000 0xFFFFFFFF RWCSTS MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx queue. 0 1 read-only RRCSTS MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 1 2 read-only RXQSTS MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx queue: 4 2 read-only PRXQ Number of Packets in Receive Queue This field indicates the current number of packets in the Rx queue. The theoretical maximum value for this field is 256Kbyte/16bytes = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size. 16 14 read-only DMAMR DMAMR DMA mode register 0x1000 0x20 0x00000000 0xFFFFFFFF SWR Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all clock domains. Before reprogramming any register, a value of zero should be read in this bit. Note: The reset operation is complete only when all resets in all active clock domains are deasserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. 0 1 read-write DA DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit. The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path. 1 1 read-write TXPR Transmit priority When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus. 11 1 read-write PR Priority ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. 12 3 read-write INTM Interrupt Mode This field defines the interrupt mode of the Ethernet peripheral. The behavior of the interrupt signal and of the RI/TI bits in the ETH_DMACSR register changes depending on the INTM value (refer to behavior). 16 2 read-write DMASBMR DMASBMR System bus mode register 0x1004 0x20 0x00000000 0xFFFFFFFF FB Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers of specified length (INCRx or SINGLE). When this bit is set to 0, the AHB master will initiate transfers of unspecified length (INCR) or SINGLE transfers. 0 1 read-write AAL Address-Aligned Beats When this bit is set to 1, the master performs address-aligned burst transfers on Read and Write channels. 12 1 read-write MB Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the AHB master performs fixed burst transfers (INCRx and SINGLE). 14 1 read-only RB Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. 15 1 read-only DMAISR DMAISR Interrupt status register 0x1008 0x20 0x00000000 0xFFFFFFFF DC0IS DMA Channel Interrupt Status This bit indicates an interrupt event in DMA Channel. To reset this bit to 0, the software must read the corresponding register in DMA Channel to get the exact cause of the interrupt and clear its source. 0 1 read-only MTLIS MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. 16 1 read-only MACIS MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. 17 1 read-only DMADSR DMADSR Debug status register 0x100C 0x20 0x00000000 0xFFFFFFFF AXWHSTS AHB Master Write Channel When high, this bit indicates that the write channel of the AHB master FMSs are in non-idle state. 0 1 read-only RPS0 DMA Channel Receive Process State This field indicates the Rx DMA FSM state for Channel: The MSB of this field always returns 0. This field does not generate an interrupt. 8 4 read-only TPS0 DMA Channel Transmit Process State This field indicates the Tx DMA FSM state for Channel: The MSB of this field always returns 0. This field does not generate an interrupt. 12 4 read-only DMACCR DMACCR Channel control register 0x1100 0x20 0x00000000 0xFFFFFFFF MSS Maximum Segment Size This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of (ETH_DMACTXCR) is set. The value programmed in this field must be more than the configured Data width in bytes. It is recommended to use a MSS value of 64 bytes or more. 0 14 read-write PBLX8 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in register (ETH_DMACTXCR) is multiplied eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. 16 1 read-write DSL Descriptor Skip Length This bit specifies the 32-bit word number to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous. 18 3 read-write DMACTXCR DMACTXCR Channel transmit control register 0x1104 0x20 0x00000000 0xFFFFFFFF ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the following positions: The current position in the list: this is the base address of the Transmit list set by the ETH_DMACTXDLAR register. The position at which the transmission was previously stopped If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the ETH_DMACSR is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the ETH_DMACTXDLAR register, the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program ETH_DMACTXDLAR register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. 0 1 read-write OSF Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 4 1 read-write TSE TCP Segmentation Enabled When this bit is set, the DMA performs the TCP segmentation for packets in Channel i. The TCP segmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor. When this bit is set, the TxPBL value must be greater than or equal to 4. 12 1 read-write TXPBL Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: Set the PBLx8 mode in ETH_DMACCR. Set the TXPBL[5:0]. Note: The maximum value of TXPBL must be less than or equal to half the Tx Queue size (TQS field of ) in terms of beats. This is required so that the Tx Queue has space to store at least another Tx PBL worth of data while the MTL Tx Queue Controller is transferring data to MAC. The total locations in Tx Queue of size 2048 bytes is 512, TXPBL and 8xPBL needs to be programmed to less than or equal to 512/2. 16 6 read-write DMACRXCR DMACRXCR Channel receive control register 0x1108 0x20 0x00000000 0xFFFFFFFF SR Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: The current position in the list: this is the address set by the list address register (ETH_DMACRXDLAR). The position at which the Rx process was previously stopped If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the ETH_DMACSR is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the register (ETH_DMACRXDLAR), the DMA behavior is unpredictable. When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state. 0 1 read-write RBSZ Receive Buffer size This field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16 Kbytes. Note: The buffer size must be a multiple of 4. This is required even if the value of buffer address pointer is not aligned to bus width. If the buffer size is not a multiple of 4, it may result into an undefined behavior. The LSB bits (1:0) are ignored and the DMA internally takes the LSB bits as all-zero. Therefore, these LSB bits are read-only (RO). 1 14 read-write RXPBL Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: Set the PBLx8 mode in the ETH_DMACCR. Set the RXPBL[5:0]. Note: The maximum value of RXPBL must be less than or equal to half the Rx Queue size (RQS field of ) in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the MTL Rx Queue Controller is transferring data to MAC.The total locations in Rx Queue of size 2048 bytes is 512, RXPBL and 8xPBL needs to be programmed to less than or equal to 512/2. 16 6 read-write RPF DMA Rx Channel Packet Flush When this bit is set to 1, the Ethernet peripheral will automatically flush the packet from the Rx queues destined to DMA Rx Channel when the DMA Rx Channel is stopped after a system bus error has occurred. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this RxDMA was stopped, are flushed out. The packets that are received by the MAC after the RxDMA is re-started are routed to the RxDMA. The flushing happens on the Read side of the Rx queue. When this bit is set to 0 the Ethernet peripheral does not flush the packet in the Rx queue destined to DMA Rx Channel after the DMA is stopped due to a system bus error. This might cause head-of-line blocking in the corresponding RxQueue. Note: The stopping of packet flow from a Rx DMA Channel to the application by setting RPF works only when there is one-to-one mapping of Rx Queue to Rx DMA channels. In Dynamic mapping mode, setting RPF bit in ETH_DMACRXCR register might flush packets from unintended Rx Queues which are destined to the stopped Rx DMA Channel. 31 1 read-write DMACTXDLAR DMACTXDLAR Channel Tx descriptor list address register 0x1114 0x20 0x00000000 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). 0 32 read-write DMACRXDLAR DMACRXDLAR Channel Rx descriptor list address register 0x111C 0x20 0x00000000 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). 0 32 read-write DMACTXDTPR DMACTXDTPR Channel Tx descriptor tail pointer register 0x1120 0x20 0x00000000 0xFFFFFFFF TDT Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers. 0 32 read-write DMACRXDTPR DMACRXDTPR Channel Rx descriptor tail pointer register 0x1128 0x20 0x00000000 0xFFFFFFFF RDT Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors referenced between the head and the tail pointer registers. 0 32 read-write DMACTXRLR DMACTXRLR Channel Tx descriptor ring length register 0x112C 0x20 0x00000000 0xFFFFFFFF TDRL Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. It is recommended to put a minimum ring descriptor length of 4. For example, you can program any value up to 0x3FF in this field. This field is 10 bits wide, if you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9. 0 10 read-write DMACRXRLR DMACRXRLR Channel Rx descriptor ring length register 0x1130 0x20 0x00000000 0xFFFFFFFF RDRL Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example, you can program any value up to 0x3FF in this field. This field is 10-bit wide. If you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9. 0 10 read-write ARBS Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS[7:0] is programmed to a non-zero value. When ARBS[7:0] = 0, Rx Buffer1 and Rx Buffer2 sizes are based on RBSZ[13:0] field of . 16 8 read-write DMACIER DMACIER Channel interrupt enable register 0x1134 0x20 0x00000000 0xFFFFFFFF TIE Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. 0 1 read-write TXSE Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled. 1 1 read-write TBUE Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled. 2 1 read-write RIE Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. 6 1 read-write RBUE Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled. 7 1 read-write RSE Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled. 8 1 read-write RWTE Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled. 9 1 read-write ETIE Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled. 10 1 read-write ERIE Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled. 11 1 read-write FBEE Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled. 12 1 read-write CDEE Context Descriptor Error Enable When this bit is set along with the AIE bit, the Context Descriptor error interrupt is enabled. When this bit is reset, the Context Descriptor error interrupt is disabled. 13 1 read-write AIE Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the : Bit 1: Transmit Process Stopped Bit 7: Rx Buffer Unavailable Bit 8: Receive Process Stopped Bit 9: Receive Watchdog Timeout Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error When this bit is reset, the abnormal interrupt summary is disabled. 14 1 read-write NIE Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the : Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt When this bit is reset, the normal interrupt summary is disabled. 15 1 read-write DMACRXIWTR DMACRXIWTR Channel Rx interrupt watchdog timer register 0x1138 0x20 0x00000000 0xFFFFFFFF RWT Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the ETH_DMACSR, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet. 0 8 read-write RWTU Receive Interrupt Watchdog Timer Count Units This field indicates the number of system clock cycles corresponding to one unit in RWT[7:0] field. For example, when RWT[7:0] = 2 and RWTU[1:0] = 1, the watchdog timer is set for 2 * 512 = 1024 system clock cycles. 16 2 read-write DMACCATXDR DMACCATXDR Channel current application transmit descriptor register 0x1144 0x20 0x00000000 0xFFFFFFFF CURTDESAPTR Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset. 0 32 read-only DMACCARXDR DMACCARXDR Channel current application receive descriptor register 0x114C 0x20 0x00000000 0xFFFFFFFF CURRDESAPTR Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset. 0 32 read-only DMACCATXBR DMACCATXBR Channel current application transmit buffer register 0x1154 0x20 0x00000000 0xFFFFFFFF CURTBUFAPTR Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset. 0 32 read-only DMACCARXBR DMACCARXBR Channel current application receive buffer register 0x115C 0x20 0x00000000 0xFFFFFFFF CURRBUFAPTR Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset. 0 32 read-only DMACSR DMACSR Channel status register 0x1160 0x20 0x00000000 0xFFFFFFFF TI Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. 0 1 read-write TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write TBU Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPSi field of the register (ETH_DMADSR) register explains the Transmit Process state transitions. To resume processing the Transmit descriptors, the application should do the following: 1. Change the ownership of the descriptor by setting Bit 31 of TDES3. 2. Issue a Transmit Poll Demand command. For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel. 2 1 read-write RI Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES1 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. The reception remains in the Running state. 6 1 read-write RBU Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. 7 1 read-write RPS Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. 8 1 read-write RWT Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. 9 1 read-write ETI Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. 10 1 read-write ERI Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.The RI bit of this register automatically clears this bit. 11 1 read-write FBE Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. 12 1 read-write CDE Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow (intermediate descriptor) or all ones descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. 13 1 read-write AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMACIER register: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. 14 1 read-write NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the ETH_DMACIER register: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in ETH_DMACIER register) affect the Normal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. 15 1 read-write TEB Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. Bit[2]: Error during data transfer by Tx DMA when 1, no Error during data transfer by Tx DMA when 0 Bit[1]: Error during descriptor access when 1, Error during data buffer access when 0 Bit[0]: Error during read transfer when 1, Error during write transfer when 0 This field is valid only when the FBE bit is set. This field does not generate an interrupt. 16 3 read-only REB Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. Bit [2]: Error during data transfer by Rx DMA when 1, no Error during data transfer by Rx DMA when 0. Bit[1]: Error during descriptor access when 1, Error during data buffer access when 0 Bit[0]: Error during read transfer when 1, Error during write transfer when 0 This field is valid only when the FBE bit is set. This field does not generate an interrupt. 19 3 read-only DMACMFCR DMACMFCR Channel missed frame count register 0x116C 0x20 0x00000000 0xFFFFFFFF MFC Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in register (ETH_DMACRXCR). The counter gets cleared when this register is read. 0 11 read-write clear MFCO Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. 15 1 read-write clear DMA1 DMA controller DMA 0x40020000 0x0 0x400 registers DMA_STR0 DMA1 Stream0 11 DMA_STR1 DMA1 Stream1 12 DMA_STR2 DMA1 Stream2 13 DMA_STR3 DMA1 Stream3 14 DMA_STR4 DMA1 Stream4 15 DMA_STR5 DMA1 Stream5 16 DMA_STR6 DMA1 Stream6 17 DMA1_STR7 DMA1 Stream7 47 LISR LISR low interrupt status register 0x0 0x20 read-only 0x00000000 TCIF0 Stream x transfer complete interrupt flag (x = 3..0) 5 1 TCIF0 NotComplete No transfer complete event on stream x 0 Complete A transfer complete event occurred on stream x 1 TCIF3 Stream x transfer complete interrupt flag (x = 3..0) 27 1 HTIF0 Stream x half transfer interrupt flag (x=3..0) 4 1 HTIF0 NotHalf No half transfer event on stream x 0 Half A half transfer event occurred on stream x 1 HTIF3 Stream x half transfer interrupt flag (x=3..0) 26 1 TEIF0 Stream x transfer error interrupt flag (x=3..0) 3 1 TEIF0 NoError No transfer error on stream x 0 Error A transfer error occurred on stream x 1 TEIF3 Stream x transfer error interrupt flag (x=3..0) 25 1 DMEIF0 Stream x direct mode error interrupt flag (x=3..0) 2 1 DMEIF0 NoError No Direct Mode error on stream x 0 Error A Direct Mode error occurred on stream x 1 DMEIF3 Stream x direct mode error interrupt flag (x=3..0) 24 1 FEIF0 Stream x FIFO error interrupt flag (x=3..0) 0 1 FEIF0 NoError No FIFO error event on stream x 0 Error A FIFO error event occurred on stream x 1 FEIF3 Stream x FIFO error interrupt flag (x=3..0) 22 1 TCIF2 Stream x transfer complete interrupt flag (x = 3..0) 21 1 HTIF2 Stream x half transfer interrupt flag (x=3..0) 20 1 TEIF2 Stream x transfer error interrupt flag (x=3..0) 19 1 DMEIF2 Stream x direct mode error interrupt flag (x=3..0) 18 1 FEIF2 Stream x FIFO error interrupt flag (x=3..0) 16 1 TCIF1 Stream x transfer complete interrupt flag (x = 3..0) 11 1 HTIF1 Stream x half transfer interrupt flag (x=3..0) 10 1 TEIF1 Stream x transfer error interrupt flag (x=3..0) 9 1 DMEIF1 Stream x direct mode error interrupt flag (x=3..0) 8 1 FEIF1 Stream x FIFO error interrupt flag (x=3..0) 6 1 HISR HISR high interrupt status register 0x4 0x20 read-only 0x00000000 TCIF4 Stream x transfer complete interrupt flag (x=7..4) 5 1 TCIF4 NotComplete No transfer complete event on stream x 0 Complete A transfer complete event occurred on stream x 1 TCIF7 Stream x transfer complete interrupt flag (x=7..4) 27 1 HTIF4 Stream x half transfer interrupt flag (x=7..4) 4 1 HTIF4 NotHalf No half transfer event on stream x 0 Half A half transfer event occurred on stream x 1 HTIF7 Stream x half transfer interrupt flag (x=7..4) 26 1 TEIF4 Stream x transfer error interrupt flag (x=7..4) 3 1 TEIF4 NoError No transfer error on stream x 0 Error A transfer error occurred on stream x 1 TEIF7 Stream x transfer error interrupt flag (x=7..4) 25 1 DMEIF4 Stream x direct mode error interrupt flag (x=7..4) 2 1 DMEIF4 NoError No Direct Mode error on stream x 0 Error A Direct Mode error occurred on stream x 1 DMEIF7 Stream x direct mode error interrupt flag (x=7..4) 24 1 FEIF4 Stream x FIFO error interrupt flag (x=7..4) 0 1 FEIF4 NoError No FIFO error event on stream x 0 Error A FIFO error event occurred on stream x 1 FEIF7 Stream x FIFO error interrupt flag (x=7..4) 22 1 TCIF6 Stream x transfer complete interrupt flag (x=7..4) 21 1 HTIF6 Stream x half transfer interrupt flag (x=7..4) 20 1 TEIF6 Stream x transfer error interrupt flag (x=7..4) 19 1 DMEIF6 Stream x direct mode error interrupt flag (x=7..4) 18 1 FEIF6 Stream x FIFO error interrupt flag (x=7..4) 16 1 TCIF5 Stream x transfer complete interrupt flag (x=7..4) 11 1 HTIF5 Stream x half transfer interrupt flag (x=7..4) 10 1 TEIF5 Stream x transfer error interrupt flag (x=7..4) 9 1 DMEIF5 Stream x direct mode error interrupt flag (x=7..4) 8 1 FEIF5 Stream x FIFO error interrupt flag (x=7..4) 6 1 LIFCR LIFCR low interrupt flag clear register 0x8 0x20 write-only 0x00000000 CTCIF0 Stream x clear transfer complete interrupt flag (x = 3..0) 5 1 CTCIF0 Clear Clear the corresponding TCIFx flag 1 CTCIF3 Stream x clear transfer complete interrupt flag (x = 3..0) 27 1 CHTIF0 Stream x clear half transfer interrupt flag (x = 3..0) 4 1 CHTIF0 Clear Clear the corresponding HTIFx flag 1 CHTIF3 Stream x clear half transfer interrupt flag (x = 3..0) 26 1 CTEIF0 Stream x clear transfer error interrupt flag (x = 3..0) 3 1 CTEIF0 Clear Clear the corresponding TEIFx flag 1 CTEIF3 Stream x clear transfer error interrupt flag (x = 3..0) 25 1 CDMEIF0 Stream x clear direct mode error interrupt flag (x = 3..0) 2 1 CDMEIF0 Clear Clear the corresponding DMEIFx flag 1 CDMEIF3 Stream x clear direct mode error interrupt flag (x = 3..0) 24 1 CFEIF0 Stream x clear FIFO error interrupt flag (x = 3..0) 0 1 CFEIF0 Clear Clear the corresponding CFEIFx flag 1 CFEIF3 Stream x clear FIFO error interrupt flag (x = 3..0) 22 1 CTCIF2 Stream x clear transfer complete interrupt flag (x = 3..0) 21 1 CHTIF2 Stream x clear half transfer interrupt flag (x = 3..0) 20 1 CTEIF2 Stream x clear transfer error interrupt flag (x = 3..0) 19 1 CDMEIF2 Stream x clear direct mode error interrupt flag (x = 3..0) 18 1 CFEIF2 Stream x clear FIFO error interrupt flag (x = 3..0) 16 1 CTCIF1 Stream x clear transfer complete interrupt flag (x = 3..0) 11 1 CHTIF1 Stream x clear half transfer interrupt flag (x = 3..0) 10 1 CTEIF1 Stream x clear transfer error interrupt flag (x = 3..0) 9 1 CDMEIF1 Stream x clear direct mode error interrupt flag (x = 3..0) 8 1 CFEIF1 Stream x clear FIFO error interrupt flag (x = 3..0) 6 1 HIFCR HIFCR high interrupt flag clear register 0xC 0x20 write-only 0x00000000 CTCIF4 Stream x clear transfer complete interrupt flag (x = 7..4) 5 1 CTCIF4 Clear Clear the corresponding TCIFx flag 1 CTCIF7 Stream x clear transfer complete interrupt flag (x = 7..4) 27 1 CHTIF4 Stream x clear half transfer interrupt flag (x = 7..4) 4 1 CHTIF4 Clear Clear the corresponding HTIFx flag 1 CHTIF7 Stream x clear half transfer interrupt flag (x = 7..4) 26 1 CTEIF4 Stream x clear transfer error interrupt flag (x = 7..4) 3 1 CTEIF4 Clear Clear the corresponding TEIFx flag 1 CTEIF7 Stream x clear transfer error interrupt flag (x = 7..4) 25 1 CDMEIF4 Stream x clear direct mode error interrupt flag (x = 7..4) 2 1 CDMEIF4 Clear Clear the corresponding DMEIFx flag 1 CDMEIF7 Stream x clear direct mode error interrupt flag (x = 7..4) 24 1 CFEIF4 Stream x clear FIFO error interrupt flag (x = 7..4) 0 1 CFEIF4 Clear Clear the corresponding CFEIFx flag 1 CFEIF7 Stream x clear FIFO error interrupt flag (x = 7..4) 22 1 CTCIF6 Stream x clear transfer complete interrupt flag (x = 7..4) 21 1 CHTIF6 Stream x clear half transfer interrupt flag (x = 7..4) 20 1 CTEIF6 Stream x clear transfer error interrupt flag (x = 7..4) 19 1 CDMEIF6 Stream x clear direct mode error interrupt flag (x = 7..4) 18 1 CFEIF6 Stream x clear FIFO error interrupt flag (x = 7..4) 16 1 CTCIF5 Stream x clear transfer complete interrupt flag (x = 7..4) 11 1 CHTIF5 Stream x clear half transfer interrupt flag (x = 7..4) 10 1 CTEIF5 Stream x clear transfer error interrupt flag (x = 7..4) 9 1 CDMEIF5 Stream x clear direct mode error interrupt flag (x = 7..4) 8 1 CFEIF5 Stream x clear FIFO error interrupt flag (x = 7..4) 6 1 8 0x18 0-7 ST%s Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers 0x10 CR S0CR stream x configuration register 0x0 0x20 read-write 0x00000000 PBURST Peripheral burst transfer configuration 21 2 PBURST Single Single transfer 0 INCR4 Incremental burst of 4 beats 1 INCR8 Incremental burst of 8 beats 2 INCR16 Incremental burst of 16 beats 3 MBURST Memory burst transfer configuration 23 2 CT Current target (only in double buffer mode) 19 1 CT Memory0 The current target memory is Memory 0 0 Memory1 The current target memory is Memory 1 1 DBM Double buffer mode 18 1 DBM Disabled No buffer switching at the end of transfer 0 Enabled Memory target switched at the end of the DMA transfer 1 PL Priority level 16 2 PL Low Low 0 Medium Medium 1 High High 2 VeryHigh Very high 3 PINCOS Peripheral increment offset size 15 1 PINCOS PSIZE The offset size for the peripheral address calculation is linked to the PSIZE 0 Fixed4 The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) 1 PSIZE Peripheral data size 11 2 PSIZE Bits8 Byte (8-bit) 0 Bits16 Half-word (16-bit) 1 Bits32 Word (32-bit) 2 MSIZE Memory data size 13 2 PINC Peripheral increment mode 9 1 PINC Fixed Address pointer is fixed 0 Incremented Address pointer is incremented after each data transfer 1 MINC Memory increment mode 10 1 CIRC Circular mode 8 1 CIRC Disabled Circular mode disabled 0 Enabled Circular mode enabled 1 DIR Data transfer direction 6 2 DIR PeripheralToMemory Peripheral-to-memory 0 MemoryToPeripheral Memory-to-peripheral 1 MemoryToMemory Memory-to-memory 2 PFCTRL Peripheral flow controller 5 1 PFCTRL DMA The DMA is the flow controller 0 Peripheral The peripheral is the flow controller 1 TCIE Transfer complete interrupt enable 4 1 TCIE Disabled TC interrupt disabled 0 Enabled TC interrupt enabled 1 HTIE Half transfer interrupt enable 3 1 HTIE Disabled HT interrupt disabled 0 Enabled HT interrupt enabled 1 TEIE Transfer error interrupt enable 2 1 TEIE Disabled TE interrupt disabled 0 Enabled TE interrupt enabled 1 DMEIE Direct mode error interrupt enable 1 1 DMEIE Disabled DME interrupt disabled 0 Enabled DME interrupt enabled 1 EN Stream enable / flag stream ready when read low 0 1 EN Disabled Stream disabled 0 Enabled Stream enabled 1 TRBUFF Enable the DMA to handle bufferable transfers 20 1 read-write TRBUFF Disabled Bufferable transfers not enabled 0 Enabled Bufferable transfers enabled 1 NDTR S0NDTR stream x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 0 65535 PAR S0PAR stream x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 M0AR S0M0AR stream x memory 0 address register 0xC 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 M1AR S0M1AR stream x memory 1 address register 0x10 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 FCR S0FCR stream x FIFO control register 0x14 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FEIE Disabled FE interrupt disabled 0 Enabled FE interrupt enabled 1 FS FIFO status 3 3 read-only FS Quarter1 0 < fifo_level < 1/4 0 Quarter2 1/4 <= fifo_level < 1/2 1 Quarter3 1/2 <= fifo_level < 3/4 2 Quarter4 3/4 <= fifo_level < full 3 Empty FIFO is empty 4 Full FIFO is full 5 DMDIS Direct mode disable 2 1 read-write DMDIS Enabled Direct mode is enabled 0 Disabled Direct mode is disabled 1 FTH FIFO threshold selection 0 2 read-write FTH Quarter 1/4 full FIFO 0 Half 1/2 full FIFO 1 ThreeQuarters 3/4 full FIFO 2 Full Full FIFO 3 DMA2 0x40020400 DMA2_STR0 DMA2 Stream0 interrupt 56 DMA2_STR1 DMA2 Stream1 interrupt 57 DMA2_STR2 DMA2 Stream2 interrupt 58 DMA2_STR3 DMA2 Stream3 interrupt 59 DMA2_STR4 DMA2 Stream4 interrupt 60 DMA2_STR5 DMA2 Stream5 interrupt 68 DMA2_STR6 DMA2 Stream6 interrupt 69 DMA2_STR7 DMA2 Stream7 interrupt 70 HRTIM_Master High Resolution Timer: Master Timers HRTIM 0x40017400 0x0 0x80 registers HRTIM1_MST HRTIM1 master timer interrupt 103 CR CR Master Timer Control Register 0x0 0x20 read-write 0x00000000 BRSTDMA Burst DMA Update 30 2 BRSTDMA Independent Update done independently from the DMA burst transfer completion 0 Completion Update done when the DMA burst transfer is completed 1 Rollover Update done on master timer roll-over following a DMA burst transfer completion 2 MREPU Master Timer Repetition update 29 1 MREPU Disabled Update on repetition disabled 0 Enabled Update on repetition enabled 1 PREEN Preload enable 27 1 PREEN Disabled Preload disabled: the write access is directly done into the active register 0 Enabled Preload enabled: the write access is done into the preload register 1 DACSYNC AC Synchronization 25 2 DACSYNC Disabled No DAC trigger generated 0 DACSync1 Trigger generated on DACSync1 1 DACSync2 Trigger generated on DACSync2 2 DACSync3 Trigger generated on DACSync3 3 5 0x1 A,B,C,D,E T%sCEN Timer %s counter enable 17 1 TACEN Disabled Timer counter disabled 0 Enabled Timer counter enabled 1 MCEN Master Counter enable 16 1 MCEN Disabled Master timer counter disabled 0 Enabled Master timer counter enabled 1 SYNCSRC Synchronization source 14 2 SYNCSRC MasterStart Master timer Start 0 MasterCompare1 Master timer Compare 1 event 1 TimerAStart Timer A start/reset 2 TimerACompare1 Timer A Compare 1 event 3 SYNCOUT Synchronization output 12 2 SYNCOUT Disabled Disabled 0 PositivePulse Positive pulse on SCOUT output (16x f_HRTIM clock cycles) 2 NegativePulse Negative pulse on SCOUT output (16x f_HRTIM clock cycles) 3 SYNCSTRT Synchronization Starts Master 11 1 SYNCSTRT Disabled No effect on the master timer 0 Start A synchroniation input event starts the master timer 1 SYNCRST Synchronization Resets Master 10 1 SYNCRST Disabled No effect on the master timer 0 Reset A synchroniation input event resets the master timer 1 SYNCIN ynchronization input 8 2 SYNCIN Disabled Disabled. HRTIM is not synchronized and runs in standalone mode 0 Internal Internal event: the HRTIM is synchronized with the on-chip timer 2 External External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM 3 HALF Half mode enable 5 1 HALF Disabled Half mode disabled 0 Enabled Half mode enabled 1 RETRIG Master Re-triggerable mode 4 1 RETRIG Disabled The timer is not re-triggerable: a counter reset can be done only if the counter is stopped 0 Enabled The timer is retriggerable: a counter reset is done whatever the counter state 1 CONT Master Continuous mode 3 1 CONT SingleShot The timer operates in single-shot mode and stops when it reaches the MPER value 0 Continuous The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value 1 CKPSC HRTIM Master Clock prescaler 0 3 0 7 ISR ISR Master Timer Interrupt Status Register 0x4 0x20 read-only 0x00000000 UPD Master Update Interrupt Flag 6 1 UPD NoEvent No timer update interrupt occurred 0 Event Timer update interrupt occurred 1 SYNC Sync Input Interrupt Flag 5 1 SYNC NoEvent No sync input interrupt occurred 0 Event Sync input interrupt occurred 1 REP Master Repetition Interrupt Flag 4 1 REP NoEvent No timer repetition interrupt occurred 0 Event Timer repetition interrupt occurred 1 4 0x1 1-4 CMP%s Master Compare %s Interrupt Flag 0 1 CMP1 NoEvent No compare interrupt occurred 0 Event Compare interrupt occurred 1 ICR ICR Master Timer Interrupt Clear Register 0x8 0x20 write-only 0x00000000 4 0x1 1-4 CMP%sC Master Compare %s Interrupt flag clear 0 1 oneToClear CMP1CW Clear Clears associated flag in ISR register 1 UPDC Master update Interrupt flag clear 6 1 oneToClear SYNCC Sync Input Interrupt flag clear 5 1 oneToClear REPC Repetition Interrupt flag clear 4 1 oneToClear DIER DIER4 MDIER4 0xC 0x20 read-write 0x00000000 4 0x1 1-4 CMP%sDE MCMP%sDE 16 1 CMP1DE Disabled DMA request disabled 0 Enabled DMA request enabled 1 UPDDE MUPDDE 22 1 SYNCDE SYNCDE 21 1 REPDE MREPDE 20 1 4 0x1 1-4 CMP%sIE MCMP%sIE 0 1 CMP1IE Disabled Interrupt disabled 0 Enabled Interrupt enabled 1 UPDIE MUPDIE 6 1 SYNCIE SYNCIE 5 1 REPIE MREPIE 4 1 CNTR CNTR Master Timer Counter Register 0x10 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 PERR PER Master Timer Period Register 0x14 0x20 read-write 0x0000FFFF PER Master Timer Period value 0 16 0 65535 REPR REP Master Timer Repetition Register 0x18 0x20 read-write 0x00000000 REP Master Timer Repetition counter value 0 8 0 255 CMP1R CMP1R Master Timer Compare 1 Register 0x1C 0x20 read-write 0x00000000 CMP Master Timer Compare 1 value 0 16 0 65535 CMP2R CMP2R Master Timer Compare 2 Register 0x24 CMP3R CMP3R Master Timer Compare 3 Register 0x28 CMP4R CMP4R Master Timer Compare 4 Register 0x2C HRTIM_TIMA High Resolution Timer: TIMA HRTIM 0x40017480 0x0 0x80 registers HRTIM1_TIMA HRTIM1 timer A interrupt 104 CR ACR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 UPDGAT Independent Update occurs independently from the DMA burst transfer 0 DMABurst Update occurs when the DMA burst transfer is completed 1 DMABurst_Update Update occurs on the update event following DMA burst transfer completion 2 Input1 Update occurs on a rising edge of HRTIM update enable input 1 3 Input2 Update occurs on a rising edge of HRTIM update enable input 2 4 Input3 Update occurs on a rising edge of HRTIM update enable input 3 5 Input1_Update Update occurs on the update event following a rising edge of HRTIM update enable input 1 6 Input2_Update Update occurs on the update event following a rising edge of HRTIM update enable input 2 7 Input3_Update Update occurs on the update event following a rising edge of HRTIM update enable input 3 8 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 MSTU Disabled Update by master timer disabled 0 Enabled Update by master timer enabled 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TRSTU Disabled Update by timer x reset/roll-over disabled 0 Enabled Update by timer x reset/roll-over enabled 1 TREPU Timer x Repetition update 17 1 TREPU Disabled Update by timer x repetition disabled 0 Enabled Update by timer x repetition enabled 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP4 Standard CMP4 register is always active (standard compare mode) 0 Capture2 CMP4 is recomputed and is active following a capture 2 event 1 Capture2_Compare1 CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match 2 Capture_Compare3 CMP4 is recomputed and is active following a capture event or a Compare 3 match 3 DELCMP2 Delayed CMP2 mode 12 2 DELCMP2 Standard CMP2 register is always active (standard compare mode) 0 Capture1 CMP2 is recomputed and is active following a capture 1 event 1 Capture1_Compare1 CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match 2 Capture1_Compare3 CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match 3 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 PSHPLL Disabled Push-pull mode disabled 0 Enabled Push-pull mode enabled 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR AISR Timerx Interrupt Status Register 0x4 0x20 read-only 0x00000000 O1STAT Output 1 State 18 1 O1STAT Inactive Output was inactive 0 Active Output was active 1 O2STAT Output 2 State 19 1 IPPSTAT Idle Push Pull Status 17 1 IPPSTAT Output1Active Protection occurred when the output 1 was active and output 2 forced inactive 0 Output2Active Protection occurred when the output 2 was active and output 1 forced inactive 1 CPPSTAT Current Push Pull Status 16 1 CPPSTAT Output1Active Signal applied on output 1 and output 2 forced inactive 0 Output2Active Signal applied on output 2 and output 1 forced inactive 1 DLYPRT Delayed Protection Flag 14 1 DLYPRT Inactive Not in delayed idle or balanced idle mode 0 Active Delayed idle or balanced idle mode entry 1 RST Reset Interrupt Flag 13 1 RST NoEvent No TIMx counter reset/roll-over interrupt occurred 0 Event TIMx counter reset/roll-over interrupt occurred 1 RST1 Output 1 Reset Interrupt Flag 10 1 RST1 NoEvent No Tx output reset interrupt occurred 0 Event Tx output reset interrupt occurred 1 RST2 Output 2 Reset Interrupt Flag 12 1 2 0x2 1-2 SET%s Output %s Set Interrupt Flag 9 1 SET1 NoEvent No Tx output set interrupt occurred 0 Event Tx output set interrupt occurred 1 2 0x1 1-2 CPT%s Capture%s Interrupt Flag 7 1 CPT1 NoEvent No timer x capture reset interrupt occurred 0 Event Timer x capture reset interrupt occurred 1 UPD Update Interrupt Flag 6 1 REP Repetition Interrupt Flag 4 1 4 0x1 1-4 CMP%s Compare %s Interrupt Flag 0 1 ICR AICR Timerx Interrupt Clear Register 0x8 0x20 write-only 0x00000000 4 0x1 1-4 CMP%sC Compare %s Interrupt flag Clear 0 1 DLYPRTC Delayed Protection Flag Clear 14 1 RSTC Reset Interrupt flag Clear 13 1 RST2C Output 2 Reset flag Clear 12 1 2 0x2 1-2 SET%sC Output %s Set flag Clear 9 1 RST1C Output 1 Reset flag Clear 10 1 2 0x1 1-2 CPT%sC Capture%s Interrupt flag Clear 7 1 UPDC Update Interrupt flag Clear 6 1 REPC Repetition Interrupt flag Clear 4 1 DIER ADIER5 TIMxDIER5 0xC 0x20 read-write 0x00000000 4 0x1 1-4 CMP%sDE CMP%sDE 16 1 DLYPRTDE DLYPRTDE 30 1 RSTDE RSTDE 29 1 RST2DE RSTx2DE 28 1 2 0x2 1-2 SET%sDE Output %s set DMA request enable 25 1 RST1DE RSTx1DE 26 1 2 0x1 1-2 CPT%sDE CPT%sDE 23 1 UPDDE UPDDE 22 1 REPDE REPDE 20 1 4 0x1 1-4 CMP%sIE CMP%sIE 0 1 DLYPRTIE DLYPRTIE 14 1 RSTIE RSTIE 13 1 RST2IE RSTx2IE 12 1 2 0x2 1-2 SET%sIE Output %s set interrupt enable 9 1 RST1IE RSTx1IE 10 1 2 0x1 1-2 CPT%sIE CPT%sIE 7 1 UPDIE UPDIE 6 1 REPIE REPIE 4 1 CNTR CNTAR Timerx Counter Register 0x10 PERR PERAR Timerx Period Register 0x14 REPR REPAR Timerx Repetition Register 0x18 CMP1R CMP1AR Timerx Compare 1 Register 0x1C CMP1CR CMP1CAR Timerx Compare 1 Compound Register 0x20 0x20 read-write 0x00000000 REP Timerx Repetition value (aliased from HRTIM_REPx register) 16 8 0 255 CMP1 Timerx Compare 1 value 0 16 0 65535 CMP2R CMP2AR Timerx Compare 2 Register 0x24 CMP3R CMP3AR Timerx Compare 3 Register 0x28 CMP4R CMP4AR Timerx Compare 4 Register 0x2C CPT1R CPT1AR Timerx Capture 1 Register 0x30 0x20 read-only 0x00000000 CPT Timerx Capture 1 value 0 16 0 65535 CPT2R CPT2AR Timerx Capture 2 Register 0x34 DTR DTAR Timerx Deadtime Register 0x38 0x20 read-write 0x00000000 DTFLK Deadtime Falling Lock 31 1 DTFLK Unlocked Deadtime falling value and sign is writable 0 Locked Deadtime falling value and sign is read-only 1 DTFSLK Deadtime Falling Sign Lock 30 1 DTFSLK Unlocked Deadtime falling sign is writable 0 Locked Deadtime falling sign is read-only 1 SDTF Sign Deadtime Falling value 25 1 SDTF Positive Positive deadtime on falling edge 0 Negative Negative deadtime on falling edge 1 DTF Deadtime Falling value 16 9 0 511 DTRLK Deadtime Rising Lock 15 1 DTRLK Unlocked Deadtime rising value and sign is writable 0 Locked Deadtime rising value and sign is read-only 1 DTRSLK Deadtime Rising Sign Lock 14 1 DTRSLK Unlocked Deadtime rising sign is writable 0 Locked Deadtime rising sign is read-only 1 DTPRSC Deadtime Prescaler 10 3 0 7 SDTR Sign Deadtime Rising value 9 1 SDTR Positive Positive deadtime on rising edge 0 Negative Negative deadtime on rising edge 1 DTR Deadtime Rising value 0 9 0 511 SET1R SETA1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 UPDATE NoEffect Register update event has no effect 0 SetActive Register update event forces the output to its active state 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 EXTEVNT1 NoEffect External event has no effect 0 SetActive External event forces the output to its active state 1 TIMBCMP1 Timer B Compare 1 12 1 TIMBCMP1 NoEffect Timer event has no effect 0 SetActive Timer event forces the output to its active state 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMDCMP2 Timer D Compare 2 18 1 TIMDCMP1 Timer D Compare 1 17 1 TIMCCMP3 Timer C Compare 3 16 1 TIMCCMP2 Timer C Compare 2 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP2 Timer B Compare 2 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTCMP1 NoEffect Master timer compare event has no effect 0 SetActive Master timer compare event forces the output to its active state 1 MSTPER Master Period 7 1 MSTPER NoEffect Master timer counter roll-over/reset has no effect 0 SetActive Master timer counter roll-over/reset forces the output to its active state 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 CMP1 NoEffect Timer compare event has no effect 0 SetActive Timer compare event forces the output to its active state 1 PER Timer A Period 2 1 PER NoEffect Timer period event has no effect 0 SetActive Timer period event forces the output to its active state 1 RESYNC Timer A resynchronizaton 1 1 RESYNC NoEffect Timer reset event coming solely from software or SYNC input event has no effect 0 SetActive Timer reset event coming solely from software or SYNC input event forces the output to its active state 1 SST Software Set trigger 0 1 SST NoEffect No effect 0 SetActive Force output to its active state 1 RST1R RSTA1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 UPDATE NoEffect Register update event has no effect 0 SetInactive Register update event forces the output to its inactive state 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 EXTEVNT1 NoEffect External event has no effect 0 SetInactive External event forces the output to its inactive state 1 TIMBCMP1 Timer B Compare 1 12 1 TIMBCMP1 NoEffect Timer event has no effect 0 SetInactive Timer event forces the output to its inactive state 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMDCMP2 Timer D Compare 2 18 1 TIMDCMP1 Timer D Compare 1 17 1 TIMCCMP3 Timer C Compare 3 16 1 TIMCCMP2 Timer C Compare 2 15 1 TIMBCMP4 Timer B Compare 4 14 1 TIMBCMP2 Timer B Compare 2 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTCMP1 NoEffect Master timer compare event has no effect 0 SetInactive Master timer compare event forces the output to its inactive state 1 MSTPER MSTPER 7 1 MSTPER NoEffect Master timer counter roll-over/reset has no effect 0 SetInactive Master timer counter roll-over/reset forces the output to its inactive state 1 4 0x1 1-4 CMP%s CMP%s 3 1 CMP1 NoEffect Timer compare event has no effect 0 SetInactive Timer compare event forces the output to its inactive state 1 PER PER 2 1 PER NoEffect Timer period event has no effect 0 SetInactive Timer period event forces the output to its inactive state 1 RESYNC RESYNC 1 1 RESYNC NoEffect Timer reset event coming solely from software or SYNC input event has no effect 0 SetInactive Timer reset event coming solely from software or SYNC input event forces the output to its inactive state 1 SRT SRT 0 1 SRT NoEffect No effect 0 SetInactive Force output to its inactive state 1 SET2R SETA2R Timerx Output2 Set Register 0x44 RST2R RSTA2R Timerx Output2 Reset Register 0x48 EEFR1 EEFAR1 Timerx External Event Filtering Register 1 0x4C 0x20 read-write 0x00000000 5 0x6 1-5 EE%sFLTR External Event %s filter 1 4 EE1FLTR Disabled No filtering 0 BlankResetToCompare1 Blanking from counter reset/roll-over to Compare 1 1 BlankResetToCompare2 Blanking from counter reset/roll-over to Compare 2 2 BlankResetToCompare3 Blanking from counter reset/roll-over to Compare 3 3 BlankResetToCompare4 Blanking from counter reset/roll-over to Compare 4 4 BlankTIMFLTR1 Blanking from another timing unit: TIMFLTR1 source 5 BlankTIMFLTR2 Blanking from another timing unit: TIMFLTR2 source 6 BlankTIMFLTR3 Blanking from another timing unit: TIMFLTR3 source 7 BlankTIMFLTR4 Blanking from another timing unit: TIMFLTR4 source 8 BlankTIMFLTR5 Blanking from another timing unit: TIMFLTR5 source 9 BlankTIMFLTR6 Blanking from another timing unit: TIMFLTR6 source 10 BlankTIMFLTR7 Blanking from another timing unit: TIMFLTR7 source 11 BlankTIMFLTR8 Blanking from another timing unit: TIMFLTR8 source 12 WindowResetToCompare2 Windowing from counter reset/roll-over to compare 2 13 WindowResetToCompare3 Windowing from counter reset/roll-over to compare 3 14 WindowTIMWIN Windowing from another timing unit: TIMWIN source 15 5 0x6 1-5 EE%sLTCH External Event %s latch 0 1 EE1LTCH Disabled Event is ignored if it happens during a blank, or passed through during a window 0 Enabled Event is latched and delayed till the end of the blanking or windowing period 1 EEFR2 EEFAR2 Timerx External Event Filtering Register 2 0x50 0x20 read-write 0x00000000 5 0x6 6-10 EE%sFLTR External Event %s filter 1 4 EE6FLTR Disabled No filtering 0 BlankResetToCompare1 Blanking from counter reset/roll-over to Compare 1 1 BlankResetToCompare2 Blanking from counter reset/roll-over to Compare 2 2 BlankResetToCompare3 Blanking from counter reset/roll-over to Compare 3 3 BlankResetToCompare4 Blanking from counter reset/roll-over to Compare 4 4 BlankTIMFLTR1 Blanking from another timing unit: TIMFLTR1 source 5 BlankTIMFLTR2 Blanking from another timing unit: TIMFLTR2 source 6 BlankTIMFLTR3 Blanking from another timing unit: TIMFLTR3 source 7 BlankTIMFLTR4 Blanking from another timing unit: TIMFLTR4 source 8 BlankTIMFLTR5 Blanking from another timing unit: TIMFLTR5 source 9 BlankTIMFLTR6 Blanking from another timing unit: TIMFLTR6 source 10 BlankTIMFLTR7 Blanking from another timing unit: TIMFLTR7 source 11 BlankTIMFLTR8 Blanking from another timing unit: TIMFLTR8 source 12 WindowResetToCompare2 Windowing from counter reset/roll-over to compare 2 13 WindowResetToCompare3 Windowing from counter reset/roll-over to compare 3 14 WindowTIMWIN Windowing from another timing unit: TIMWIN source 15 5 0x6 6-10 EE%sLTCH External Event %s latch 0 1 EE6LTCH Disabled Event is ignored if it happens during a blank, or passed through during a window 0 Enabled Event is latched and delayed till the end of the blanking or windowing period 1 RSTR RSTAR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMBCMP1 Timer B Compare 1 19 1 TIMBCMP1 NoEffect Timer Y compare Z event has no effect 0 ResetCounter Timer X counter is reset upon timer Y compare Z event 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMCCMP4 Timer C Compare 4 24 1 TIMCCMP2 Timer C Compare 2 23 1 TIMCCMP1 Timer C Compare 1 22 1 TIMBCMP4 Timer B Compare 4 21 1 TIMBCMP2 Timer B Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 EXTEVNT1 NoEffect External event Z has no effect 0 ResetCounter Timer X counter is reset upon external event Z 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTCMP1 NoEffect Master timer compare Z event has no effect 0 ResetCounter Timer X counter is reset upon master timer compare Z event 1 MSTPER Master timer Period 4 1 MSTPER NoEffect Master timer period event has no effect 0 ResetCounter Timer X counter is reset upon master timer period event 1 CMP2 Timer A compare 2 reset 2 1 CMP2 NoEffect Timer X compare Z event has no effect 0 ResetCounter Timer X counter is reset upon timer X compare Z event 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 UPDT NoEffect Update event has no effect 0 ResetCounter Timer X counter is reset upon update event 1 CHPR CHPAR Timerx Chopper Register 0x58 0x20 read-write 0x00000000 STRTPW STRTPW 7 4 0 15 CARDTY Timerx chopper duty cycle value 4 3 0 7 CARFRQ Timerx carrier frequency value 0 4 0 15 CPT1CR CPT1ACR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TBCMP1 Timer B Compare 1 18 1 TBCMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TB1RST Timer B output 1 Reset 17 1 TB1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TB1SET Timer B output 1 Set 16 1 TB1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2ACR CPT2xCR 0x60 OUTR OUTAR Timerx Output Register 0x64 0x20 read-write 0x00000000 DIDL1 Output 1 Deadtime upon burst mode Idle entry 7 1 DIDL1 Disabled The programmed idle state is applied immediately to the output 0 Enabled Deadtime (inactive level) is inserted on output before entering the idle mode 1 DIDL2 Output 2 Deadtime upon burst mode Idle entry 23 1 CHP1 Output 1 Chopper enable 6 1 CHP1 Disabled Output signal not altered 0 Enabled Output signal is chopped by a carrier signal 1 CHP2 Output 2 Chopper enable 22 1 FAULT1 Output 1 Fault state 4 2 FAULT1 Disabled No action: the output is not affected by the fault input and stays in run mode 0 SetActive Output goes to active state after a fault event 1 SetInactive Output goes to inactive state after a fault event 2 SetHighZ Output goes to high-z state after a fault event 3 FAULT2 Output 2 Fault state 20 2 IDLES1 Output 1 Idle State 3 1 IDLES1 Inactive Output idle state is inactive 0 Active Output idle state is active 1 IDLES2 Output 2 Idle State 19 1 IDLEM1 Output 1 Idle mode 2 1 IDLEM1 NoEffect No action: the output is not affected by the burst mode operation 0 SetIdle The output is in idle state when requested by the burst mode controller 1 IDLEM2 Output 2 Idle mode 18 1 POL1 Output 1 polarity 1 1 POL1 ActiveHigh Positive polarity (output active high) 0 ActiveLow Negative polarity (output active low) 1 POL2 Output 2 polarity 17 1 DLYPRT Delayed Protection 10 3 DLYPRT Output1_EE6 Output 1 delayed idle on external event 6 0 Output2_EE6 Output 2 delayed idle on external event 6 1 Output1_2_EE6 Output 1 and 2 delayed idle on external event 6 2 Balanced_EE6 Balanced idle on external event 6 3 Output1_EE7 Output 1 delayed idle on external event 7 4 Output2_EE7 Output 2 delayed idle on external event 7 5 Output1_2_EE7 Output 1 and 2 delayed idle on external event 7 6 Balanced_EE7 Balanced idle on external event 7 7 DLYPRTEN Delayed Protection Enable 9 1 DLYPRTEN Disabled No action 0 Enabled Delayed protection is enabled, as per DLYPRT bits 1 DTEN Deadtime enable 8 1 DTEN Disabled Output 1 and 2 signals are independent 0 Enabled Deadtime is inserted between output 1 and output 2 1 FLTR FLTAR Timerx Fault Register 0x68 0x20 read-write 0x00000000 FLTLCK Fault sources Lock 31 1 FLTLCK Unlocked FLT1EN..FLT5EN bits are read/write 0 Locked FLT1EN..FLT5EN bits are read only 1 5 0x1 1-5 FLT%sEN Fault %s enable 0 1 FLT1EN Ignored Fault input ignored 0 Active Fault input is active and can disable HRTIM outputs 1 HRTIM_TIMB High Resolution Timer: TIMB HRTIM 0x40017500 0x0 0x80 registers HRTIM_TIMB HRTIM1 timer B interrupt 105 CR BCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR BISR Timerx Interrupt Status Register 0x4 ICR BICR Timerx Interrupt Clear Register 0x8 DIER BDIER5 TIMxDIER5 0xC CNTR CNTR Timerx Counter Register 0x10 PERR PERBR Timerx Period Register 0x14 REPR REPBR Timerx Repetition Register 0x18 CMP1R CMP1BR Timerx Compare 1 Register 0x1C CMP1CR CMP1CBR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2BR Timerx Compare 2 Register 0x24 CMP3R CMP3BR Timerx Compare 3 Register 0x28 CMP4R CMP4BR Timerx Compare 4 Register 0x2C CPT1R CPT1BR Timerx Capture 1 Register 0x30 CPT2R CPT2BR Timerx Capture 2 Register 0x34 DTR DTBR Timerx Deadtime Register 0x38 SET1R SETB1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMDCMP4 Timer D Compare 4 18 1 TIMDCMP3 Timer D Compare 3 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMCCMP3 Timer C Compare 3 15 1 TIMACMP4 Timer A Compare 4 14 1 TIMACMP2 Timer A Compare 2 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTB1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMDCMP4 Timer D Compare 4 18 1 TIMDCMP3 Timer D Compare 3 17 1 TIMCCMP4 Timer C Compare 4 16 1 TIMCCMP3 Timer C Compare 3 15 1 TIMACMP4 Timer A Compare 4 14 1 TIMACMP2 Timer A Compare 2 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETB2R Timerx Output2 Set Register 0x44 RST2R RSTB2R Timerx Output2 Reset Register 0x48 EEFR1 EEFBR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFBR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTBR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMCCMP4 Timer C Compare 4 24 1 TIMCCMP2 Timer C Compare 2 23 1 TIMCCMP1 Timer C Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPBR Timerx Chopper Register 0x58 CPT1CR CPT1BCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2BCR CPT2xCR 0x60 OUTR OUTBR Timerx Output Register 0x64 FLTR FLTBR Timerx Fault Register 0x68 HRTIM_TIMC High Resolution Timer: TIMC HRTIM 0x40017580 0x0 0x80 registers HRTIM1_TIMC HRTIM1 timer C interrupt 106 CR CCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR CISR Timerx Interrupt Status Register 0x4 ICR CICR Timerx Interrupt Clear Register 0x8 DIER CDIER5 TIMxDIER5 0xC CNTR CNTCR Timerx Counter Register 0x10 PERR PERCR Timerx Period Register 0x14 REPR REPCR Timerx Repetition Register 0x18 CMP1R CMP1CR Timerx Compare 1 Register 0x1C CMP1CR CMP1CCR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2CR Timerx Compare 2 Register 0x24 CMP3R CMP3CR Timerx Compare 3 Register 0x28 CMP4R CMP4CR Timerx Compare 4 Register 0x2C CPT1R CPT1CR Timerx Capture 1 Register 0x30 CPT2R CPT2CR Timerx Capture 2 Register 0x34 DTR DTCR Timerx Deadtime Register 0x38 SET1R SETC1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP2 Timer A Compare 2 12 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMECMP2 Timer E Compare 2 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP2 Timer D Compare 2 16 1 TIMBCMP3 Timer B Compare 3 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP3 Timer A Compare 3 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTC1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP2 Timer A Compare 2 12 1 TIMECMP4 Timer E Compare 4 20 1 TIMECMP3 Timer E Compare 3 19 1 TIMECMP2 Timer E Compare 2 18 1 TIMDCMP4 Timer D Compare 4 17 1 TIMDCMP2 Timer D Compare 2 16 1 TIMBCMP3 Timer B Compare 3 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP3 Timer A Compare 3 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETC2R Timerx Output2 Set Register 0x44 RST2R RSTC2R Timerx Output2 Reset Register 0x48 EEFR1 EEFCR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFCR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTCR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMDCMP4 Timer D Compare 4 27 1 TIMDCMP2 Timer D Compare 2 26 1 TIMDCMP1 Timer D Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPCR Timerx Chopper Register 0x58 CPT1CR CPT1CCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TD1RST Timer D output 1 Reset 25 1 TD1SET Timer D output 1 Set 24 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2CCR CPT2xCR 0x60 OUTR OUTCR Timerx Output Register 0x64 FLTR FLTCR Timerx Fault Register 0x68 HRTIM_TIMD High Resolution Timer: TIMD HRTIM 0x40017600 0x0 0x80 registers HRTIM1_TIMD HRTIM1 timer D interrupt 107 CR DCR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR DISR Timerx Interrupt Status Register 0x4 ICR DICR Timerx Interrupt Clear Register 0x8 DIER DDIER5 TIMxDIER5 0xC CNTR CNTDR Timerx Counter Register 0x10 PERR PERDR Timerx Period Register 0x14 REPR REPDR Timerx Repetition Register 0x18 CMP1R CMP1DR Timerx Compare 1 Register 0x1C CMP1CR CMP1CDR Timerx Compare 1 Compound Register 0x20 CMP2R CMP2DR Timerx Compare 2 Register 0x24 CMP3R CMP3DR Timerx Compare 3 Register 0x28 CMP4R CMP4DR Timerx Compare 4 Register 0x2C CPT1R CPT1DR Timerx Capture 1 Register 0x30 CPT2R CPT2DR Timerx Capture 2 Register 0x34 DTR DTDR Timerx Deadtime Register 0x38 SET1R SETD1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMCCMP4 Timer C Compare 4 18 1 TIMCCMP3 Timer C Compare 3 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTD1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP1 Timer A Compare 1 12 1 TIMECMP2 Timer E Compare 2 20 1 TIMECMP1 Timer E Compare 1 19 1 TIMCCMP4 Timer C Compare 4 18 1 TIMCCMP3 Timer C Compare 3 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP2 Timer B Compare 2 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETD2R Timerx Output2 Set Register 0x44 RST2R RSTD2R Timerx Output2 Reset Register 0x48 EEFR1 EEFDR1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFDR2 Timerx External Event Filtering Register 2 0x50 RSTR RSTDR TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMECMP4 Timer E Compare 4 30 1 TIMECMP2 Timer E Compare 2 29 1 TIMECMP1 Timer E Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPDR Timerx Chopper Register 0x58 CPT1CR CPT1DCR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TECMP2 Timer E Compare 2 31 1 TECMP1 Timer E Compare 1 30 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TE1RST Timer E output 1 Reset 29 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TE1SET Timer E output 1 Set 28 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2DCR CPT2xCR 0x60 OUTR OUTDR Timerx Output Register 0x64 FLTR FLTDR Timerx Fault Register 0x68 HRTIM_TIME High Resolution Timer: TIME HRTIM 0x40017680 0x0 0x80 registers HRTIM_TIME HRTIM1 timer E interrupt 108 CR ECR Timerx Control Register 0x0 0x20 read-write 0x00000000 UPDGAT Update Gating 28 4 PREEN Preload enable 27 1 DACSYNC AC Synchronization 25 2 MSTU Master Timer update 24 1 TBU TBU 20 1 TBU Disabled Update by timer x disabled 0 Enabled Update by timer x enabled 1 TEU TEU 23 1 TDU TDU 22 1 TCU TCU 21 1 TRSTU Timerx reset update 18 1 TREPU Timer x Repetition update 17 1 DELCMP4 Delayed CMP4 mode 14 2 DELCMP2 Delayed CMP2 mode 12 2 SYNCSTRT Synchronization Starts Timer x 11 1 SYNCRST Synchronization Resets Timer x 10 1 PSHPLL Push-Pull mode enable 6 1 HALF Half mode enable 5 1 RETRIG Re-triggerable mode 4 1 CONT Continuous mode 3 1 CKPSC HRTIM Timer x Clock prescaler 0 3 ISR EISR Timerx Interrupt Status Register 0x4 ICR EICR Timerx Interrupt Clear Register 0x8 DIER EDIER5 TIMxDIER5 0xC CNTR CNTER Timerx Counter Register 0x10 PERR PERER Timerx Period Register 0x14 REPR REPER Timerx Repetition Register 0x18 CMP1R CMP1ER Timerx Compare 1 Register 0x1C CMP1CR CMP1CER Timerx Compare 1 Compound Register 0x20 CMP2R CMP2ER Timerx Compare 2 Register 0x24 CMP3R CMP3ER Timerx Compare 3 Register 0x28 CMP4R CMP4ER Timerx Compare 4 Register 0x2C CPT1R CPT1ER Timerx Capture 1 Register 0x30 CPT2R CPT2ER Timerx Capture 2 Register 0x34 DTR DTER Timerx Deadtime Register 0x38 SET1R SETE1R Timerx Output1 Set Register 0x3C 0x20 read-write 0x00000000 UPDATE Registers update (transfer preload to active) 31 1 10 0x1 1-10 EXTEVNT%s External Event %s 21 1 TIMACMP3 Timer A Compare 3 12 1 TIMDCMP4 Timer D Compare 4 20 1 TIMDCMP2 Timer D Compare 2 19 1 TIMDCMP1 Timer D Compare 1 18 1 TIMCCMP2 Timer C Compare 2 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP3 Timer B Compare 3 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s Master Compare %s 8 1 MSTPER Master Period 7 1 4 0x1 1-4 CMP%s Timer A compare %s 3 1 PER Timer A Period 2 1 RESYNC Timer A resynchronizaton 1 1 SST Software Set trigger 0 1 RST1R RSTE1R Timerx Output1 Reset Register 0x40 0x20 read-write 0x00000000 UPDATE UPDATE 31 1 10 0x1 1-10 EXTEVNT%s EXTEVNT%s 21 1 TIMACMP3 Timer A Compare 3 12 1 TIMDCMP4 Timer D Compare 4 20 1 TIMDCMP2 Timer D Compare 2 19 1 TIMDCMP1 Timer D Compare 1 18 1 TIMCCMP2 Timer C Compare 2 17 1 TIMCCMP1 Timer C Compare 1 16 1 TIMBCMP4 Timer B Compare 4 15 1 TIMBCMP3 Timer B Compare 3 14 1 TIMACMP4 Timer A Compare 4 13 1 4 0x1 1-4 MSTCMP%s MSTCMP%s 8 1 MSTPER MSTPER 7 1 4 0x1 1-4 CMP%s CMP%s 3 1 PER PER 2 1 RESYNC RESYNC 1 1 SRT SRT 0 1 SET2R SETE2R Timerx Output2 Set Register 0x44 RST2R RSTE2R Timerx Output2 Reset Register 0x48 EEFR1 EEFER1 Timerx External Event Filtering Register 1 0x4C EEFR2 EEFER2 Timerx External Event Filtering Register 2 0x50 RSTR RSTER TimerA Reset Register 0x54 0x20 read-write 0x00000000 TIMACMP1 Timer A Compare 1 19 1 TIMDCMP4 Timer D Compare 4 30 1 TIMDCMP2 Timer D Compare 2 29 1 TIMDCMP1 Timer D Compare 1 28 1 TIMCCMP4 Timer C Compare 4 27 1 TIMCCMP2 Timer C Compare 2 26 1 TIMCCMP1 Timer C Compare 1 25 1 TIMBCMP4 Timer B Compare 4 24 1 TIMBCMP2 Timer B Compare 2 23 1 TIMBCMP1 Timer B Compare 1 22 1 TIMACMP4 Timer A Compare 4 21 1 TIMACMP2 Timer A Compare 2 20 1 10 0x1 1-10 EXTEVNT%s External Event %s 9 1 4 0x1 1-4 MSTCMP%s Master compare %s 5 1 MSTPER Master timer Period 4 1 CMP2 Timer A compare 2 reset 2 1 CMP4 Timer A compare 4 reset 3 1 UPDT Timer A Update reset 1 1 CHPR CHPER Timerx Chopper Register 0x58 CPT1CR CPT1ECR Timerx Capture 2 Control Register 0x5C 0x20 read-write 0x00000000 TACMP1 Timer A Compare 1 14 1 TACMP1 NoEffect Timer X compare Y has no effect 0 TriggerCapture Timer X compare Y triggers capture Z 1 TDCMP2 Timer D Compare 2 27 1 TDCMP1 Timer D Compare 1 26 1 TA1RST Timer A output 1 Reset 13 1 TA1RST NoEffect Timer X output Y active to inactive transition has no effect 0 TriggerCapture Timer X output Y active to inactive transition triggers capture Z 1 TD1RST Timer D output 1 Reset 25 1 TA1SET Timer A output 1 Set 12 1 TA1SET NoEffect Timer X output Y inactive to active transition has no effect 0 TriggerCapture Timer X output Y inactive to active transition triggers capture Z 1 TD1SET Timer D output 1 Set 24 1 TCCMP2 Timer C Compare 2 23 1 TCCMP1 Timer C Compare 1 22 1 TC1RST Timer C output 1 Reset 21 1 TC1SET Timer C output 1 Set 20 1 TBCMP2 Timer B Compare 2 19 1 TBCMP1 Timer B Compare 1 18 1 TB1RST Timer B output 1 Reset 17 1 TB1SET Timer B output 1 Set 16 1 TACMP2 Timer A Compare 2 15 1 10 0x1 1-10 EXEV%sCPT External Event %s Capture 2 1 EXEV1CPT NoEffect External event Y has no effect 0 TriggerCapture External event Y triggers capture Z 1 UPDCPT Update Capture 1 1 UPDCPT NoEffect Update event has no effect 0 TriggerCapture Update event triggers capture Z 1 SWCPT Software Capture 0 1 SWCPT NoEffect No effect 0 TriggerCapture Force capture Z 1 CPT2CR CPT2ECR CPT2xCR 0x60 OUTR OUTER Timerx Output Register 0x64 FLTR FLTER Timerx Fault Register 0x68 HRTIM_Common High Resolution Timer: Common functions HRTIM 0x40017780 0x0 0x80 registers HRTIM1_FLT HRTIM1 fault interrupt 109 CR1 CR1 Control Register 1 0x0 0x20 read-write 0x00000000 4 0x3 1-4 AD%sUSRC ADC Trigger %s Update Source 16 3 AD1USRC Master ADC trigger update from master timer 0 TimerA ADC trigger update from timer A 1 TimerB ADC trigger update from timer B 2 TimerC ADC trigger update from timer C 3 TimerD ADC trigger update from timer D 4 TimerE ADC trigger update from timer E 5 MUDIS Master Update Disable 0 1 MUDIS Enabled Timer update enabled 0 Disabled Timer update disabled 1 5 0x1 A,B,C,D,E T%sUDIS Timer %s Update Disable 1 1 CR2 CR2 Control Register 2 0x4 0x20 read-write 0x00000000 MRST Master Counter software reset 8 1 MRST Reset Reset timer 1 5 0x1 A,B,C,D,E T%sRST Timer %s counter software reset 9 1 MSWU Master Timer Software update 0 1 MSWU Update Force immediate update 1 5 0x1 A,B,C,D,E T%sSWU Timer %s Software Update 1 1 ISR ISR Interrupt Status Register 0x8 0x20 0x00000000 BMPER Burst mode Period Interrupt Flag 17 1 read-only BMPERR NoEvent No burst mode period interrupt occurred 0 Event Burst mode period interrupt occured 1 SYSFLT System Fault Interrupt Flag 5 1 read-write SYSFLTR read NoEvent No fault interrupt occurred 0 Event Fault interrupt occurred 1 FLT1 Fault 1 Interrupt Flag 0 1 read-only FLT1R NoEvent No fault interrupt occurred 0 Event Fault interrupt occurred 1 FLT5 Fault 5 Interrupt Flag 4 1 read-only FLT4 Fault 4 Interrupt Flag 3 1 read-only FLT3 Fault 3 Interrupt Flag 2 1 read-only FLT2 Fault 2 Interrupt Flag 1 1 read-only ICR ICR Interrupt Clear Register 0xC 0x20 0x00000000 FLT1C Fault 1 Interrupt Flag Clear 0 1 write-only oneToClear FLT1CW Clear Clears associated flag in ISR register 1 BMPERC Burst mode period flag Clear 17 1 write-only oneToClear SYSFLTC System Fault Interrupt Flag Clear 5 1 write-only oneToClear FLT5C Fault 5 Interrupt Flag Clear 4 1 write-only oneToClear FLT4C Fault 4 Interrupt Flag Clear 3 1 write-only oneToClear FLT3C Fault 3 Interrupt Flag Clear 2 1 write-only oneToClear FLT2C Fault 2 Interrupt Flag Clear 1 1 write-only oneToClear IER IER Interrupt Enable Register 0x10 0x20 read-write 0x00000000 BMPERIE Burst mode period Interrupt Enable 17 1 BMPERIE Disabled Burst mode period interrupt disabled 0 Enabled Burst mode period interrupt enabled 1 FLT1IE Fault 1 Interrupt Enable 0 1 FLT1IE Disabled Fault interrupt disabled 0 Enabled Fault interrupt enabled 1 SYSFLTIE System Fault Interrupt Enable 5 1 FLT5IE Fault 5 Interrupt Enable 4 1 FLT4IE Fault 4 Interrupt Enable 3 1 FLT3IE Fault 3 Interrupt Enable 2 1 FLT2IE Fault 2 Interrupt Enable 1 1 OENR OENR Output Enable Register 0x14 0x20 read-write 0x00000000 5 0x2 A,B,C,D,E T%s1OEN Timer %s Output 1 Enable 0 1 oneToSet TOENR read Disabled Output disabled 0 Enabled Output enabled 1 TORNW write Enable Enable output 1 5 0x2 A,B,C,D,E T%s2OEN Timer %s Output 2 Enable 1 1 oneToSet read write ODISR DISR DISR 0x18 0x20 write-only 0x00000000 5 0x2 A,B,C,D,E T%s1ODIS T%s1ODIS 0 1 oneToSet TODIS Disable Disable output 1 5 0x2 A,B,C,D,E T%s2ODIS T%s2ODIS 1 1 oneToSet ODSR ODSR Output Disable Status Register 0x1C 0x20 read-only 0x00000000 5 0x2 A,B,C,D,E T%s1ODS Timer %s Output 1 disable status 0 1 TODS Idle Output disabled in idle state 0 Fault Output disabled in fault state 1 5 0x2 A,B,C,D,E T%s2ODS Timer %s Output 2 disable status 1 1 BMCR BMCR Burst Mode Control Register 0x20 0x20 read-write 0x00000000 BMSTAT Burst Mode Status 31 1 zeroToClear BMSTATR read Normal Normal operation 0 Burst Burst operation ongoing 1 BMSTATW write Cancel Terminate burst mode 0 MTBM Master Timer Burst Mode 16 1 MTBM Normal Counter clock is maintained and timer operates normally 0 Stopped Counter clock is stopped and counter is reset 1 5 0x1 A,B,C,D,E T%sBM Timer %s Burst Mode 17 1 BMPREN Burst Mode Preload Enable 10 1 BMPREN Disabled Preload disabled: the write access is directly done into active registers 0 Enabled Preload enabled: the write access is done into preload registers 1 BMPRSC Burst Mode Prescaler 6 4 BMPRSC Div1 Clock not divided 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 Div16 Division by 16 4 Div32 Division by 32 5 Div64 Division by 64 6 Div128 Division by 128 7 Div256 Division by 256 8 Div512 Division by 512 9 Div1024 Division by 1024 10 Div2048 Division by 2048 11 Div4096 Division by 4096 12 Div8192 Division by 8192 13 Div16384 Division by 16384 14 Div32768 Division by 32768 15 BMCLK Burst Mode Clock source 2 4 BMCLK Master Master timer reset/roll-over 0 TimerA Timer A counter reset/roll-over 1 TimerB Timer B counter reset/roll-over 2 TimerC Timer C counter reset/roll-over 3 TimerD Timer D counter reset/roll-over 4 TimerE Timer E counter reset/roll-over 5 Event1 On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock 6 Event2 On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock 7 Event3 On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock 8 Event4 On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock 9 Clock Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting 10 BMOM Burst Mode operating mode 1 1 BMOM SingleShot Single-shot mode 0 Continuous Continuous operation 1 BME Burst Mode enable 0 1 BME Disabled Burst mode disabled 0 Enabled Burst mode enabled 1 BMTRGR BMTRG BMTRG 0x24 0x20 read-write 0x00000000 OCHPEV OCHPEV 31 1 OCHPEV NoEffect Rising edge on an on-chip event has no effect 0 Trigger Rising edge on an on-chip event triggers a burst mode entry 1 TACMP1 TACMP1 9 1 TACMP1 NoEffect Timer X compare Y event has no effect 0 Trigger Timer X compare Y event triggers a burst mode entry 1 TECMP2 TECMP2 26 1 TECMP1 TECMP1 25 1 TAREP TAREP 8 1 TAREP NoEffect Timer X repetition event has no effect 0 Trigger Timer X repetition event triggers a burst mode entry 1 TEREP TEREP 24 1 TARST TARST 7 1 TARST NoEffect Timer X reset/roll-over event has no effect 0 Trigger Timer X reset/roll-over event triggers a burst mode entry 1 TERST TERST 23 1 TDCMP2 TDCMP2 22 1 TDCMP1 TDCMP1 21 1 TDREP TDREP 20 1 TDRST TDRST 19 1 TCCMP2 TCCMP2 18 1 TCCMP1 TCCMP1 17 1 TCREP TCREP 16 1 TCRST TCRST 15 1 TBCMP2 TBCMP2 14 1 TBCMP1 TBCMP1 13 1 TBREP TBREP 12 1 TBRST TBRST 11 1 TACMP2 TACMP2 10 1 MSTCMP1 MSTCMP1 3 1 MSTCMP1 NoEffect Master timer compare X event has no effect 0 Trigger Master timer compare X event triggers a burst mode entry 1 MSTCMP4 MSTCMP4 6 1 MSTCMP3 MSTCMP3 5 1 MSTCMP2 MSTCMP2 4 1 MSTREP MSTREP 2 1 MSTREP NoEffect Master timer repetition event has no effect 0 Trigger Master timer repetition event triggers a burst mode entry 1 MSTRST MSTRST 1 1 MSTRST NoEffect Master timer reset/roll-over event has no effect 0 Trigger Master timer reset/roll-over event triggers a burst mode entry 1 SW SW 0 1 SW NoEffect No effect 0 Trigger Trigger immediate burst mode operation 1 TAEEV7 Timer A period following External Event 7 27 1 TDEEV8 Timer D period following External Event 8 28 1 EEV7 External Event 7 (TIMA filters applied) 29 1 EEV8 External Event 8 (TIMD filters applied) 30 1 BMCMPR BMCMPR6 BMCMPR6 0x28 0x20 read-write 0x00000000 BMCMP BMCMP 0 16 0 65535 BMPER BMPER Burst Mode Period Register 0x2C 0x20 read-write 0x00000000 BMPER Burst mode Period 0 16 0 65535 EECR1 EECR1 Timer External Event Control Register 1 0x30 0x20 read-write 0x00000000 5 0x6 1-5 EE%sFAST External Event %s Fast mode 5 1 EE1FAST Resynchronized External event is re-synchronised by the HRTIM logic before acting on outputs 0 Asynchronous External event is acting asynchronously on outputs (low-latency mode) 1 5 0x6 1-5 EE%sSNS External Event %s Sensitivity 3 2 EE1SNS Active On active level defined by EExPOL bit 0 Rising Rising edge 1 Falling Falling edge 2 Both Both edges 3 5 0x6 1-5 EE%sPOL External Event %s Polarity 2 1 EE1POL ActiveHigh External event is active high 0 ActiveLow External event is active low 1 5 0x6 1-5 EE%sSRC External Event %s Source 0 2 EE1SRC Src1 Source 1 0 Src2 Source 2 1 Src3 Source 3 2 Src4 Source 4 3 EECR2 EECR2 Timer External Event Control Register 2 0x34 0x20 read-write 0x00000000 5 0x6 6-10 EE%sSNS External Event %s Sensitivity 3 2 EE6SNS Active On active level defined by EExPOL bit 0 Rising Rising edge 1 Falling Falling edge 2 Both Both edges 3 5 0x6 6-10 EE%sPOL External Event %s Polarity 2 1 EE6POL ActiveHigh External event is active high 0 ActiveLow External event is active low 1 5 0x6 6-10 EE%sSRC External Event %s Source 0 2 EE6SRC Src1 Source 1 0 Src2 Source 2 1 Src3 Source 3 2 Src4 Source 4 3 EECR3 EECR3 Timer External Event Control Register 3 0x38 0x20 read-write 0x00000000 EE6F External event 6 filter 0 4 EE6F Disabled Filter disabled 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_EEVS/2, N=6 4 Div2_N8 f_SAMPLING=f_EEVS/2, N=8 5 Div4_N6 f_SAMPLING=f_EEVS/4, N=6 6 Div4_N8 f_SAMPLING=f_EEVS/4, N=8 7 Div8_N6 f_SAMPLING=f_EEVS/8, N=6 8 Div8_N8 f_SAMPLING=f_EEVS/8, N=8 9 Div16_N5 f_SAMPLING=f_EEVS/16, N=5 10 Div16_N6 f_SAMPLING=f_EEVS/16, N=6 11 Div16_N8 f_SAMPLING=f_EEVS/16, N=8 12 Div32_N5 f_SAMPLING=f_EEVS/32, N=5 13 Div32_N6 f_SAMPLING=f_EEVS/32, N=6 14 Div32_N8 f_SAMPLING=f_EEVS/32, N=8 15 EE7F External event 7 filter 6 4 EE8F External event 8 filter 12 4 EE9F External event 9 filter 18 4 EE10F External event 10 filter 24 4 EEVSD External event sampling clock division 30 2 EEVSD Div1 f_EEVS=f_HRTIM 0 Div2 f_EEVS=f_HRTIM/2 1 Div4 f_EEVS=f_HRTIM/4 2 Div8 f_EEVS=f_HRTIM/8 3 ADC1R ADC1R ADC Trigger 1 Register 0x3C 0x20 read-write 0x00000000 MPER ADC trigger 1 on Master Period 4 1 MPER Disabled No generation of ADC trigger on timer period event 0 Enabled Generation of ADC trigger on timer period event 1 EPER ADC trigger 1 on Timer E Period 31 1 AC2 ADC trigger 1 on Timer A compare 2 10 1 AC2 Disabled No generation of ADC trigger on timer compare event 0 Enabled Generation of ADC trigger on timer compare event 1 EC4 ADC trigger 1 on Timer E compare 4 30 1 EC3 ADC trigger 1 on Timer E compare 3 29 1 EC2 ADC trigger 1 on Timer E compare 2 28 1 DPER ADC trigger 1 on Timer D Period 27 1 DC4 ADC trigger 1 on Timer D compare 4 26 1 DC3 ADC trigger 1 on Timer D compare 3 25 1 DC2 ADC trigger 1 on Timer D compare 2 24 1 CPER ADC trigger 1 on Timer C Period 23 1 CC4 ADC trigger 1 on Timer C compare 4 22 1 CC3 ADC trigger 1 on Timer C compare 3 21 1 CC2 ADC trigger 1 on Timer C compare 2 20 1 ARST ADC trigger 1 on Timer A Reset 14 1 ARST Disabled No generation of ADC trigger on timer reset and roll-over 0 Enabled Generation of ADC trigger on timer reset and roll-over 1 BRST ADC trigger 1 on Timer B Reset 19 1 BPER ADC trigger 1 on Timer B Period 18 1 BC4 ADC trigger 1 on Timer B compare 4 17 1 BC3 ADC trigger 1 on Timer B compare 3 16 1 BC2 ADC trigger 1 on Timer B compare 2 15 1 APER ADC trigger 1 on Timer A Period 13 1 AC4 ADC trigger 1 on Timer A compare 4 12 1 AC3 ADC trigger 1 on Timer A compare 3 11 1 5 0x1 1-5 EEV%s ADC trigger 1 on External Event %s 5 1 EEV1 Disabled No generation of ADC trigger on external event 0 Enabled Generation of ADC trigger on external event 1 4 0x1 1-4 MC%s ADC trigger 1 on Master Compare %s 0 1 MC1 Disabled No generation of ADC trigger on master compare event 0 Enabled Generation of ADC trigger on master compare event 1 ADC2R ADC2R ADC Trigger 2 Register 0x40 0x20 read-write 0x00000000 CRST ADC trigger 2 on Timer C Reset 22 1 CRST Disabled No generation of ADC trigger on timer reset and roll-over 0 Enabled Generation of ADC trigger on timer reset and roll-over 1 ERST ADC trigger 2 on Timer E Reset 31 1 AC2 ADC trigger 2 on Timer A compare 2 10 1 AC2 Disabled No generation of ADC trigger on timer compare event 0 Enabled Generation of ADC trigger on timer compare event 1 EC4 ADC trigger 2 on Timer E compare 4 30 1 EC3 ADC trigger 2 on Timer E compare 3 29 1 EC2 ADC trigger 2 on Timer E compare 2 28 1 DRST ADC trigger 2 on Timer D Reset 27 1 MPER ADC trigger 2 on Master Period 4 1 MPER Disabled No generation of ADC trigger on timer period event 0 Enabled Generation of ADC trigger on timer period event 1 DPER ADC trigger 2 on Timer D Period 26 1 DC4 ADC trigger 2 on Timer D compare 4 25 1 DC3 ADC trigger 2 on Timer D compare 3 24 1 DC2 ADC trigger 2 on Timer D compare 2 23 1 CPER ADC trigger 2 on Timer C Period 21 1 CC4 ADC trigger 2 on Timer C compare 4 20 1 CC3 ADC trigger 2 on Timer C compare 3 19 1 CC2 ADC trigger 2 on Timer C compare 2 18 1 BPER ADC trigger 2 on Timer B Period 17 1 BC4 ADC trigger 2 on Timer B compare 4 16 1 BC3 ADC trigger 2 on Timer B compare 3 15 1 BC2 ADC trigger 2 on Timer B compare 2 14 1 APER ADC trigger 2 on Timer A Period 13 1 AC4 ADC trigger 2 on Timer A compare 4 12 1 AC3 ADC trigger 2 on Timer A compare 3 11 1 5 0x1 6-10 EEV%s ADC trigger 2 on External Event %s 5 1 EEV6 Disabled No generation of ADC trigger on external event 0 Enabled Generation of ADC trigger on external event 1 4 0x1 1-4 MC%s ADC trigger 2 on Master Compare %s 0 1 MC1 Disabled No generation of ADC trigger on master compare event 0 Enabled Generation of ADC trigger on master compare event 1 ADC3R ADC3R ADC Trigger 3 Register 0x44 ADC4R ADC4R ADC Trigger 4 Register 0x48 FLTINR1 FLTINR1 HRTIM Fault Input Register 1 0x50 0x20 read-write 0x00000000 FLT1LCK FLT1LCK 7 1 FLT1LCKR read Unlocked Fault bits are read/write 0 Locked Fault bits are read-only 1 FLT1LCKW write Lock Lock corresponding fault bits 1 FLT4LCK FLT4LCK 31 1 read write 4 0x8 1-4 FLT%sF FLT%sF 3 4 FLT1F Disabled No filter, FLTx acts asynchronously 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_HRTIM/2, N=6 4 Div2_N8 f_SAMPLING=f_HRTIM/2, N=8 5 Div4_N6 f_SAMPLING=f_HRTIM/4, N=6 6 Div4_N8 f_SAMPLING=f_HRTIM/4, N=8 7 Div8_N6 f_SAMPLING=f_HRTIM/8, N=6 8 Div8_N8 f_SAMPLING=f_HRTIM/8, N=8 9 Div16_N5 f_SAMPLING=f_HRTIM/16, N=5 10 Div16_N6 f_SAMPLING=f_HRTIM/16, N=6 11 Div16_N8 f_SAMPLING=f_HRTIM/16, N=8 12 Div32_N5 f_SAMPLING=f_HRTIM/32, N=5 13 Div32_N6 f_SAMPLING=f_HRTIM/32, N=6 14 Div32_N8 f_SAMPLING=f_HRTIM/32, N=8 15 4 0x8 1-4 FLT%sSRC Fault %s source 2 1 FLT1SRC Input Fault input is FLTx input pin 0 Internal Fault input is FLTn_Int signal 1 4 0x8 1-4 FLT%sP FLT%sP 1 1 FLT1P ActiveLow Fault input is active low 0 ActiveHigh Fault input is active high 1 4 0x8 1-4 FLT%sE FLT%sE 0 1 FLT1E Disabled Fault input disabled 0 Enabled Fault input enabled 1 FLT3LCK FLT3LCK 23 1 read write FLT2LCK FLT2LCK 15 1 read write FLTINR2 FLTINR2 HRTIM Fault Input Register 2 0x54 0x20 read-write 0x00000000 FLTSD FLTSD 24 2 FLTSD Div1 f_FLTS=f_HRTIM 0 Div2 f_FLTS=f_HRTIM/2 1 Div4 f_FLTS=f_HRTIM/4 2 Div8 f_FLTS=f_HRTIM/8 3 FLT5LCK FLT5LCK 7 1 FLT5LCKR read Unlocked Fault bits are read/write 0 Locked Fault bits are read-only 1 FLT5LCKW write Lock Lock corresponding fault bits 1 1 0x0 5-5 FLT%sF FLT%sF 3 4 FLT5F Disabled No filter, FLTx acts asynchronously 0 Div1_N2 f_SAMPLING=f_HRTIM, N=2 1 Div1_N4 f_SAMPLING=f_HRTIM, N=4 2 Div1_N8 f_SAMPLING=f_HRTIM, N=8 3 Div2_N6 f_SAMPLING=f_HRTIM/2, N=6 4 Div2_N8 f_SAMPLING=f_HRTIM/2, N=8 5 Div4_N6 f_SAMPLING=f_HRTIM/4, N=6 6 Div4_N8 f_SAMPLING=f_HRTIM/4, N=8 7 Div8_N6 f_SAMPLING=f_HRTIM/8, N=6 8 Div8_N8 f_SAMPLING=f_HRTIM/8, N=8 9 Div16_N5 f_SAMPLING=f_HRTIM/16, N=5 10 Div16_N6 f_SAMPLING=f_HRTIM/16, N=6 11 Div16_N8 f_SAMPLING=f_HRTIM/16, N=8 12 Div32_N5 f_SAMPLING=f_HRTIM/32, N=5 13 Div32_N6 f_SAMPLING=f_HRTIM/32, N=6 14 Div32_N8 f_SAMPLING=f_HRTIM/32, N=8 15 1 0x0 5-5 FLT%sSRC Fault %s source 2 1 FLT5SRC Input Fault input is FLTx input pin 0 Internal Fault input is FLTn_Int signal 1 1 0x0 5-5 FLT%sP FLT%sP 1 1 FLT5P ActiveLow Fault input is active low 0 ActiveHigh Fault input is active high 1 1 0x0 5-5 FLT%sE FLT%sE 0 1 FLT5E Disabled Fault input disabled 0 Enabled Fault input enabled 1 BDMUPR BDMUPDR BDMUPDR 0x58 0x20 read-write 0x00000000 MCR MCR 0 1 MCR NotUpdated Register not updated by burst DMA access 0 Updated Register updated by burst DMA access 1 MCMP4 MCMP4 9 1 MCMP3 MCMP3 8 1 MCMP2 MCMP2 7 1 MCMP1 MCMP1 6 1 MREP MREP 5 1 MPER MPER 4 1 MCNT MCNT 3 1 MDIER MDIER 2 1 MICR MICR 1 1 BDTAUPR BDTxUPR Burst DMA Timerx update Register 0x5C 0x20 read-write 0x00000000 CR HRTIM_TIMxCR register update enable 0 1 CR NotUpdated Register not updated by burst DMA access 0 Updated Register updated by burst DMA access 1 FLTR HRTIM_FLTxR register update enable 20 1 OUTR HRTIM_OUTxR register update enable 19 1 CHPR HRTIM_CHPxR register update enable 18 1 RSTR HRTIM_RSTxR register update enable 17 1 EEFR2 HRTIM_EEFxR2 register update enable 16 1 EEFR1 HRTIM_EEFxR1 register update enable 15 1 RST2R HRTIM_RST2xR register update enable 14 1 SET2R HRTIM_SET2xR register update enable 13 1 RST1R HRTIM_RST1xR register update enable 12 1 SET1R HRTIM_SET1xR register update enable 11 1 DTR HRTIM_DTxR register update enable 10 1 CMP4 HRTIM_CMP4xR register update enable 9 1 CMP3 HRTIM_CMP3xR register update enable 8 1 CMP2 HRTIM_CMP2xR register update enable 7 1 CMP1 HRTIM_CMP1xR register update enable 6 1 REP HRTIM_REPxR register update enable 5 1 PER HRTIM_PERxR register update enable 4 1 CNT HRTIM_CNTxR register update enable 3 1 DIER HRTIM_TIMxDIER register update enable 2 1 ICR HRTIM_TIMxICR register update enable 1 1 BDMADR BDMADR Burst DMA Data Register 0x70 0x20 read-write 0x00000000 BDMADR Burst DMA Data register 0 32 0 4294967295 BDTBUPR 0x60 BDTCUPR 0x64 BDTDUPR 0x68 BDTEUPR 0x6C DFSDM Digital filter for sigma delta modulators DFSDM 0x40017000 0x0 0x400 registers DFSDM1_FLT0 DFSDM1 filter 0 interrupt 110 DFSDM1_FLT1 DFSDM1 filter 1 interrupt 111 DFSDM1_FLT2 DFSDM1 filter 2 interrupt 112 DFSDM1_FLT3 DFSDM1 filter 3 interrupt 113 8 0x20 0-7 CH%s DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers 0x0 CFGR1 CH0CFGR1 channel configuration y register 0x0 0x20 read-write 0x00000000 DFSDMEN DFSDMEN 31 1 DFSDMEN Disabled DFSDM interface disabled 0 Enabled DFSDM interface enabled 1 CKOUTSRC CKOUTSRC 30 1 CKOUTSRC SYSCLK Source for output clock is from system clock 0 AUDCLK Source for output clock is from audio clock 1 CKOUTDIV CKOUTDIV 16 8 0 255 DATPACK DATPACK 14 2 DATPACK Standard Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y 0 Interleaved : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y) 1 Dual Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1) 2 DATMPX DATMPX 12 2 DATMPX External Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected 0 ADC Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register 1 Internal Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting 2 CHINSEL CHINSEL 8 1 CHINSEL SameChannel Channel inputs are taken from pins of the same channel y 0 FollowingChannel Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8) 1 CHEN CHEN 7 1 CHEN Disabled Channel y disabled 0 Enabled Channel y enabled 1 CKABEN CKABEN 6 1 CKABEN Disabled Clock absence detector disabled on channel y 0 Enabled Clock absence detector enabled on channel y 1 SCDEN SCDEN 5 1 SCDEN Disabled Input channel y will not be guarded by the short-circuit detector 0 Enabled Input channel y will be continuously guarded by the short-circuit detector 1 SPICKSEL SPICKSEL 2 2 SPICKSEL CKIN Clock coming from external CKINy input - sampling point according SITP[1:0] 0 CKOUT Clock coming from internal CKOUT output - sampling point according SITP[1:0] 1 CKOUTSecondFalling Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge) 2 CKOUTSecondRising Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge) 3 SITP SITP 0 2 SITP SPIRisingEdge SPI with rising edge to strobe data 0 SPIFallingEdge SPI with falling edge to strobe data 1 Manchester Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 2 ManchesterInverted Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 3 CFGR2 CH0CFGR2 channel configuration y register 0x4 0x20 read-write 0x00000000 OFFSET OFFSET 8 24 0 16777215 DTRBS DTRBS 3 5 0 31 AWSCDR CH0AWSCDR analog watchdog and short-circuit detector register 0x8 0x20 read-write 0x00000000 AWFORD AWFORD 22 2 AWFORD FastSinc FastSinc filter type 0 Sinc1 Sinc1 filter type 1 Sinc2 Sinc2 filter type 2 Sinc3 Sinc3 filter type 3 AWFOSR AWFOSR 16 5 0 31 BKSCD BKSCD 12 4 0 15 SCDT SCDT 0 8 0 255 WDATR CH0WDATR channel watchdog filter data register 0xC 0x20 read-write 0x00000000 WDATA WDATA 0 16 0 65535 DATINR CH0DATINR channel data input register 0x10 0x20 read-write 0x00000000 INDAT1 INDAT1 16 16 0 65535 INDAT0 INDAT0 0 16 0 65535 4 0x80 0-3 FLT%s Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR 0x100 CR1 FLT0CR1 control register 1 0x0 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 AWFSEL Output Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0 Transceiver Analog watchdog on channel transceivers value (after watchdog filter) 1 FAST Fast conversion mode selection for regular conversions 29 1 FAST Disabled Fast conversion mode disabled 0 Enabled Fast conversion mode enabled 1 RCH Regular channel selection 24 3 RCH Channel0 Channel 0 is selected as regular channel 0 Channel1 Channel 1 is selected as regular channel 1 Channel2 Channel 2 is selected as regular channel 2 Channel3 Channel 3 is selected as regular channel 3 Channel4 Channel 4 is selected as regular channel 4 Channel5 Channel 5 is selected as regular channel 5 Channel6 Channel 6 is selected as regular channel 6 Channel7 Channel 7 is selected as regular channel 7 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RDMAEN Disabled The DMA channel is not enabled to read regular data 0 Enabled The DMA channel is enabled to read regular data 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RSYNC NoLaunch Do not launch a regular conversion synchronously with DFSDM_FLT0 0 Launch Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 1 RCONT Continuous mode selection for regular conversions 18 1 RCONT Once The regular channel is converted just once for each conversion request 0 Continuous The regular channel is converted repeatedly after each conversion request 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSWSTARTW write Start Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTEN Disabled Trigger detection is disabled 0 RisingEdge Each rising edge on the selected trigger makes a request to launch an injected conversion 1 FallingEdge Each falling edge on the selected trigger makes a request to launch an injected conversion 2 BothEdges Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 3 JEXTSEL Trigger signal selection for launching injected conversions 8 5 0 31 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JDMAEN Disabled The DMA channel is not enabled to read injected data 0 Enabled The DMA channel is enabled to read injected data 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSCAN Single One channel conversion is performed from the injected channel group and next the selected channel from this group is selected 0 Series The series of conversions for the injected group channels is executed, starting over with the lowest selected channel 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSYNC Disabled Do not launch an injected conversion synchronously with DFSDM_FLT0 0 Enabled Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSWSTARTW write Start Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1 1 DFEN DFSDM enable 0 1 DFEN Disabled DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped 0 Enabled DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting 1 CR2 FLT0CR2 control register 2 0x4 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 AWDCH Disabled Analog watchdog is disabled on channel y 0 Enabled Analog watchdog is enabled on channel y 1 EXCH Extremes detector channel selection 8 8 EXCH Disabled Extremes detector does not accept data from channel y 0 Enabled Extremes detector accepts data from channel y 1 CKABIE Clock absence interrupt enable 6 1 CKABIE Disabled Detection of channel input clock absence interrupt is disabled 0 Enabled Detection of channel input clock absence interrupt is enabled 1 SCDIE Short-circuit detector interrupt enable 5 1 SCDIE Disabled Short-circuit detector interrupt is disabled 0 Enabled Short-circuit detector interrupt is enabled 1 AWDIE Analog watchdog interrupt enable 4 1 AWDIE Disabled Analog watchdog interrupt is disabled 0 Enabled Analog watchdog interrupt is enabled 1 ROVRIE Regular data overrun interrupt enable 3 1 ROVRIE Disabled Regular data overrun interrupt is disabled 0 Enabled Regular data overrun interrupt is enabled 1 JOVRIE Injected data overrun interrupt enable 2 1 JOVRIE Disabled Injected data overrun interrupt is disabled 0 Enabled Injected data overrun interrupt is enabled 1 REOCIE Regular end of conversion interrupt enable 1 1 REOCIE Disabled Regular end of conversion interrupt is disabled 0 Enabled Regular end of conversion interrupt is enabled 1 JEOCIE Injected end of conversion interrupt enable 0 1 JEOCIE Disabled Injected end of conversion interrupt is disabled 0 Enabled Injected end of conversion interrupt is enabled 1 ISR FLT0ISR interrupt and status register 0x8 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 SCDF Clear No short-circuit detector event occurred on channel y 0 Set The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers 1 CKABF Clock absence flag 16 8 CKABF Clear Clock signal on channel y is present. 0 Set Clock signal on channel y is not present 1 RCIP Regular conversion in progress status 14 1 RCIP NotInProgress No request to convert the regular channel has been issued 0 InProgress The conversion of the regular channel is in progress or a request for a regular conversion is pending 1 JCIP Injected conversion in progress status 13 1 JCIP NotInProgress No request to convert the injected channel group (neither by software nor by trigger) has been issued 0 InProgress The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection 1 AWDF Analog watchdog 4 1 AWDF Clear No Analog watchdog event occurred 0 Set The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers 1 ROVRF Regular conversion overrun flag 3 1 ROVRF Clear No regular conversion overrun has occurred 0 Set A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns 1 JOVRF Injected conversion overrun flag 2 1 JOVRF Clear No injected conversion overrun has occurred 0 Set An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns 1 REOCF End of regular conversion flag 1 1 REOCF Clear No regular conversion has completed 0 Set A regular conversion has completed and its data may be read 1 JEOCF End of injected conversion flag 0 1 JEOCF Clear No injected conversion has completed 0 Set An injected conversion has completed and its data may be read 1 ICR FLT0ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 0 255 CLRCKABF Clear the clock absence flag 16 8 0 255 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRROVRFW write Clear Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRJOVRFW write Clear Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register 1 JCHGR FLT0JCHGR injected channel group selection register 0x10 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 0 255 FCR FLT0FCR filter control register 0x14 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FORD FastSinc FastSinc filter type 0 Sinc1 Sinc1 filter type 1 Sinc2 Sinc2 filter type 2 Sinc3 Sinc3 filter type 3 Sinc4 Sinc4 filter type 4 Sinc5 Sinc5 filter type 5 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 0 1023 IOSR Integrator oversampling ratio (averaging length) 0 8 0 255 JDATAR FLT0JDATAR data register for injected group 0x18 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 0 16777215 JDATACH Injected channel most recently converted 0 3 0 7 RDATAR FLT0RDATAR data register for the regular channel 0x1C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 0 16777215 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 0 7 AWHTR FLT0AWHTR analog watchdog high threshold register 0x20 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 0 16777215 4 0x1 0-3 BKAWH%s Break signal assignment to analog watchdog high threshold event 0 1 BKAWH0 NotAssigned Break i signal is not assigned to an analog watchdog high threshold event 0 Assigned Break i signal is assigned to an analog watchdog high threshold event 1 AWLTR FLT0AWLTR analog watchdog low threshold register 0x24 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 0 16777215 4 0x1 0-3 BKAWL%s Break signal assignment to analog watchdog low threshold event 0 1 BKAWL0 NotAssigned Break i signal is not assigned to an analog watchdog low threshold event 0 Assigned Break i signal is assigned to an analog watchdog low threshold event 1 AWSR FLT0AWSR analog watchdog status register 0x28 0x20 read-only 0x00000000 8 0x1 0-7 AWHTF%s Analog watchdog high threshold flag 8 1 AWHTF0 NoError No high threshold error 0 Error A high threshold error on channel y 1 8 0x1 0-7 AWLTF%s Analog watchdog low threshold flag 0 1 AWLTF0 NoError No low threshold error 0 Error A low threshold error on channel y 1 AWCFR FLT0AWCFR analog watchdog clear flag register 0x2C 0x20 read-write 0x00000000 8 0x1 0-7 CLRAWHTF%s Clear the analog watchdog high threshold flag 8 1 oneToClear CLRAWHTF0W write Clear Clear the corresponding AWHTF[y] bit 1 8 0x1 0-7 CLRAWLTF%s Clear the analog watchdog low threshold flag 0 1 oneToClear CLRAWLTF0W write Clear Clear the corresponding AWLTF[y] bit 1 EXMAX FLT0EXMAX Extremes detector maximum register 0x30 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 0 16777215 EXMAXCH Extremes detector maximum data channel 0 3 0 7 EXMIN FLT0EXMIN Extremes detector minimum register 0x34 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 0 16777215 EXMINCH Extremes detector minimum data channel 0 3 0 7 CNVTIMR FLT0CNVTIMR conversion timer register 0x38 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 0 268435455 TIM16 General-purpose-timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 117 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 1 0x0 1-1 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 1 0x0 1-1 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 SR SR status register 0x10 0x10 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF Copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x10 read-write 0x00000000 REP Repetition counter value 0 8 0 255 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 TIM16_AF1 TIM16_AF1 TIM16 alternate function register 1 0x60 0x20 read-write 0x00000000 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK1E BRK dfsdm1_break[1] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 TIM16_TISEL TIM16_TISEL TIM16 input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TIM17 General-purpose-timers TIM 0x40014800 0x0 0x400 registers TIM17 TIM17 global interrupt 118 CR1 CR1 control register 1 0x0 CR2 CR2 control register 2 0x4 DIER DIER DMA/Interrupt enable register 0xC SR SR status register 0x10 EGR EGR event generation register 0x14 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 CCER CCER capture/compare enable register 0x20 CNT CNT counter 0x24 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 ARR ARR auto-reload register 0x2C RCR RCR repetition counter register 0x30 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 BDTR BDTR break and dead-time register 0x44 DCR DCR DMA control register 0x48 DMAR DMAR DMA address for full transfer 0x4C TIM17_AF1 TIM17_AF1 TIM17 alternate function register 1 0x60 0x20 read-write 0x00000000 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK1E BRK dfsdm1_break[1] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 TIM17_TISEL TIM17_TISEL TIM17 input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM15 global interrupt 116 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 2 0x2 1-2 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 1 0x0 1-1 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 TS Trigger selection 4 3 MSM Master/Slave mode 7 1 SMS_3 Slave mode selection bit 3 16 1 TS2 Trigger selection - bit 4:3 20 2 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 2 0x1 1-2 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 1 0x0 1-1 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 RCR RCR repetition counter register 0x30 0x10 read-write 0x00000000 REP Repetition counter value 0 8 0 255 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 DTG Dead-time generator setup 0 8 0 255 BKF Break filter 16 4 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM15 alternate fdfsdm1_breakon register 1 0x60 0x20 read-write 0x00000000 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK0E BRK dfsdm1_break[0] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 TISEL TISEL TIM15 input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TI2SEL selects TI2[0] to TI2[15] input 8 4 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40011000 0x0 0x400 registers USART1 USART1 global interrupt 37 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFIFO Full interrupt enable 31 1 RXFFIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when RXFF = 1 in the USART_ISR register 1 TXFEIE TXFIFO empty interrupt enable 30 1 TXFEIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when TXFE = 1 in the USART_ISR register 1 FIFOEN FIFO mode enable 29 1 FIFOEN Disabled FIFO mode is disabled 0 Enabled FIFO mode is enabled 1 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable de-assertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input is ignored 3 1 DIS_NSS Disabled SPI slave selection depends on NSS input pin 0 Enabled SPI slave is always selected and NSS input pin is ignored 1 SLVEN Synchronous Slave mode enable 0 1 SLVEN Disabled Slave mode disabled 0 Enabled Slave mode enabled 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFIFO threshold configuration 29 3 TXFTCFG Depth_1_8 TXFIFO reaches 1/8 of its depth 0 Depth_1_4 TXFIFO reaches 1/4 of its depth 1 Depth_1_2 TXFIFO reaches 1/2 of its depth 2 Depth_3_4 TXFIFO reaches 3/4 of its depth 3 Depth_7_8 TXFIFO reaches 7/8 of its depth 4 Empty TXFIFO becomes empty 5 RXFTIE RXFIFO threshold interrupt enable 28 1 RXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTCFG Depth_1_8 RXFIFO reaches 1/8 of its depth 0 Depth_1_4 RXFIFO reaches 1/4 of its depth 1 Depth_1_2 RXFIFO reaches 1/2 of its depth 2 Depth_3_4 RXFIFO reaches 3/4 of its depth 3 Depth_7_8 RXFIFO reaches 7/8 of its depth 4 Full RXFIFO becomes full 5 TCBGTIE Transmission Complete before guard time, interrupt enable 24 1 TCBGTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated whenever TCBGT=1 in the USART_ISR register 1 TXFTIE TXFIFO threshold interrupt enable 23 1 TXFTIE Disabled Interrupt inhibited 0 Enabled USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP Ir low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN Ir mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR DIV_Mantissa 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFIFO threshold flag 27 1 TXFT NotReached TXFIFO does not reach the programmed threshold. 0 Reached TXFIFO reached the programmed threshold. 1 RXFT RXFIFO threshold flag 26 1 RXFT NotReached Receive FIFO does not reach the programmed threshold. 0 Reached Receive FIFO reached the programmed threshold. 1 TCBGT Transmission complete before guard time flag 25 1 TCBGT NotCompleted Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 0 Completed Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card) 1 RXFF RXFIFO Full 24 1 RXFF NotFull RXFIFO not full. 0 Full RXFIFO Full. 1 TXFE TXFIFO Empty 23 1 TXFE NotEmpty TXFIFO not empty. 0 Empty TXFIFO empty. 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR SPI slave underrun error flag 13 1 UDR NoUnderrun No underrun error 0 Underrun underrun error 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 UDRCF SPI slave underrun clear flag 13 1 oneToClear UDRCF Clear Clear the UDR flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 oneToClear TCBGTCF Clear Clear the TCBGT flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 TXFECF TXFIFO empty clear flag 5 1 oneToClear TXFECF Clear Clear the TXFE flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 PRESC PRESC USART prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 4 PRESCALER Div1 Input clock divided by 1 0 Div2 Input clock divided by 2 1 Div4 Input clock divided by 4 2 Div6 Input clock divided by 6 3 Div8 Input clock divided by 8 4 Div10 Input clock divided by 10 5 Div12 Input clock divided by 12 6 Div16 Input clock divided by 16 7 Div32 Input clock divided by 32 8 Div64 Input clock divided by 64 9 Div128 Input clock divided by 128 10 Div256 Input clock divided by 256 11 USART2 0x40004400 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 UART4 0x40004C00 UART4 UART4 global interrupt 52 UART5 0x40005000 UART5 UART5 global interrupt 53 USART6 0x40011400 USART6 USART6 global interrupt 71 UART7 0x40007800 UART7 UART7 global interrupt 82 UART8 0x40007C00 UART8 UART8 global interrupt 83 TIM1 Advanced-timers TIM 0x40010000 0x0 0x400 registers TIM1_BRK TIM1 break interrupt 24 TIM1_UP TIM1 update interrupt 25 TIM1_TRG_COM TIM1 trigger and commutation 26 TIM_CC TIM1 capture / compare 27 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS2 Master mode selection 2 20 4 6 0x2 1-6 OIS%s Output Idle state (OC%s output) 8 1 OIS1 Reset OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 0 Set OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 1 3 0x2 1-3 OIS%sN Output Idle state (OC%sN output) 9 1 OIS1N Reset OCxN=0 after a dead-time when MOE=0 0 Set OCxN=1 after a dead-time when MOE=0 1 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 CCUS Capture/compare control update selection 2 1 CCUS Sw When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 0 SwOrEdge When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI 1 CCPC Capture/compare preloaded control 0 1 CCPC NotPreloaded CCxE, CCxNE and OCxM bits are not preloaded 0 Preloaded CCxE, CCxNE and OCxM bits are preloaded 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 SMS_3 Slave mode selection - bit 3 16 1 TS2 Trigger selection - bit 4:3 20 2 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 COMDE COM DMA request enable 13 1 COMDE Disabled COM DMA request disabled 0 Enabled COM DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 BIE Break interrupt enable 7 1 BIE Disabled Break interrupt disabled 0 Enabled Break interrupt enabled 1 COMIE COM interrupt enable 5 1 COMIE Disabled COM interrupt disabled 0 Enabled COM interrupt enabled 1 SR SR status register 0x10 0x20 read-write 0x00000000 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 CC6IF Compare 6 interrupt flag 17 1 zeroToClear read write CC5IF Compare 5 interrupt flag 16 1 zeroToClear read write SBIF System Break interrupt flag 13 1 zeroToClear SBIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 SBIFW write Clear Clear flag 0 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 B2IF Break 2 interrupt flag 8 1 zeroToClear B2IFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 B2IFW write Clear Clear flag 0 BIF Break interrupt flag 7 1 zeroToClear BIFR read NoTrigger No break event occurred 0 Trigger An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register 1 BIFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 COMIF COM interrupt flag 5 1 zeroToClear COMIFR read NoCOM No COM event occurred 0 COM COM interrupt pending 1 COMIFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 COMG Capture/Compare control update generation 5 1 COMGW Trigger When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated 1 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 BG Break generation 7 1 BGW Trigger A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled 1 B2G Break 2 generation 8 1 B2GW Trigger A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 6 0x4 1-6 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 6 0x4 1-6 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 3 0x4 1-3 CC%sNE Capture/Compare %s complementary output enable 2 1 CC1NE Disabled Complementary output disabled 0 Enabled Complementary output enabled 1 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP ActiveHigh OCxN active high 0 ActiveLow OCxN active low 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write 0 65535 UIFCPY UIF copy 31 1 read-only CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 0 65535 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 0 255 LOCK Lock configuration 8 2 LOCK Off No bit is write protected 0 Level1 Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written 1 Level2 LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written 2 Level3 LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written 3 OSSI Off-state selection for Idle mode 10 1 OSSI HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are forced to idle level 1 OSSR Off-state selection for Run mode 11 1 OSSR HiZ When inactive, OC/OCN outputs are disabled 0 IdleLevel When inactive, OC/OCN outputs are enabled with their inactive level 1 BKE Break enable 12 1 BKE Disabled Break function x disabled 0 Enabled Break function x enabled 1 BKP Break polarity 13 1 BKP ActiveLow Break input BRKx is active low 0 ActiveHigh Break input BRKx is active high 1 AOE Automatic output enable 14 1 AOE Manual MOE can be set only by software 0 Automatic MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) 1 MOE Main output enable 15 1 MOE DisabledIdle OC/OCN are disabled or forced idle depending on OSSI 0 Enabled OC/OCN are enabled if CCxE/CCxNE are set 1 BKF Break filter 16 4 BK2F Break 2 filter 20 4 BK2E Break 2 enable 24 1 BK2P Break 2 polarity 25 1 CCMR3_Output CCMR3_Output capture/compare mode register 3 (output mode) 0x54 0x20 read-write 0x00000000 2 0x8 5-6 OC%sFE Output compare %s fast enable 2 1 2 0x8 5-6 OC%sPE Output compare %s preload enable 3 1 2 0x8 5-6 OC%sM Output compare %s mode 4 3 2 0x8 5-6 OC%sCE Output compare %s clear enable 7 1 2 0x8 5-6 OC%sM_3 Output compare %s mode, bit 3 16 1 CCR5 CCR5 capture/compare register 0x58 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 0x5C 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 AF1 AF1 TIM1 alternate function option register 1 0x60 0x20 read-write 0x00000000 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDF1BK0E BRK dfsdm1_break[0] enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM1 Alternate function odfsdm1_breakster 2 0x64 0x20 read-write 0x00000000 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DF1BK1E BRK2 dfsdm1_break[1] enable 8 1 BK2INP BRK2 BKIN2 input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarit 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 TISEL TISEL TIM1 timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL selects TI1[0] to TI1[15] input 0 4 TI2SEL selects TI2[0] to TI2[15] input 8 4 TI3SEL selects TI3[0] to TI3[15] input 16 4 TI4SEL selects TI4[0] to TI4[15] input 24 4 TIM8 TIM 0x40010400 TIM8_BRK_TIM12 TIM8 and 12 break global 43 TIM8_UP_TIM13 TIM8 and 13 update global 44 TIM8_TRG_COM_TIM14 TIM8 and 14 trigger /commutation and global 45 TIM8_CC TIM8 capture / compare 46 FDCAN1 FDCAN1 FDCAN 0x4000A000 0x0 0x400 registers FDCAN1_IT0 FDCAN1 Interrupt 0 19 FDCAN1_IT1 FDCAN1 Interrupt 1 21 CREL CREL FDCAN Core Release Register 0x0 0x20 read-only 0x00000000 REL Core release 28 4 STEP Step of Core release 24 4 SUBSTEP Sub-step of Core release 20 4 YEAR Timestamp Year 16 4 MON Timestamp Month 8 8 DAY Timestamp Day 0 8 ENDN ENDN FDCAN Core Release Register 0x4 0x20 read-only 0x00000000 ETV Endiannes Test Value 0 32 DBTP DBTP FDCAN Data Bit Timing and Prescaler Register 0xC 0x20 read-write 0x00000000 DSJW Synchronization Jump Width 0 4 DTSEG2 Data time segment after sample point 4 4 DTSEG1 Data time segment after sample point 8 5 DBRP Data BIt Rate Prescaler 16 5 TDC Transceiver Delay Compensation 23 1 TEST TEST FDCAN Test Register 0x10 0x20 read-write 0x00000000 LBCK Loop Back mode 4 1 read-write TX Loop Back mode 5 2 read-write RX Control of Transmit Pin 7 1 RWD RWD FDCAN RAM Watchdog Register 0x14 0x20 read-only 0x00000000 WDV Watchdog value 8 8 WDC Watchdog configuration 0 8 read-write CCCR CCCR FDCAN CC Control Register 0x18 0x20 read-write 0x00000000 INIT Initialization 0 1 CCE Configuration Change Enable 1 1 ASM ASM Restricted Operation Mode 2 1 CSA Clock Stop Acknowledge 3 1 CSR Clock Stop Request 4 1 MON Bus Monitoring Mode 5 1 DAR Disable Automatic Retransmission 6 1 TEST Test Mode Enable 7 1 FDOE FD Operation Enable 8 1 BSE FDCAN Bit Rate Switching 9 1 PXHD Protocol Exception Handling Disable 12 1 EFBI Edge Filtering during Bus Integration 13 1 TXP TXP 14 1 NISO Non ISO Operation 15 1 NBTP NBTP FDCAN Nominal Bit Timing and Prescaler Register 0x1C 0x20 read-write 0x00000000 NSJW NSJW: Nominal (Re)Synchronization Jump Width 25 7 NBRP Bit Rate Prescaler 16 9 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 read-write 0x00000000 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 read-write 0x00000000 TSC Timestamp Counter 0 16 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 0x20 read-write 0x00000000 ETOC Enable Timeout Counter 0 1 TOS Timeout Select 1 2 TOP Timeout Period 16 16 TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 read-write 0x00000000 TOC Timeout Counter 0 16 ECR ECR FDCAN Error Counter Register 0x40 0x20 read-write 0x00000000 CEL AN Error Logging 16 8 RP Receive Error Passive 15 1 REC Receive Error Counter 8 7 TEC Transmit Error Counter 0 8 PSR PSR FDCAN Protocol Status Register 0x44 0x20 read-write 0x00000000 LEC Last Error Code 0 3 ACT Activity 3 2 EP Error Passive 5 1 EW Warning Status 6 1 BO Bus_Off Status 7 1 DLEC Data Last Error Code 8 3 RESI ESI flag of last received FDCAN Message 11 1 RBRS BRS flag of last received FDCAN Message 12 1 REDL Received FDCAN Message 13 1 PXE Protocol Exception Event 14 1 TDCV Transmitter Delay Compensation Value 16 7 TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 read-write 0x00000000 TDCF Transmitter Delay Compensation Filter Window Length 0 7 TDCO Transmitter Delay Compensation Offset 8 7 IR IR FDCAN Interrupt Register 0x50 0x20 read-write 0x00000000 RF0N Rx FIFO 0 New Message 0 1 RF0W Rx FIFO 0 Full 1 1 RF0F Rx FIFO 0 Full 2 1 RF0L Rx FIFO 0 Message Lost 3 1 RF1N Rx FIFO 1 New Message 4 1 RF1W Rx FIFO 1 Watermark Reached 5 1 RF1F Rx FIFO 1 Watermark Reached 6 1 RF1L Rx FIFO 1 Message Lost 7 1 HPM High Priority Message 8 1 TC Transmission Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEF Tx FIFO Empty 11 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TSW Timestamp Wraparound 16 1 MRAF Message RAM Access Failure 17 1 TOO Timeout Occurred 18 1 DRX Message stored to Dedicated Rx Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 BO Bus_Off Status 25 1 WDI Watchdog Interrupt 26 1 PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 27 1 PED Protocol Error in Data Phase (Data Bit Time is used) 28 1 ARA Access to Reserved Address 29 1 IE IE FDCAN Interrupt Enable Register 0x54 0x20 read-write 0x00000000 RF0NE Rx FIFO 0 New Message Enable 0 1 RF0WE Rx FIFO 0 Full Enable 1 1 RF0FE Rx FIFO 0 Full Enable 2 1 RF0LE Rx FIFO 0 Message Lost Enable 3 1 RF1NE Rx FIFO 1 New Message Enable 4 1 RF1WE Rx FIFO 1 Watermark Reached Enable 5 1 RF1FE Rx FIFO 1 Watermark Reached Enable 6 1 RF1LE Rx FIFO 1 Message Lost Enable 7 1 HPME High Priority Message Enable 8 1 TCE Transmission Completed Enable 9 1 TCFE Transmission Cancellation Finished Enable 10 1 TEFE Tx FIFO Empty Enable 11 1 TEFNE Tx Event FIFO New Entry Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Enable 13 1 TEFFE Tx Event FIFO Full Enable 14 1 TEFLE Tx Event FIFO Element Lost Enable 15 1 TSWE Timestamp Wraparound Enable 16 1 MRAFE Message RAM Access Failure Enable 17 1 TOOE Timeout Occurred Enable 18 1 DRXE Message stored to Dedicated Rx Buffer Enable 19 1 BECE Bit Error Corrected Interrupt Enable 20 1 BEUE Bit Error Uncorrected Interrupt Enable 21 1 ELOE Error Logging Overflow Enable 22 1 EPE Error Passive Enable 23 1 EWE Warning Status Enable 24 1 BOE Bus_Off Status Enable 25 1 WDIE Watchdog Interrupt Enable 26 1 PEAE Protocol Error in Arbitration Phase Enable 27 1 PEDE Protocol Error in Data Phase Enable 28 1 ARAE Access to Reserved Address Enable 29 1 ILS ILS FDCAN Interrupt Line Select Register 0x58 0x20 read-write 0x00000000 RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF0FL Rx FIFO 0 Full Interrupt Line 2 1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 RF1FL Rx FIFO 1 Full Interrupt Line 6 1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 HPML High Priority Message Interrupt Line 8 1 TCL Transmission Completed Interrupt Line 9 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TEFL Tx FIFO Empty Interrupt Line 11 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Element Lost Interrupt Line 15 1 TSWL Timestamp Wraparound Interrupt Line 16 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 TOOL Timeout Occurred Interrupt Line 18 1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 BECL Bit Error Corrected Interrupt Line 20 1 BEUL Bit Error Uncorrected Interrupt Line 21 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 BOL Bus_Off Status 25 1 WDIL Watchdog Interrupt Line 26 1 PEAL Protocol Error in Arbitration Phase Line 27 1 PEDL Protocol Error in Data Phase Line 28 1 ARAL Access to Reserved Address Line 29 1 ILE ILE FDCAN Interrupt Line Enable Register 0x5C 0x20 read-write 0x00000000 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 GFC GFC FDCAN Global Filter Configuration Register 0x80 0x20 read-write 0x00000000 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 ANFE Accept Non-matching Frames Extended 2 2 ANFS Accept Non-matching Frames Standard 4 2 SIDFC SIDFC FDCAN Standard ID Filter Configuration Register 0x84 0x20 read-write 0x00000000 FLSSA Filter List Standard Start Address 2 14 LSS List Size Standard 16 8 XIDFC XIDFC FDCAN Extended ID Filter Configuration Register 0x88 0x20 read-write 0x00000000 FLESA Filter List Standard Start Address 2 14 LSE List Size Extended 16 8 XIDAM XIDAM FDCAN Extended ID and Mask Register 0x90 0x20 read-write 0x00000000 EIDM Extended ID Mask 0 29 HPMS HPMS FDCAN High Priority Message Status Register 0x94 0x20 read-only 0x00000000 BIDX Buffer Index 0 6 MSI Message Storage Indicator 6 2 FIDX Filter Index 8 7 FLST Filter List 15 1 NDAT1 NDAT1 FDCAN New Data 1 Register 0x98 0x20 read-write 0x00000000 ND0 New data 0 1 ND1 New data 1 1 ND2 New data 2 1 ND3 New data 3 1 ND4 New data 4 1 ND5 New data 5 1 ND6 New data 6 1 ND7 New data 7 1 ND8 New data 8 1 ND9 New data 9 1 ND10 New data 10 1 ND11 New data 11 1 ND12 New data 12 1 ND13 New data 13 1 ND14 New data 14 1 ND15 New data 15 1 ND16 New data 16 1 ND17 New data 17 1 ND18 New data 18 1 ND19 New data 19 1 ND20 New data 20 1 ND21 New data 21 1 ND22 New data 22 1 ND23 New data 23 1 ND24 New data 24 1 ND25 New data 25 1 ND26 New data 26 1 ND27 New data 27 1 ND28 New data 28 1 ND29 New data 29 1 ND30 New data 30 1 ND31 New data 31 1 NDAT2 NDAT2 FDCAN New Data 2 Register 0x9C 0x20 read-write 0x00000000 ND32 New data 0 1 ND33 New data 1 1 ND34 New data 2 1 ND35 New data 3 1 ND36 New data 4 1 ND37 New data 5 1 ND38 New data 6 1 ND39 New data 7 1 ND40 New data 8 1 ND41 New data 9 1 ND42 New data 10 1 ND43 New data 11 1 ND44 New data 12 1 ND45 New data 13 1 ND46 New data 14 1 ND47 New data 15 1 ND48 New data 16 1 ND49 New data 17 1 ND50 New data 18 1 ND51 New data 19 1 ND52 New data 20 1 ND53 New data 21 1 ND54 New data 22 1 ND55 New data 23 1 ND56 New data 24 1 ND57 New data 25 1 ND58 New data 26 1 ND59 New data 27 1 ND60 New data 28 1 ND61 New data 29 1 ND62 New data 30 1 ND63 New data 31 1 RXF0C RXF0C FDCAN Rx FIFO 0 Configuration Register 0xA0 0x20 read-write 0x00000000 F0SA Rx FIFO 0 Start Address 2 14 F0S Rx FIFO 0 Size 16 7 F0WM FIFO 0 Watermark 24 7 F0OM FIFO 0 operation mode 31 1 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0xA4 0x20 read-write 0x00000000 F0FL Rx FIFO 0 Fill Level 0 7 F0GI Rx FIFO 0 Get Index 8 6 F0PI Rx FIFO 0 Put Index 16 6 F0F Rx FIFO 0 Full 24 1 RF0L Rx FIFO 0 Message Lost 25 1 RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0xA8 0x20 read-write 0x00000000 F0AI Rx FIFO 0 Acknowledge Index 0 6 RXBC RXBC FDCAN Rx Buffer Configuration Register 0xAC 0x20 read-write 0x00000000 RBSA Rx Buffer Start Address 2 14 RXF1C RXF1C FDCAN Rx FIFO 1 Configuration Register 0xB0 0x20 read-write 0x00000000 F1SA Rx FIFO 1 Start Address 2 14 F1S Rx FIFO 1 Size 16 7 F1WM Rx FIFO 1 Watermark 24 7 F1OM FIFO 1 operation mode 31 1 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0xB4 0x20 read-write 0x00000000 F1FL Rx FIFO 1 Fill Level 0 7 F1GI Rx FIFO 1 Get Index 8 7 F1PI Rx FIFO 1 Put Index 16 7 F1F Rx FIFO 1 Full 24 1 RF1L Rx FIFO 1 Message Lost 25 1 DMS Debug Message Status 30 2 RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0xB8 0x20 read-write 0x00000000 F1AI Rx FIFO 1 Acknowledge Index 0 6 RXESC RXESC FDCAN Rx Buffer Element Size Configuration Register 0xBC 0x20 read-write 0x00000000 F0DS Rx FIFO 1 Data Field Size: 0 3 F1DS Rx FIFO 0 Data Field Size: 4 3 RBDS Rx Buffer Data Field Size: 8 3 TXBC TXBC FDCAN Tx Buffer Configuration Register 0xC0 0x20 read-write 0x00000000 TBSA Tx Buffers Start Address 2 14 NDTB Number of Dedicated Transmit Buffers 16 6 TFQS Transmit FIFO/Queue Size 24 6 TFQM Tx FIFO/Queue Mode 30 1 TXFQS TXFQS FDCAN Tx FIFO/Queue Status Register 0xC4 0x20 read-only 0x00000000 TFFL Tx FIFO Free Level 0 6 TFGI TFGI 8 5 TFQPI Tx FIFO/Queue Put Index 16 5 TFQF Tx FIFO/Queue Full 21 1 TXESC TXESC FDCAN Tx Buffer Element Size Configuration Register 0xC8 0x20 read-write 0x00000000 TBDS Tx Buffer Data Field Size: 0 3 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xCC 0x20 read-only 0x00000000 TRP Transmission Request Pending 0 32 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xD0 0x20 read-write 0x00000000 AR Add Request 0 32 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD4 0x20 read-write 0x00000000 CR Cancellation Request 0 32 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD8 0x20 read-write 0x00000000 TO Transmission Occurred. 0 32 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xDC 0x20 read-only 0x00000000 CF Cancellation Finished 0 32 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xE0 0x20 read-write 0x00000000 TIE Transmission Interrupt Enable 0 32 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE4 0x20 read-write 0x00000000 CF Cancellation Finished Interrupt Enable 0 32 TXEFC TXEFC FDCAN Tx Event FIFO Configuration Register 0xF0 0x20 read-write 0x00000000 EFSA Event FIFO Start Address 2 14 EFS Event FIFO Size 16 6 EFWM Event FIFO Watermark 24 6 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xF4 0x20 read-write 0x00000000 EFFL Event FIFO Fill Level 0 6 EFGI Event FIFO Get Index. 8 5 EFPI Event FIFO put index. 16 5 EFF Event FIFO Full. 24 1 TEFL Tx Event FIFO Element Lost. 25 1 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xF8 0x20 read-write 0x00000000 EFAI Event FIFO Acknowledge Index 0 5 TTTMC TTTMC FDCAN TT Trigger Memory Configuration Register 0x100 0x20 read-write 0x00000000 TMSA Trigger Memory Start Address 2 14 TME Trigger Memory Elements 16 7 TTRMC TTRMC FDCAN TT Reference Message Configuration Register 0x104 0x20 read-write 0x00000000 RID Reference Identifier. 0 29 XTD Extended Identifier 30 1 RMPS Reference Message Payload Select 31 1 TTOCF TTOCF FDCAN TT Operation Configuration Register 0x108 0x20 read-write 0x00000000 OM Operation Mode 0 2 GEN Gap Enable 3 1 TM Time Master 4 1 LDSDL LD of Synchronization Deviation Limit 5 3 IRTO Initial Reference Trigger Offset 8 7 EECS Enable External Clock Synchronization 15 1 AWL Application Watchdog Limit 16 8 EGTF Enable Global Time Filtering 24 1 ECC Enable Clock Calibration 25 1 EVTP Event Trigger Polarity 26 1 TTMLM TTMLM FDCAN TT Matrix Limits Register 0x10C 0x20 read-write 0x00000000 CCM Cycle Count Max 0 6 CSS Cycle Start Synchronization 6 2 TXEW Tx Enable Window 8 4 ENTT Expected Number of Tx Triggers 16 12 TURCF TURCF FDCAN TUR Configuration Register 0x110 0x20 read-write 0x00000000 NCL Numerator Configuration Low. 0 16 DC Denominator Configuration. 16 14 ELT Enable Local Time 31 1 TTOCN TTOCN FDCAN TT Operation Control Register 0x114 0x20 read-write 0x00000000 SGT Set Global time 0 1 ECS External Clock Synchronization 1 1 SWP Stop Watch Polarity 2 1 SWS Stop Watch Source. 3 2 RTIE Register Time Mark Interrupt Pulse Enable 5 1 TMC Register Time Mark Compare 6 2 TTIE Trigger Time Mark Interrupt Pulse Enable 8 1 GCS Gap Control Select 9 1 FGP Finish Gap. 10 1 TMG Time Mark Gap 11 1 NIG Next is Gap 12 1 ESCN External Synchronization Control 13 1 LCKC TT Operation Control Register Locked 15 1 TTGTP CAN_TTGTP FDCAN TT Global Time Preset Register 0x118 0x20 read-write 0x00000000 NCL Time Preset 0 16 CTP Cycle Time Target Phase 16 16 TTTMK TTTMK FDCAN TT Time Mark Register 0x11C 0x20 read-write 0x00000000 TM Time Mark 0 16 TICC Time Mark Cycle Code 16 7 LCKM TT Time Mark Register Locked 31 1 TTIR TTIR FDCAN TT Interrupt Register 0x120 0x20 read-write 0x00000000 SBC Start of Basic Cycle 0 1 SMC Start of Matrix Cycle 1 1 CSM Change of Synchronization Mode 2 1 SOG Start of Gap 3 1 RTMI Register Time Mark Interrupt. 4 1 TTMI Trigger Time Mark Event Internal 5 1 SWE Stop Watch Event 6 1 GTW Global Time Wrap 7 1 GTD Global Time Discontinuity 8 1 GTE Global Time Error 9 1 TXU Tx Count Underflow 10 1 TXO Tx Count Overflow 11 1 SE1 Scheduling Error 1 12 1 SE2 Scheduling Error 2 13 1 ELC Error Level Changed. 14 1 IWTG Initialization Watch Trigger 15 1 WT Watch Trigger 16 1 AW Application Watchdog 17 1 CER Configuration Error 18 1 TTIE TTIE FDCAN TT Interrupt Enable Register 0x124 0x20 read-write 0x00000000 SBCE Start of Basic Cycle Interrupt Enable 0 1 SMCE Start of Matrix Cycle Interrupt Enable 1 1 CSME Change of Synchronization Mode Interrupt Enable 2 1 SOGE Start of Gap Interrupt Enable 3 1 RTMIE Register Time Mark Interrupt Enable 4 1 TTMIE Trigger Time Mark Event Internal Interrupt Enable 5 1 SWEE Stop Watch Event Interrupt Enable 6 1 GTWE Global Time Wrap Interrupt Enable 7 1 GTDE Global Time Discontinuity Interrupt Enable 8 1 GTEE Global Time Error Interrupt Enable 9 1 TXUE Tx Count Underflow Interrupt Enable 10 1 TXOE Tx Count Overflow Interrupt Enable 11 1 SE1E Scheduling Error 1 Interrupt Enable 12 1 SE2E Scheduling Error 2 Interrupt Enable 13 1 ELCE Change Error Level Interrupt Enable 14 1 IWTGE Initialization Watch Trigger Interrupt Enable 15 1 WTE Watch Trigger Interrupt Enable 16 1 AWE Application Watchdog Interrupt Enable 17 1 CERE Configuration Error Interrupt Enable 18 1 TTILS TTILS FDCAN TT Interrupt Line Select Register 0x128 0x20 read-write 0x00000000 SBCL Start of Basic Cycle Interrupt Line 0 1 SMCL Start of Matrix Cycle Interrupt Line 1 1 CSML Change of Synchronization Mode Interrupt Line 2 1 SOGL Start of Gap Interrupt Line 3 1 RTMIL Register Time Mark Interrupt Line 4 1 TTMIL Trigger Time Mark Event Internal Interrupt Line 5 1 SWEL Stop Watch Event Interrupt Line 6 1 GTWL Global Time Wrap Interrupt Line 7 1 GTDL Global Time Discontinuity Interrupt Line 8 1 GTEL Global Time Error Interrupt Line 9 1 TXUL Tx Count Underflow Interrupt Line 10 1 TXOL Tx Count Overflow Interrupt Line 11 1 SE1L Scheduling Error 1 Interrupt Line 12 1 SE2L Scheduling Error 2 Interrupt Line 13 1 ELCL Change Error Level Interrupt Line 14 1 IWTGL Initialization Watch Trigger Interrupt Line 15 1 WTL Watch Trigger Interrupt Line 16 1 AWL Application Watchdog Interrupt Line 17 1 CERL Configuration Error Interrupt Line 18 1 TTOST TTOST FDCAN TT Operation Status Register 0x12C 0x20 read-write 0x00000000 EL Error Level 0 2 MS Master State. 2 2 SYS Synchronization State 4 2 QGTP Quality of Global Time Phase 6 1 QCS Quality of Clock Speed 7 1 RTO Reference Trigger Offset 8 8 WGTD Wait for Global Time Discontinuity 22 1 GFI Gap Finished Indicator. 23 1 TMP Time Master Priority 24 3 GSI Gap Started Indicator. 27 1 WFE Wait for Event 28 1 AWE Application Watchdog Event 29 1 WECS Wait for External Clock Synchronization 30 1 SPL Schedule Phase Lock 31 1 TURNA TURNA FDCAN TUR Numerator Actual Register 0x130 0x20 read-only 0x00000000 NAV Numerator Actual Value 0 18 TTLGT TTLGT FDCAN TT Local and Global Time Register 0x134 0x20 read-only 0x00000000 LT Local Time 0 16 GT Global Time 16 16 TTCTC TTCTC FDCAN TT Cycle Time and Count Register 0x138 0x20 read-only 0x00000000 CT Cycle Time 0 16 CC Cycle Count 16 6 TTCPT TTCPT FDCAN TT Capture Time Register 0x13C 0x20 read-only 0x00000000 CCV Cycle Count Value 0 6 SWV Stop Watch Value 16 16 TTCSM TTCSM FDCAN TT Cycle Sync Mark Register 0x140 0x20 read-only 0x00000000 CSM Cycle Sync Mark 0 16 TTTS TTTS FDCAN TT Trigger Select Register 0x300 0x20 read-write 0x00000000 SWTDEL Stop watch trigger input selection 0 2 EVTSEL Event trigger input selection 4 2 FDCAN2 0x4000A400 FDCAN2_IT0 FDCAN2 Interrupt 0 20 FDCAN2_IT1 FDCAN2 Interrupt 1 22 CAN_CCU CCU registers FDCAN 0x4000A800 0x0 0x400 registers CREL CREL Clock Calibration Unit Core Release Register 0x0 0x20 read-write 0x00000000 DAY Time Stamp Day 0 8 MON Time Stamp Month 8 8 YEAR Time Stamp Year 16 4 SUBSTEP Sub-step of Core Release 20 4 STEP Step of Core Release 24 4 REL Core Release 28 4 CCFG CCFG Calibration Configuration Register 0x4 0x20 read-write 0x00000000 TQBT Time Quanta per Bit Time 0 5 BCC Bypass Clock Calibration 6 1 CFL Calibration Field Length 7 1 OCPM Oscillator Clock Periods Minimum 8 8 CDIV Clock Divider 16 4 SWR Software Reset 31 1 CSTAT CSTAT Calibration Status Register 0x8 0x20 read-write 0x00000000 OCPC Oscillator Clock Period Counter 0 18 TQC Time Quanta Counter 18 11 CALS Calibration State 30 2 CWD CWD Calibration Watchdog Register 0xC 0x20 read-write 0x00000000 WDC WDC 0 16 WDV WDV 16 16 IR IR Clock Calibration Unit Interrupt Register 0x10 0x20 read-write 0x00000000 CWE Calibration Watchdog Event 0 1 CSC Calibration State Changed 1 1 IE IE Clock Calibration Unit Interrupt Enable Register 0x14 0x20 read-write 0x00000000 CWEE Calibration Watchdog Event Enable 0 1 CSCE Calibration State Changed Enable 1 1 MDIOS Management data input/output slave MDIOS 0x40009400 0x0 0x400 registers MDIOS_WKUP MDIOS wakeup 119 MDIOS MDIOS global interrupt 120 CR CR MDIOS configuration register 0x0 0x20 read-write 0x00000000 EN Peripheral enable 0 1 WRIE Register write interrupt enable 1 1 RDIE Register Read Interrupt Enable 2 1 EIE Error interrupt enable 3 1 DPC Disable Preamble Check 7 1 PORT_ADDRESS Slaves's address 8 5 WRFR WRFR MDIOS write flag register 0x4 0x20 read-only 0x00000000 WRF Write flags for MDIO registers 0 to 31 0 32 CWRFR CWRFR MDIOS clear write flag register 0x8 0x20 read-write 0x00000000 CWRF Clear the write flag 0 32 RDFR RDFR MDIOS read flag register 0xC 0x20 read-only 0x00000000 RDF Read flags for MDIO registers 0 to 31 0 32 CRDFR CRDFR MDIOS clear read flag register 0x10 0x20 read-write 0x00000000 CRDF Clear the read flag 0 32 SR SR MDIOS status register 0x14 0x20 read-only 0x00000000 PERF Preamble error flag 0 1 SERF Start error flag 1 1 TERF Turnaround error flag 2 1 CLRFR CLRFR MDIOS clear flag register 0x18 0x20 read-write 0x00000000 CPERF Clear the preamble error flag 0 1 CSERF Clear the start error flag 1 1 CTERF Clear the turnaround error flag 2 1 DINR0 DINR0 MDIOS input data register 0 0x1C 0x20 read-only 0x00000000 DIN0 Input data received from MDIO Master during write frames 0 16 DINR1 DINR1 MDIOS input data register 1 0x20 0x20 read-only 0x00000000 DIN1 Input data received from MDIO Master during write frames 0 16 DINR2 DINR2 MDIOS input data register 2 0x24 0x20 read-only 0x00000000 DIN2 Input data received from MDIO Master during write frames 0 16 DINR3 DINR3 MDIOS input data register 3 0x28 0x20 read-only 0x00000000 DIN3 Input data received from MDIO Master during write frames 0 16 DINR4 DINR4 MDIOS input data register 4 0x2C 0x20 read-only 0x00000000 DIN4 Input data received from MDIO Master during write frames 0 16 DINR5 DINR5 MDIOS input data register 5 0x30 0x20 read-only 0x00000000 DIN5 Input data received from MDIO Master during write frames 0 16 DINR6 DINR6 MDIOS input data register 6 0x34 0x20 read-only 0x00000000 DIN6 Input data received from MDIO Master during write frames 0 16 DINR7 DINR7 MDIOS input data register 7 0x38 0x20 read-only 0x00000000 DIN7 Input data received from MDIO Master during write frames 0 16 DINR8 DINR8 MDIOS input data register 8 0x3C 0x20 read-only 0x00000000 DIN8 Input data received from MDIO Master during write frames 0 16 DINR9 DINR9 MDIOS input data register 9 0x40 0x20 read-only 0x00000000 DIN9 Input data received from MDIO Master during write frames 0 16 DINR10 DINR10 MDIOS input data register 10 0x44 0x20 read-only 0x00000000 DIN10 Input data received from MDIO Master during write frames 0 16 DINR11 DINR11 MDIOS input data register 11 0x48 0x20 read-only 0x00000000 DIN11 Input data received from MDIO Master during write frames 0 16 DINR12 DINR12 MDIOS input data register 12 0x4C 0x20 read-only 0x00000000 DIN12 Input data received from MDIO Master during write frames 0 16 DINR13 DINR13 MDIOS input data register 13 0x50 0x20 read-only 0x00000000 DIN13 Input data received from MDIO Master during write frames 0 16 DINR14 DINR14 MDIOS input data register 14 0x54 0x20 read-only 0x00000000 DIN14 Input data received from MDIO Master during write frames 0 16 DINR15 DINR15 MDIOS input data register 15 0x58 0x20 read-only 0x00000000 DIN15 Input data received from MDIO Master during write frames 0 16 DINR16 DINR16 MDIOS input data register 16 0x5C 0x20 read-only 0x00000000 DIN16 Input data received from MDIO Master during write frames 0 16 DINR17 DINR17 MDIOS input data register 17 0x60 0x20 read-only 0x00000000 DIN17 Input data received from MDIO Master during write frames 0 16 DINR18 DINR18 MDIOS input data register 18 0x64 0x20 read-only 0x00000000 DIN18 Input data received from MDIO Master during write frames 0 16 DINR19 DINR19 MDIOS input data register 19 0x68 0x20 read-only 0x00000000 DIN19 Input data received from MDIO Master during write frames 0 16 DINR20 DINR20 MDIOS input data register 20 0x6C 0x20 read-only 0x00000000 DIN20 Input data received from MDIO Master during write frames 0 16 DINR21 DINR21 MDIOS input data register 21 0x70 0x20 read-only 0x00000000 DIN21 Input data received from MDIO Master during write frames 0 16 DINR22 DINR22 MDIOS input data register 22 0x74 0x20 read-only 0x00000000 DIN22 Input data received from MDIO Master during write frames 0 16 DINR23 DINR23 MDIOS input data register 23 0x78 0x20 read-only 0x00000000 DIN23 Input data received from MDIO Master during write frames 0 16 DINR24 DINR24 MDIOS input data register 24 0x7C 0x20 read-only 0x00000000 DIN24 Input data received from MDIO Master during write frames 0 16 DINR25 DINR25 MDIOS input data register 25 0x80 0x20 read-only 0x00000000 DIN25 Input data received from MDIO Master during write frames 0 16 DINR26 DINR26 MDIOS input data register 26 0x84 0x20 read-only 0x00000000 DIN26 Input data received from MDIO Master during write frames 0 16 DINR27 DINR27 MDIOS input data register 27 0x88 0x20 read-only 0x00000000 DIN27 Input data received from MDIO Master during write frames 0 16 DINR28 DINR28 MDIOS input data register 28 0x8C 0x20 read-only 0x00000000 DIN28 Input data received from MDIO Master during write frames 0 16 DINR29 DINR29 MDIOS input data register 29 0x90 0x20 read-only 0x00000000 DIN29 Input data received from MDIO Master during write frames 0 16 DINR30 DINR30 MDIOS input data register 30 0x94 0x20 read-only 0x00000000 DIN30 Input data received from MDIO Master during write frames 0 16 DINR31 DINR31 MDIOS input data register 31 0x98 0x20 read-only 0x00000000 DIN31 Input data received from MDIO Master during write frames 0 16 DOUTR0 DOUTR0 MDIOS output data register 0 0x9C 0x20 read-write 0x00000000 DOUT0 Output data sent to MDIO Master during read frames 0 16 DOUTR1 DOUTR1 MDIOS output data register 1 0xA0 0x20 read-write 0x00000000 DOUT1 Output data sent to MDIO Master during read frames 0 16 DOUTR2 DOUTR2 MDIOS output data register 2 0xA4 0x20 read-write 0x00000000 DOUT2 Output data sent to MDIO Master during read frames 0 16 DOUTR3 DOUTR3 MDIOS output data register 3 0xA8 0x20 read-write 0x00000000 DOUT3 Output data sent to MDIO Master during read frames 0 16 DOUTR4 DOUTR4 MDIOS output data register 4 0xAC 0x20 read-write 0x00000000 DOUT4 Output data sent to MDIO Master during read frames 0 16 DOUTR5 DOUTR5 MDIOS output data register 5 0xB0 0x20 read-write 0x00000000 DOUT5 Output data sent to MDIO Master during read frames 0 16 DOUTR6 DOUTR6 MDIOS output data register 6 0xB4 0x20 read-write 0x00000000 DOUT6 Output data sent to MDIO Master during read frames 0 16 DOUTR7 DOUTR7 MDIOS output data register 7 0xB8 0x20 read-write 0x00000000 DOUT7 Output data sent to MDIO Master during read frames 0 16 DOUTR8 DOUTR8 MDIOS output data register 8 0xBC 0x20 read-write 0x00000000 DOUT8 Output data sent to MDIO Master during read frames 0 16 DOUTR9 DOUTR9 MDIOS output data register 9 0xC0 0x20 read-write 0x00000000 DOUT9 Output data sent to MDIO Master during read frames 0 16 DOUTR10 DOUTR10 MDIOS output data register 10 0xC4 0x20 read-write 0x00000000 DOUT10 Output data sent to MDIO Master during read frames 0 16 DOUTR11 DOUTR11 MDIOS output data register 11 0xC8 0x20 read-write 0x00000000 DOUT11 Output data sent to MDIO Master during read frames 0 16 DOUTR12 DOUTR12 MDIOS output data register 12 0xCC 0x20 read-write 0x00000000 DOUT12 Output data sent to MDIO Master during read frames 0 16 DOUTR13 DOUTR13 MDIOS output data register 13 0xD0 0x20 read-write 0x00000000 DOUT13 Output data sent to MDIO Master during read frames 0 16 DOUTR14 DOUTR14 MDIOS output data register 14 0xD4 0x20 read-write 0x00000000 DOUT14 Output data sent to MDIO Master during read frames 0 16 DOUTR15 DOUTR15 MDIOS output data register 15 0xD8 0x20 read-write 0x00000000 DOUT15 Output data sent to MDIO Master during read frames 0 16 DOUTR16 DOUTR16 MDIOS output data register 16 0xDC 0x20 read-write 0x00000000 DOUT16 Output data sent to MDIO Master during read frames 0 16 DOUTR17 DOUTR17 MDIOS output data register 17 0xE0 0x20 read-write 0x00000000 DOUT17 Output data sent to MDIO Master during read frames 0 16 DOUTR18 DOUTR18 MDIOS output data register 18 0xE4 0x20 read-write 0x00000000 DOUT18 Output data sent to MDIO Master during read frames 0 16 DOUTR19 DOUTR19 MDIOS output data register 19 0xE8 0x20 read-write 0x00000000 DOUT19 Output data sent to MDIO Master during read frames 0 16 DOUTR20 DOUTR20 MDIOS output data register 20 0xEC 0x20 read-write 0x00000000 DOUT20 Output data sent to MDIO Master during read frames 0 16 DOUTR21 DOUTR21 MDIOS output data register 21 0xF0 0x20 read-write 0x00000000 DOUT21 Output data sent to MDIO Master during read frames 0 16 DOUTR22 DOUTR22 MDIOS output data register 22 0xF4 0x20 read-write 0x00000000 DOUT22 Output data sent to MDIO Master during read frames 0 16 DOUTR23 DOUTR23 MDIOS output data register 23 0xF8 0x20 read-write 0x00000000 DOUT23 Output data sent to MDIO Master during read frames 0 16 DOUTR24 DOUTR24 MDIOS output data register 24 0xFC 0x20 read-write 0x00000000 DOUT24 Output data sent to MDIO Master during read frames 0 16 DOUTR25 DOUTR25 MDIOS output data register 25 0x100 0x20 read-write 0x00000000 DOUT25 Output data sent to MDIO Master during read frames 0 16 DOUTR26 DOUTR26 MDIOS output data register 26 0x104 0x20 read-write 0x00000000 DOUT26 Output data sent to MDIO Master during read frames 0 16 DOUTR27 DOUTR27 MDIOS output data register 27 0x108 0x20 read-write 0x00000000 DOUT27 Output data sent to MDIO Master during read frames 0 16 DOUTR28 DOUTR28 MDIOS output data register 28 0x10C 0x20 read-write 0x00000000 DOUT28 Output data sent to MDIO Master during read frames 0 16 DOUTR29 DOUTR29 MDIOS output data register 29 0x110 0x20 read-write 0x00000000 DOUT29 Output data sent to MDIO Master during read frames 0 16 DOUTR30 DOUTR30 MDIOS output data register 30 0x114 0x20 read-write 0x00000000 DOUT30 Output data sent to MDIO Master during read frames 0 16 DOUTR31 DOUTR31 MDIOS output data register 31 0x118 0x20 read-write 0x00000000 DOUT31 Output data sent to MDIO Master during read frames 0 16 OPAMP Operational amplifiers OPAMP 0x40009000 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP Force internal reference on VP (reserved for test 1 1 VP_SEL Operational amplifier PGA mode 2 2 VM_SEL Inverting input selection 5 2 OPAHSM Operational amplifier high-speed mode 8 1 CALON Calibration mode enabled 11 1 CALSEL Calibration selection 12 2 PGA_GAIN allows to switch from AOP offset trimmed values to AOP offset 14 4 USERTRIM User trimming enable 18 1 TSTREF OPAMP calibration reference voltage output control (reserved for test) 29 1 CALOUT Operational amplifier calibration output 30 1 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP1_HSOTR OPAMP1_HSOTR OPAMP1 offset trimming register in low-power mode 0x8 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x10 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP Force internal reference on VP (reserved for test) 1 1 VM_SEL Inverting input selection 5 2 OPAHSM Operational amplifier high-speed mode 8 1 CALON Calibration mode enabled 11 1 CALSEL Calibration selection 12 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 14 4 USERTRIM User trimming enable 18 1 TSTREF OPAMP calibration reference voltage output control (reserved for test) 29 1 CALOUT Operational amplifier calibration output 30 1 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_HSOTR OPAMP2_HSOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 SWPMI Single Wire Protocol Master Interface SWPMI 0x40008800 0x0 0x400 registers SWPMI1 SWPMI global interrupt 115 CR CR SWPMI Configuration/Control register 0x0 0x20 read-write 0x00000000 RXDMA Reception DMA enable 0 1 TXDMA Transmission DMA enable 1 1 RXMODE Reception buffering mode 2 1 TXMODE Transmission buffering mode 3 1 LPBK Loopback mode enable 4 1 SWPACT Single wire protocol master interface activate 5 1 DEACT Single wire protocol master interface deactivate 10 1 SWPTEN Single wire protocol master transceiver enable 11 1 BRR BRR SWPMI Bitrate register 0x4 0x20 read-write 0x00000001 BR Bitrate prescaler 0 8 ISR ISR SWPMI Interrupt and Status register 0xC 0x20 read-only 0x000002C2 RXBFF Receive buffer full flag 0 1 TXBEF Transmit buffer empty flag 1 1 RXBERF Receive CRC error flag 2 1 RXOVRF Receive overrun error flag 3 1 TXUNRF Transmit underrun error flag 4 1 RXNE Receive data register not empty 5 1 TXE Transmit data register empty 6 1 TCF Transfer complete flag 7 1 SRF Slave resume flag 8 1 SUSP SUSPEND flag 9 1 DEACTF DEACTIVATED flag 10 1 RDYF transceiver ready flag 11 1 ICR ICR SWPMI Interrupt Flag Clear register 0x10 0x20 write-only 0x00000000 CRXBFF Clear receive buffer full flag 0 1 CTXBEF Clear transmit buffer empty flag 1 1 CRXBERF Clear receive CRC error flag 2 1 CRXOVRF Clear receive overrun error flag 3 1 CTXUNRF Clear transmit underrun error flag 4 1 CTCF Clear transfer complete flag 7 1 CSRF Clear slave resume flag 8 1 CRDYF Clear transceiver ready flag 11 1 IER IER SWPMI Interrupt Enable register 0x14 0x20 read-write 0x00000000 RXBFIE Receive buffer full interrupt enable 0 1 TXBEIE Transmit buffer empty interrupt enable 1 1 RXBERIE Receive CRC error interrupt enable 2 1 RXOVRIE Receive overrun error interrupt enable 3 1 TXUNRIE Transmit underrun error interrupt enable 4 1 RIE Receive interrupt enable 5 1 TIE Transmit interrupt enable 6 1 TCIE Transmit complete interrupt enable 7 1 SRIE Slave resume interrupt enable 8 1 RDYIE Transceiver ready interrupt enable 11 1 RFL RFL SWPMI Receive Frame Length register 0x18 0x20 read-only 0x00000000 RFL Receive frame length 0 5 TDR TDR SWPMI Transmit data register 0x1C 0x20 write-only 0x00000000 TD Transmit data 0 32 RDR RDR SWPMI Receive data register 0x20 0x20 read-only 0x00000000 RD received data 0 32 OR OR SWPMI Option register 0x24 0x20 read-write 0x00000000 SWP_TBYP SWP transceiver bypass 0 1 SWP_CLASS SWP class selection 1 1 TIM2 General purpose timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS2 Trigger selection 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT low counter value 0 32 CNT32 CNT32 32-bit counter register CNT 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 read-write 0 4294967295 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 32 0 4294967295 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 32 0 4294967295 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 TISEL TISEL TIM timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM3 General purpose timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 29 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS2 Trigger selection 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 OC%sM_3 Output compare %s mode, bit 3 16 1 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 TISEL TISEL TIM timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM4 TIM 0x40000800 TIM4 TIM4 global interrupt 30 TIM5 TIM 0x40000C00 TIM5 TIM5 global interrupt 50 TIM12 General purpose timers TIM 0x40001800 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS2 Trigger selection 20 2 SMS_3 Slave mode selection - bit 3 16 1 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 2 0x8 1-2 OC%sM_3 Output compare %s mode, bit 3 16 1 OC1M_3 Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 TISEL TISEL TIM timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TIM13 General purpose timers TIM 0x40001C00 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 1 0x0 1-1 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 1 0x0 1-1 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 1 0x0 1-1 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 1 0x0 1-1 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 1 0x0 1-1 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 1 0x0 1-1 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 1 0x0 1-1 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 1 0x0 1-1 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 1 0x0 1-1 OC%sCE Output compare %s clear enable 7 1 1 0x0 1-1 OC%sM_3 Output compare %s mode, bit 3 16 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 1 0x0 1-1 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 1 0x0 1-1 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 1 0x0 1-1 CC%sNP Capture/Compare %s output Polarity 3 1 1 0x0 1-1 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 1 0x0 1-1 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Counter value 0 16 0 65535 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 1 0x2 1-1 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 TISEL TISEL TIM timer input selection register 0x68 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TIM14 TIM 0x40002000 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers TIM6_DAC TIM6 global interrupt 54 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 UIFREMAP UIF status bit remapping 11 1 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 0 65535 UIFCPY UIF Copy 31 1 CNT16 CNT16 16-bit counter register CNT 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 read-write PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Low Auto-reload value 0 16 0 65535 TIM7 TIM 0x40001400 TIM7 TIM7 global interrupt 55 DBGMCU Microcontroller Debug Unit DBGMCU 0x5C001000 0x0 0x400 registers IDC IDC DBGMCU Identity Code Register 0x0 0x20 read-only 0x10006450 DEV_ID Device ID 0 12 REV_ID Revision 16 16 CR CR DBGMCU Configuration Register 0x4 0x20 read-write 0x00000000 DBGSLEEP_D1 Allow D1 domain debug in Sleep mode 0 1 DBGSTOP_D1 Allow D1 domain debug in Stop mode 1 1 DBGSTBY_D1 Allow D1 domain debug in Standby mode 2 1 TRACECLKEN Trace port clock enable 20 1 D1DBGCKEN D1 debug clock enable 21 1 D3DBGCKEN D3 debug clock enable 22 1 TRGOEN External trigger output enable 28 1 APB3FZ1 APB3FZ1 DBGMCU APB3 peripheral freeze register 0x34 0x20 read-write 0x00000000 WWDG1 WWDG1 stop in debug 6 1 APB1LFZ1 APB1LFZ1 DBGMCU APB1L peripheral freeze register 0x3C 0x20 read-write 0x00000000 DBG_TIM2 TIM2 stop in debug 0 1 DBG_TIM3 TIM3 stop in debug 1 1 DBG_TIM4 TIM4 stop in debug 2 1 DBG_TIM5 TIM5 stop in debug 3 1 DBG_TIM6 TIM6 stop in debug 4 1 DBG_TIM7 TIM7 stop in debug 5 1 DBG_TIM12 TIM12 stop in debug 6 1 DBG_TIM13 TIM13 stop in debug 7 1 DBG_TIM14 TIM14 stop in debug 8 1 DBG_LPTIM1 LPTIM1 stop in debug 9 1 DBG_I2C1 I2C1 SMBUS timeout stop in debug 21 1 DBG_I2C2 I2C2 SMBUS timeout stop in debug 22 1 DBG_I2C3 I2C3 SMBUS timeout stop in debug 23 1 APB2FZ1 APB2FZ1 DBGMCU APB2 peripheral freeze register 0x4C 0x20 read-write 0x00000000 DBG_TIM1 TIM1 stop in debug 0 1 DBG_TIM8 TIM8 stop in debug 1 1 DBG_TIM15 TIM15 stop in debug 16 1 DBG_TIM16 TIM16 stop in debug 17 1 DBG_TIM17 TIM17 stop in debug 18 1 DBG_HRTIM HRTIM stop in debug 29 1 APB4FZ1 APB4FZ1 DBGMCU APB4 peripheral freeze register 0x54 0x20 read-write 0x00000000 DBG_I2C4 I2C4 SMBUS timeout stop in debug 7 1 DBG_LPTIM2 LPTIM2 stop in debug 9 1 DBG_LPTIM3 LPTIM2 stop in debug 10 1 DBG_LPTIM4 LPTIM4 stop in debug 11 1 DBG_LPTIM5 LPTIM5 stop in debug 12 1 DBG_RTC RTC stop in debug 16 1 DBG_WDGLSD1 Independent watchdog for D1 stop in debug 18 1 GPIOB GPIO GPIO 0x58020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF 16 0x2 0-15 MODER%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 16 0x2 0-15 OSPEEDR%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 16 0x2 0-15 PUPDR%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24