Fields In MPU_MPU_RASR (0xE000ED90, 0x0010)

Field	Offset	Width	STM32L4x2	STM32L4P5	STM32L4R5	STM32L4R9	STM32L4x1	STM32L4x2	STM32L4x3	STM32L4x5	STM32L4x6
ENABLE	0	1	✘	✔	✘	✘	✘	✘	✘	✘	✘
SIZE	1	5	✘	✔	✘	✘	✘	✘	✘	✘	✘
SRD	8	8	✘	✔	✘	✘	✘	✘	✘	✘	✘
B	16	1	✘	✔	✘	✘	✘	✘	✘	✘	✘
C	17	1	✘	✔	✘	✘	✘	✘	✘	✘	✘
S	18	1	✘	✔	✘	✘	✘	✘	✘	✘	✘
TEX	19	3	✘	✔	✘	✘	✘	✘	✘	✘	✘
AP	24	3	✘	✔	✘	✘	✘	✘	✘	✘	✘
XN	28	1	✘	✔	✘	✘	✘	✘	✘	✘	✘