STM32L0x1 1.6 STM32L0x1 CM0+ r0p0 little true false 2 false 8 32 0x20 0x00000000 0xFFFFFFFF AES Advanced encryption standard hardware accelerator AES 0x40026000 0x0 0x400 registers AES_RNG_LPUART1 AES global interrupt RNG global interrupt and LPUART1 global interrupt through 29 CR CR control register 0x0 0x20 read-write 0x00000000 DMAOUTEN Enable DMA management of data output phase 12 1 DMAOUTEN Disabled Disable DMA Output 0 Enabled Enabled DMA Output 1 DMAINEN Enable DMA management of data input phase 11 1 DMAINEN Disabled Disable DMA Input 0 Enabled Enable DMA Input 1 ERRIE Error interrupt enable 10 1 ERRIE Disabled Disable (mask) error interrupt 0 Enabled Enable error interrupt 1 CCFIE CCF flag interrupt enable 9 1 CCFIE Disabled Disable (mask) CCF interrupt 0 Enabled Enable CCF interrupt 1 ERRC Error clear 8 1 ERRCW write Clear Clear RDERR and WRERR flags 1 CCFC Computation Complete Flag Clear 7 1 CCFCW write Clear Clear computation complete flag 1 CHMOD AES chaining mode 5 2 CHMOD ECB Electronic codebook (ECB) 0 CBC Cipher-Block Chaining (CBC) 1 CTR Counter Mode (CTR) 2 MODE AES operating mode 3 2 MODE Mode1 Mode 1: encryption 0 Mode2 Mode 2: key derivation (or key preparation for ECB/CBC decryption) 1 Mode3 Mode 3: decryption 2 Mode4 Mode 4: key derivation then single decryption 3 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DATATYPE None Word 0 HalfWord Half-word (16-bit) 1 Byte Byte (8-bit) 2 Bit Bit 3 EN AES enable 0 1 EN Disabled Disable AES 0 Enabled Enable AES 1 SR SR status register 0x4 0x20 read-only 0x00000000 WRERR Write error flag 2 1 WRERR NoError Write error not detected 0 Error Write error detected 1 RDERR Read error flag 1 1 RDERR NoError Read error not detected 0 Error Read error detected 1 CCF Computation complete flag 0 1 CCF Complete Computation complete 0 NotComplete Computation not complete 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 DIN Data Input Register. 0 32 0 4294967295 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Data output register 0 32 0 4294967295 KEYR0 KEYR0 key register 0 0x10 0x20 read-write 0x00000000 KEY Data Output Register (LSB key [31:0]) 0 32 0 4294967295 KEYR1 KEYR1 key register 1 0x14 0x20 read-write 0x00000000 KEY AES key register (key [63:32]) 0 32 0 4294967295 KEYR2 KEYR2 key register 2 0x18 0x20 read-write 0x00000000 KEY AES key register (key [95:64]) 0 32 0 4294967295 KEYR3 KEYR3 key register 3 0x1C 0x20 read-write 0x00000000 KEY AES key register (MSB key [127:96]) 0 32 0 4294967295 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI initialization vector register (LSB IVR [31:0]) 0 32 0 4294967295 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [63:32]) 0 32 0 4294967295 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization Vector Register (IVR [95:64]) 0 32 0 4294967295 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization Vector Register (MSB IVR [127:96]) 0 32 0 4294967295 DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 9 DMA1_Channel2_3 DMA1 Channel2 and 3 interrupts 10 DMA1_Channel4_7 DMA1 Channel4 to 7 interrupts 11 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 7 0x4 1-7 TEIF%s Channel %s Transfer Error flag 3 1 TEIF1 NoError No transfer error 0 Error A transfer error has occured 1 7 0x4 1-7 HTIF%s Channel %s Half Transfer Complete flag 2 1 HTIF1 NotHalf No half transfer event 0 Half A half transfer event has occured 1 7 0x4 1-7 TCIF%s Channel %s Transfer Complete flag 1 1 TCIF1 NotComplete No transfer complete event 0 Complete A transfer complete event has occured 1 7 0x4 1-7 GIF%s Channel %s Global interrupt flag 0 1 GIF1 NoEvent No transfer error, half event, complete event 0 Event A transfer error, half event or complete event has occured 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 7 0x4 1-7 CTEIF%s Channel %s Transfer Error clear 3 1 CTEIF1 Clear Clears the TEIF flag in the ISR register 1 7 0x4 1-7 CHTIF%s Channel %s Half Transfer clear 2 1 CHTIF1 Clear Clears the HTIF flag in the ISR register 1 7 0x4 1-7 CTCIF%s Channel %s Transfer Complete clear 1 1 CTCIF1 Clear Clears the TCIF flag in the ISR register 1 7 0x4 1-7 CGIF%s Channel %s Global interrupt clear 0 1 CGIF1 Clear Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register 1 7 0x14 1-7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8 CR CCR1 channel x configuration register 0x0 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 MEM2MEM Disabled Memory to memory mode disabled 0 Enabled Memory to memory mode enabled 1 PL Channel priority level 12 2 PL Low Low priority 0 Medium Medium priority 1 High High priority 2 VeryHigh Very high priority 3 PSIZE Peripheral size 8 2 PSIZE Bits8 8-bit size 0 Bits16 16-bit size 1 Bits32 32-bit size 2 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PINC Disabled Increment mode disabled 0 Enabled Increment mode enabled 1 MINC Memory increment mode 7 1 CIRC Circular mode 5 1 CIRC Disabled Circular buffer disabled 0 Enabled Circular buffer enabled 1 DIR Data transfer direction 4 1 DIR FromPeripheral Read from peripheral 0 FromMemory Read from memory 1 TEIE Transfer error interrupt enable 3 1 TEIE Disabled Transfer Error interrupt disabled 0 Enabled Transfer Error interrupt enabled 1 HTIE Half transfer interrupt enable 2 1 HTIE Disabled Half Transfer interrupt disabled 0 Enabled Half Transfer interrupt enabled 1 TCIE Transfer complete interrupt enable 1 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 EN Channel enable 0 1 EN Disabled Channel disabled 0 Enabled Channel enabled 1 NDTR CNDTR1 channel x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 0 65535 PAR CPAR1 channel x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 MAR CMAR1 channel x memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 CSELR CSELR channel selection register 0xA8 0x20 read-write 0x00000000 C1S DMA channel 1 selection 0 4 C1S NoMapping Default mapping 0 Map1 Mapping 1 1 Map2 Mapping 2 2 Map3 Mapping 3 3 Map4 Mapping 4 4 Map5 Mapping 5 5 Map6 Mapping 6 6 Map7 Mapping 7 7 Map8 Mapping 8 8 Map9 Mapping 9 9 Map10 Mapping 10 10 Map11 Mapping 11 11 Map12 Mapping 12 12 Map13 Mapping 13 13 Map14 Mapping 14 14 Map15 Mapping 15 15 C7S DMA channel 7 selection 24 4 C6S DMA channel 6 selection 20 4 C5S DMA channel 5 selection 16 4 C4S DMA channel 4 selection 12 4 C3S DMA channel 3 selection 8 4 C2S DMA channel 2 selection 4 4 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 0 4294967295 DR8 Data register - byte sized DR 0x0 0x8 read-write 0x000000FF DR8 Data register bits 0 8 0 255 DR16 Data register - half-word sized DR 0x0 0x10 read-write 0x0000FFFF DR16 Data register bits 0 16 0 65535 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 8 0 255 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_OUT Normal Bit order not affected 0 Reversed Bit reversed output 1 REV_IN Reverse input data 5 2 read-write REV_IN Normal Bit order not affected 0 Byte Bit reversal done by byte 1 HalfWord Bit reversal done by half-word 2 Word Bit reversal done by word 3 POLYSIZE Polynomial size 3 2 read-write POLYSIZE Polysize32 32-bit polynomial 0 Polysize16 16-bit polynomial 1 Polysize8 8-bit polynomial 2 Polysize7 7-bit polynomial 3 RESET RESET bit 0 1 write-only RESETW Reset Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF 1 INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 0 4294967295 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 0 4294967295 GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xEBFFFCFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 Mode Input Input mode 0 Output General purpose output mode 1 Alternate Alternate function mode 2 Analog Analog mode 3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 16 0x1 0-15 OT%s Port x configuration pin %s 0 1 OutputType PushPull Output push-pull (reset state) 0 OpenDrain Output open-drain 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 OutputSpeed LowSpeed Low speed 0 MediumSpeed Medium speed 1 HighSpeed High speed 2 VeryHighSpeed Very high speed 3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x24000000 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 Pull Floating No pull-up, pull-down 0 PullUp Pull-up 1 PullDown Pull-down 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 16 0x1 0-15 ID%s Port input data pin %s 0 1 InputData Low Input is logic low 0 High Input is logic high 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 16 0x1 0-15 OD%s Port output data pin %s 0 1 OutputData Low Set output to logic low 0 High Set output to logic high 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 16 1 BitReset Reset Resets the corresponding ODx bit 1 16 0x1 0-15 BS%s Port x set pin %s 0 1 BitSet Set Sets the corresponding ODx bit 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LockKey NotActive Port configuration lock key not active 0 Active Port configuration lock key active 1 16 0x1 0-15 LCK%s Port x lock pin %s 0 1 Lock Unlocked Port configuration not locked 0 Locked Port configuration locked 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 8 0x4 0-7 AFSEL%s Alternate function selection for port x pin y (y = 0..7) 0 4 AlternateFunction AF0 AF0 0 AF1 AF1 1 AF2 AF2 2 AF3 AF3 3 AF4 AF4 4 AF5 AF5 5 AF6 AF6 6 AF7 AF7 7 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 8 0x4 8-15 AFSEL%s Alternate function selection for port x pin y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 16 0x1 0-15 BR%s Port x reset pin %s 0 1 BitReset NoAction No action on the corresponding ODx bit 0 Reset Reset the ODx bit 1 GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF 16 0x2 0-15 MODE%s Port x configuration pin %s 0 2 OTYPER OTYPER GPIO port output type register 0x4 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 16 0x2 0-15 OSPEED%s Port x configuration pin %s 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 16 0x2 0-15 PUPD%s Port x configuration pin %s 0 2 IDR IDR GPIO port input data register 0x10 ODR ODR GPIO port output data register 0x14 BSRR BSRR GPIO port bit set/reset register 0x18 LCKR LCKR GPIO port configuration lock register 0x1C AFRL AFRL GPIO alternate function low register 0x20 AFRH AFRH GPIO alternate function high register 0x24 BRR BRR GPIO port bit reset register 0x28 GPIOC 0x50000800 GPIOD 0x50000C00 GPIOH 0x50001C00 GPIOE 0x50001000 LPTIM Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LPTIMER1 interrupt through EXTI29 13 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 DOWNR Set Counter direction change up to down 1 UP Counter direction change down to up 5 1 UPR Set Counter direction change down to up 1 ARROK Autoreload register update OK 4 1 ARROKR Set Autoreload register update OK 1 CMPOK Compare register update OK 3 1 CMPOKR Set Compare register update OK 1 EXTTRIG External trigger edge event 2 1 EXTTRIGR Set External trigger edge event 1 ARRM Autoreload match 1 1 ARRMR Set Autoreload match 1 CMPM Compare match 0 1 CMPMR Set Compare match 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 DOWNCFW Clear Direction change to down Clear Flag 1 UPCF Direction change to UP Clear Flag 5 1 UPCFW Clear Direction change to up Clear Flag 1 ARROKCF Autoreload register update OK Clear Flag 4 1 ARROKCFW Clear Autoreload register update OK Clear Flag 1 CMPOKCF Compare register update OK Clear Flag 3 1 CMPOKCFW Clear Compare register update OK Clear Flag 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 EXTTRIGCFW Clear External trigger valid edge Clear Flag 1 ARRMCF Autoreload match Clear Flag 1 1 ARRMCFW Clear Autoreload match Clear Flag 1 CMPMCF compare match Clear Flag 0 1 CMPMCFW Clear Compare match Clear Flag 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 DOWNIE Disabled DOWN interrupt disabled 0 Enabled DOWN interrupt enabled 1 UPIE Direction change to UP Interrupt Enable 5 1 UPIE Disabled UP interrupt disabled 0 Enabled UP interrupt enabled 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 ARROKIE Disabled ARROK interrupt disabled 0 Enabled ARROK interrupt enabled 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 CMPOKIE Disabled CMPOK interrupt disabled 0 Enabled CMPOK interrupt enabled 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 EXTTRIGIE Disabled EXTTRIG interrupt disabled 0 Enabled EXTTRIG interrupt enabled 1 ARRMIE Autoreload match Interrupt Enable 1 1 ARRMIE Disabled ARRM interrupt disabled 0 Enabled ARRM interrupt enabled 1 CMPMIE Compare match Interrupt Enable 0 1 CMPMIE Disabled CMPM interrupt disabled 0 Enabled CMPM interrupt enabled 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 ENC Disabled Encoder mode disabled 0 Enabled Encoder mode enabled 1 COUNTMODE counter mode enabled 23 1 COUNTMODE Internal The counter is incremented following each internal clock pulse 0 External The counter is incremented following each valid clock pulse on the LPTIM external Input1 1 PRELOAD Registers update mode 22 1 PRELOAD Immediate Registers are updated after each APB bus write access 0 EndOfPeriod Registers are updated at the end of the current LPTIM period 1 WAVPOL Waveform shape polarity 21 1 WAVPOL Positive The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 0 Negative The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 1 WAVE Waveform shape 20 1 WAVE Inactive Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 0 Active Activate the Set-once mode 1 TIMOUT Timeout enable 19 1 TIMOUT Disabled A trigger event arriving when the timer is already started will be ignored 0 Enabled A trigger event arriving when the timer is already started will reset and restart the counter 1 TRIGEN Trigger enable and polarity 17 2 TRIGEN SW Software trigger (counting start is initiated by software) 0 RisingEdge Rising edge is the active edge 1 FallingEdge Falling edge is the active edge 2 BothEdges Both edges are active edges 3 TRIGSEL Trigger selector 13 3 TRIGSEL Trig0 lptim_ext_trig0 0 Trig1 lptim_ext_trig1 1 Trig2 lptim_ext_trig2 2 Trig3 lptim_ext_trig3 3 Trig4 lptim_ext_trig4 4 Trig5 lptim_ext_trig5 5 Trig6 lptim_ext_trig6 6 Trig7 lptim_ext_trig7 7 PRESC Clock prescaler 9 3 PRESC Div1 /1 0 Div2 /2 1 Div4 /4 2 Div8 /8 3 Div16 /16 4 Div32 /32 5 Div64 /64 6 Div128 /128 7 TRGFLT Configurable digital filter for trigger 6 2 TRGFLT Immediate Any trigger active level change is considered as a valid trigger 0 Clocks2 Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger 1 Clocks4 Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger 2 Clocks8 Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger 3 CKFLT Configurable digital filter for external clock 3 2 CKFLT Immediate Any external clock signal level change is considered as a valid transition 0 Clocks2 External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 1 Clocks4 External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition 2 Clocks8 External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition 3 CKPOL Clock Polarity 1 2 CKPOL RisingEdge The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active. 0 FallingEdge The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active. 1 BothEdges Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active. 2 CKSEL Clock selector 0 1 CKSEL Internal LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 0 External LPTIM is clocked by an external clock source through the LPTIM external Input1 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 CNTSTRT Timer start in continuous mode 2 1 CNTSTRTW write Start Timer start in Continuous mode 1 SNGSTRT LPTIM start in single mode 1 1 SNGSTRTW write Start LPTIM start in Single mode 1 ENABLE LPTIM Enable 0 1 ENABLE Disabled LPTIM is disabled 0 Enabled LPTIM is enabled 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value. 0 16 0 65535 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value. 0 16 0 65535 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value. 0 16 0 65535 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC RTC global interrupt 2 TR TR RTC time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 DR DR RTC date register 0x4 0x20 read-write 0x00000000 YT Year tens in BCD format 20 4 0 15 YU Year units in BCD format 16 4 0 15 WDU Week day units 13 3 1 7 MT Month tens in BCD format 12 1 MT Zero Month tens is 0 0 One Month tens is 1 1 MU Month units in BCD format 8 4 0 15 DT Date tens in BCD format 4 2 0 3 DU Date units in BCD format 0 4 0 15 CR CR RTC control register 0x8 0x20 0x00000000 COE Calibration output enable 23 1 read-write COE Disabled Calibration output disabled 0 Enabled Calibration output enabled 1 OSEL Output selection 21 2 read-write OSEL Disabled Output disabled 0 AlarmA Alarm A output enabled 1 AlarmB Alarm B output enabled 2 Wakeup Wakeup output enabled 3 POL Output polarity 20 1 read-write POL High The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 0 Low The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1 COSEL Calibration output selection 19 1 read-write COSEL CalFreq_512Hz Calibration output is 512 Hz (with default prescaler setting) 0 CalFreq_1Hz Calibration output is 1 Hz (with default prescaler setting) 1 BKP Backup 18 1 read-write BKP DST_Not_Changed Daylight Saving Time change has not been performed 0 DST_Changed Daylight Saving Time change has been performed 1 SUB1H Subtract 1 hour (winter time change) 17 1 write-only SUB1HW Sub1 Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode 1 ADD1H Add 1 hour (summer time change) 16 1 write-only ADD1HW Add1 Adds 1 hour to the current time. This can be used for summer time change outside initialization mode 1 TSIE Time-stamp interrupt enable 15 1 read-write TSIE Disabled Time-stamp Interrupt disabled 0 Enabled Time-stamp Interrupt enabled 1 WUTIE Wakeup timer interrupt enable 14 1 read-write WUTIE Disabled Wakeup timer interrupt disabled 0 Enabled Wakeup timer interrupt enabled 1 2 0x1 A,B ALR%sIE Alarm %s interrupt enable 12 1 read-write ALRAIE Disabled Alarm Interrupt disabled 0 Enabled Alarm Interrupt enabled 1 TSE timestamp enable 11 1 read-write TSE Disabled Timestamp disabled 0 Enabled Timestamp enabled 1 WUTE Wakeup timer enable 10 1 read-write WUTE Disabled Wakeup timer disabled 0 Enabled Wakeup timer enabled 1 2 0x1 A,B ALR%sE Alarm %s enable 8 1 read-write ALRAE Disabled Alarm disabled 0 Enabled Alarm enabled 1 FMT Hour format 6 1 read-write FMT Twenty_Four_Hour 24 hour/day format 0 AM_PM AM/PM hour format 1 BYPSHAD Bypass the shadow registers 5 1 read-write BYPSHAD ShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles 0 BypassShadowReg Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters 1 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) 4 1 read-write REFCKON Disabled RTC_REFIN detection disabled 0 Enabled RTC_REFIN detection enabled 1 TSEDGE Time-stamp event active edge 3 1 read-write TSEDGE RisingEdge RTC_TS input rising edge generates a time-stamp event 0 FallingEdge RTC_TS input falling edge generates a time-stamp event 1 WUCKSEL Wakeup clock selection 0 3 read-write WUCKSEL Div16 RTC/16 clock is selected 0 Div8 RTC/8 clock is selected 1 Div4 RTC/4 clock is selected 2 Div2 RTC/2 clock is selected 3 ClockSpare ck_spre (usually 1 Hz) clock is selected 4 ClockSpareWithOffset ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value 6 ISR ISR RTC initialization and status register 0xC 0x20 0x00000000 TAMP1F RTC_TAMP1 detection flag 13 1 read-write zeroToClear TAMP1FR read Tampered This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input 1 TAMP1FW write Clear Flag cleared by software writing 0 0 TAMP2F RTC_TAMP2 detection flag 14 1 read-write zeroToClear read write TSOVF Time-stamp overflow flag 12 1 read-write zeroToClear TSOVFR read Overflow This flag is set by hardware when a time-stamp event occurs while TSF is already set 1 TSOVFW write Clear This flag is cleared by software by writing 0 0 TSF Time-stamp flag 11 1 read-write zeroToClear TSFR read TimestampEvent This flag is set by hardware when a time-stamp event occurs 1 TSFW write Clear This flag is cleared by software by writing 0 0 WUTF Wakeup timer flag 10 1 read-write zeroToClear WUTFR read Zero This flag is set by hardware when the wakeup auto-reload counter reaches 0 1 WUTFW write Clear This flag is cleared by software by writing 0 0 2 0x1 A,B ALR%sF Alarm %s flag 8 1 read-write zeroToClear ALRAFR read Match This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR) 1 ALRAFW write Clear This flag is cleared by software by writing 0 0 INIT Initialization mode 7 1 read-write INIT FreeRunningMode Free running mode 0 InitMode Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. 1 INITF Initialization flag 6 1 read-only INITFR NotAllowed Calendar registers update is not allowed 0 Allowed Calendar registers update is allowed 1 RSF Registers synchronization flag 5 1 read-write zeroToClear RSFR read NotSynced Calendar shadow registers not yet synchronized 0 Synced Calendar shadow registers synchronized 1 RSFW write Clear This flag is cleared by software by writing 0 0 INITS Initialization status flag 4 1 read-only INITSR NotInitalized Calendar has not been initialized 0 Initalized Calendar has been initialized 1 SHPF Shift operation pending 3 1 read-only SHPFR NoShiftPending No shift operation is pending 0 ShiftPending A shift operation is pending 1 WUTWF Wakeup timer write flag 2 1 read-only WUTWFR UpdateNotAllowed Wakeup timer configuration update not allowed 0 UpdateAllowed Wakeup timer configuration update allowed 1 2 0x1 A,B ALR%sWF Alarm %s write flag 0 1 read-only ALRAWFR UpdateNotAllowed Alarm update not allowed 0 UpdateAllowed Alarm update allowed 1 RECALPF Recalibration pending flag 16 1 RECALPFR read Pending The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 1 TAMP3F RTC_TAMP3 detection flag 15 1 zeroToClear read write PRER PRER RTC prescaler register 0x10 0x20 read-write 0x00000000 PREDIV_A Asynchronous prescaler factor 16 7 0 127 PREDIV_S Synchronous prescaler factor 0 16 0 32767 WUTR WUTR RTC wakeup timer register 0x14 0x20 read-write 0x00000000 WUT Wakeup auto-reload value bits 0 16 0 65535 2 0x4 A,B ALRM%sR ALRM%sR Alarm %s register 0x1C 0x20 read-write 0x00000000 MSK1 Alarm seconds mask 7 1 MSK1 Mask Alarm set if the date/day match 0 NotMask Date/day don’t care in Alarm comparison 1 MSK4 Alarm date mask 31 1 WDSEL Week day selection 30 1 WDSEL DateUnits DU[3:0] represents the date units 0 WeekDay DU[3:0] represents the week day. DT[1:0] is don’t care. 1 DT Date tens in BCD format 28 2 0 3 DU Date units or day in BCD format 24 4 0 15 MSK3 Alarm hours mask 23 1 PM AM/PM notation 22 1 PM AM AM or 24-hour format 0 PM PM 1 HT Hour tens in BCD format 20 2 0 3 HU Hour units in BCD format 16 4 0 15 MSK2 Alarm minutes mask 15 1 MNT Minute tens in BCD format 12 3 0 7 MNU Minute units in BCD format 8 4 0 15 ST Second tens in BCD format 4 3 0 7 SU Second units in BCD format 0 4 0 15 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 0 255 SSR SSR RTC sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 0 65535 SHIFTR SHIFTR RTC shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SW Add1 Add one second to the clock/calendar 1 SUBFS Subtract a fraction of a second 0 15 0 32767 TSTR TSTR RTC timestamp time register 0x30 TSDR TSDR RTC timestamp date register 0x34 TSSSR TSSSR RTC time-stamp sub second register 0x38 CALR CALR RTC calibration register 0x3C 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALP NoChange No RTCCLK pulses are added 0 IncreaseFreq One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8 Eight_Second When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16 Sixteen_Second When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 1 CALM Calibration minus 0 9 0 511 TAMPCR TAMPCR RTC tamper configuration register 0x40 0x20 read-write 0x00000000 TAMP1MF Tamper 1 mask flag 18 1 TAMP1MF NotMasked Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection 0 Masked Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. 1 TAMP2MF Tamper 2 mask flag 21 1 TAMP1NOERASE Tamper 1 no erase 17 1 TAMP1NOERASE Erase Tamper x event erases the backup registers 0 NoErase Tamper x event does not erase the backup registers 1 TAMP2NOERASE Tamper 2 no erase 20 1 TAMP1IE Tamper 1 interrupt enable 16 1 TAMP1IE Disabled Tamper x interrupt is disabled if TAMPIE = 0 0 Enabled Tamper x interrupt enabled 1 TAMP2IE Tamper 2 interrupt enable 19 1 TAMPPUDIS RTC_TAMPx pull-up disable 15 1 TAMPPUDIS Enabled Precharge RTC_TAMPx pins before sampling (enable internal pull-up) 0 Disabled Disable precharge of RTC_TAMPx pins 1 TAMPPRCH RTC_TAMPx precharge duration 13 2 TAMPPRCH Cycles1 1 RTCCLK cycle 0 Cycles2 2 RTCCLK cycles 1 Cycles4 4 RTCCLK cycles 2 Cycles8 8 RTCCLK cycles 3 TAMPFLT RTC_TAMPx filter count 11 2 TAMPFLT Immediate Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) 0 Samples2 Tamper event is activated after 2 consecutive samples at the active level 1 Samples4 Tamper event is activated after 4 consecutive samples at the active level 2 Samples8 Tamper event is activated after 8 consecutive samples at the active level 3 TAMPFREQ Tamper sampling frequency 8 3 TAMPFREQ Div32768 RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0 Div16384 RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 1 Div8192 RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 2 Div4096 RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 3 Div2048 RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 4 Div1024 RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 5 Div512 RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 6 Div256 RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) 7 TAMPTS Activate timestamp on tamper detection event 7 1 TAMPTS NoSave Tamper detection event does not cause a timestamp to be saved 0 Save Save timestamp on tamper detection event 1 TAMP1TRG Active level for RTC_TAMP1 input 1 1 TAMP1TRG RisingEdge If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event. 0 FallingEdge If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event 1 TAMP2TRG Active level for RTC_TAMP2 input 4 1 TAMP1E RTC_TAMP1 input detection enable 0 1 TAMP1E Disabled RTC_TAMPx input detection disabled 0 Enabled RTC_TAMPx input detection enabled 1 TAMP2E RTC_TAMP2 input detection enable 3 1 TAMPIE Tamper interrupt enable 2 1 TAMPIE Disabled Tamper interrupt disabled 0 Enabled Tamper interrupt enabled 1 TAMP3MF Tamper 3 mask flag 24 1 TAMP3NOERASE Tamper 3 no erase 23 1 TAMP3IE Tamper 3 interrupt enable 22 1 TAMP3TRG Active level for RTC_TAMP3 input 6 1 TAMP3E RTC_TAMP3 detection enable 5 1 2 0x4 A,B ALRM%sSSR ALRM%sSSR Alarm %s sub-second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 0 15 SS Sub seconds value 0 15 0 32767 OR OR option register 0x4C 0x20 read-write 0x00000000 RTC_OUT_RMP RTC_ALARM on PC13 output type 1 1 0 1 RTC_ALARM_TYPE RTC_ALARM on PC13 output type 0 1 0 1 5 0x4 0-4 BKP%sR BKP%sR RTC backup registers 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 0 4294967295 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 27 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 EOBIE End of Block interrupt enable 27 1 EOBIE Disabled Interrupt is inhibited 0 Enabled A USART interrupt is generated when the EOBF flag is set in the ISR register 1 RTOIE Receiver timeout interrupt enable 26 1 RTOIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated when the RTOF bit is set in the ISR register 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable de-assertion time 16 5 0 31 OVER8 Oversampling mode 15 1 OVER8 Oversampling16 Oversampling by 16 0 Oversampling8 Oversampling by 8 1 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 RTOEN Receiver timeout enable 23 1 RTOEN Disabled Receiver timeout feature disabled 0 Enabled Receiver timeout feature enabled 1 ABRMOD Auto baud rate mode 21 2 ABRMOD Start Measurement of the start bit is used to detect the baud rate 0 Edge Falling edge to falling edge measurement 1 Frame7F 0x7F frame detection 2 Frame55 0x55 frame detection 3 ABREN Auto baud rate enable 20 1 ABREN Disabled Auto baud rate detection is disabled 0 Enabled Auto baud rate detection is enabled 1 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 LINEN LIN mode enable 14 1 LINEN Disabled LIN mode disabled 0 Enabled LIN mode enabled 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 CPOL Clock polarity 10 1 CPOL Low Steady low value on CK pin outside transmission window 0 High Steady high value on CK pin outside transmission window 1 CPHA Clock phase 9 1 CPHA First The first clock transition is the first data capture edge 0 Second The second clock transition is the first data capture edge 1 LBCL Last bit clock pulse 8 1 LBCL NotOutput The clock pulse of the last data bit is not output to the CK pin 0 Output The clock pulse of the last data bit is output to the CK pin 1 LBDIE LIN break detection interrupt enable 6 1 LBDIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever LBDF=1 in the ISR register 1 LBDL LIN break detection length 5 1 LBDL Bit10 10-bit break detection 0 Bit11 11-bit break detection 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 SCARCNT Smartcard auto-retry count 17 3 0 7 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 ONEBIT One sample bit method enable 11 1 ONEBIT Sample3 Three sample bit method 0 Sample1 One sample bit method 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 SCEN Smartcard mode enable 5 1 SCEN Disabled Smartcard Mode disabled 0 Enabled Smartcard Mode enabled 1 NACK Smartcard NACK enable 4 1 NACK Disabled NACK transmission in case of parity error is disabled 0 Enabled NACK transmission during parity error is enabled 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 IRLP Ir low-power 2 1 IRLP Normal Normal mode 0 LowPower Low-power mode 1 IREN Ir mode enable 1 1 IREN Disabled IrDA disabled 0 Enabled IrDA enabled 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR DIV_Mantissa 0 16 0 65535 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 0 255 PSC Prescaler value 0 8 0 255 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 0 255 RTO Receiver timeout value 0 24 0 16777215 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 TXFRQ Discard Set the TXE flags. This allows to discard the transmit data 1 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ABRRQ Auto baud rate request 0 1 ABRRQ Request resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 EOBF NotReached End of Block not reached 0 Reached End of Block (number of characters) reached 1 RTOF RTOF 11 1 RTOF NotReached Timeout value not reached 0 Reached Timeout value reached without any data reception 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 LBDF LBDF 8 1 LBDF NotDetected LIN break not detected 0 Detected LIN break detected 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 EOBCF End of block clear flag 12 1 oneToClear EOBCF Clear Clears the EOBF flag in the ISR register 1 RTOCF Receiver timeout clear flag 11 1 oneToClear RTOCF Clear Clears the RTOF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 LBDCF LIN break detection clear flag 8 1 oneToClear LBDCF Clear Clears the LBDF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 USART2 0x40004400 USART2 USART2 global interrupt 28 USART4 0x40004C00 USART4_USART5 USART4/USART5 global interrupt 14 USART5 0x40005000 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x10 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 KEY Unlock Enable access to PR, RLR and WINR registers 21845 Feed Feed watchdog with RLR register value 43690 Start Start the watchdog 52428 PR PR Prescaler register 0x4 0x10 read-write 0x00000000 PR Prescaler divider 0 3 PR DivideBy4 Divider /4 0 DivideBy8 Divider /8 1 DivideBy16 Divider /16 2 DivideBy32 Divider /32 3 DivideBy64 Divider /64 4 DivideBy128 Divider /128 5 DivideBy256 Divider /256 true RLR RLR Reload register 0x8 0x10 read-write 0x00000FFF RL Watchdog counter reload value 0 12 0 4095 SR SR Status register 0xC 0x10 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x10 read-write 0x00000FFF WIN Watchdog counter window value 0 12 0 4095 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x10 read-write 0x0000007F WDGA Activation bit 7 1 WDGA Disabled Watchdog disabled 0 Enabled Watchdog enabled 1 T 7-bit counter (MSB to LSB) 0 7 0 127 CFR CFR Configuration register 0x4 0x10 read-write 0x0000007F EWI Early wakeup interrupt 9 1 EWIW write Enable interrupt occurs whenever the counter reaches the value 0x40 1 WDGTB Timer base 7 2 WDGTB Div1 Counter clock (PCLK1 div 4096) div 1 0 Div2 Counter clock (PCLK1 div 4096) div 2 1 Div4 Counter clock (PCLK1 div 4096) div 4 2 Div8 Counter clock (PCLK1 div 4096) div 8 3 W 7-bit window value 0 7 0 127 SR SR Status register 0x8 0x10 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 zeroToClear EWIFR read Finished The EWI Interrupt Service Routine has been serviced 0 Pending The EWI Interrupt Service Routine has been triggered 1 EWIFW write Finished The EWI Interrupt Service Routine has been serviced 0 FW Firewall Firewall 0x40011C00 0x0 0x400 registers CSSA CSSA Code segment start address 0x0 0x20 read-write 0x00000000 ADD code segment start address 8 16 0 65535 CSL CSL Code segment length 0x4 0x20 read-write 0x00000000 LENG code segment length 8 14 0 16383 NVDSSA NVDSSA Non-volatile data segment start address 0x8 0x20 read-write 0x00000000 ADD Non-volatile data segment start address 8 16 0 65535 NVDSL NVDSL Non-volatile data segment length 0xC 0x20 read-write 0x00000000 LENG Non-volatile data segment length 8 14 0 16383 VDSSA VDSSA Volatile data segment start address 0x10 0x20 read-write 0x00000000 ADD Volatile data segment start address 6 10 0 1023 VDSL VDSL Volatile data segment length 0x14 0x20 read-write 0x00000000 LENG Non-volatile data segment length 6 10 0 1023 CR CR Configuration register 0x20 0x20 read-write 0x00000000 VDE Volatile data execution 2 1 VDER read NotExecutable Volatile data segment cannot be executed if VDS = 0 0 Executable Volatile data segment is declared executable whatever VDS bit value 1 VDEW write Reset Resets volatile data execution bit 0 VDS Volatile data shared 1 1 VDSR read NotShared Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed 0 Shared Volatile data segment is shared with non protected application code 1 VDSW write Reset Resets volatile data shared bit 0 FPA Firewall pre alarm 0 1 FPAW write PreArmReset Any code executed outside the protected segment when the Firewall is opened will generate a system reset 0 PreArmSet Any code executed outside the protected segment will close the Firewall 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 4 CR CR Clock control register 0x0 0x20 0x00000300 PLLRDY PLL clock ready flag 25 1 read-only PLLRDYR Unlocked PLL unlocked 0 Locked PLL locked 1 HSI16ON 16 MHz high-speed internal clock enable 0 1 read-write HSI16ON Disabled Clock disabled 0 Enabled Clock enabled 1 PLLON PLL enable bit 24 1 read-write RTCPRE TC/LCD prescaler 20 2 read-write RTCPRE Div2 HSE divided by 2 0 Div4 HSE divided by 4 1 Div8 HSE divided by 8 2 Div16 HSE divided by 16 3 CSSHSEON Clock security system on HSE enable bit 19 1 read-write HSEBYP HSE clock bypass bit 18 1 read-write HSEBYP NotBypassed HSE oscillator not bypassed 0 Bypassed HSE oscillator bypassed 1 MSIRDY MSI clock ready flag 9 1 read-only MSIRDYR NotReady Oscillator is not stable 0 Ready Oscillator is stable 1 HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable bit 16 1 read-write MSION MSI clock enable bit 8 1 read-write HSI16DIVF HSI16DIVF 4 1 read-only HSI16DIVFR NotDivided 16 MHz HSI clock not divided 0 Div4 16 MHz HSI clock divided by 4 1 HSI16DIVEN HSI16DIVEN 3 1 read-write HSI16DIVEN NotDivided no 16 MHz HSI division requested 0 Div4 16 MHz HSI division by 4 requested 1 HSI16RDYF Internal high-speed clock ready flag 2 1 read-write HSI16RDYFR read NotReady HSI 16 MHz oscillator not ready 0 Ready HSI 16 MHz oscillator ready 1 HSI16KERON High-speed internal clock enable bit for some IP kernels 1 1 read-only HSI16OUTEN 16 MHz high-speed internal clock output enable 5 1 read-write HSI16OUTEN Disabled HSI output clock disabled 0 Enabled HSI output clock enabled 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x0000B000 MSITRIM MSI clock trimming 24 8 read-write 0 255 MSICAL MSI clock calibration 16 8 read-only 0 255 MSIRANGE MSI clock ranges 13 3 read-write MSIRANGE Range0 range 0 around 65.536 kHz 0 Range1 range 1 around 131.072 kHz 1 Range2 range 2 around 262.144 kHz 2 Range3 range 3 around 524.288 kHz 3 Range4 range 4 around 1.048 MHz 4 Range5 range 5 around 2.097 MHz (reset value) 5 Range6 range 6 around 4.194 MHz 6 Range7 not allowed 7 HSI16TRIM High speed internal clock trimming 8 5 read-write 0 31 HSI16CAL nternal high speed clock calibration 0 8 read-only 0 255 CFGR CFGR Clock configuration register 0xC 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOPRE Div1 No division 0 Div2 Division by 2 1 Div4 Division by 4 2 Div8 Division by 8 3 Div16 Division by 16 4 MCOSEL Microcontroller clock output selection 24 3 read-write MCOSEL NoClock No clock 0 SYSCLK SYSCLK clock selected 1 HSI16 HSI oscillator clock selected 2 MSI MSI oscillator clock selected 3 HSE HSE oscillator clock selected 4 PLL PLL clock selected 5 LSI LSI oscillator clock selected 6 LSE LSE oscillator clock selected 7 PLLDIV PLL output division 22 2 read-write PLLDIV Div2 PLLVCO / 2 1 Div3 PLLVCO / 3 2 Div4 PLLVCO / 4 3 PLLMUL PLL multiplication factor 18 4 read-write PLLMUL Mul3 PLL clock entry x 3 0 Mul4 PLL clock entry x 4 1 Mul6 PLL clock entry x 6 2 Mul8 PLL clock entry x 8 3 Mul12 PLL clock entry x 12 4 Mul16 PLL clock entry x 16 5 Mul24 PLL clock entry x 24 6 Mul32 PLL clock entry x 32 7 Mul48 PLL clock entry x 48 8 PLLSRC PLL entry clock source 16 1 read-write PLLSRC HSI16 HSI selected as PLL input clock 0 HSE HSE selected as PLL input clock 1 STOPWUCK Wake-up from stop clock selection 15 1 read-write STOPWUCK MSI Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock 0 HSI16 Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) 1 PPRE1 APB low-speed prescaler (APB1) 8 3 read-write PPRE1 Div2 HCLK divided by 2 4 Div4 HCLK divided by 4 5 Div8 HCLK divided by 8 6 Div16 HCLK divided by 16 7 Div1 HCLK not divided true PPRE2 APB high-speed prescaler (APB2) 11 3 read-write HPRE AHB prescaler 4 4 read-write HPRE Div2 system clock divided by 2 8 Div4 system clock divided by 4 9 Div8 system clock divided by 8 10 Div16 system clock divided by 16 11 Div64 system clock divided by 64 12 Div128 system clock divided by 128 13 Div256 system clock divided by 256 14 Div512 system clock divided by 512 15 Div1 system clock not divided true SWS System clock switch status 2 2 read-only SWS MSI MSI oscillator used as system clock 0 HSI16 HSI oscillator used as system clock 1 HSE HSE oscillator used as system clock 2 PLL PLL used as system clock 3 SW System clock switch 0 2 read-write SW MSI MSI oscillator used as system clock 0 HSI16 HSI oscillator used as system clock 1 HSE HSE oscillator used as system clock 2 PLL PLL used as system clock 3 CIER CIER Clock interrupt enable register 0x10 0x20 read-write 0x00000000 CSSLSE LSE CSS interrupt flag 7 1 CSSLSE Disabled LSE CSS interrupt disabled 0 Enabled LSE CSS interrupt enabled 1 LSIRDYIE LSI ready interrupt flag 0 1 LSIRDYIE Disabled Ready interrupt disabled 0 Enabled Ready interrupt enabled 1 MSIRDYIE MSI ready interrupt flag 5 1 PLLRDYIE PLL ready interrupt flag 4 1 HSERDYIE HSE ready interrupt flag 3 1 HSI16RDYIE HSI16 ready interrupt flag 2 1 LSERDYIE LSE ready interrupt flag 1 1 CIFR CIFR Clock interrupt flag register 0x14 0x20 read-only 0x00000000 CSSHSEF Clock Security System Interrupt flag 8 1 CSSHSEF NoClock No clock security interrupt caused by HSE clock failure 0 Clock Clock security interrupt caused by HSE clock failure 1 CSSLSEF LSE Clock Security System Interrupt flag 7 1 CSSLSEF NoFailure No failure detected on LSE clock failure 0 Failure Failure detected on LSE clock failure 1 LSIRDYF LSI ready interrupt flag 0 1 LSIRDYFR NotInterrupted No clock ready interrupt 0 Interrupted Clock ready interrupt 1 MSIRDYF MSI ready interrupt flag 5 1 PLLRDYF PLL ready interrupt flag 4 1 HSERDYF HSE ready interrupt flag 3 1 HSI16RDYF HSI16 ready interrupt flag 2 1 LSERDYF LSE ready interrupt flag 1 1 CICR CICR Clock interrupt clear register 0x18 0x20 write-only 0x00000000 LSIRDYC LSI ready Interrupt clear 0 1 LSIRDYCW Clear Clear interrupt flag 1 CSSHSEC Clock Security System Interrupt clear 8 1 CSSLSEC LSE Clock Security System Interrupt clear 7 1 MSIRDYC MSI ready Interrupt clear 5 1 PLLRDYC PLL ready Interrupt clear 4 1 HSERDYC HSE ready Interrupt clear 3 1 HSI16RDYC HSI16 ready Interrupt clear 2 1 LSERDYC LSE ready Interrupt clear 1 1 IOPRSTR IOPRSTR GPIO reset register 0x1C 0x20 read-write 0x00000000 IOPARST I/O port A reset 0 1 IOPARST Reset Reset I/O port 1 IOPHRST I/O port H reset 7 1 IOPDRST I/O port D reset 3 1 IOPCRST I/O port A reset 2 1 IOPBRST I/O port B reset 1 1 IOPERST I/O port E reset 4 1 AHBRSTR AHBRSTR AHB peripheral reset register 0x20 0x20 read-write 0x00000000 DMARST DMA reset 0 1 DMARSTW write Reset Reset the module 1 CRYPRST Crypto module reset 24 1 CRCRST Test integration module reset 12 1 MIFRST Memory interface reset 8 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x24 0x20 read-write 0x00000000 SYSCFGRST System configuration controller reset 0 1 SYSCFGRSTW write Reset Reset the module 1 DBGRST DBG reset 22 1 USART1RST USART1 reset 14 1 SPI1RST SPI 1 reset 12 1 ADCRST ADC interface reset 9 1 TIM22RST TIM22 timer reset 5 1 TIM21RST TIM21 timer reset 2 1 APB1RSTR APB1RSTR APB1 peripheral reset register 0x28 0x20 read-write 0x00000000 TIM2RST Timer 2 reset 0 1 TIM2RSTW write Reset Reset the module 1 LPTIM1RST Low power timer reset 31 1 PWRRST Power interface reset 28 1 I2C2RST I2C2 reset 22 1 I2C1RST I2C1 reset 21 1 LPUART1RST LPUART1 reset 18 1 USART2RST USART2 reset 17 1 SPI2RST SPI2 reset 14 1 WWDGRST Window watchdog reset 11 1 TIM6RST Timer 6 reset 4 1 TIM3RST Timer 3 reset 1 1 TIM7RST Timer 7 reset 5 1 USART4RST USART4 reset 19 1 USART5RST USART5 reset 20 1 CRCRST CRC reset 27 1 I2C3RST I2C3 reset 30 1 IOPENR IOPENR GPIO clock enable register 0x2C 0x20 read-write 0x00000000 IOPAEN IO port A clock enable bit 0 1 IOPAEN Disabled Port clock disabled 0 Enabled Port clock enabled 1 IOPHEN I/O port H clock enable bit 7 1 IOPDEN I/O port D clock enable bit 3 1 IOPCEN IO port A clock enable bit 2 1 IOPBEN IO port B clock enable bit 1 1 IOPEEN IO port E clock enable bit 4 1 AHBENR AHBENR AHB peripheral clock enable register 0x30 0x20 read-write 0x00000100 DMAEN DMA clock enable bit 0 1 DMAEN Disabled Clock disabled 0 Enabled Clock enabled 1 CRYPEN Crypto clock enable bit 24 1 CRCEN CRC clock enable bit 12 1 MIFEN NVM interface clock enable bit 8 1 APB2ENR APB2ENR APB2 peripheral clock enable register 0x34 0x20 read-write 0x00000000 SYSCFGEN System configuration controller clock enable bit 0 1 SYSCFGEN Disabled Clock disabled 0 Enabled Clock enabled 1 DBGEN DBG clock enable bit 22 1 USART1EN USART1 clock enable bit 14 1 SPI1EN SPI1 clock enable bit 12 1 ADCEN ADC clock enable bit 9 1 FWEN Firewall clock enable bit 7 1 TIM22EN TIM22 timer clock enable bit 5 1 TIM21EN TIM21 timer clock enable bit 2 1 APB1ENR APB1ENR APB1 peripheral clock enable register 0x38 0x20 read-write 0x00000000 TIM2EN Timer2 clock enable bit 0 1 TIM2EN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1EN Low power timer clock enable bit 31 1 PWREN Power interface clock enable bit 28 1 I2C2EN I2C2 clock enable bit 22 1 I2C1EN I2C1 clock enable bit 21 1 LPUART1EN LPUART1 clock enable bit 18 1 USART2EN UART2 clock enable bit 17 1 SPI2EN SPI2 clock enable bit 14 1 WWDGEN Window watchdog clock enable bit 11 1 TIM6EN Timer 6 clock enable bit 4 1 TIM3EN Timer 3 clock enbale bit 1 1 TIM7EN Timer 7 clock enable bit 5 1 USART4EN USART4 clock enable bit 19 1 USART5EN USART5 clock enable bit 20 1 I2C3EN I2C3 clock enable bit 30 1 IOPSMEN IOPSMEN GPIO clock enable in sleep mode register 0x3C 0x20 read-write 0x0000008F IOPASMEN Port A clock enable during Sleep mode bit 0 1 IOPASMEN Disabled Port x clock is disabled in Sleep mode 0 Enabled Port x clock is enabled in Sleep mode (if enabled by IOPHEN) 1 IOPHSMEN Port H clock enable during Sleep mode bit 7 1 IOPDSMEN Port D clock enable during Sleep mode bit 3 1 IOPCSMEN Port C clock enable during Sleep mode bit 2 1 IOPBSMEN Port B clock enable during Sleep mode bit 1 1 IOPESMEN Port E clock enable during Sleep mode bit 4 1 AHBSMENR AHBSMENR AHB peripheral clock enable in sleep mode register 0x40 0x20 read-write 0x01111301 CRYPSMEN Crypto clock enable during sleep mode bit 24 1 CRYPSMEN Disabled Crypto clock disabled in Sleep mode 0 Enabled Crypto clock enabled in Sleep mode 1 CRCSMEN CRC clock enable during sleep mode bit 12 1 CRCSMEN Disabled Test integration module clock disabled in Sleep mode 0 Enabled Test integration module clock enabled in Sleep mode (if enabled by CRCEN) 1 SRAMSMEN SRAM interface clock enable during sleep mode bit 9 1 SRAMSMEN Disabled NVM interface clock disabled in Sleep mode 0 Enabled NVM interface clock enabled in Sleep mode 1 MIFSMEN NVM interface clock enable during sleep mode bit 8 1 MIFSMEN Disabled NVM interface clock disabled in Sleep mode 0 Enabled NVM interface clock enabled in Sleep mode 1 DMASMEN DMA clock enable during sleep mode bit 0 1 DMASMEN Disabled DMA clock disabled in Sleep mode 0 Enabled DMA clock enabled in Sleep mode 1 APB2SMENR APB2SMENR APB2 peripheral clock enable in sleep mode register 0x44 0x20 read-write 0x00405225 SYSCFGSMEN System configuration controller clock enable during sleep mode bit 0 1 SYSCFGSMEN Disabled Clock disabled 0 Enabled Clock enabled 1 DBGSMEN DBG clock enable during sleep mode bit 22 1 USART1SMEN USART1 clock enable during sleep mode bit 14 1 SPI1SMEN SPI1 clock enable during sleep mode bit 12 1 ADCSMEN ADC clock enable during sleep mode bit 9 1 TIM22SMEN TIM22 timer clock enable during sleep mode bit 5 1 TIM21SMEN TIM21 timer clock enable during sleep mode bit 2 1 APB1SMENR APB1SMENR APB1 peripheral clock enable in sleep mode register 0x48 0x20 read-write 0xB8E64A11 TIM2SMEN Timer2 clock enable during sleep mode bit 0 1 TIM2SMEN Disabled Clock disabled 0 Enabled Clock enabled 1 LPTIM1SMEN Low power timer clock enable during sleep mode bit 31 1 PWRSMEN Power interface clock enable during sleep mode bit 28 1 CRSSMEN Clock recovery system clock enable during sleep mode bit 27 1 I2C2SMEN I2C2 clock enable during sleep mode bit 22 1 I2C1SMEN I2C1 clock enable during sleep mode bit 21 1 LPUART1SMEN LPUART1 clock enable during sleep mode bit 18 1 USART2SMEN UART2 clock enable during sleep mode bit 17 1 SPI2SMEN SPI2 clock enable during sleep mode bit 14 1 WWDGSMEN Window watchdog clock enable during sleep mode bit 11 1 TIM6SMEN Timer 6 clock enable during sleep mode bit 4 1 TIM3SMEN Timer 3 clock enable during sleep mode bit 1 1 TIM7SMEN Timer 7 clock enable during sleep mode bit 5 1 USART4SMEN USART4 clock enabe during sleep mode bit 19 1 USART5SMEN USART5 clock enable during sleep mode bit 20 1 I2C3SMEN I2C3 clock enable during sleep mode bit 30 1 CCIPR CCIPR Clock configuration register 0x4C 0x20 read-write 0x00000000 LPTIM1SEL Low Power Timer clock source selection bits 18 2 LPTIM1SEL APB APB clock selected as Timer clock 0 LSI LSI clock selected as Timer clock 1 HSI16 HSI16 clock selected as Timer clock 2 LSE LSE clock selected as Timer clock 3 I2C1SEL I2C1 clock source selection bits 12 2 I2C1SEL APB APB clock selected as peripheral clock 0 SYSTEM System clock selected as peripheral clock 1 HSI16 HSI16 clock selected as peripheral clock 2 USART1SEL USART1 clock source selection bits 0 2 USART1SEL APB APB clock selected as peripheral clock 0 SYSTEM System clock selected as peripheral clock 1 HSI16 HSI16 clock selected as peripheral clock 2 LSE LSE clock selected as peripheral clock 3 LPUART1SEL LPUART1 clock source selection bits 10 2 USART2SEL USART2 clock source selection bits 2 2 I2C3SEL I2C3 clock source selection bits 16 2 CSR CSR Control and status register 0x50 0x20 0x0C000000 FWRSTF Firewall reset flag 24 1 read-write FWRSTFR read NoReset No reset has occured 0 Reset A reset has occured 1 LPWRRSTF Low-power reset flag 31 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write SFTRSTF Software reset flag 28 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write PINRSTF PIN reset flag 26 1 read-write OBLRSTF OBLRSTF 25 1 read-write RTCRST RTC software reset bit 19 1 read-write RTCRSTW write Reset Resets the RTC peripheral 1 RTCEN RTC clock enable bit 18 1 read-write RTCEN Disabled RTC clock disabled 0 Enabled RTC clock enabled 1 RTCSEL RTC and LCD clock source selection bits 16 2 read-write RTCSEL NoClock No clock 0 LSE LSE oscillator clock used as RTC clock 1 LSI LSI oscillator clock used as RTC clock 2 HSE HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock 3 CSSLSED CSS on LSE failure detection flag 14 1 read-write CSSLSED NoFailure No failure detected on LSE (32 kHz oscillator) 0 Failure Failure detected on LSE (32 kHz oscillator) 1 LSION Internal low-speed oscillator enable 0 1 read-write LSION Off Oscillator OFF 0 On Oscillator ON 1 CSSLSEON CSSLSEON 13 1 read-write LSEDRV LSEDRV 11 2 read-write LSEDRV Low Lowest drive 0 MediumLow Medium low drive 1 MediumHigh Medium high drive 2 High Highest drive 3 LSEBYP External low-speed oscillator bypass bit 10 1 read-write LSEBYP NotBypassed LSE oscillator not bypassed 0 Bypassed LSE oscillator bypassed 1 LSIRDY Internal low-speed oscillator ready bit 1 1 read-only LSIRDY NotReady Oscillator not ready 0 Ready Oscillator ready 1 LSERDY External low-speed oscillator ready bit 9 1 read-only LSEON External low-speed oscillator enable bit 8 1 read-write RMVF Remove reset flag 23 1 read-write RMVFW write Clear Clears the reset flag 1 SYSCFG System configuration controller and COMP register SYSCFG 0x40010000 0x0 0x400 registers CFGR1 CFGR1 SYSCFG configuration register 1 0x0 0x20 0x00000000 BOOT_MODE Boot mode selected by the boot pins status bits 8 2 read-only BOOT_MODE MainFlash Main Flash memory boot mode 0 SystemFlash System Flash memory boot mode 1 SRAM Embedded SRAM boot mode 3 MEM_MODE Memory mapping selection bits 0 2 read-write MEM_MODE MainFlash Main Flash memory mapped at 0x0000_0000 0 SystemFlash System Flash memory mapped at 0x0000_0000 1 SRAM Embedded SRAM mapped at 0x0000_0000 3 UFB User bank swapping 3 1 UFB Bank1 Flash Program memory Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 1 at 0x0808 0000 (aliased at 0x0008 0000 if MEM_MODE=00) 0 Bank2 Flash Program memory Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 2 at 0x0808 0000 (and aliased at 0x0008 0000 if MEM_MODE=00) 1 CFGR2 CFGR2 SYSCFG configuration register 2 0x4 0x20 read-write 0x00000000 I2C2_FMP I2C2 Fm+ drive capability enable bit 13 1 I2C2_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers 1 I2C1_FMP I2C1 Fm+ drive capability enable bit 12 1 I2C1_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers 1 I2C_PB9_FMP Fm+ drive capability on PB9 enable bit 11 1 I2C_PB9_FMP Standard PB9 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB9 and the Speed control is bypassed 1 I2C_PB8_FMP Fm+ drive capability on PB8 enable bit 10 1 I2C_PB8_FMP Standard PB8 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB8 and the Speed control is bypassed 1 I2C_PB7_FMP Fm+ drive capability on PB7 enable bit 9 1 I2C_PB7_FMP Standard PB7 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB7 and the Speed control is bypassed 1 I2C_PB6_FMP Fm+ drive capability on PB6 enable bit 8 1 I2C_PB6_FMP Standard PB6 pin operate in standard mode 0 FMP I2C FM+ mode enabled on PB6 and the Speed control is bypassed 1 I2C3_FMP I2C3 Fm+ drive capability enable bit 14 1 I2C3_FMP Standard FM+ mode is controlled by I2C_Pxx_FMP bits only 0 FMP FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers 1 FWDIS Firewall disable bit 0 1 FWDIS Enabled Firewall access enabled 0 Disabled Firewall access disabled 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 ExtiAbcdeh PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 PH Select PHx as the source input for the EXTIx external interrupt 5 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 ExtiAbcde PA Select PAx as the source input for the EXTIx external interrupt 0 PB Select PBx as the source input for the EXTIx external interrupt 1 PC Select PCx as the source input for the EXTIx external interrupt 2 PD Select PDx as the source input for the EXTIx external interrupt 3 PE Select PEx as the source input for the EXTIx external interrupt 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI14 8 4 EXTI13 EXTI13 4 4 EXTI12 EXTI12 0 4 CFGR3 CFGR3 SYSCFG configuration register 3 0x20 0x20 0x00000000 VREFINT_RDYF VREFINT ready flag 30 1 read-only VREFINT_RDYF NotReady VREFINT OFF 0 Ready VREFINT ready 1 ENBUF_SENSOR_ADC Sensor reference for ADC enable bit 9 1 read-write ENBUF_SENSOR_ADC Disabled Disables the buffer used to generate VREFINT reference for the temperature sensor 0 Enabled Enables the buffer used to generate VREFINT reference for the temperature sensor 1 SEL_VREF_OUT BGAP_ADC connection bit 4 2 read-write SEL_VREF_OUT NoConnection no pad connected 0 PB0 PB0 connected 1 PB1 PB1 connected 2 Both PB0 and PB1 connected 3 REF_LOCK SYSCFG_CFGR3 lock bit 31 1 read-write REF_LOCK ReadWrite SYSCFG_CFGR3[31:0] bits are read/write 0 ReadOnly SYSCFG_CFGR3[31:0] bits are read-only 1 ENBUF_VREFINT_COMP2 VREFINT reference for COMP2 scaler enable bit 12 1 ENBUF_VREFINT_COMP2 Disabled Disables the buffer used to generate VREFINT references for COMP2 0 Enabled Enables the buffer used to generate VREFINT references for COMP2 1 ENBUF_VREFINT_ADC VREFINT reference for ADC enable bit 8 1 ENBUF_VREFINT_ADC Disabled Disables the buffer used to generate VREFINT reference for the ADC 0 Enabled Enables the buffer used to generate VREFINT reference for the ADC 1 EN_VREFINT VREFINT enable and scaler control for COMP2 enable bit 0 1 EN_VREFINT Disabled VREFINT voltage disabled in low-power mode (if ULP=1) and scaler for COMP2 disabled 0 Enabled VREFINT voltage enabled in low-power mode and scaler for COMP2 enabled 1 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x18 0x20 read-write 0x00000000 COMP1EN Comparator 1 enable bit 0 1 COMP1EN Disabled Comparator 1 switched OFF 0 Enabled Comparator 1 switched ON 1 COMP1INNSEL Comparator 1 Input Minus connection configuration bit 4 2 COMP1INNSEL VREFINT VREFINT 0 PA0 PA0 1 PA4 PA4 2 PA5 PA5 3 COMP1WM Comparator 1 window mode selection bit 8 1 COMP1WM PA1 Plus input of comparator 1 connected to PA1 0 Comp2Plus Plus input of comparator 1 shorted with Plus input of comparator 2 (see COMP1_CSR) 1 COMP1LPTIMIN1 Comparator 1 LPTIM input propagation bit 12 1 COMP1LPTIMIN1 Gated Comparator 1 output gated 0 NotGated Comparator 1 output sent to LPTIM input 1 1 COMP1POLARITY Comparator 1 polarity selection bit 15 1 COMP1POLARITY NotInverted Comparator 1 output value not inverted 0 Inverted Comparator 1 output value inverted 1 COMP1VALUE Comparator 1 output status bit 30 1 COMP1VALUER read NotEqual Comparator values are not equal 0 Equal Comparator values are equal 1 COMP1LOCK COMP1_CSR register lock bit 31 1 COMP1LOCK ReadWrite COMP1_CSR[31:0] for comparator 1 are read/write 0 ReadOnly COMP1_CSR[31:0] for comparator 1 are read-only 1 COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x1C 0x20 read-write 0x00000000 COMP2EN Comparator 2 enable bit 0 1 COMP2EN Disabled Comparator 2 switched OFF 0 Enabled Comparator 2 switched ON 1 COMP2SPEED Comparator 2 power mode selection bit 3 1 COMP2SPEED Slow Slow speed 0 Fast Fast speed 1 COMP2INNSEL Comparator 2 Input Minus connection configuration bit 4 3 COMP2INNSEL VREFINT VREFINT 0 PA2 PA2 1 PA4 PA4 2 PA5 PA5 3 VREFINT_Div4 1/4 VREFINT 4 VREFINT_Div2 1/2 VREFINT 5 VREFINT_Div3_4 3/4 VREFINT 6 PB3 PB3 7 COMP2INPSEL Comparator 2 Input Plus connection configuration bit 8 3 COMP2INPSEL PA3 PA3 0 PB4 PB4 1 PB5 PB5 2 PB6 PB6 3 PB7 PB7 4 PA7 PA7 5 COMP2LPTIMIN2 Comparator 2 LPTIM input 2 propagation bit 12 1 COMP2LPTIMIN2 Gated Comparator 2 output gated 0 NotGated Comparator 2 output sent to LPTIM input 2 1 COMP2LPTIMIN1 Comparator 2 LPTIM input 1 propagation bit 13 1 COMP2LPTIMIN1 Gated Comparator 2 output gated 0 NotGated Comparator 2 output sent to LPTIM input 1 1 COMP2POLARITY Comparator 2 polarity selection bit 15 1 COMP2POLARITY NotInverted Comparator 2 output value not inverted 0 Inverted Comparator 2 output value inverted 1 COMP2VALUE Comparator 2 output status bit 30 1 COMP2VALUER read NotEqual Comparator values are not equal 0 Equal Comparator values are equal 1 COMP2LOCK COMP2_CSR register lock bit 31 1 COMP2LOCK ReadWrite COMP2_CSR[31:0] for comparator 2 are read/write 0 ReadOnly COMP2_CSR[31:0] for comparator 2 are read-only 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1_global_interrupt 25 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODE Unidirectional 2-line unidirectional data mode selected 0 Bidirectional 1-line bidirectional data mode selected 1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOE OutputDisabled Output disabled (receive-only mode) 0 OutputEnabled Output enabled (transmit-only mode) 1 CRCEN Hardware CRC calculation enable 13 1 CRCEN Disabled CRC calculation disabled 0 Enabled CRC calculation enabled 1 CRCNEXT CRC transfer next 12 1 CRCNEXT TxBuffer Next transmit value is from Tx buffer 0 CRC Next transmit value is from Tx CRC register 1 DFF Data frame format 11 1 DFF EightBit 8-bit data frame format is selected for transmission/reception 0 SixteenBit 16-bit data frame format is selected for transmission/reception 1 RXONLY Receive only 10 1 RXONLY FullDuplex Full duplex (Transmit and receive) 0 OutputDisabled Output disabled (Receive-only mode) 1 SSM Software slave management 9 1 SSM Disabled Software slave management disabled 0 Enabled Software slave management enabled 1 SSI Internal slave select 8 1 SSI SlaveSelected 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 0 SlaveNotSelected 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored 1 LSBFIRST Frame format 7 1 LSBFIRST MSBFirst Data is transmitted/received with the MSB first 0 LSBFirst Data is transmitted/received with the LSB first 1 SPE SPI enable 6 1 SPE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 BR Baud rate control 3 3 BR Div2 f_PCLK / 2 0 Div4 f_PCLK / 4 1 Div8 f_PCLK / 8 2 Div16 f_PCLK / 16 3 Div32 f_PCLK / 32 4 Div64 f_PCLK / 64 5 Div128 f_PCLK / 128 6 Div256 f_PCLK / 256 7 MSTR Master selection 2 1 MSTR Slave Slave configuration 0 Master Master configuration 1 CPOL Clock polarity 1 1 CPOL IdleLow CK to 0 when idle 0 IdleHigh CK to 1 when idle 1 CPHA Clock phase 0 1 CPHA FirstEdge The first clock transition is the first data capture edge 0 SecondEdge The second clock transition is the first data capture edge 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 RXDMAEN Rx buffer DMA enable 0 1 RXDMAEN Disabled Rx buffer DMA disabled 0 Enabled Rx buffer DMA enabled 1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAEN Disabled Tx buffer DMA disabled 0 Enabled Tx buffer DMA enabled 1 SSOE SS output enable 2 1 SSOE Disabled SS output is disabled in master mode 0 Enabled SS output is enabled in master mode 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 ERRIE Masked Error interrupt masked 0 NotMasked Error interrupt not masked 1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIE Masked RXE interrupt masked 0 NotMasked RXE interrupt not masked 1 TXEIE Tx buffer empty interrupt enable 7 1 TXEIE Masked TXE interrupt masked 0 NotMasked TXE interrupt not masked 1 SR SR status register 0x8 0x10 0x00000002 RXNE Receive buffer not empty 0 1 read-only RXNE Empty Rx buffer empty 0 NotEmpty Rx buffer not empty 1 TXE Transmit buffer empty 1 1 read-only TXE NotEmpty Tx buffer not empty 0 Empty Tx buffer empty 1 CHSIDE Channel side 2 1 read-only UDR Underrun flag 3 1 read-only CRCERR CRC error flag 4 1 read-write zeroToClear CRCERRR read Match CRC value received matches the SPIx_RXCRCR value 0 NoMatch CRC value received does not match the SPIx_RXCRCR value 1 CRCERRW write Clear Clear flag 0 MODF Mode fault 5 1 read-only MODFR NoFault No mode fault occurred 0 Fault Mode fault occurred 1 OVR Overrun flag 6 1 read-only OVRR NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 BSY Busy flag 7 1 read-only BSYR NotBusy SPI not busy 0 Busy SPI busy 1 FRE TI frame format error 8 1 read-only DR DR data register 0xC 0x10 read-write 0x00000000 DR Data register 0 16 0 65535 DR8 Direct 8-bit access to data register DR 0xC 0x8 read-write DR Data register 0 8 0 255 CRCPR CRCPR CRC polynomial register 0x10 0x10 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 0 65535 RXCRCR RXCRCR RX CRC register 0x14 0x10 read-only 0x00000000 RxCRC Rx CRC register 0 16 0 65535 TXCRCR TXCRCR TX CRC register 0x18 0x10 read-only 0x00000000 TxCRC Tx CRC register 0 16 0 65535 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x10 read-write 0x00000000 I2SMOD I2S mode selection 11 1 I2SE I2S Enable 10 1 I2SCFG I2S configuration mode 8 2 PCMSYNC PCM frame synchronization 7 1 I2SSTD I2S standard selection 4 2 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 CHLEN Channel length (number of bits per audio channel) 0 1 I2SPR I2SPR I2S prescaler register 0x20 0x10 read-write 0x00000010 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 I2SDIV I2S Linear prescaler 0 8 SPI2 0x40003800 SPI2 SPI2 global interrupt 26 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global interrupt 23 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 PE Disabled Peripheral disabled 0 Enabled Peripheral enabled 1 TXIE TX Interrupt enable 1 1 TXIE Disabled Transmit (TXIS) interrupt disabled 0 Enabled Transmit (TXIS) interrupt enabled 1 RXIE RX Interrupt enable 2 1 RXIE Disabled Receive (RXNE) interrupt disabled 0 Enabled Receive (RXNE) interrupt enabled 1 ADDRIE Address match interrupt enable (slave only) 3 1 ADDRIE Disabled Address match (ADDR) interrupts disabled 0 Enabled Address match (ADDR) interrupts enabled 1 NACKIE Not acknowledge received interrupt enable 4 1 NACKIE Disabled Not acknowledge (NACKF) received interrupts disabled 0 Enabled Not acknowledge (NACKF) received interrupts enabled 1 STOPIE STOP detection Interrupt enable 5 1 STOPIE Disabled Stop detection (STOPF) interrupt disabled 0 Enabled Stop detection (STOPF) interrupt enabled 1 TCIE Transfer Complete interrupt enable 6 1 TCIE Disabled Transfer Complete interrupt disabled 0 Enabled Transfer Complete interrupt enabled 1 ERRIE Error interrupts enable 7 1 ERRIE Disabled Error detection interrupts disabled 0 Enabled Error detection interrupts enabled 1 DNF Digital noise filter 8 4 DNF NoFilter Digital filter disabled 0 Filter1 Digital filter enabled and filtering capability up to 1 tI2CCLK 1 Filter2 Digital filter enabled and filtering capability up to 2 tI2CCLK 2 Filter3 Digital filter enabled and filtering capability up to 3 tI2CCLK 3 Filter4 Digital filter enabled and filtering capability up to 4 tI2CCLK 4 Filter5 Digital filter enabled and filtering capability up to 5 tI2CCLK 5 Filter6 Digital filter enabled and filtering capability up to 6 tI2CCLK 6 Filter7 Digital filter enabled and filtering capability up to 7 tI2CCLK 7 Filter8 Digital filter enabled and filtering capability up to 8 tI2CCLK 8 Filter9 Digital filter enabled and filtering capability up to 9 tI2CCLK 9 Filter10 Digital filter enabled and filtering capability up to 10 tI2CCLK 10 Filter11 Digital filter enabled and filtering capability up to 11 tI2CCLK 11 Filter12 Digital filter enabled and filtering capability up to 12 tI2CCLK 12 Filter13 Digital filter enabled and filtering capability up to 13 tI2CCLK 13 Filter14 Digital filter enabled and filtering capability up to 14 tI2CCLK 14 Filter15 Digital filter enabled and filtering capability up to 15 tI2CCLK 15 ANFOFF Analog noise filter OFF 12 1 ANFOFF Enabled Analog noise filter enabled 0 Disabled Analog noise filter disabled 1 TXDMAEN DMA transmission requests enable 14 1 TXDMAEN Disabled DMA mode disabled for transmission 0 Enabled DMA mode enabled for transmission 1 RXDMAEN DMA reception requests enable 15 1 RXDMAEN Disabled DMA mode disabled for reception 0 Enabled DMA mode enabled for reception 1 SBC Slave byte control 16 1 SBC Disabled Slave byte control disabled 0 Enabled Slave byte control enabled 1 NOSTRETCH Clock stretching disable 17 1 NOSTRETCH Enabled Clock stretching enabled 0 Disabled Clock stretching disabled 1 WUPEN Wakeup from STOP enable 18 1 WUPEN Disabled Wakeup from Stop mode disabled 0 Enabled Wakeup from Stop mode enabled 1 GCEN General call enable 19 1 GCEN Disabled General call disabled. Address 0b00000000 is NACKed 0 Enabled General call enabled. Address 0b00000000 is ACKed 1 SMBHEN SMBus Host address enable 20 1 SMBHEN Disabled Host address disabled. Address 0b0001000x is NACKed 0 Enabled Host address enabled. Address 0b0001000x is ACKed 1 SMBDEN SMBus Device Default address enable 21 1 SMBDEN Disabled Device default address disabled. Address 0b1100001x is NACKed 0 Enabled Device default address enabled. Address 0b1100001x is ACKed 1 ALERTEN SMBUS alert enable 22 1 ALERTEN Disabled In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported 0 Enabled In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported 1 PECEN PEC enable 23 1 PECEN Disabled PEC calculation disabled 0 Enabled PEC calculation enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 oneToSet PECBYTER read NoPec No PEC transfer 0 Pec PEC transmission/reception is requested 1 PECBYTEW write Pec PEC transmission/reception is requested 1 AUTOEND Automatic end mode (master mode) 25 1 AUTOEND Software Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low 0 Automatic Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred 1 RELOAD NBYTES reload mode 24 1 RELOAD Completed The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) 0 NotCompleted The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) 1 NBYTES Number of bytes 16 8 0 255 NACK NACK generation (slave mode) 15 1 oneToSet NACKR read Ack an ACK is sent after current received byte 0 Nack a NACK is sent after current received byte 1 NACKW write Nack a NACK is sent after current received byte 1 STOP Stop generation (master mode) 14 1 oneToSet STOPR read NoStop No Stop generation 0 Stop Stop generation after current byte transfer 1 STOPW write Stop Stop generation after current byte transfer 1 START Start generation 13 1 oneToSet STARTR read NoStart No Start generation 0 Start Restart/Start generation 1 STARTW write Start Restart/Start generation 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 HEAD10R Complete The master sends the complete 10 bit slave address read sequence 0 Partial The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction 1 ADD10 10-bit addressing mode (master mode) 11 1 ADD10 Bit7 The master operates in 7-bit addressing mode 0 Bit10 The master operates in 10-bit addressing mode 1 RD_WRN Transfer direction (master mode) 10 1 RD_WRN Write Master requests a write transfer 0 Read Master requests a read transfer 1 SADD Slave address bit (master mode) 0 10 0 1023 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 0 1023 OA1MODE Own Address 1 10-bit mode 10 1 OA1MODE Bit7 Own address 1 is a 7-bit address 0 Bit10 Own address 1 is a 10-bit address 1 OA1EN Own Address 1 enable 15 1 OA1EN Disabled Own address 1 disabled. The received slave address OA1 is NACKed 0 Enabled Own address 1 enabled. The received slave address OA1 is ACKed 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 0 127 OA2MSK Own Address 2 masks 8 3 OA2MSK NoMask No mask 0 Mask1 OA2[1] is masked and don’t care. Only OA2[7:2] are compared 1 Mask2 OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared 2 Mask3 OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared 3 Mask4 OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared 4 Mask5 OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared 5 Mask6 OA2[6:1] are masked and don’t care. Only OA2[7] is compared. 6 Mask7 OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged 7 OA2EN Own Address 2 enable 15 1 OA2EN Disabled Own address 2 disabled. The received slave address OA2 is NACKed 0 Enabled Own address 2 enabled. The received slave address OA2 is ACKed 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 0 255 SCLH SCL high period (master mode) 8 8 0 255 SDADEL Data hold time 16 4 0 15 SCLDEL Data setup time 20 4 0 15 PRESC Timing prescaler 28 4 0 15 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 0 4095 TIDLE Idle clock timeout detection 12 1 TIDLE Disabled TIMEOUTA is used to detect SCL low timeout 0 Enabled TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) 1 TIMOUTEN Clock timeout enable 15 1 TIMOUTEN Disabled SCL timeout detection is disabled 0 Enabled SCL timeout detection is enabled 1 TIMEOUTB Bus timeout B 16 12 0 4095 TEXTEN Extended clock timeout enable 31 1 TEXTEN Disabled Extended clock timeout detection is disabled 0 Enabled Extended clock timeout detection is enabled 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only 0 127 DIR Transfer direction (Slave mode) 16 1 read-only DIR Write Write transfer, slave enters receiver mode 0 Read Read transfer, slave enters transmitter mode 1 BUSY Bus busy 15 1 read-only BUSY NotBusy No communication is in progress on the bus 0 Busy A communication is in progress on the bus 1 ALERT SMBus alert 13 1 read-only ALERT NoAlert SMBA alert is not detected 0 Alert SMBA alert event is detected on SMBA pin 1 TIMEOUT Timeout or t_low detection flag 12 1 read-only TIMEOUT NoTimeout No timeout occured 0 Timeout Timeout occured 1 PECERR PEC Error in reception 11 1 read-only PECERR Match Received PEC does match with PEC register 0 NoMatch Received PEC does not match with PEC register 1 OVR Overrun/Underrun (slave mode) 10 1 read-only OVR NoOverrun No overrun/underrun error occurs 0 Overrun slave mode with NOSTRETCH=1, when an overrun/underrun error occurs 1 ARLO Arbitration lost 9 1 read-only ARLO NotLost No arbitration lost 0 Lost Arbitration lost 1 BERR Bus error 8 1 read-only BERR NoError No bus error 0 Error Misplaced Start and Stop condition is detected 1 TCR Transfer Complete Reload 7 1 read-only TCR NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 TC Transfer Complete (master mode) 6 1 read-only TC NotComplete Transfer is not complete 0 Complete NBYTES has been transfered 1 STOPF Stop detection flag 5 1 read-only STOPF NoStop No Stop condition detected 0 Stop Stop condition detected 1 NACKF Not acknowledge received flag 4 1 read-only NACKF NoNack No NACK has been received 0 Nack NACK has been received 1 ADDR Address matched (slave mode) 3 1 read-only ADDR NotMatch Adress mismatched or not received 0 Match Received slave address matched with one of the enabled slave addresses 1 RXNE Receive data register not empty (receivers) 2 1 read-only RXNE Empty The RXDR register is empty 0 NotEmpty Received data is copied into the RXDR register, and is ready to be read 1 TXIS Transmit interrupt status (transmitters) 1 1 read-write oneToSet TXISR read NotEmpty The TXDR register is not empty 0 Empty The TXDR register is empty and the data to be transmitted must be written in the TXDR register 1 TXISW write Trigger Generate a TXIS event 1 TXE Transmit data register empty (transmitters) 0 1 read-write oneToSet TXER read NotEmpty TXDR register not empty 0 Empty TXDR register empty 1 TXEW write Flush Flush the transmit data register 1 ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 oneToClear ALERTCF Clear Clears the ALERT flag in ISR register 1 TIMOUTCF Timeout detection flag clear 12 1 oneToClear TIMOUTCF Clear Clears the TIMOUT flag in ISR register 1 PECCF PEC Error flag clear 11 1 oneToClear PECCF Clear Clears the PEC flag in ISR register 1 OVRCF Overrun/Underrun flag clear 10 1 oneToClear OVRCF Clear Clears the OVR flag in ISR register 1 ARLOCF Arbitration lost flag clear 9 1 oneToClear ARLOCF Clear Clears the ARLO flag in ISR register 1 BERRCF Bus error flag clear 8 1 oneToClear BERRCF Clear Clears the BERR flag in ISR register 1 STOPCF Stop detection flag clear 5 1 oneToClear STOPCF Clear Clears the STOP flag in ISR register 1 NACKCF Not Acknowledge flag clear 4 1 oneToClear NACKCF Clear Clears the NACK flag in ISR register 1 ADDRCF Address Matched flag clear 3 1 oneToClear ADDRCF Clear Clears the ADDR flag in ISR register 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 0 255 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 0 255 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 0 255 I2C2 0x40005800 I2C2 I2C2 global interrupt 24 I2C3 0x40007800 I2C3 I2C3 global interrupt 21 PWR Power control PWR 0x40007000 0x0 0x400 registers CR CR power control register 0x0 0x20 read-write 0x00001000 LPSDSR Low-power deepsleep/Sleep/Low-power run 0 1 LPSDSR MAIN_MODE Voltage regulator on during Deepsleep/Sleep/Low-power run mode 0 LOW_POWER_MODE Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode 1 PDDS Power down deepsleep 1 1 PDDS STOP_MODE Enter Stop mode when the CPU enters deepsleep 0 STANDBY_MODE Enter Standby mode when the CPU enters deepsleep 1 CWUF Clear wakeup flag 2 1 CWUFW write Clear Clear the WUF Wakeup flag after 2 system clock cycles 1 CSBF Clear standby flag 3 1 CSBFW write Clear Clear the SBF Standby flag 1 PVDE Power voltage detector enable 4 1 PVDE Disabled PVD Disabled 0 Enabled PVD Enabled 1 PLS PVD level selection 5 3 PLS V1_9 1.9 V 0 V2_1 2.1 V 1 V2_3 2.3 V 2 V2_5 2.5 V 3 V2_7 2.7 V 4 V2_9 2.9 V 5 V3_1 3.1 V 6 External External input analog voltage (Compare internally to VREFINT) 7 DBP Disable backup domain write protection 8 1 DBP Disabled Access to RTC, RTC Backup and RCC CSR registers disabled 0 Enabled Access to RTC, RTC Backup and RCC CSR registers enabled 1 ULP Ultra-low-power mode 9 1 ULP Enabled VREFINT is on in low-power mode 0 Disabled VREFINT is off in low-power mode 1 FWU Fast wakeup 10 1 FWU Disabled Low-power modes exit occurs only when VREFINT is ready 0 Enabled VREFINT start up time is ignored when exiting low-power modes 1 VOS Voltage scaling range selection 11 2 VOS V1_8 1.8 V (range 1) 1 V1_5 1.5 V (range 2) 2 V1_2 1.2 V (range 3) 3 DS_EE_KOFF Deep sleep mode with Flash memory kept off 13 1 DS_EE_KOFF NVMWakeUp NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set 0 NVMSleep NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) 1 LPRUN Low power run mode 14 1 LPRUN MAIN_MODE Voltage regulator in Main mode in Low-power run mode 0 LOW_POWER_MODE Voltage regulator in low-power mode in Low-power run mode 1 LPDS Regulator in Low-power deepsleep mode This bit allows switching the regulator to low-power mode when the CPU enters Stop mode. Its behavior depends on LPSDSR bit 16 1 LPDS MAIN_MODE Voltage regulator in Main mode during Deepsleep mode (Stop mode) 0 LOW_POWER_MODE Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode) 1 CSR CSR power control/status register 0x4 0x20 0x00000000 EWUP3 Enable WKUP pin 3 10 1 read-write EWUP3 Disabled WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode 0 Enabled WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode) 1 EWUP2 Enable WKUP pin 2 9 1 read-write EWUP2 Disabled WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode 0 Enabled WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode) 1 EWUP1 Enable WKUP pin 1 8 1 read-write EWUP1 Disabled WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode 0 Enabled WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode) 1 REGLPF Regulator LP flag 5 1 read-only REGLPFR Ready Regulator is ready in Main mode 0 NotReady Regulator voltage is in low-power mode 1 VOSF Voltage Scaling select flag 4 1 read-only VOSFR Ready Regulator is ready in the selected voltage range 0 NotReady Regulator voltage output is changing to the required VOS level 1 VREFINTRDYF Internal voltage reference (VREFINT) ready flag This bit indicates the state of the internal voltage reference, VREFINT. 3 1 read-only VREFINTRDYFR NotReady VREFINT is OFF 0 Ready VREFINT is ready 1 PVDO PVD output 2 1 read-only PVDOR AboveThreshold VDD is higher than the PVD threshold selected with the PLS[2:0] bits 0 BelowThreshold VDD is lower than the PVD threshold selected with the PLS[2:0] bits 1 SBF Standby flag 1 1 read-only SBFR NoStandbyEvent Device has not been in Standby mode 0 StandbyEvent Device has been in Standby mode 1 WUF Wakeup flag 0 1 read-only WUFR NoWakeupEvent No wakeup event occurred 0 WakeupEvent A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup) 1 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash memory and data EEPROM global interrupt 3 ACR ACR Access control register 0x0 0x20 read-write 0x00000000 LATENCY Latency 0 1 LATENCY WS0 Zero wait state is used to read a word in the NVM 0 WS1 One wait state is used to read a word in the NVM 1 PRFTEN Prefetch enable 1 1 PRFTEN Disabled Prefetch is disabled 0 Enabled Prefetch is enabled 1 SLEEP_PD Flash mode during Sleep 3 1 SLEEP_PD NVMIdleMode When the device is in Sleep mode, the NVM is in Idle mode 0 NVMPwrDownMode When the device is in Sleep mode, the NVM is in power-down mode 1 RUN_PD Flash mode during Run 4 1 RUN_PD NVMIdleMode When the device is in Run mode, the NVM is in Idle mode 0 NVMPwrDownMode When the device is in Run mode, the NVM is in power-down mode 1 DISAB_BUF Disable Buffer 5 1 DISAB_BUF Enabled The buffers are enabled 0 Disabled The buffers are disabled 1 PRE_READ Pre-read data address 6 1 PRE_READ Disabled The pre-read is disabled 0 Enabled The pre-read is enabled 1 PECR PECR Program/erase control register 0x4 0x20 read-write 0x00000007 PELOCK FLASH_PECR and data EEPROM lock 0 1 PELOCK Unlocked The FLASH_PECR register is unlocked 0 Locked The FLASH_PECR register is locked and no write/erase operation can start 1 PRGLOCK Program memory lock 1 1 PRGLOCK Unlocked The write and erase operations in the Flash program memory are disabled 0 Locked The write and erase operations in the Flash program memory are enabled 1 OPTLOCK Option bytes block lock 2 1 OPTLOCK Unlocked The write and erase operations in the Option bytes area are disabled 0 Locked The write and erase operations in the Option bytes area are enabled 1 PROG Program memory selection 3 1 PROG NotSelected The Flash program memory is not selected 0 Selected The Flash program memory is selected 1 DATA Data EEPROM selection 4 1 DATA NotSelected Data EEPROM not selected 0 Selected Data memory selected 1 FIX Fixed time data write for Byte, Half Word and Word programming 8 1 FIX AutoErase An erase phase is automatically performed 0 PrelimErase The program operation is always performed with a preliminary erase 1 ERASE Page or Double Word erase mode 9 1 ERASE NoErase No erase operation requested 0 Erase Erase operation requested 1 FPRG Half Page/Double Word programming mode 10 1 FPRG Disabled Half Page programming disabled 0 Enabled Half Page programming enabled 1 PARALLELBANK Parallel bank mode 15 1 PARALLELBANK Disabled Parallel bank mode disabled 0 Enabled Parallel bank mode enabled 1 EOPIE End of programming interrupt enable 16 1 EOPIE Disabled End of program interrupt disable 0 Enabled End of program interrupt enable 1 ERRIE Error interrupt enable 17 1 ERRIE Disabled Error interrupt disable 0 Enabled Error interrupt enable 1 OBL_LAUNCH Launch the option byte loading 18 1 OBL_LAUNCHR read Complete Option byte loaded 0 NotComplete Option byte loading to be done 1 OBL_LAUNCHW write Reload Reload option byte 1 NZDISABLE Non-Zero check notification disable 23 1 PDKEYR PDKEYR Power down key register 0x8 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 0 4294967295 PEKEYR PEKEYR Program/erase key register 0xC 0x20 write-only 0x00000000 PEKEYR FLASH_PEC and data EEPROM key 0 32 0 4294967295 PRGKEYR PRGKEYR Program memory key register 0x10 0x20 write-only 0x00000000 PRGKEYR Program memory key 0 32 0 4294967295 OPTKEYR OPTKEYR Option byte key register 0x14 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 0 4294967295 SR SR Status register 0x18 0x20 0x00000004 BSY Write/erase operations in progress 0 1 read-only BSY Inactive No write/erase operation is in progress 0 Active No write/erase operation is in progress 1 EOP End of operation 1 1 read-write EOP NoEvent No EOP operation occurred 0 Event An EOP event occurred 1 ENDHV End of high voltage 2 1 read-only ENDHV Active High voltage is executing a write/erase operation in the NVM 0 Inactive High voltage is off, no write/erase operation is ongoing 1 READY Flash memory module ready after low power mode 3 1 read-only READY NotReady The NVM is not ready 0 Ready The NVM is ready 1 WRPERR Write protected error 8 1 read-write WRPERRR read NoError No protection error happened 0 Error One protection error happened 1 WRPERRW write Clear Clear the flag 1 PGAERR Programming alignment error 9 1 read-write PGAERRR read NoError No alignment error happened 0 Error One alignment error happened 1 PGAERRW write Clear Clear the flag 1 SIZERR Size error 10 1 read-write SIZERRR read NoError No size error happened 0 Error One size error happened 1 SIZERRW write Clear Clear the flag 1 OPTVERR Option validity error 11 1 read-write OPTVERRR read NoError No error happened during the Option bytes loading 0 Error One or more errors happened during the Option bytes loading 1 OPTVERRW write Clear Clear the flag 1 RDERR RDERR 13 1 read-write RDERRR read NoError No read protection error happened. 0 Error One read protection error happened 1 RDERRW write Clear Clear the flag 1 NOTZEROERR NOTZEROERR 16 1 read-write NOTZEROERRR read NoEvent The write operation is done in an erased region or the memory interface can apply an erase before a write 0 Event The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write 1 NOTZEROERRW write Clear Clear the flag 1 FWWERR FWWERR 17 1 read-write FWWERRR read NoError No write/erase operation aborted to perform a fetch 0 Error A write/erase operation aborted to perform a fetch 1 FWWERRW write Clear Clear the flag 1 OPTR OPTR Option byte register 0x1C 0x20 read-only 0x00F80000 RDPROT Read protection 0 8 RDPROT Level1 Level 1 0 Level0 Level 0 170 Level2 Level 2 204 WPRMOD WPRMOD 8 1 WPRMOD Disabled PCROP disabled. The WRPROT bits are used as a write protection on a sector. 0 Enabled PCROP enabled. The WRPROT bits are used as a read protection on a sector. 1 BOR_LEV BOR_LEV 16 4 BOR_LEV BOR_Off This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only) 0 BOR_Level1 Reset threshold level for VBOR0 (around 1.8 V) 1 BOR_Level2 Reset threshold level for VBOR1 (around 2.0 V) 2 BOR_Level3 Reset threshold level for VBOR2 (around 2.5 V) 3 BOR_Level4 Reset threshold level for VBOR3 (around 2.7 V) 4 BOR_Level5 Reset threshold level for VBOR4 (around 3.0 V) 5 WDG_SW WDG_SW 20 1 nRST_STOP nRST_STOP 21 1 nRST_STDBY nRST_STDBY 22 1 BFB2 BFB2 23 1 nBOOT1 nBOOT1 31 1 WRPROT1 WRPROT1 Write protection register 0x20 0x20 read-only 0x00000000 WRPROT1 Write protection 0 32 0 4294967295 WRPROT2 WRPROT2 Write protection register 0x80 0x20 read-only 0x00000000 WRPROT2 Write protection 0 16 0 65535 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers PVD PVD through EXTI line detection 1 EXTI0_1 EXTI Line[1:0] interrupts 5 EXTI2_3 EXTI Line[3:2] interrupts 6 EXTI4_15 EXTI Line15 and EXTI4 interrupts 7 IMR IMR Interrupt mask register (EXTI_IMR) 0x0 0x20 read-write 0xFF840000 IM0 Interrupt Mask on line 0 0 1 InterruptMask Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1 IM1 Interrupt Mask on line 1 1 1 IM2 Interrupt Mask on line 2 2 1 IM3 Interrupt Mask on line 3 3 1 IM4 Interrupt Mask on line 4 4 1 IM5 Interrupt Mask on line 5 5 1 IM6 Interrupt Mask on line 6 6 1 IM7 Interrupt Mask on line 7 7 1 IM8 Interrupt Mask on line 8 8 1 IM9 Interrupt Mask on line 9 9 1 IM10 Interrupt Mask on line 10 10 1 IM11 Interrupt Mask on line 11 11 1 IM12 Interrupt Mask on line 12 12 1 IM13 Interrupt Mask on line 13 13 1 IM14 Interrupt Mask on line 14 14 1 IM15 Interrupt Mask on line 15 15 1 IM16 Interrupt Mask on line 16 16 1 IM17 Interrupt Mask on line 17 17 1 IM18 Interrupt Mask on line 18 18 1 IM19 Interrupt Mask on line 19 19 1 IM20 Interrupt Mask on line 20 20 1 IM21 Interrupt Mask on line 21 21 1 IM22 Interrupt Mask on line 22 22 1 IM23 Interrupt Mask on line 23 23 1 IM24 Interrupt Mask on line 24 24 1 IM25 Interrupt Mask on line 25 25 1 IM26 Interrupt Mask on line 27 26 1 IM28 Interrupt Mask on line 27 28 1 IM29 Interrupt Mask on line 27 29 1 EMR EMR Event mask register (EXTI_EMR) 0x4 0x20 read-write 0x00000000 EM0 Event Mask on line 0 0 1 EventMask Masked Event request line is masked 0 Unmasked Event request line is unmasked 1 EM1 Event Mask on line 1 1 1 EM2 Event Mask on line 2 2 1 EM3 Event Mask on line 3 3 1 EM4 Event Mask on line 4 4 1 EM5 Event Mask on line 5 5 1 EM6 Event Mask on line 6 6 1 EM7 Event Mask on line 7 7 1 EM8 Event Mask on line 8 8 1 EM9 Event Mask on line 9 9 1 EM10 Event Mask on line 10 10 1 EM11 Event Mask on line 11 11 1 EM12 Event Mask on line 12 12 1 EM13 Event Mask on line 13 13 1 EM14 Event Mask on line 14 14 1 EM15 Event Mask on line 15 15 1 EM16 Event Mask on line 16 16 1 EM17 Event Mask on line 17 17 1 EM18 Event Mask on line 18 18 1 EM19 Event Mask on line 19 19 1 EM20 Event Mask on line 20 20 1 EM21 Event Mask on line 21 21 1 EM22 Event Mask on line 22 22 1 EM23 Event Mask on line 23 23 1 EM24 Event Mask on line 24 24 1 EM25 Event Mask on line 25 25 1 EM26 Event Mask on line 26 26 1 EM28 Event Mask on line 28 28 1 EM29 Event Mask on line 29 29 1 RTSR RTSR Rising Trigger selection register (EXTI_RTSR) 0x8 0x20 read-write 0x00000000 RT0 Rising trigger event configuration of line 0 0 1 RisingTrigger Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1 RT1 Rising trigger event configuration of line 1 1 1 RT2 Rising trigger event configuration of line 2 2 1 RT3 Rising trigger event configuration of line 3 3 1 RT4 Rising trigger event configuration of line 4 4 1 RT5 Rising trigger event configuration of line 5 5 1 RT6 Rising trigger event configuration of line 6 6 1 RT7 Rising trigger event configuration of line 7 7 1 RT8 Rising trigger event configuration of line 8 8 1 RT9 Rising trigger event configuration of line 9 9 1 RT10 Rising trigger event configuration of line 10 10 1 RT11 Rising trigger event configuration of line 11 11 1 RT12 Rising trigger event configuration of line 12 12 1 RT13 Rising trigger event configuration of line 13 13 1 RT14 Rising trigger event configuration of line 14 14 1 RT15 Rising trigger event configuration of line 15 15 1 RT16 Rising trigger event configuration of line 16 16 1 RT17 Rising trigger event configuration of line 17 17 1 RT19 Rising trigger event configuration of line 19 19 1 RT20 Rising trigger event configuration of line 20 20 1 RT21 Rising trigger event configuration of line 21 21 1 RT22 Rising trigger event configuration of line 22 22 1 FTSR FTSR Falling Trigger selection register (EXTI_FTSR) 0xC 0x20 read-write 0x00000000 FT0 Falling trigger event configuration of line 0 0 1 FallingTrigger Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1 FT1 Falling trigger event configuration of line 1 1 1 FT2 Falling trigger event configuration of line 2 2 1 FT3 Falling trigger event configuration of line 3 3 1 FT4 Falling trigger event configuration of line 4 4 1 FT5 Falling trigger event configuration of line 5 5 1 FT6 Falling trigger event configuration of line 6 6 1 FT7 Falling trigger event configuration of line 7 7 1 FT8 Falling trigger event configuration of line 8 8 1 FT9 Falling trigger event configuration of line 9 9 1 FT10 Falling trigger event configuration of line 10 10 1 FT11 Falling trigger event configuration of line 11 11 1 FT12 Falling trigger event configuration of line 12 12 1 FT13 Falling trigger event configuration of line 13 13 1 FT14 Falling trigger event configuration of line 14 14 1 FT15 Falling trigger event configuration of line 15 15 1 FT16 Falling trigger event configuration of line 16 16 1 FT17 Falling trigger event configuration of line 17 17 1 FT19 Falling trigger event configuration of line 19 19 1 FT20 Falling trigger event configuration of line 20 20 1 FT21 Falling trigger event configuration of line 21 21 1 FT22 Falling trigger event configuration of line 22 22 1 SWIER SWIER Software interrupt event register (EXTI_SWIER) 0x10 0x20 read-write 0x00000000 SWI0 Software Interrupt on line 0 0 1 SoftwareInterrupt write Pend Generates an interrupt request 1 SWI1 Software Interrupt on line 1 1 1 SWI2 Software Interrupt on line 2 2 1 SWI3 Software Interrupt on line 3 3 1 SWI4 Software Interrupt on line 4 4 1 SWI5 Software Interrupt on line 5 5 1 SWI6 Software Interrupt on line 6 6 1 SWI7 Software Interrupt on line 7 7 1 SWI8 Software Interrupt on line 8 8 1 SWI9 Software Interrupt on line 9 9 1 SWI10 Software Interrupt on line 10 10 1 SWI11 Software Interrupt on line 11 11 1 SWI12 Software Interrupt on line 12 12 1 SWI13 Software Interrupt on line 13 13 1 SWI14 Software Interrupt on line 14 14 1 SWI15 Software Interrupt on line 15 15 1 SWI16 Software Interrupt on line 16 16 1 SWI17 Software Interrupt on line 17 17 1 SWI19 Software Interrupt on line 19 19 1 SWI20 Software Interrupt on line 20 20 1 SWI21 Software Interrupt on line 21 21 1 SWI22 Software Interrupt on line 22 22 1 PR PR Pending register (EXTI_PR) 0x14 0x20 read-write 0x00000000 PIF0 Pending bit 0 0 1 oneToClear PIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 PIF0W write Clear Clears pending bit 1 PIF1 Pending bit 1 1 1 oneToClear read write PIF2 Pending bit 2 2 1 oneToClear read write PIF3 Pending bit 3 3 1 oneToClear read write PIF4 Pending bit 4 4 1 oneToClear read write PIF5 Pending bit 5 5 1 oneToClear read write PIF6 Pending bit 6 6 1 oneToClear read write PIF7 Pending bit 7 7 1 oneToClear read write PIF8 Pending bit 8 8 1 oneToClear read write PIF9 Pending bit 9 9 1 oneToClear read write PIF10 Pending bit 10 10 1 oneToClear read write PIF11 Pending bit 11 11 1 oneToClear read write PIF12 Pending bit 12 12 1 oneToClear read write PIF13 Pending bit 13 13 1 oneToClear read write PIF14 Pending bit 14 14 1 oneToClear read write PIF15 Pending bit 15 15 1 oneToClear read write PIF16 Pending bit 16 16 1 oneToClear read write PIF17 Pending bit 17 17 1 oneToClear read write PIF19 Pending bit 19 19 1 oneToClear read write PIF20 Pending bit 20 20 1 oneToClear read write PIF21 Pending bit 21 21 1 oneToClear read write PIF22 Pending bit 22 22 1 oneToClear read write ADC Analog-to-digital converter ADC 0x40012400 0x0 0x400 registers ADC_COMP ADC and comparator 1 and 2 12 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 ADRDY ADC ready 0 1 oneToClear ADRDYR read NotReady ADC not yet ready to start conversion 0 Ready ADC ready to start conversion 1 ADRDYW write Clear Clear the ADC ready flag 1 EOSMP End of sampling flag 1 1 oneToClear EOSMPR read NotAtEnd Not at the end of the samplings phase 0 AtEnd End of sampling phase reached 1 EOSMPW write Clear Clear the sampling phase flag 1 EOC End of conversion flag 2 1 oneToClear EOCR read NotComplete Channel conversion is not complete 0 Complete Channel conversion complete 1 EOCW write Clear Clear the channel conversion flag 1 EOS End of sequence flag 3 1 oneToClear EOSR read NotComplete Conversion sequence is not complete 0 Complete Conversion sequence complete 1 EOSW write Clear Clear the conversion sequence flag 1 OVR ADC overrun 4 1 oneToClear OVRR read NoOverrun No overrun occurred 0 Overrun Overrun occurred 1 OVRW write Clear Clear the overrun flag 1 AWD Analog watchdog flag 7 1 oneToClear AWDR read NoEvent No analog watchdog event occurred 0 Event Analog watchdog event occurred 1 AWDW write Clear Clear the analog watchdog event flag 1 EOCAL End Of Calibration flag 11 1 oneToClear EOCALR read NotComplete Calibration is not complete 0 Complete Calibration complete 1 EOCALW write Clear Clear the calibration flag 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 ADRDYIE ADC ready interrupt enable 0 1 ADRDYIE Disabled ADRDY interrupt disabled 0 Enabled ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. 1 EOSMPIE End of sampling flag interrupt enable 1 1 EOSMPIE Disabled EOSMP interrupt disabled 0 Enabled EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. 1 EOCIE End of conversion interrupt enable 2 1 EOCIE Disabled EOC interrupt disabled 0 Enabled EOC interrupt enabled. An interrupt is generated when the EOC bit is set. 1 EOSIE End of conversion sequence interrupt enable 3 1 EOSIE Disabled EOS interrupt disabled 0 Enabled EOS interrupt enabled. An interrupt is generated when the EOS bit is set. 1 OVRIE Overrun interrupt enable 4 1 OVRIE Disabled Overrun interrupt disabled 0 Enabled Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. 1 AWDIE Analog watchdog interrupt enable 7 1 AWDIE Disabled Analog watchdog interrupt disabled 0 Enabled Analog watchdog interrupt enabled 1 EOCALIE End of calibration interrupt enable 11 1 EOCALIE Disabled End of calibration interrupt disabled 0 Enabled End of calibration interrupt enabled 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADEN ADC enable command 0 1 oneToSet ADENR read Disabled ADC disabled 0 Enabled ADC enabled 1 ADENW write Enabled Enable the ADC 1 ADDIS ADC disable command 1 1 oneToSet ADDISR read NotDisabling No disable command active 0 Disabling ADC disabling 1 ADDISW write Disable Disable the ADC 1 ADSTART ADC start conversion command 2 1 oneToSet ADSTARTR read NotActive No conversion ongoing 0 Active ADC operating and may be converting 1 ADSTARTW write StartConversion Start the ADC conversion (may be delayed for hardware triggers) 1 ADSTP ADC stop conversion command 4 1 oneToSet ADSTPR read NotStopping No stop command active 0 Stopping ADC stopping conversion 1 ADSTPW write StopConversion Stop the active conversion 1 ADVREGEN ADC Voltage Regulator Enable 28 1 ADVREGEN Disabled ADC voltage regulator disabled 0 Enabled ADC voltage regulator enabled 1 ADCAL ADC calibration 31 1 oneToSet ADCALR read NotCalibrating ADC calibration either not yet performed or completed 0 Calibrating ADC calibration in progress 1 ADCALW write StartCalibration Start the ADC calibration sequence 1 CFGR1 CFGR1 configuration register 1 0xC 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 26 5 0 18 AWDEN Analog watchdog enable 23 1 AWDEN Disabled Analog watchdog disabled 0 Enabled Analog watchdog enabled 1 AWDSGL Enable the watchdog on a single channel or on all channels 22 1 AWDSGL AllChannels Analog watchdog enabled on all channels 0 SingleChannel Analog watchdog enabled on a single channel 1 DISCEN Discontinuous mode 16 1 DISCEN Disabled Discontinuous mode disabled 0 Enabled Discontinuous mode enabled 1 AUTOFF Auto-off mode 15 1 AUTOFF Disabled Auto-off mode disabled 0 Enabled Auto-off mode enabled 1 WAIT Auto-delayed conversion mode 14 1 WAIT Disabled Wait conversion mode off 0 Enabled Wait conversion mode on 1 CONT Single / continuous conversion mode 13 1 CONT Single Single conversion mode 0 Continuous Continuous conversion mode 1 OVRMOD Overrun management mode 12 1 OVRMOD Preserve ADC_DR register is preserved with the old data when an overrun is detected 0 Overwrite ADC_DR register is overwritten with the last conversion result when an overrun is detected 1 EXTEN External trigger enable and polarity selection 10 2 EXTEN Disabled Hardware trigger detection disabled 0 RisingEdge Hardware trigger detection on the rising edge 1 FallingEdge Hardware trigger detection on the falling edge 2 BothEdges Hardware trigger detection on both the rising and falling edges 3 EXTSEL External trigger selection 6 3 EXTSEL TIM6_TRGO Timer 6 TRGO event 0 TIM21_CH2 Timer 21 CH2 event 1 TIM2_TRGO Timer 2 TRGO event 2 TIM2_CH4 Timer 2 CH4 event 3 TIM22_TRGO Timer 22 TRGO, Timer 21 TRGO event 4 TIM2_CH3 Timer 2 CH3 event 5 TIM3_TRGO Timer 3 TRGO event 6 EXTI_LINE11 EXTI line 11 event 7 ALIGN Data alignment 5 1 ALIGN Right Right alignment 0 Left Left alignment 1 RES Data resolution 3 2 RES TwelveBit 12 bits 0 TenBit 10 bits 1 EightBit 8 bits 2 SixBit 6 bits 3 SCANDIR Scan sequence direction 2 1 SCANDIR Upward Upward scan (from CHSEL0 to CHSEL18) 0 Backward Backward scan (from CHSEL18 to CHSEL0) 1 DMACFG Direct memery access configuration 1 1 DMACFG OneShot DMA one shot mode selected 0 Circular DMA circular mode selected 1 DMAEN Direct memory access enable 0 1 DMAEN Disabled DMA disabled 0 Enabled DMA enabled 1 CFGR2 CFGR2 configuration register 2 0x10 0x20 read-write 0x00000000 OVSE Oversampler Enable 0 1 OVSE Disabled Oversampler disabled 0 Enabled Oversampler enabled 1 OVSR Oversampling ratio 2 3 OVSR Mul2 2x 0 Mul4 4x 1 Mul8 8x 2 Mul16 16x 3 Mul32 32x 4 Mul64 64x 5 Mul128 128x 6 Mul256 256x 7 OVSS Oversampling shift 5 4 0 8 TOVS Triggered Oversampling 9 1 TOVS TriggerAll All oversampled conversions for a channel are done consecutively after a trigger 0 TriggerEach Each oversampled conversion for a channel needs a trigger 1 CKMODE ADC clock mode 30 2 CKMODE ADCLK ADCCLK (Asynchronous clock mode) 0 PCLK_Div2 PCLK/2 (Synchronous clock mode) 1 PCLK_Div4 PCLK/4 (Synchronous clock mode) 2 PCLK PCLK (Synchronous clock mode) 3 SMPR SMPR sampling time register 0x14 0x20 read-write 0x00000000 SMP Sampling time selection 0 3 SMP Cycles1_5 1.5 ADC clock cycles 0 Cycles3_5 3.5 ADC clock cycles 1 Cycles7_5 7.5 ADC clock cycles 2 Cycles12_5 12.5 ADC clock cycles 3 Cycles19_5 19.5 ADC clock cycles 4 Cycles39_5 39.5 ADC clock cycles 5 Cycles79_5 79.5 ADC clock cycles 6 Cycles160_5 160.5 ADC clock cycles 7 TR TR watchdog threshold register 0x20 0x20 read-write 0x0FFF0000 HT Analog watchdog higher threshold 16 12 0 2047 LT Analog watchdog lower threshold 0 12 0 2047 CHSELR CHSELR channel selection register 0x28 0x20 read-write 0x00000000 19 0x1 0-18 CHSEL%s Channel-x selection 0 1 CHSEL0 NotSelected Input Channel is not selected for conversion 0 Selected Input Channel is selected for conversion 1 DR DR data register 0x40 0x20 read-only 0x00000000 DATA Converted data 0 16 0 65535 CALFACT CALFACT ADC Calibration factor 0xB4 0x20 read-write 0x00000000 CALFACT Calibration factor 0 7 0 127 CCR CCR ADC common configuration register 0x308 0x20 read-write 0x00000000 PRESC ADC prescaler 18 4 PRESC Div1 Input ADC clock not divided 0 Div2 Input ADC clock divided by 2 1 Div4 Input ADC clock divided by 4 2 Div6 Input ADC clock divided by 6 3 Div8 Input ADC clock divided by 8 4 Div10 Input ADC clock divided by 10 5 Div12 Input ADC clock divided by 12 6 Div16 Input ADC clock divided by 16 7 Div32 Input ADC clock divided by 32 8 Div64 Input ADC clock divided by 64 9 Div128 Input ADC clock divided by 128 10 Div256 Input ADC clock divided by 256 11 VREFEN VREFINT enable 22 1 VREFEN Disabled The selected ADC channel disabled 0 Enabled The selected ADC channel enabled 1 TSEN Temperature sensor enable 23 1 VLCDEN VLCD enable 24 1 VLCDEN Disabled VLCD reading circuitry disabled 0 Enabled VLCD reading circuitry enabled 1 LFMEN Low Frequency Mode enable 25 1 LFMEN Disabled Low Frequency Mode disabled 0 Enabled Low Frequency Mode enabled 1 DBG Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x00000000 DEV_ID Device Identifier 0 12 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x00000000 DBG_STOP Debug Stop Mode 1 1 DBG_STOP Disabled Debug Stop Mode Disabled 0 Enabled Debug Stop Mode Enabled 1 DBG_STANDBY Debug Standby Mode 2 1 DBG_STANDBY Disabled Debug Standby Mode Disabled 0 Enabled Debug Standby Mode Enabled 1 DBG_SLEEP Debug Sleep Mode 0 1 DBG_SLEEP Disabled Debug Sleep Mode Disabled 0 Enabled Debug Sleep Mode Enabled 1 APB1_FZ APB1_FZ APB Low Freeze Register 0x8 0x20 read-write 0x00000000 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIMER2_STOP Continue The counter clock of TIMx is fed even if the core is halted 0 Stop The counter clock of TIMx is stopped when the core is halted 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_RTC_STOP Continue The clock of the RTC counter is fed even if the core is halted 0 Stop The clock of the RTC counter is stopped when the core is halted 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_WWDG_STOP Continue The window watchdog counter clock continues even if the core is halted 0 Stop The window watchdog counter clock is stopped when the core is halted 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_IWDG_STOP Continue The independent watchdog counter clock continues even if the core is halted 0 Stop The independent watchdog counter clock is stopped when the core is halted 1 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C1_STOP NormalMode Same behavior as in normal mode 0 SMBusTimeoutFrozen I2C3 SMBUS timeout is frozen 1 DBG_I2C2_STOP I2C2 SMBUS timeout mode stopped when core is halted 22 1 DBG_LPTIMER_STOP LPTIM1 counter stopped when core is halted 31 1 DBG_LPTIMER_STOP Continue LPTIM1 counter clock is fed even if the core is halted 0 Stop LPTIM1 counter clock is stopped when the core is halted 1 APB2_FZ APB2_FZ APB High Freeze Register 0xC 0x20 read-write 0x00000000 DBG_TIMER21_STOP Debug Timer 21 stopped when Core is halted 2 1 DBG_TIMER21_STOP Continue The counter clock of TIMx is fed even if the core is halted 0 Stop The counter clock of TIMx is stopped when the core is halted 1 DBG_TIMER22_STO Debug Timer 22 stopped when Core is halted 6 1 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 15 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 TI1S TI1 selection 7 1 TI1S Normal The TIMx_CH1 pin is connected to TI1 input 0 XOR The TIMx_CH1, CH2, CH3 pins are connected to TI1 input 1 MMS Master mode selection 4 3 MMS Reset The UG bit from the TIMx_EGR register is used as trigger output 0 Enable The counter enable signal, CNT_EN, is used as trigger output 1 Update The update event is selected as trigger output 2 ComparePulse The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred 3 CompareOC1 OC1REF signal is used as trigger output 4 CompareOC2 OC2REF signal is used as trigger output 5 CompareOC3 OC3REF signal is used as trigger output 6 CompareOC4 OC4REF signal is used as trigger output 7 CCDS Capture/compare DMA selection 3 1 CCDS OnCompare CCx DMA request sent when CCx event occurs 0 OnUpdate CCx DMA request sent when update event occurs 1 SMCR SMCR slave mode control register 0x8 0x10 read-write 0x00000000 ETP External trigger polarity 15 1 ETP NotInverted ETR is noninverted, active at high level or rising edge 0 Inverted ETR is inverted, active at low level or falling edge 1 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TDE Trigger DMA request enable 14 1 TDE Disabled Trigger DMA request disabled 0 Enabled Trigger DMA request enabled 1 4 0x1 1-4 CC%sDE Capture/Compare %s DMA request enable 9 1 CC1DE Disabled CCx DMA request disabled 0 Enabled CCx DMA request enabled 1 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 4 0x1 1-4 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 4 0x1 1-4 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 4 0x1 1-4 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 4 0x1 1-4 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x10 read-write 0x00000000 2 0x8 1-2 OC%sCE Output compare %s clear enable 7 1 OC1CE Disabled OCxRef is not affected by the ETRF signal 0 Enabled OCxRef is cleared as soon as a High level is detected on ETRF signal 1 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x10 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x10 read-write 0x00000000 2 0x8 3-4 OC%sCE Output compare %s clear enable 7 1 2 0x8 3-4 OC%sM Output compare %s mode 4 3 2 0x8 3-4 OC%sPE Output compare %s preload enable 3 1 2 0x8 3-4 OC%sFE Output compare %s fast enable 2 1 2 0x8 3-4 CC%sS Capture/Compare %s selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x10 read-write 0x00000000 2 0x8 3-4 IC%sF Input capture %s filter 4 4 2 0x8 3-4 IC%sPSC Input capture %s prescaler 2 2 CC4S Capture/Compare 4 selection 8 2 CC4S TI4 CC4 channel is configured as input, IC4 is mapped on TI4 1 TI3 CC4 channel is configured as input, IC4 is mapped on TI3 2 TRC CC4 channel is configured as input, IC4 is mapped on TRC 3 CC3S Capture/Compare 3 selection 0 2 CC3S TI3 CC3 channel is configured as input, IC3 is mapped on TI3 1 TI4 CC3 channel is configured as input, IC3 is mapped on TI4 2 TRC CC3 channel is configured as input, IC3 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 4 0x4 1-4 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP Negative Negative polarity 0 Positive Positive polarity 1 4 0x4 1-4 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 4 0x4 1-4 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x10 read-write 0x00000000 CNT Counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 4 0x4 1-4 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 DCR DCR DMA control register 0x48 0x10 read-write 0x00000000 DBL DMA burst length 8 5 0 18 DBA DMA base address 0 5 0 31 DMAR DMAR DMA address for full transfer 0x4C 0x10 read-write 0x00000000 DMAB DMA register for burst accesses 0 16 0 65535 OR OR TIM2 option register 0x50 0x10 read-write 0x00000000 ETR_RMP Timer2 ETR remap 0 3 ETR_RMP HSI TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set 3 LSE TIM2 ETR input is connected to LSE 5 COMP2_OUT TIM2 ETR input is connected to COMP2_OUT 6 COMP1_OUT TIM2 ETR input is connected to COMP1_OUT 7 TI4_RMP Internal trigger 3 2 TI4_RMP COMP2_OUT TIM2 TI4 input connected to COMP2_OUT 1 COMP1_OUT TIM2 TI4 input connected to COMP1_OUT 2 TIM3 TIM 0x40000400 TIM3 TIM3 global interrupt 16 TIM6 Basic-timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt and DAC 17 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Use UG bit from TIMx_EGR register 0 Enable Use CNT bit from TIMx_CEN register 1 Update Use the update event 2 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 UDE Update DMA request enable 8 1 UDE Disabled Update DMA request disabled 0 Enabled Update DMA request enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CNT CNT counter 0x24 0x10 read-write 0x00000000 CNT Low counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Low Auto-reload value 0 16 0 65535 TIM7 TIM 0x40001400 TIM7 TIM7 global interrupt and DAC 18 TIM21 General-purpose-timers TIM 0x40010800 0x0 0x400 registers TIM21 TIMER21 global interrupt 20 CR1 CR1 control register 1 0x0 0x10 read-write 0x00000000 CEN Counter enable 0 1 CEN Disabled Counter disabled 0 Enabled Counter enabled 1 UDIS Update disable 1 1 UDIS Enabled Update event enabled 0 Disabled Update event disabled 1 URS Update request source 2 1 URS AnyEvent Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request 0 CounterOnly Only counter overflow/underflow generates an update interrupt or DMA request 1 OPM One-pulse mode 3 1 OPM Disabled Counter is not stopped at update event 0 Enabled Counter stops counting at the next update event (clearing the CEN bit) 1 DIR Direction 4 1 DIR Up Counter used as upcounter 0 Down Counter used as downcounter 1 CMS Center-aligned mode selection 5 2 CMS EdgeAligned The counter counts up or down depending on the direction bit 0 CenterAligned1 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. 1 CenterAligned2 The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. 2 CenterAligned3 The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. 3 ARPE Auto-reload preload enable 7 1 ARPE Disabled TIMx_APRR register is not buffered 0 Enabled TIMx_APRR register is buffered 1 CKD Clock division 8 2 CKD Div1 t_DTS = t_CK_INT 0 Div2 t_DTS = 2 × t_CK_INT 1 Div4 t_DTS = 4 × t_CK_INT 2 CR2 CR2 control register 2 0x4 0x10 read-write 0x00000000 MMS Master mode selection 4 3 MMS Reset Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO) 0 Enable Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO) 1 Update Update - The update event is selected as trigger output (TRGO) 2 ComparePulse Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred 3 OC1REF OC1REF signal is used as trigger output (TRGO) 4 OC2REF OC2REF signal is used as trigger output (TRGO) 5 SMCR SMCR slave mode control register 0x8 0x10 read-write 0x00000000 SMS Slave mode selection 0 3 SMS Disabled Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 0 Encoder_Mode_1 Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 1 Encoder_Mode_2 Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 2 Encoder_Mode_3 Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 3 Reset_Mode Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 4 Gated_Mode Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 5 Trigger_Mode Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 6 Ext_Clock_Mode External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 7 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 MSM NoSync No action 0 Sync The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 1 ETF External trigger filter 8 4 ETF NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 ETPS External trigger prescaler 12 2 ETPS Div1 Prescaler OFF 0 Div2 ETRP frequency divided by 2 1 Div4 ETRP frequency divided by 4 2 Div8 ETRP frequency divided by 8 3 ECE External clock enable 14 1 ECE Disabled External clock mode 2 disabled 0 Enabled External clock mode 2 enabled 1 ETP External trigger polarity 15 1 ETP RisingEdge ETR is non-inverted, active at high level or rising edge 0 FallingEdge ETR is inverted, active at low level or falling edge 1 DIER DIER DMA/Interrupt enable register 0xC 0x10 read-write 0x00000000 TIE Trigger interrupt enable 6 1 TIE Disabled Trigger interrupt disabled 0 Enabled Trigger interrupt enabled 1 2 0x1 1-2 CC%sIE Capture/Compare %s interrupt enable 1 1 CC1IE Disabled CCx interrupt disabled 0 Enabled CCx interrupt enabled 1 UIE Update interrupt enable 0 1 UIE Disabled Update interrupt disabled 0 Enabled Update interrupt enabled 1 SR SR status register 0x10 0x10 read-write 0x00000000 2 0x1 1-2 CC%sOF Capture/Compare %s overcapture flag 9 1 zeroToClear CC1OFR read NoOvercapture No overcapture has been detected 0 Overcapture The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set 1 CC1OFW write Clear Clear flag 0 TIF Trigger interrupt flag 6 1 zeroToClear TIFR read NoTrigger No trigger event occurred 0 Trigger Trigger interrupt pending 1 TIFW write Clear Clear flag 0 2 0x1 1-2 CC%sIF Capture/compare %s interrupt flag 1 1 zeroToClear CC1IFR read NoMatch No campture/compare has been detected 0 Match If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. 1 CC1IFW write Clear Clear flag 0 UIF Update interrupt flag 0 1 zeroToClear UIFR read NoUpdateOccurred No update occurred 0 UpdatePending Update interrupt pending 1 UIFW write Clear Clear flag 0 EGR EGR event generation register 0x14 0x10 write-only 0x00000000 TG Trigger generation 6 1 TGW Trigger The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. 1 2 0x1 1-2 CC%sG Capture/compare %s generation 1 1 CC1GW Trigger If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. 1 UG Update generation 0 1 UG Update Re-initializes the timer counter and generates an update of the registers. 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x10 read-write 0x00000000 2 0x8 1-2 OC%sM Output compare %s mode 4 3 OC1M Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7 2 0x8 1-2 OC%sPE Output compare %s preload enable 3 1 OC1PE Disabled Preload register on CCRx disabled. New values written to CCRx are taken into account immediately 0 Enabled Preload register on CCRx enabled. Preload value is loaded into active register on each update event 1 2 0x8 1-2 OC%sFE Output compare %s fast enable 2 1 OC1FE Disabled Fast output disabled 0 Enabled Fast output enabled 1 2 0x8 1-2 CC%sS Capture/Compare %s selection 0 2 CC1S Output CCx channel is configured as output 0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x10 read-write 0x00000000 2 0x8 1-2 IC%sF Input capture %s filter 4 4 ICFilter NoFilter No filter, sampling is done at fDTS 0 FCK_INT_N2 fSAMPLING=fCK_INT, N=2 1 FCK_INT_N4 fSAMPLING=fCK_INT, N=4 2 FCK_INT_N8 fSAMPLING=fCK_INT, N=8 3 FDTS_Div2_N6 fSAMPLING=fDTS/2, N=6 4 FDTS_Div2_N8 fSAMPLING=fDTS/2, N=8 5 FDTS_Div4_N6 fSAMPLING=fDTS/4, N=6 6 FDTS_Div4_N8 fSAMPLING=fDTS/4, N=8 7 FDTS_Div8_N6 fSAMPLING=fDTS/8, N=6 8 FDTS_Div8_N8 fSAMPLING=fDTS/8, N=8 9 FDTS_Div16_N5 fSAMPLING=fDTS/16, N=5 10 FDTS_Div16_N6 fSAMPLING=fDTS/16, N=6 11 FDTS_Div16_N8 fSAMPLING=fDTS/16, N=8 12 FDTS_Div32_N5 fSAMPLING=fDTS/32, N=5 13 FDTS_Div32_N6 fSAMPLING=fDTS/32, N=6 14 FDTS_Div32_N8 fSAMPLING=fDTS/32, N=8 15 2 0x8 1-2 IC%sPSC Input capture %s prescaler 2 2 ICPrescaler NoPrescaler No prescaler, capture is done each time an edge is detected on the capture input 0 TwoEvents Capture is done once every 2 events 1 FourEvents Capture is done once every 4 events 2 EightEvents Capture is done once every 8 events 3 CC2S Capture/Compare 2 selection 8 2 CC2S TI2 CC2 channel is configured as input, IC2 is mapped on TI2 1 TI1 CC2 channel is configured as input, IC2 is mapped on TI1 2 TRC CC2 channel is configured as input, IC2 is mapped on TRC 3 CC1S Capture/Compare 1 selection 0 2 CC1S TI1 CC1 channel is configured as input, IC1 is mapped on TI1 1 TI2 CC1 channel is configured as input, IC1 is mapped on TI2 2 TRC CC1 channel is configured as input, IC1 is mapped on TRC 3 CCER CCER capture/compare enable register 0x20 0x10 read-write 0x00000000 2 0x4 1-2 CC%sNP Capture/Compare %s output Polarity 3 1 CC1NP Negative Negative polarity 0 Positive Positive polarity 1 2 0x4 1-2 CC%sP Capture/Compare %s output Polarity 1 1 CC1P RisingEdge Noninverted/rising edge 0 FallingEdge Inverted/falling edge 1 2 0x4 1-2 CC%sE Capture/Compare %s output enable 0 1 CC1E Disabled Capture disabled 0 Enabled Capture enabled 1 CNT CNT counter 0x24 0x10 read-write 0x00000000 CNT counter value 0 16 0 65535 PSC PSC prescaler 0x28 0x10 read-write 0x00000000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x10 read-write 0x0000FFFF ARR Auto-reload value 0 16 0 65535 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 0x10 read-write 0x00000000 CCR Capture/Compare value 0 16 0 65535 OR OR TIM21 option register 0x50 0x10 read-write 0x00000000 ETR_RMP Timer21 ETR remap 0 2 ETR_RMP GPIO TIM2x ETR input connected to GPIO 0 COMP2_OUT TIM2x ETR input connected to COMP2_OUT 1 COMP1_OUT TIM2x ETR input connected to COMP1_OUT 2 LSE TIM2x ETR input connected to LSE clock 3 TI1_RMP Timer21 TI1 2 3 TI1_RMP GPIO TIM2x TI1 input connected to GPIO 0 COMP2_OUT TIM2x TI1 input connected to COMP2_OUT 1 COMP1_OUT TIM2x TI1 input connected to COMP1_OUT 2 TI2_RMP Timer21 TI2 5 1 TI2_RMP GPIO TIM2x TI2 input connected to GPIO 0 COMP2_OUT TIM2x TI2 input connected to COMP2_OUT 1 TIM22 General-purpose-timers TIM 0x40011400 0x0 0x400 registers TIM22 TIMER22 global interrupt 22 CR1 CR1 control register 1 0x0 CR2 CR2 control register 2 0x4 SMCR SMCR slave mode control register 0x8 0x10 read-write 0x00000000 SMS Slave mode selection 0 3 TS Trigger selection 4 3 TS ITR0 Internal Trigger 0 (ITR0) 0 ITR1 Internal Trigger 1 (ITR1) 1 ITR2 Internal Trigger 2 (ITR2) 2 TI1F_ED TI1 Edge Detector (TI1F_ED) 4 TI1FP1 Filtered Timer Input 1 (TI1FP1) 5 TI2FP2 Filtered Timer Input 2 (TI2FP2) 6 ETRF External Trigger input (ETRF) 7 MSM Master/Slave mode 7 1 ETF External trigger filter 8 4 ETPS External trigger prescaler 12 2 ECE External clock enable 14 1 ETP External trigger polarity 15 1 DIER DIER DMA/Interrupt enable register 0xC SR SR status register 0x10 EGR EGR event generation register 0x14 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 CCER CCER capture/compare enable register 0x20 CNT CNT counter 0x24 PSC PSC prescaler 0x28 ARR ARR auto-reload register 0x2C 2 0x4 1-2 CCR%s CCR%s capture/compare register 0x34 OR OR TIM22 option register 0x50 0x10 read-write 0x00000000 ETR_RMP Timer22 ETR remap 0 2 ETR_RMP GPIO TIM2x ETR input connected to GPIO 0 COMP2_OUT TIM2x ETR input connected to COMP2_OUT 1 COMP1_OUT TIM2x ETR input connected to COMP1_OUT 2 LSE TIM2x ETR input connected to LSE clock 3 TI1_RMP Timer22 TI1 2 2 TI1_RMP GPIO TIM2x TI1 input connected to GPIO 0 COMP2_OUT TIM2x TI1 input connected to COMP2_OUT 1 COMP1_OUT TIM2x TI1 input connected to COMP1_OUT 2 LPUART1 Lower power Universal asynchronous receiver transmitter USART 0x40004800 0x0 0x400 registers CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 M1 Word length 28 1 M1 M0 Use M0 to set the data bits 0 Bit7 1 start bit, 7 data bits, n stop bits 1 DEAT Driver Enable assertion time 21 5 0 31 DEDT Driver Enable de-assertion time 16 5 0 31 CMIE Character match interrupt enable 14 1 CMIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated when the CMF bit is set in the ISR register 1 MME Mute mode enable 13 1 MME Disabled Receiver in active mode permanently 0 Enabled Receiver can switch between mute mode and active mode 1 M0 Word length 12 1 M0 Bit8 1 start bit, 8 data bits, n stop bits 0 Bit9 1 start bit, 9 data bits, n stop bits 1 WAKE Receiver wakeup method 11 1 WAKE Idle Idle line 0 Address Address mask 1 PCE Parity control enable 10 1 PCE Disabled Parity control disabled 0 Enabled Parity control enabled 1 PS Parity selection 9 1 PS Even Even parity 0 Odd Odd parity 1 PEIE PE interrupt enable 8 1 PEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever PE=1 in the ISR register 1 TXEIE interrupt enable 7 1 TXEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TXE=1 in the ISR register 1 TCIE Transmission complete interrupt enable 6 1 TCIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever TC=1 in the ISR register 1 RXNEIE RXNE interrupt enable 5 1 RXNEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register 1 IDLEIE IDLE interrupt enable 4 1 IDLEIE Disabled Interrupt is disabled 0 Enabled Interrupt is generated whenever IDLE=1 in the ISR register 1 TE Transmitter enable 3 1 TE Disabled Transmitter is disabled 0 Enabled Transmitter is enabled 1 RE Receiver enable 2 1 RE Disabled Receiver is disabled 0 Enabled Receiver is enabled 1 UESM USART enable in Stop mode 1 1 UESM Disabled USART not able to wake up the MCU from Stop mode 0 Enabled USART able to wake up the MCU from Stop mode 1 UE USART enable 0 1 UE Disabled UART is disabled 0 Enabled UART is enabled 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the USART node 24 8 0 255 MSBFIRST Most significant bit first 19 1 MSBFIRST LSB data is transmitted/received with data bit 0 first, following the start bit 0 MSB data is transmitted/received with MSB (bit 7/8/9) first, following the start bit 1 DATAINV Binary data inversion 18 1 DATAINV Positive Logical data from the data register are send/received in positive/direct logic 0 Negative Logical data from the data register are send/received in negative/inverse logic 1 TXINV TX pin active level inversion 17 1 TXINV Standard TX pin signal works using the standard logic levels 0 Inverted TX pin signal values are inverted 1 RXINV RX pin active level inversion 16 1 RXINV Standard RX pin signal works using the standard logic levels 0 Inverted RX pin signal values are inverted 1 SWAP Swap TX/RX pins 15 1 SWAP Standard TX/RX pins are used as defined in standard pinout 0 Swapped The TX and RX pins functions are swapped 1 STOP STOP bits 12 2 STOP Stop1 1 stop bit 0 Stop0p5 0.5 stop bit 1 Stop2 2 stop bit 2 Stop1p5 1.5 stop bit 3 CLKEN Clock enable 11 1 CLKEN Disabled CK pin disabled 0 Enabled CK pin enabled 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 ADDM7 Bit4 4-bit address detection 0 Bit7 7-bit address detection 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUFIE Disabled Interrupt is inhibited 0 Enabled An USART interrupt is generated whenever WUF=1 in the ISR register 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 WUS Address WUF active on address match 0 Start WuF active on Start bit detection 2 RXNE WUF active on RXNE 3 DEP Driver enable polarity selection 15 1 DEP High DE signal is active high 0 Low DE signal is active low 1 DEM Driver enable mode 14 1 DEM Disabled DE function is disabled 0 Enabled The DE signal is output on the RTS pin 1 DDRE DMA Disable on Reception Error 13 1 DDRE NotDisabled DMA is not disabled in case of reception error 0 Disabled DMA is disabled following a reception error 1 OVRDIS Overrun Disable 12 1 OVRDIS Enabled Overrun Error Flag, ORE, is set when received data is not read before receiving new data 0 Disabled Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register 1 CTSIE CTS interrupt enable 10 1 CTSIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated whenever CTSIF=1 in the ISR register 1 CTSE CTS enable 9 1 CTSE Disabled CTS hardware flow control disabled 0 Enabled CTS mode enabled, data is only transmitted when the CTS input is asserted 1 RTSE RTS enable 8 1 RTSE Disabled RTS hardware flow control disabled 0 Enabled RTS output enabled, data is only requested when there is space in the receive buffer 1 DMAT DMA enable transmitter 7 1 DMAT Disabled DMA mode is disabled for transmission 0 Enabled DMA mode is enabled for transmission 1 DMAR DMA enable receiver 6 1 DMAR Disabled DMA mode is disabled for reception 0 Enabled DMA mode is enabled for reception 1 HDSEL Half-duplex selection 3 1 HDSEL NotSelected Half duplex mode is not selected 0 Selected Half duplex mode is selected 1 EIE Error interrupt enable 0 1 EIE Disabled Interrupt is inhibited 0 Enabled An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 BRR BRR 0 20 0 1048575 RQR RQR Request register 0x18 0x20 write-only 0x00000000 RXFRQ Receive data flush request 3 1 RXFRQ Discard clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition 1 MMRQ Mute mode request 2 1 MMRQ Mute Puts the USART in mute mode and sets the RWU flag 1 SBKRQ Send break request 1 1 SBKRQ Break sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 RWU Active Receiver in Active mode 0 Mute Receiver in Mute mode 1 SBKF SBKF 18 1 SBKF NoBreak No break character transmitted 0 Break Break character transmitted 1 CMF CMF 17 1 CMF NoMatch No Character match detected 0 Match Character match detected 1 BUSY BUSY 16 1 BUSY Idle USART is idle (no reception) 0 Busy Reception on going 1 CTS CTS 10 1 CTS Set CTS line set 0 Reset CTS line reset 1 CTSIF CTSIF 9 1 CTSIF NotChanged No change occurred on the CTS status line 0 Changed A change occurred on the CTS status line 1 TXE TXE 7 1 TXE Full Transmit FIFO is full 0 NotFull Transmit FIFO is not full 1 TC TC 6 1 TC TxNotComplete Transmission is not complete 0 TxComplete Transmission is complete 1 RXNE RXNE 5 1 RXNE NoData Data is not received 0 DataReady Received data is ready to be read 1 IDLE IDLE 4 1 IDLE NoIdle No Idle Line is detected 0 Idle Idle Line is detected 1 ORE ORE 3 1 ORE NoOverrun No Overrun error 0 Overrun Overrun error is detected 1 NF NF 2 1 NF NoNoise No noise is detected 0 Noise Noise is detected 1 FE FE 1 1 FE NoError No Framing error is detected 0 Error Framing error or break character is detected 1 PE PE 0 1 PE NoError No parity error 0 Error Parity error 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 oneToClear WUCF Clear Clears the WUF flag in the ISR register 1 CMCF Character match clear flag 17 1 oneToClear CMCF Clear Clears the CMF flag in the ISR register 1 CTSCF CTS clear flag 9 1 oneToClear CTSCF Clear Clears the CTSIF flag in the ISR register 1 TCCF Transmission complete clear flag 6 1 oneToClear TCCF Clear Clears the TC flag in the ISR register 1 IDLECF Idle line detected clear flag 4 1 oneToClear IDLECF Clear Clears the IDLE flag in the ISR register 1 ORECF Overrun error clear flag 3 1 oneToClear ORECF Clear Clears the ORE flag in the ISR register 1 NCF Noise detected clear flag 2 1 oneToClear NCF Clear Clears the NF flag in the ISR register 1 FECF Framing error clear flag 1 1 oneToClear FECF Clear Clears the FE flag in the ISR register 1 PECF Parity error clear flag 0 1 oneToClear PECF Clear Clears the PE flag in the ISR register 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 0 511 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 0 511 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x33D registers ISER ISER Interrupt Set Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 0 4294967295 ICER ICER Interrupt Clear Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 0 4294967295 ISPR ISPR Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 0 4294967295 ICPR ICPR Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 0 4294967295 IPR0 IPR0 Interrupt Priority Register 0 0x300 0x20 read-write 0x00000000 PRI_0 priority for interrupt 0 0 8 0 255 PRI_1 priority for interrupt 1 8 8 0 255 PRI_2 priority for interrupt 2 16 8 0 255 PRI_3 priority for interrupt 3 24 8 0 255 IPR1 IPR1 Interrupt Priority Register 1 0x304 0x20 read-write 0x00000000 PRI_4 priority for interrupt n 0 8 0 255 PRI_5 priority for interrupt n 8 8 0 255 PRI_6 priority for interrupt n 16 8 0 255 PRI_7 priority for interrupt n 24 8 0 255 IPR2 IPR2 Interrupt Priority Register 2 0x308 0x20 read-write 0x00000000 PRI_8 priority for interrupt n 0 8 0 255 PRI_9 priority for interrupt n 8 8 0 255 PRI_10 priority for interrupt n 16 8 0 255 PRI_11 priority for interrupt n 24 8 0 255 IPR3 IPR3 Interrupt Priority Register 3 0x30C 0x20 read-write 0x00000000 PRI_12 priority for interrupt n 0 8 0 255 PRI_13 priority for interrupt n 8 8 0 255 PRI_14 priority for interrupt n 16 8 0 255 PRI_15 priority for interrupt n 24 8 0 255 IPR4 IPR4 Interrupt Priority Register 4 0x310 0x20 read-write 0x00000000 PRI_16 priority for interrupt n 0 8 0 255 PRI_17 priority for interrupt n 8 8 0 255 PRI_18 priority for interrupt n 16 8 0 255 PRI_19 priority for interrupt n 24 8 0 255 IPR5 IPR5 Interrupt Priority Register 5 0x314 0x20 read-write 0x00000000 PRI_20 priority for interrupt n 0 8 0 255 PRI_21 priority for interrupt n 8 8 0 255 PRI_22 priority for interrupt n 16 8 0 255 PRI_23 priority for interrupt n 24 8 0 255 IPR6 IPR6 Interrupt Priority Register 6 0x318 0x20 read-write 0x00000000 PRI_24 priority for interrupt n 0 8 0 255 PRI_25 priority for interrupt n 8 8 0 255 PRI_26 priority for interrupt n 16 8 0 255 PRI_27 priority for interrupt n 24 8 0 255 IPR7 IPR7 Interrupt Priority Register 7 0x31C 0x20 read-write 0x00000000 PRI_28 priority for interrupt n 0 8 0 255 PRI_29 priority for interrupt n 8 8 0 255 PRI_30 priority for interrupt n 16 8 0 255 PRI_31 priority for interrupt n 24 8 0 255